1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #define SWSMU_CODE_LAYER_L3
24
25 #include <linux/firmware.h>
26 #include "amdgpu.h"
27 #include "amdgpu_smu.h"
28 #include "atomfirmware.h"
29 #include "amdgpu_atomfirmware.h"
30 #include "amdgpu_atombios.h"
31 #include "smu_v12_0.h"
32 #include "soc15_common.h"
33 #include "atom.h"
34 #include "smu_cmn.h"
35
36 #include "asic_reg/mp/mp_12_0_0_offset.h"
37 #include "asic_reg/mp/mp_12_0_0_sh_mask.h"
38 #include "asic_reg/smuio/smuio_12_0_0_offset.h"
39 #include "asic_reg/smuio/smuio_12_0_0_sh_mask.h"
40
41 /*
42 * DO NOT use these for err/warn/info/debug messages.
43 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
44 * They are more MGPU friendly.
45 */
46 #undef pr_err
47 #undef pr_warn
48 #undef pr_info
49 #undef pr_debug
50
51 // because some SMU12 based ASICs use older ip offset tables
52 // we should undefine this register from the smuio12 header
53 // to prevent confusion down the road
54 #undef mmPWR_MISC_CNTL_STATUS
55
56 #define smnMP1_FIRMWARE_FLAGS 0x3010024
57
smu_v12_0_check_fw_status(struct smu_context * smu)58 int smu_v12_0_check_fw_status(struct smu_context *smu)
59 {
60 struct amdgpu_device *adev = smu->adev;
61 uint32_t mp1_fw_flags;
62
63 mp1_fw_flags = RREG32_PCIE(MP1_Public |
64 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
65
66 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
67 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
68 return 0;
69
70 return -EIO;
71 }
72
smu_v12_0_powergate_sdma(struct smu_context * smu,bool gate)73 int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate)
74 {
75 if (!smu->is_apu)
76 return 0;
77
78 if (gate)
79 return smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownSdma, NULL);
80 else
81 return smu_cmn_send_smc_msg(smu, SMU_MSG_PowerUpSdma, NULL);
82 }
83
smu_v12_0_set_gfx_cgpg(struct smu_context * smu,bool enable)84 int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
85 {
86 /* Until now the SMU12 only implemented for Renoir series so here neen't do APU check. */
87 if (!(smu->adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) || smu->adev->in_s0ix)
88 return 0;
89
90 return smu_cmn_send_smc_msg_with_param(smu,
91 SMU_MSG_SetGfxCGPG,
92 enable ? 1 : 0,
93 NULL);
94 }
95
96 /**
97 * smu_v12_0_get_gfxoff_status - get gfxoff status
98 *
99 * @smu: amdgpu_device pointer
100 *
101 * This function will be used to get gfxoff status
102 *
103 * Returns 0=GFXOFF(default).
104 * Returns 1=Transition out of GFX State.
105 * Returns 2=Not in GFXOFF.
106 * Returns 3=Transition into GFXOFF.
107 */
smu_v12_0_get_gfxoff_status(struct smu_context * smu)108 uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu)
109 {
110 uint32_t reg;
111 uint32_t gfxOff_Status = 0;
112 struct amdgpu_device *adev = smu->adev;
113
114 reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_GFX_MISC_CNTL);
115 gfxOff_Status = (reg & SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK)
116 >> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT;
117
118 return gfxOff_Status;
119 }
120
smu_v12_0_gfx_off_control(struct smu_context * smu,bool enable)121 int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable)
122 {
123 int ret = 0, timeout = 500;
124
125 if (enable) {
126 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
127
128 } else {
129 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
130
131 /* confirm gfx is back to "on" state, timeout is 0.5 second */
132 while (!(smu_v12_0_get_gfxoff_status(smu) == 2)) {
133 msleep(1);
134 timeout--;
135 if (timeout == 0) {
136 DRM_ERROR("disable gfxoff timeout and failed!\n");
137 break;
138 }
139 }
140 }
141
142 return ret;
143 }
144
smu_v12_0_fini_smc_tables(struct smu_context * smu)145 int smu_v12_0_fini_smc_tables(struct smu_context *smu)
146 {
147 struct smu_table_context *smu_table = &smu->smu_table;
148
149 kfree(smu_table->clocks_table);
150 smu_table->clocks_table = NULL;
151
152 kfree(smu_table->metrics_table);
153 smu_table->metrics_table = NULL;
154
155 kfree(smu_table->watermarks_table);
156 smu_table->watermarks_table = NULL;
157
158 smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPU_METRICS);
159
160 return 0;
161 }
162
smu_v12_0_set_default_dpm_tables(struct smu_context * smu)163 int smu_v12_0_set_default_dpm_tables(struct smu_context *smu)
164 {
165 struct smu_table_context *smu_table = &smu->smu_table;
166
167 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
168 }
169
smu_v12_0_mode2_reset(struct smu_context * smu)170 int smu_v12_0_mode2_reset(struct smu_context *smu)
171 {
172 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_2, NULL);
173 }
174
smu_v12_0_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max,bool automatic)175 int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
176 uint32_t min, uint32_t max, bool automatic)
177 {
178 int ret = 0;
179
180 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
181 return 0;
182
183 switch (clk_type) {
184 case SMU_GFXCLK:
185 case SMU_SCLK:
186 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, min, NULL);
187 if (ret)
188 return ret;
189
190 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, max, NULL);
191 if (ret)
192 return ret;
193 break;
194 case SMU_FCLK:
195 case SMU_MCLK:
196 case SMU_UCLK:
197 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min, NULL);
198 if (ret)
199 return ret;
200
201 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max, NULL);
202 if (ret)
203 return ret;
204 break;
205 case SMU_SOCCLK:
206 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min, NULL);
207 if (ret)
208 return ret;
209
210 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max, NULL);
211 if (ret)
212 return ret;
213 break;
214 case SMU_VCLK:
215 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinVcn, min, NULL);
216 if (ret)
217 return ret;
218
219 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxVcn, max, NULL);
220 if (ret)
221 return ret;
222 break;
223 default:
224 return -EINVAL;
225 }
226
227 return ret;
228 }
229
smu_v12_0_set_driver_table_location(struct smu_context * smu)230 int smu_v12_0_set_driver_table_location(struct smu_context *smu)
231 {
232 struct smu_table *driver_table = &smu->smu_table.driver_table;
233 int ret = 0;
234
235 if (driver_table->mc_address) {
236 ret = smu_cmn_send_smc_msg_with_param(smu,
237 SMU_MSG_SetDriverDramAddrHigh,
238 upper_32_bits(driver_table->mc_address),
239 NULL);
240 if (!ret)
241 ret = smu_cmn_send_smc_msg_with_param(smu,
242 SMU_MSG_SetDriverDramAddrLow,
243 lower_32_bits(driver_table->mc_address),
244 NULL);
245 }
246
247 return ret;
248 }
249
smu_v12_0_atom_get_smu_clockinfo(struct amdgpu_device * adev,uint8_t clk_id,uint8_t syspll_id,uint32_t * clk_freq)250 static int smu_v12_0_atom_get_smu_clockinfo(struct amdgpu_device *adev,
251 uint8_t clk_id,
252 uint8_t syspll_id,
253 uint32_t *clk_freq)
254 {
255 struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
256 struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
257 int ret, index;
258
259 input.clk_id = clk_id;
260 input.syspll_id = syspll_id;
261 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
262 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
263 getsmuclockinfo);
264
265 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
266 (uint32_t *)&input, sizeof(input));
267 if (ret)
268 return -EINVAL;
269
270 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
271 *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
272
273 return 0;
274 }
275
smu_v12_0_get_vbios_bootup_values(struct smu_context * smu)276 int smu_v12_0_get_vbios_bootup_values(struct smu_context *smu)
277 {
278 int ret, index;
279 uint16_t size;
280 uint8_t frev, crev;
281 struct atom_common_table_header *header;
282 struct atom_firmware_info_v3_1 *v_3_1;
283 struct atom_firmware_info_v3_3 *v_3_3;
284
285 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
286 firmwareinfo);
287
288 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
289 (uint8_t **)&header);
290 if (ret)
291 return ret;
292
293 if (header->format_revision != 3) {
294 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu12\n");
295 return -EINVAL;
296 }
297
298 switch (header->content_revision) {
299 case 0:
300 case 1:
301 case 2:
302 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
303 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
304 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
305 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
306 smu->smu_table.boot_values.socclk = 0;
307 smu->smu_table.boot_values.dcefclk = 0;
308 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
309 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
310 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
311 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
312 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
313 smu->smu_table.boot_values.pp_table_id = 0;
314 smu->smu_table.boot_values.firmware_caps = v_3_1->firmware_capability;
315 break;
316 case 3:
317 case 4:
318 default:
319 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
320 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
321 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
322 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
323 smu->smu_table.boot_values.socclk = 0;
324 smu->smu_table.boot_values.dcefclk = 0;
325 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
326 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
327 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
328 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
329 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
330 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
331 smu->smu_table.boot_values.firmware_caps = v_3_3->firmware_capability;
332 }
333
334 smu->smu_table.boot_values.format_revision = header->format_revision;
335 smu->smu_table.boot_values.content_revision = header->content_revision;
336
337 smu_v12_0_atom_get_smu_clockinfo(smu->adev,
338 (uint8_t)SMU12_SYSPLL0_SOCCLK_ID,
339 (uint8_t)SMU12_SYSPLL0_ID,
340 &smu->smu_table.boot_values.socclk);
341
342 smu_v12_0_atom_get_smu_clockinfo(smu->adev,
343 (uint8_t)SMU12_SYSPLL1_DCFCLK_ID,
344 (uint8_t)SMU12_SYSPLL1_ID,
345 &smu->smu_table.boot_values.dcefclk);
346
347 smu_v12_0_atom_get_smu_clockinfo(smu->adev,
348 (uint8_t)SMU12_SYSPLL0_VCLK_ID,
349 (uint8_t)SMU12_SYSPLL0_ID,
350 &smu->smu_table.boot_values.vclk);
351
352 smu_v12_0_atom_get_smu_clockinfo(smu->adev,
353 (uint8_t)SMU12_SYSPLL0_DCLK_ID,
354 (uint8_t)SMU12_SYSPLL0_ID,
355 &smu->smu_table.boot_values.dclk);
356
357 if ((smu->smu_table.boot_values.format_revision == 3) &&
358 (smu->smu_table.boot_values.content_revision >= 2))
359 smu_v12_0_atom_get_smu_clockinfo(smu->adev,
360 (uint8_t)SMU12_SYSPLL3_0_FCLK_ID,
361 (uint8_t)SMU12_SYSPLL3_0_ID,
362 &smu->smu_table.boot_values.fclk);
363
364 smu_v12_0_atom_get_smu_clockinfo(smu->adev,
365 (uint8_t)SMU12_SYSPLL0_LCLK_ID,
366 (uint8_t)SMU12_SYSPLL0_ID,
367 &smu->smu_table.boot_values.lclk);
368
369 return 0;
370 }
371
smu_v12_0_init_msg_ctl(struct smu_context * smu,const struct cmn2asic_msg_mapping * message_map)372 void smu_v12_0_init_msg_ctl(struct smu_context *smu,
373 const struct cmn2asic_msg_mapping *message_map)
374 {
375 struct amdgpu_device *adev = smu->adev;
376 struct smu_msg_ctl *ctl = &smu->msg_ctl;
377
378 ctl->smu = smu;
379 mutex_init(&ctl->lock);
380 ctl->config.msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
381 ctl->config.resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
382 ctl->config.arg_regs[0] = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
383 ctl->config.num_arg_regs = 1;
384 ctl->ops = &smu_msg_v1_ops;
385 ctl->default_timeout = adev->usec_timeout * 20;
386 ctl->message_map = message_map;
387 }
388