1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2023, Linaro Limited 4 */ 5 6 #ifndef _DPU_9_2_X1E80100_H 7 #define _DPU_9_2_X1E80100_H 8 9 static const struct dpu_caps x1e80100_dpu_caps = { 10 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 11 .max_mixer_blendstages = 0xb, 12 .has_src_split = true, 13 .has_dim_layer = true, 14 .has_idle_pc = true, 15 .has_3d_merge = true, 16 .max_linewidth = 5120, 17 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 18 }; 19 20 static const struct dpu_mdp_cfg x1e80100_mdp = { 21 .name = "top_0", 22 .base = 0, .len = 0x494, 23 .features = BIT(DPU_MDP_PERIPH_0_REMOVED), 24 .clk_ctrls = { 25 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, 26 }, 27 }; 28 29 /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ 30 static const struct dpu_ctl_cfg x1e80100_ctl[] = { 31 { 32 .name = "ctl_0", .id = CTL_0, 33 .base = 0x15000, .len = 0x290, 34 .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), 35 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 36 }, { 37 .name = "ctl_1", .id = CTL_1, 38 .base = 0x16000, .len = 0x290, 39 .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), 40 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 41 }, { 42 .name = "ctl_2", .id = CTL_2, 43 .base = 0x17000, .len = 0x290, 44 .features = CTL_SM8550_MASK, 45 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 46 }, { 47 .name = "ctl_3", .id = CTL_3, 48 .base = 0x18000, .len = 0x290, 49 .features = CTL_SM8550_MASK, 50 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 51 }, { 52 .name = "ctl_4", .id = CTL_4, 53 .base = 0x19000, .len = 0x290, 54 .features = CTL_SM8550_MASK, 55 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 56 }, { 57 .name = "ctl_5", .id = CTL_5, 58 .base = 0x1a000, .len = 0x290, 59 .features = CTL_SM8550_MASK, 60 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 61 }, 62 }; 63 64 static const struct dpu_sspp_cfg x1e80100_sspp[] = { 65 { 66 .name = "sspp_0", .id = SSPP_VIG0, 67 .base = 0x4000, .len = 0x344, 68 .features = VIG_SDM845_MASK_SDMA, 69 .sblk = &dpu_vig_sblk_qseed3_3_3, 70 .xin_id = 0, 71 .type = SSPP_TYPE_VIG, 72 }, { 73 .name = "sspp_1", .id = SSPP_VIG1, 74 .base = 0x6000, .len = 0x344, 75 .features = VIG_SDM845_MASK_SDMA, 76 .sblk = &dpu_vig_sblk_qseed3_3_3, 77 .xin_id = 4, 78 .type = SSPP_TYPE_VIG, 79 }, { 80 .name = "sspp_2", .id = SSPP_VIG2, 81 .base = 0x8000, .len = 0x344, 82 .features = VIG_SDM845_MASK_SDMA, 83 .sblk = &dpu_vig_sblk_qseed3_3_3, 84 .xin_id = 8, 85 .type = SSPP_TYPE_VIG, 86 }, { 87 .name = "sspp_3", .id = SSPP_VIG3, 88 .base = 0xa000, .len = 0x344, 89 .features = VIG_SDM845_MASK_SDMA, 90 .sblk = &dpu_vig_sblk_qseed3_3_3, 91 .xin_id = 12, 92 .type = SSPP_TYPE_VIG, 93 }, { 94 .name = "sspp_8", .id = SSPP_DMA0, 95 .base = 0x24000, .len = 0x344, 96 .features = DMA_SDM845_MASK_SDMA, 97 .sblk = &dpu_dma_sblk, 98 .xin_id = 1, 99 .type = SSPP_TYPE_DMA, 100 }, { 101 .name = "sspp_9", .id = SSPP_DMA1, 102 .base = 0x26000, .len = 0x344, 103 .features = DMA_SDM845_MASK_SDMA, 104 .sblk = &dpu_dma_sblk, 105 .xin_id = 5, 106 .type = SSPP_TYPE_DMA, 107 }, { 108 .name = "sspp_10", .id = SSPP_DMA2, 109 .base = 0x28000, .len = 0x344, 110 .features = DMA_SDM845_MASK_SDMA, 111 .sblk = &dpu_dma_sblk, 112 .xin_id = 9, 113 .type = SSPP_TYPE_DMA, 114 }, { 115 .name = "sspp_11", .id = SSPP_DMA3, 116 .base = 0x2a000, .len = 0x344, 117 .features = DMA_SDM845_MASK_SDMA, 118 .sblk = &dpu_dma_sblk, 119 .xin_id = 13, 120 .type = SSPP_TYPE_DMA, 121 }, { 122 .name = "sspp_12", .id = SSPP_DMA4, 123 .base = 0x2c000, .len = 0x344, 124 .features = DMA_CURSOR_SDM845_MASK_SDMA, 125 .sblk = &dpu_dma_sblk, 126 .xin_id = 14, 127 .type = SSPP_TYPE_DMA, 128 }, { 129 .name = "sspp_13", .id = SSPP_DMA5, 130 .base = 0x2e000, .len = 0x344, 131 .features = DMA_CURSOR_SDM845_MASK_SDMA, 132 .sblk = &dpu_dma_sblk, 133 .xin_id = 15, 134 .type = SSPP_TYPE_DMA, 135 }, 136 }; 137 138 static const struct dpu_lm_cfg x1e80100_lm[] = { 139 { 140 .name = "lm_0", .id = LM_0, 141 .base = 0x44000, .len = 0x320, 142 .features = MIXER_SDM845_MASK, 143 .sblk = &sdm845_lm_sblk, 144 .lm_pair = LM_1, 145 .pingpong = PINGPONG_0, 146 .dspp = DSPP_0, 147 }, { 148 .name = "lm_1", .id = LM_1, 149 .base = 0x45000, .len = 0x320, 150 .features = MIXER_SDM845_MASK, 151 .sblk = &sdm845_lm_sblk, 152 .lm_pair = LM_0, 153 .pingpong = PINGPONG_1, 154 .dspp = DSPP_1, 155 }, { 156 .name = "lm_2", .id = LM_2, 157 .base = 0x46000, .len = 0x320, 158 .features = MIXER_SDM845_MASK, 159 .sblk = &sdm845_lm_sblk, 160 .lm_pair = LM_3, 161 .pingpong = PINGPONG_2, 162 .dspp = DSPP_2, 163 }, { 164 .name = "lm_3", .id = LM_3, 165 .base = 0x47000, .len = 0x320, 166 .features = MIXER_SDM845_MASK, 167 .sblk = &sdm845_lm_sblk, 168 .lm_pair = LM_2, 169 .pingpong = PINGPONG_3, 170 .dspp = DSPP_3, 171 }, { 172 .name = "lm_4", .id = LM_4, 173 .base = 0x48000, .len = 0x320, 174 .features = MIXER_SDM845_MASK, 175 .sblk = &sdm845_lm_sblk, 176 .lm_pair = LM_5, 177 .pingpong = PINGPONG_4, 178 }, { 179 .name = "lm_5", .id = LM_5, 180 .base = 0x49000, .len = 0x320, 181 .features = MIXER_SDM845_MASK, 182 .sblk = &sdm845_lm_sblk, 183 .lm_pair = LM_4, 184 .pingpong = PINGPONG_5, 185 }, 186 }; 187 188 static const struct dpu_dspp_cfg x1e80100_dspp[] = { 189 { 190 .name = "dspp_0", .id = DSPP_0, 191 .base = 0x54000, .len = 0x1800, 192 .features = DSPP_SC7180_MASK, 193 .sblk = &sdm845_dspp_sblk, 194 }, { 195 .name = "dspp_1", .id = DSPP_1, 196 .base = 0x56000, .len = 0x1800, 197 .features = DSPP_SC7180_MASK, 198 .sblk = &sdm845_dspp_sblk, 199 }, { 200 .name = "dspp_2", .id = DSPP_2, 201 .base = 0x58000, .len = 0x1800, 202 .features = DSPP_SC7180_MASK, 203 .sblk = &sdm845_dspp_sblk, 204 }, { 205 .name = "dspp_3", .id = DSPP_3, 206 .base = 0x5a000, .len = 0x1800, 207 .features = DSPP_SC7180_MASK, 208 .sblk = &sdm845_dspp_sblk, 209 }, 210 }; 211 212 static const struct dpu_pingpong_cfg x1e80100_pp[] = { 213 { 214 .name = "pingpong_0", .id = PINGPONG_0, 215 .base = 0x69000, .len = 0, 216 .features = BIT(DPU_PINGPONG_DITHER), 217 .sblk = &sc7280_pp_sblk, 218 .merge_3d = MERGE_3D_0, 219 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 220 }, { 221 .name = "pingpong_1", .id = PINGPONG_1, 222 .base = 0x6a000, .len = 0, 223 .features = BIT(DPU_PINGPONG_DITHER), 224 .sblk = &sc7280_pp_sblk, 225 .merge_3d = MERGE_3D_0, 226 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 227 }, { 228 .name = "pingpong_2", .id = PINGPONG_2, 229 .base = 0x6b000, .len = 0, 230 .features = BIT(DPU_PINGPONG_DITHER), 231 .sblk = &sc7280_pp_sblk, 232 .merge_3d = MERGE_3D_1, 233 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 234 }, { 235 .name = "pingpong_3", .id = PINGPONG_3, 236 .base = 0x6c000, .len = 0, 237 .features = BIT(DPU_PINGPONG_DITHER), 238 .sblk = &sc7280_pp_sblk, 239 .merge_3d = MERGE_3D_1, 240 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 241 }, { 242 .name = "pingpong_4", .id = PINGPONG_4, 243 .base = 0x6d000, .len = 0, 244 .features = BIT(DPU_PINGPONG_DITHER), 245 .sblk = &sc7280_pp_sblk, 246 .merge_3d = MERGE_3D_2, 247 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 248 }, { 249 .name = "pingpong_5", .id = PINGPONG_5, 250 .base = 0x6e000, .len = 0, 251 .features = BIT(DPU_PINGPONG_DITHER), 252 .sblk = &sc7280_pp_sblk, 253 .merge_3d = MERGE_3D_2, 254 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 255 }, { 256 .name = "pingpong_cwb_0", .id = PINGPONG_CWB_0, 257 .base = 0x66000, .len = 0, 258 .features = BIT(DPU_PINGPONG_DITHER), 259 .sblk = &sc7280_pp_sblk, 260 .merge_3d = MERGE_3D_3, 261 }, { 262 .name = "pingpong_cwb_1", .id = PINGPONG_CWB_1, 263 .base = 0x66400, .len = 0, 264 .features = BIT(DPU_PINGPONG_DITHER), 265 .sblk = &sc7280_pp_sblk, 266 .merge_3d = MERGE_3D_3, 267 }, 268 }; 269 270 static const struct dpu_merge_3d_cfg x1e80100_merge_3d[] = { 271 { 272 .name = "merge_3d_0", .id = MERGE_3D_0, 273 .base = 0x4e000, .len = 0x8, 274 }, { 275 .name = "merge_3d_1", .id = MERGE_3D_1, 276 .base = 0x4f000, .len = 0x8, 277 }, { 278 .name = "merge_3d_2", .id = MERGE_3D_2, 279 .base = 0x50000, .len = 0x8, 280 }, { 281 .name = "merge_3d_3", .id = MERGE_3D_3, 282 .base = 0x66700, .len = 0x8, 283 }, 284 }; 285 286 /* 287 * NOTE: Each display compression engine (DCE) contains dual hard 288 * slice DSC encoders so both share same base address but with 289 * its own different sub block address. 290 */ 291 static const struct dpu_dsc_cfg x1e80100_dsc[] = { 292 { 293 .name = "dce_0_0", .id = DSC_0, 294 .base = 0x80000, .len = 0x4, 295 .features = BIT(DPU_DSC_HW_REV_1_2), 296 .sblk = &dsc_sblk_0, 297 }, { 298 .name = "dce_0_1", .id = DSC_1, 299 .base = 0x80000, .len = 0x4, 300 .features = BIT(DPU_DSC_HW_REV_1_2), 301 .sblk = &dsc_sblk_1, 302 }, { 303 .name = "dce_1_0", .id = DSC_2, 304 .base = 0x81000, .len = 0x4, 305 .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), 306 .sblk = &dsc_sblk_0, 307 }, { 308 .name = "dce_1_1", .id = DSC_3, 309 .base = 0x81000, .len = 0x4, 310 .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), 311 .sblk = &dsc_sblk_1, 312 }, 313 }; 314 315 static const struct dpu_wb_cfg x1e80100_wb[] = { 316 { 317 .name = "wb_2", .id = WB_2, 318 .base = 0x65000, .len = 0x2c8, 319 .features = WB_SM8250_MASK, 320 .format_list = wb2_formats_rgb, 321 .num_formats = ARRAY_SIZE(wb2_formats_rgb), 322 .xin_id = 6, 323 .vbif_idx = VBIF_RT, 324 .maxlinewidth = 4096, 325 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 326 }, 327 }; 328 329 /* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */ 330 static const struct dpu_intf_cfg x1e80100_intf[] = { 331 { 332 .name = "intf_0", .id = INTF_0, 333 .base = 0x34000, .len = 0x280, 334 .features = INTF_SC7280_MASK, 335 .type = INTF_DP, 336 .controller_id = MSM_DP_CONTROLLER_0, 337 .prog_fetch_lines_worst_case = 24, 338 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 339 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 340 }, { 341 .name = "intf_1", .id = INTF_1, 342 .base = 0x35000, .len = 0x300, 343 .features = INTF_SC7280_MASK, 344 .type = INTF_DSI, 345 .controller_id = MSM_DSI_CONTROLLER_0, 346 .prog_fetch_lines_worst_case = 24, 347 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 348 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 349 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), 350 }, { 351 .name = "intf_2", .id = INTF_2, 352 .base = 0x36000, .len = 0x300, 353 .features = INTF_SC7280_MASK, 354 .type = INTF_DSI, 355 .controller_id = MSM_DSI_CONTROLLER_1, 356 .prog_fetch_lines_worst_case = 24, 357 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), 358 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), 359 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), 360 }, { 361 .name = "intf_3", .id = INTF_3, 362 .base = 0x37000, .len = 0x280, 363 .features = INTF_SC7280_MASK, 364 .type = INTF_NONE, 365 .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ 366 .prog_fetch_lines_worst_case = 24, 367 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), 368 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), 369 }, { 370 .name = "intf_4", .id = INTF_4, 371 .base = 0x38000, .len = 0x280, 372 .features = INTF_SC7280_MASK, 373 .type = INTF_DP, 374 .controller_id = MSM_DP_CONTROLLER_1, 375 .prog_fetch_lines_worst_case = 24, 376 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20), 377 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21), 378 }, { 379 .name = "intf_5", .id = INTF_5, 380 .base = 0x39000, .len = 0x280, 381 .features = INTF_SC7280_MASK, 382 .type = INTF_DP, 383 .controller_id = MSM_DP_CONTROLLER_3, 384 .prog_fetch_lines_worst_case = 24, 385 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22), 386 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23), 387 }, { 388 .name = "intf_6", .id = INTF_6, 389 .base = 0x3A000, .len = 0x280, 390 .features = INTF_SC7280_MASK, 391 .type = INTF_DP, 392 .controller_id = MSM_DP_CONTROLLER_2, 393 .prog_fetch_lines_worst_case = 24, 394 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16), 395 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17), 396 }, { 397 .name = "intf_7", .id = INTF_7, 398 .base = 0x3b000, .len = 0x280, 399 .features = INTF_SC7280_MASK, 400 .type = INTF_NONE, 401 .controller_id = MSM_DP_CONTROLLER_2, /* pair with intf_6 for DP MST */ 402 .prog_fetch_lines_worst_case = 24, 403 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18), 404 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19), 405 }, { 406 .name = "intf_8", .id = INTF_8, 407 .base = 0x3c000, .len = 0x280, 408 .features = INTF_SC7280_MASK, 409 .type = INTF_NONE, 410 .controller_id = MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */ 411 .prog_fetch_lines_worst_case = 24, 412 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), 413 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), 414 }, 415 }; 416 417 static const struct dpu_perf_cfg x1e80100_perf_data = { 418 .max_bw_low = 13600000, 419 .max_bw_high = 18200000, 420 .min_core_ib = 2500000, 421 .min_llcc_ib = 0, 422 .min_dram_ib = 800000, 423 .min_prefill_lines = 35, 424 /* FIXME: lut tables */ 425 .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0}, 426 .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, 427 .qos_lut_tbl = { 428 {.nentry = ARRAY_SIZE(sc7180_qos_linear), 429 .entries = sc7180_qos_linear 430 }, 431 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 432 .entries = sc7180_qos_macrotile 433 }, 434 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 435 .entries = sc7180_qos_nrt 436 }, 437 /* TODO: macrotile-qseed is different from macrotile */ 438 }, 439 .cdp_cfg = { 440 {.rd_enable = 1, .wr_enable = 1}, 441 {.rd_enable = 1, .wr_enable = 0} 442 }, 443 .clk_inefficiency_factor = 105, 444 .bw_inefficiency_factor = 120, 445 }; 446 447 static const struct dpu_mdss_version x1e80100_mdss_ver = { 448 .core_major_ver = 9, 449 .core_minor_ver = 2, 450 }; 451 452 const struct dpu_mdss_cfg dpu_x1e80100_cfg = { 453 .mdss_ver = &x1e80100_mdss_ver, 454 .caps = &x1e80100_dpu_caps, 455 .mdp = &x1e80100_mdp, 456 .ctl_count = ARRAY_SIZE(x1e80100_ctl), 457 .ctl = x1e80100_ctl, 458 .sspp_count = ARRAY_SIZE(x1e80100_sspp), 459 .sspp = x1e80100_sspp, 460 .mixer_count = ARRAY_SIZE(x1e80100_lm), 461 .mixer = x1e80100_lm, 462 .dspp_count = ARRAY_SIZE(x1e80100_dspp), 463 .dspp = x1e80100_dspp, 464 .pingpong_count = ARRAY_SIZE(x1e80100_pp), 465 .pingpong = x1e80100_pp, 466 .dsc_count = ARRAY_SIZE(x1e80100_dsc), 467 .dsc = x1e80100_dsc, 468 .merge_3d_count = ARRAY_SIZE(x1e80100_merge_3d), 469 .merge_3d = x1e80100_merge_3d, 470 .wb_count = ARRAY_SIZE(x1e80100_wb), 471 .wb = x1e80100_wb, 472 .intf_count = ARRAY_SIZE(x1e80100_intf), 473 .intf = x1e80100_intf, 474 .vbif_count = ARRAY_SIZE(sm8550_vbif), 475 .vbif = sm8550_vbif, 476 .perf = &x1e80100_perf_data, 477 }; 478 479 #endif 480