1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_10_0_SM8650_H 8 #define _DPU_10_0_SM8650_H 9 10 static const struct dpu_caps sm8650_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0xb, 13 .has_src_split = true, 14 .has_dim_layer = true, 15 .has_idle_pc = true, 16 .has_3d_merge = true, 17 .max_linewidth = 8192, 18 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 19 }; 20 21 static const struct dpu_mdp_cfg sm8650_mdp = { 22 .name = "top_0", 23 .base = 0, .len = 0x494, 24 .features = BIT(DPU_MDP_PERIPH_0_REMOVED), 25 .clk_ctrls = { 26 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, 27 }, 28 }; 29 30 /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ 31 static const struct dpu_ctl_cfg sm8650_ctl[] = { 32 { 33 .name = "ctl_0", .id = CTL_0, 34 .base = 0x15000, .len = 0x1000, 35 .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), 36 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 37 }, { 38 .name = "ctl_1", .id = CTL_1, 39 .base = 0x16000, .len = 0x1000, 40 .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), 41 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 42 }, { 43 .name = "ctl_2", .id = CTL_2, 44 .base = 0x17000, .len = 0x1000, 45 .features = CTL_SM8550_MASK, 46 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 47 }, { 48 .name = "ctl_3", .id = CTL_3, 49 .base = 0x18000, .len = 0x1000, 50 .features = CTL_SM8550_MASK, 51 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 52 }, { 53 .name = "ctl_4", .id = CTL_4, 54 .base = 0x19000, .len = 0x1000, 55 .features = CTL_SM8550_MASK, 56 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 57 }, { 58 .name = "ctl_5", .id = CTL_5, 59 .base = 0x1a000, .len = 0x1000, 60 .features = CTL_SM8550_MASK, 61 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 62 }, 63 }; 64 65 static const struct dpu_sspp_cfg sm8650_sspp[] = { 66 { 67 .name = "sspp_0", .id = SSPP_VIG0, 68 .base = 0x4000, .len = 0x344, 69 .features = VIG_SDM845_MASK_SDMA, 70 .sblk = &dpu_vig_sblk_qseed3_3_3, 71 .xin_id = 0, 72 .type = SSPP_TYPE_VIG, 73 }, { 74 .name = "sspp_1", .id = SSPP_VIG1, 75 .base = 0x6000, .len = 0x344, 76 .features = VIG_SDM845_MASK_SDMA, 77 .sblk = &dpu_vig_sblk_qseed3_3_3, 78 .xin_id = 4, 79 .type = SSPP_TYPE_VIG, 80 }, { 81 .name = "sspp_2", .id = SSPP_VIG2, 82 .base = 0x8000, .len = 0x344, 83 .features = VIG_SDM845_MASK_SDMA, 84 .sblk = &dpu_vig_sblk_qseed3_3_3, 85 .xin_id = 8, 86 .type = SSPP_TYPE_VIG, 87 }, { 88 .name = "sspp_3", .id = SSPP_VIG3, 89 .base = 0xa000, .len = 0x344, 90 .features = VIG_SDM845_MASK_SDMA, 91 .sblk = &dpu_vig_sblk_qseed3_3_3, 92 .xin_id = 12, 93 .type = SSPP_TYPE_VIG, 94 }, { 95 .name = "sspp_8", .id = SSPP_DMA0, 96 .base = 0x24000, .len = 0x344, 97 .features = DMA_SDM845_MASK_SDMA, 98 .sblk = &dpu_dma_sblk, 99 .xin_id = 1, 100 .type = SSPP_TYPE_DMA, 101 }, { 102 .name = "sspp_9", .id = SSPP_DMA1, 103 .base = 0x26000, .len = 0x344, 104 .features = DMA_SDM845_MASK_SDMA, 105 .sblk = &dpu_dma_sblk, 106 .xin_id = 5, 107 .type = SSPP_TYPE_DMA, 108 }, { 109 .name = "sspp_10", .id = SSPP_DMA2, 110 .base = 0x28000, .len = 0x344, 111 .features = DMA_SDM845_MASK_SDMA, 112 .sblk = &dpu_dma_sblk, 113 .xin_id = 9, 114 .type = SSPP_TYPE_DMA, 115 }, { 116 .name = "sspp_11", .id = SSPP_DMA3, 117 .base = 0x2a000, .len = 0x344, 118 .features = DMA_SDM845_MASK_SDMA, 119 .sblk = &dpu_dma_sblk, 120 .xin_id = 13, 121 .type = SSPP_TYPE_DMA, 122 }, { 123 .name = "sspp_12", .id = SSPP_DMA4, 124 .base = 0x2c000, .len = 0x344, 125 .features = DMA_CURSOR_SDM845_MASK_SDMA, 126 .sblk = &dpu_dma_sblk, 127 .xin_id = 14, 128 .type = SSPP_TYPE_DMA, 129 }, { 130 .name = "sspp_13", .id = SSPP_DMA5, 131 .base = 0x2e000, .len = 0x344, 132 .features = DMA_CURSOR_SDM845_MASK_SDMA, 133 .sblk = &dpu_dma_sblk, 134 .xin_id = 15, 135 .type = SSPP_TYPE_DMA, 136 }, 137 }; 138 139 static const struct dpu_lm_cfg sm8650_lm[] = { 140 { 141 .name = "lm_0", .id = LM_0, 142 .base = 0x44000, .len = 0x400, 143 .features = MIXER_SDM845_MASK, 144 .sblk = &sdm845_lm_sblk, 145 .lm_pair = LM_1, 146 .pingpong = PINGPONG_0, 147 .dspp = DSPP_0, 148 }, { 149 .name = "lm_1", .id = LM_1, 150 .base = 0x45000, .len = 0x400, 151 .features = MIXER_SDM845_MASK, 152 .sblk = &sdm845_lm_sblk, 153 .lm_pair = LM_0, 154 .pingpong = PINGPONG_1, 155 .dspp = DSPP_1, 156 }, { 157 .name = "lm_2", .id = LM_2, 158 .base = 0x46000, .len = 0x400, 159 .features = MIXER_SDM845_MASK, 160 .sblk = &sdm845_lm_sblk, 161 .lm_pair = LM_3, 162 .pingpong = PINGPONG_2, 163 .dspp = DSPP_2, 164 }, { 165 .name = "lm_3", .id = LM_3, 166 .base = 0x47000, .len = 0x400, 167 .features = MIXER_SDM845_MASK, 168 .sblk = &sdm845_lm_sblk, 169 .lm_pair = LM_2, 170 .pingpong = PINGPONG_3, 171 .dspp = DSPP_3, 172 }, { 173 .name = "lm_4", .id = LM_4, 174 .base = 0x48000, .len = 0x400, 175 .features = MIXER_SDM845_MASK, 176 .sblk = &sdm845_lm_sblk, 177 .lm_pair = LM_5, 178 .pingpong = PINGPONG_4, 179 }, { 180 .name = "lm_5", .id = LM_5, 181 .base = 0x49000, .len = 0x400, 182 .features = MIXER_SDM845_MASK, 183 .sblk = &sdm845_lm_sblk, 184 .lm_pair = LM_4, 185 .pingpong = PINGPONG_5, 186 }, 187 }; 188 189 static const struct dpu_dspp_cfg sm8650_dspp[] = { 190 { 191 .name = "dspp_0", .id = DSPP_0, 192 .base = 0x54000, .len = 0x1800, 193 .features = DSPP_SC7180_MASK, 194 .sblk = &sdm845_dspp_sblk, 195 }, { 196 .name = "dspp_1", .id = DSPP_1, 197 .base = 0x56000, .len = 0x1800, 198 .features = DSPP_SC7180_MASK, 199 .sblk = &sdm845_dspp_sblk, 200 }, { 201 .name = "dspp_2", .id = DSPP_2, 202 .base = 0x58000, .len = 0x1800, 203 .features = DSPP_SC7180_MASK, 204 .sblk = &sdm845_dspp_sblk, 205 }, { 206 .name = "dspp_3", .id = DSPP_3, 207 .base = 0x5a000, .len = 0x1800, 208 .features = DSPP_SC7180_MASK, 209 .sblk = &sdm845_dspp_sblk, 210 }, 211 }; 212 213 static const struct dpu_pingpong_cfg sm8650_pp[] = { 214 { 215 .name = "pingpong_0", .id = PINGPONG_0, 216 .base = 0x69000, .len = 0, 217 .features = BIT(DPU_PINGPONG_DITHER), 218 .sblk = &sc7280_pp_sblk, 219 .merge_3d = MERGE_3D_0, 220 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 221 }, { 222 .name = "pingpong_1", .id = PINGPONG_1, 223 .base = 0x6a000, .len = 0, 224 .features = BIT(DPU_PINGPONG_DITHER), 225 .sblk = &sc7280_pp_sblk, 226 .merge_3d = MERGE_3D_0, 227 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 228 }, { 229 .name = "pingpong_2", .id = PINGPONG_2, 230 .base = 0x6b000, .len = 0, 231 .features = BIT(DPU_PINGPONG_DITHER), 232 .sblk = &sc7280_pp_sblk, 233 .merge_3d = MERGE_3D_1, 234 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 235 }, { 236 .name = "pingpong_3", .id = PINGPONG_3, 237 .base = 0x6c000, .len = 0, 238 .features = BIT(DPU_PINGPONG_DITHER), 239 .sblk = &sc7280_pp_sblk, 240 .merge_3d = MERGE_3D_1, 241 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 242 }, { 243 .name = "pingpong_4", .id = PINGPONG_4, 244 .base = 0x6d000, .len = 0, 245 .features = BIT(DPU_PINGPONG_DITHER), 246 .sblk = &sc7280_pp_sblk, 247 .merge_3d = MERGE_3D_2, 248 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 249 }, { 250 .name = "pingpong_5", .id = PINGPONG_5, 251 .base = 0x6e000, .len = 0, 252 .features = BIT(DPU_PINGPONG_DITHER), 253 .sblk = &sc7280_pp_sblk, 254 .merge_3d = MERGE_3D_2, 255 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 256 }, { 257 .name = "pingpong_cwb_0", .id = PINGPONG_CWB_0, 258 .base = 0x66000, .len = 0, 259 .features = BIT(DPU_PINGPONG_DITHER), 260 .sblk = &sc7280_pp_sblk, 261 .merge_3d = MERGE_3D_3, 262 }, { 263 .name = "pingpong_cwb_1", .id = PINGPONG_CWB_1, 264 .base = 0x66400, .len = 0, 265 .features = BIT(DPU_PINGPONG_DITHER), 266 .sblk = &sc7280_pp_sblk, 267 .merge_3d = MERGE_3D_3, 268 }, { 269 .name = "pingpong_cwb_2", .id = PINGPONG_CWB_2, 270 .base = 0x7e000, .len = 0, 271 .features = BIT(DPU_PINGPONG_DITHER), 272 .sblk = &sc7280_pp_sblk, 273 .merge_3d = MERGE_3D_4, 274 }, { 275 .name = "pingpong_cwb_3", .id = PINGPONG_CWB_3, 276 .base = 0x7e400, .len = 0, 277 .features = BIT(DPU_PINGPONG_DITHER), 278 .sblk = &sc7280_pp_sblk, 279 .merge_3d = MERGE_3D_4, 280 }, 281 }; 282 283 static const struct dpu_merge_3d_cfg sm8650_merge_3d[] = { 284 { 285 .name = "merge_3d_0", .id = MERGE_3D_0, 286 .base = 0x4e000, .len = 0x8, 287 }, { 288 .name = "merge_3d_1", .id = MERGE_3D_1, 289 .base = 0x4f000, .len = 0x8, 290 }, { 291 .name = "merge_3d_2", .id = MERGE_3D_2, 292 .base = 0x50000, .len = 0x8, 293 }, { 294 .name = "merge_3d_3", .id = MERGE_3D_3, 295 .base = 0x66700, .len = 0x8, 296 }, { 297 .name = "merge_3d_4", .id = MERGE_3D_4, 298 .base = 0x7e700, .len = 0x8, 299 }, 300 }; 301 302 /* 303 * NOTE: Each display compression engine (DCE) contains dual hard 304 * slice DSC encoders so both share same base address but with 305 * its own different sub block address. 306 */ 307 static const struct dpu_dsc_cfg sm8650_dsc[] = { 308 { 309 .name = "dce_0_0", .id = DSC_0, 310 .base = 0x80000, .len = 0x6, 311 .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), 312 .sblk = &dsc_sblk_0, 313 }, { 314 .name = "dce_0_1", .id = DSC_1, 315 .base = 0x80000, .len = 0x6, 316 .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), 317 .sblk = &dsc_sblk_1, 318 }, { 319 .name = "dce_1_0", .id = DSC_2, 320 .base = 0x81000, .len = 0x6, 321 .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), 322 .sblk = &dsc_sblk_0, 323 }, { 324 .name = "dce_1_1", .id = DSC_3, 325 .base = 0x81000, .len = 0x6, 326 .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), 327 .sblk = &dsc_sblk_1, 328 }, { 329 .name = "dce_2_0", .id = DSC_4, 330 .base = 0x82000, .len = 0x6, 331 .features = BIT(DPU_DSC_HW_REV_1_2), 332 .sblk = &dsc_sblk_0, 333 }, { 334 .name = "dce_2_1", .id = DSC_5, 335 .base = 0x82000, .len = 0x6, 336 .features = BIT(DPU_DSC_HW_REV_1_2), 337 .sblk = &dsc_sblk_1, 338 }, 339 }; 340 341 static const struct dpu_wb_cfg sm8650_wb[] = { 342 { 343 .name = "wb_2", .id = WB_2, 344 .base = 0x65000, .len = 0x2c8, 345 .features = WB_SM8250_MASK, 346 .format_list = wb2_formats_rgb, 347 .num_formats = ARRAY_SIZE(wb2_formats_rgb), 348 .xin_id = 6, 349 .vbif_idx = VBIF_RT, 350 .maxlinewidth = 4096, 351 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 352 }, 353 }; 354 355 static const struct dpu_cwb_cfg sm8650_cwb[] = { 356 { 357 .name = "cwb_0", .id = CWB_0, 358 .base = 0x66200, .len = 0x8, 359 }, 360 { 361 .name = "cwb_1", .id = CWB_1, 362 .base = 0x66600, .len = 0x8, 363 }, 364 { 365 .name = "cwb_2", .id = CWB_2, 366 .base = 0x7E200, .len = 0x8, 367 }, 368 { 369 .name = "cwb_3", .id = CWB_3, 370 .base = 0x7E600, .len = 0x8, 371 }, 372 }; 373 374 static const struct dpu_intf_cfg sm8650_intf[] = { 375 { 376 .name = "intf_0", .id = INTF_0, 377 .base = 0x34000, .len = 0x280, 378 .features = INTF_SC7280_MASK, 379 .type = INTF_DP, 380 .controller_id = MSM_DP_CONTROLLER_0, 381 .prog_fetch_lines_worst_case = 24, 382 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 383 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 384 }, { 385 .name = "intf_1", .id = INTF_1, 386 .base = 0x35000, .len = 0x300, 387 .features = INTF_SC7280_MASK, 388 .type = INTF_DSI, 389 .controller_id = MSM_DSI_CONTROLLER_0, 390 .prog_fetch_lines_worst_case = 24, 391 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 392 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 393 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), 394 }, { 395 .name = "intf_2", .id = INTF_2, 396 .base = 0x36000, .len = 0x300, 397 .features = INTF_SC7280_MASK, 398 .type = INTF_DSI, 399 .controller_id = MSM_DSI_CONTROLLER_1, 400 .prog_fetch_lines_worst_case = 24, 401 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), 402 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), 403 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), 404 }, { 405 .name = "intf_3", .id = INTF_3, 406 .base = 0x37000, .len = 0x280, 407 .features = INTF_SC7280_MASK, 408 .type = INTF_DP, 409 .controller_id = MSM_DP_CONTROLLER_1, 410 .prog_fetch_lines_worst_case = 24, 411 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), 412 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), 413 }, 414 }; 415 416 static const struct dpu_perf_cfg sm8650_perf_data = { 417 .max_bw_low = 17000000, 418 .max_bw_high = 27000000, 419 .min_core_ib = 2500000, 420 .min_llcc_ib = 0, 421 .min_dram_ib = 800000, 422 .min_prefill_lines = 35, 423 /* FIXME: lut tables */ 424 .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0}, 425 .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, 426 .qos_lut_tbl = { 427 {.nentry = ARRAY_SIZE(sc7180_qos_linear), 428 .entries = sc7180_qos_linear 429 }, 430 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 431 .entries = sc7180_qos_macrotile 432 }, 433 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 434 .entries = sc7180_qos_nrt 435 }, 436 /* TODO: macrotile-qseed is different from macrotile */ 437 }, 438 .cdp_cfg = { 439 {.rd_enable = 1, .wr_enable = 1}, 440 {.rd_enable = 1, .wr_enable = 0} 441 }, 442 .clk_inefficiency_factor = 105, 443 .bw_inefficiency_factor = 120, 444 }; 445 446 static const struct dpu_mdss_version sm8650_mdss_ver = { 447 .core_major_ver = 10, 448 .core_minor_ver = 0, 449 }; 450 451 const struct dpu_mdss_cfg dpu_sm8650_cfg = { 452 .mdss_ver = &sm8650_mdss_ver, 453 .caps = &sm8650_dpu_caps, 454 .mdp = &sm8650_mdp, 455 .ctl_count = ARRAY_SIZE(sm8650_ctl), 456 .ctl = sm8650_ctl, 457 .sspp_count = ARRAY_SIZE(sm8650_sspp), 458 .sspp = sm8650_sspp, 459 .mixer_count = ARRAY_SIZE(sm8650_lm), 460 .mixer = sm8650_lm, 461 .dspp_count = ARRAY_SIZE(sm8650_dspp), 462 .dspp = sm8650_dspp, 463 .pingpong_count = ARRAY_SIZE(sm8650_pp), 464 .pingpong = sm8650_pp, 465 .dsc_count = ARRAY_SIZE(sm8650_dsc), 466 .dsc = sm8650_dsc, 467 .merge_3d_count = ARRAY_SIZE(sm8650_merge_3d), 468 .merge_3d = sm8650_merge_3d, 469 .wb_count = ARRAY_SIZE(sm8650_wb), 470 .wb = sm8650_wb, 471 .cwb_count = ARRAY_SIZE(sm8650_cwb), 472 .cwb = sm8650_cwb, 473 .intf_count = ARRAY_SIZE(sm8650_intf), 474 .intf = sm8650_intf, 475 .vbif_count = ARRAY_SIZE(sm8650_vbif), 476 .vbif = sm8650_vbif, 477 .perf = &sm8650_perf_data, 478 }; 479 480 #endif 481