1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_9_0_SM8550_H 8 #define _DPU_9_0_SM8550_H 9 10 static const struct dpu_caps sm8550_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0xb, 13 .has_src_split = true, 14 .has_dim_layer = true, 15 .has_idle_pc = true, 16 .has_3d_merge = true, 17 .max_linewidth = 5120, 18 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 19 }; 20 21 static const struct dpu_mdp_cfg sm8550_mdp = { 22 .name = "top_0", 23 .base = 0, .len = 0x494, 24 .features = BIT(DPU_MDP_PERIPH_0_REMOVED), 25 .clk_ctrls = { 26 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, 27 }, 28 }; 29 30 /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ 31 static const struct dpu_ctl_cfg sm8550_ctl[] = { 32 { 33 .name = "ctl_0", .id = CTL_0, 34 .base = 0x15000, .len = 0x290, 35 .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), 36 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 37 }, { 38 .name = "ctl_1", .id = CTL_1, 39 .base = 0x16000, .len = 0x290, 40 .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), 41 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 42 }, { 43 .name = "ctl_2", .id = CTL_2, 44 .base = 0x17000, .len = 0x290, 45 .features = CTL_SM8550_MASK, 46 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 47 }, { 48 .name = "ctl_3", .id = CTL_3, 49 .base = 0x18000, .len = 0x290, 50 .features = CTL_SM8550_MASK, 51 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 52 }, { 53 .name = "ctl_4", .id = CTL_4, 54 .base = 0x19000, .len = 0x290, 55 .features = CTL_SM8550_MASK, 56 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 57 }, { 58 .name = "ctl_5", .id = CTL_5, 59 .base = 0x1a000, .len = 0x290, 60 .features = CTL_SM8550_MASK, 61 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 62 }, 63 }; 64 65 static const struct dpu_sspp_cfg sm8550_sspp[] = { 66 { 67 .name = "sspp_0", .id = SSPP_VIG0, 68 .base = 0x4000, .len = 0x344, 69 .features = VIG_SDM845_MASK, 70 .sblk = &dpu_vig_sblk_qseed3_3_2, 71 .xin_id = 0, 72 .type = SSPP_TYPE_VIG, 73 }, { 74 .name = "sspp_1", .id = SSPP_VIG1, 75 .base = 0x6000, .len = 0x344, 76 .features = VIG_SDM845_MASK, 77 .sblk = &dpu_vig_sblk_qseed3_3_2, 78 .xin_id = 4, 79 .type = SSPP_TYPE_VIG, 80 }, { 81 .name = "sspp_2", .id = SSPP_VIG2, 82 .base = 0x8000, .len = 0x344, 83 .features = VIG_SDM845_MASK, 84 .sblk = &dpu_vig_sblk_qseed3_3_2, 85 .xin_id = 8, 86 .type = SSPP_TYPE_VIG, 87 }, { 88 .name = "sspp_3", .id = SSPP_VIG3, 89 .base = 0xa000, .len = 0x344, 90 .features = VIG_SDM845_MASK, 91 .sblk = &dpu_vig_sblk_qseed3_3_2, 92 .xin_id = 12, 93 .type = SSPP_TYPE_VIG, 94 }, { 95 .name = "sspp_8", .id = SSPP_DMA0, 96 .base = 0x24000, .len = 0x344, 97 .features = DMA_SDM845_MASK, 98 .sblk = &dpu_dma_sblk, 99 .xin_id = 1, 100 .type = SSPP_TYPE_DMA, 101 }, { 102 .name = "sspp_9", .id = SSPP_DMA1, 103 .base = 0x26000, .len = 0x344, 104 .features = DMA_SDM845_MASK, 105 .sblk = &dpu_dma_sblk, 106 .xin_id = 5, 107 .type = SSPP_TYPE_DMA, 108 }, { 109 .name = "sspp_10", .id = SSPP_DMA2, 110 .base = 0x28000, .len = 0x344, 111 .features = DMA_SDM845_MASK, 112 .sblk = &dpu_dma_sblk, 113 .xin_id = 9, 114 .type = SSPP_TYPE_DMA, 115 }, { 116 .name = "sspp_11", .id = SSPP_DMA3, 117 .base = 0x2a000, .len = 0x344, 118 .features = DMA_SDM845_MASK, 119 .sblk = &dpu_dma_sblk, 120 .xin_id = 13, 121 .type = SSPP_TYPE_DMA, 122 }, { 123 .name = "sspp_12", .id = SSPP_DMA4, 124 .base = 0x2c000, .len = 0x344, 125 .features = DMA_CURSOR_SDM845_MASK, 126 .sblk = &dpu_dma_sblk, 127 .xin_id = 14, 128 .type = SSPP_TYPE_DMA, 129 }, { 130 .name = "sspp_13", .id = SSPP_DMA5, 131 .base = 0x2e000, .len = 0x344, 132 .features = DMA_CURSOR_SDM845_MASK, 133 .sblk = &dpu_dma_sblk, 134 .xin_id = 15, 135 .type = SSPP_TYPE_DMA, 136 }, 137 }; 138 139 static const struct dpu_lm_cfg sm8550_lm[] = { 140 { 141 .name = "lm_0", .id = LM_0, 142 .base = 0x44000, .len = 0x320, 143 .features = MIXER_SDM845_MASK, 144 .sblk = &sdm845_lm_sblk, 145 .lm_pair = LM_1, 146 .pingpong = PINGPONG_0, 147 .dspp = DSPP_0, 148 }, { 149 .name = "lm_1", .id = LM_1, 150 .base = 0x45000, .len = 0x320, 151 .features = MIXER_SDM845_MASK, 152 .sblk = &sdm845_lm_sblk, 153 .lm_pair = LM_0, 154 .pingpong = PINGPONG_1, 155 .dspp = DSPP_1, 156 }, { 157 .name = "lm_2", .id = LM_2, 158 .base = 0x46000, .len = 0x320, 159 .features = MIXER_SDM845_MASK, 160 .sblk = &sdm845_lm_sblk, 161 .lm_pair = LM_3, 162 .pingpong = PINGPONG_2, 163 }, { 164 .name = "lm_3", .id = LM_3, 165 .base = 0x47000, .len = 0x320, 166 .features = MIXER_SDM845_MASK, 167 .sblk = &sdm845_lm_sblk, 168 .lm_pair = LM_2, 169 .pingpong = PINGPONG_3, 170 }, { 171 .name = "lm_4", .id = LM_4, 172 .base = 0x48000, .len = 0x320, 173 .features = MIXER_SDM845_MASK, 174 .sblk = &sdm845_lm_sblk, 175 .lm_pair = LM_5, 176 .pingpong = PINGPONG_4, 177 }, { 178 .name = "lm_5", .id = LM_5, 179 .base = 0x49000, .len = 0x320, 180 .features = MIXER_SDM845_MASK, 181 .sblk = &sdm845_lm_sblk, 182 .lm_pair = LM_4, 183 .pingpong = PINGPONG_5, 184 }, 185 }; 186 187 static const struct dpu_dspp_cfg sm8550_dspp[] = { 188 { 189 .name = "dspp_0", .id = DSPP_0, 190 .base = 0x54000, .len = 0x1800, 191 .features = DSPP_SC7180_MASK, 192 .sblk = &sdm845_dspp_sblk, 193 }, { 194 .name = "dspp_1", .id = DSPP_1, 195 .base = 0x56000, .len = 0x1800, 196 .features = DSPP_SC7180_MASK, 197 .sblk = &sdm845_dspp_sblk, 198 }, { 199 .name = "dspp_2", .id = DSPP_2, 200 .base = 0x58000, .len = 0x1800, 201 .features = DSPP_SC7180_MASK, 202 .sblk = &sdm845_dspp_sblk, 203 }, { 204 .name = "dspp_3", .id = DSPP_3, 205 .base = 0x5a000, .len = 0x1800, 206 .features = DSPP_SC7180_MASK, 207 .sblk = &sdm845_dspp_sblk, 208 }, 209 }; 210 static const struct dpu_pingpong_cfg sm8550_pp[] = { 211 { 212 .name = "pingpong_0", .id = PINGPONG_0, 213 .base = 0x69000, .len = 0, 214 .features = BIT(DPU_PINGPONG_DITHER), 215 .sblk = &sc7280_pp_sblk, 216 .merge_3d = MERGE_3D_0, 217 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 218 }, { 219 .name = "pingpong_1", .id = PINGPONG_1, 220 .base = 0x6a000, .len = 0, 221 .features = BIT(DPU_PINGPONG_DITHER), 222 .sblk = &sc7280_pp_sblk, 223 .merge_3d = MERGE_3D_0, 224 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 225 }, { 226 .name = "pingpong_2", .id = PINGPONG_2, 227 .base = 0x6b000, .len = 0, 228 .features = BIT(DPU_PINGPONG_DITHER), 229 .sblk = &sc7280_pp_sblk, 230 .merge_3d = MERGE_3D_1, 231 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 232 }, { 233 .name = "pingpong_3", .id = PINGPONG_3, 234 .base = 0x6c000, .len = 0, 235 .features = BIT(DPU_PINGPONG_DITHER), 236 .sblk = &sc7280_pp_sblk, 237 .merge_3d = MERGE_3D_1, 238 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 239 }, { 240 .name = "pingpong_4", .id = PINGPONG_4, 241 .base = 0x6d000, .len = 0, 242 .features = BIT(DPU_PINGPONG_DITHER), 243 .sblk = &sc7280_pp_sblk, 244 .merge_3d = MERGE_3D_2, 245 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 246 }, { 247 .name = "pingpong_5", .id = PINGPONG_5, 248 .base = 0x6e000, .len = 0, 249 .features = BIT(DPU_PINGPONG_DITHER), 250 .sblk = &sc7280_pp_sblk, 251 .merge_3d = MERGE_3D_2, 252 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 253 }, { 254 .name = "pingpong_6", .id = PINGPONG_6, 255 .base = 0x66000, .len = 0, 256 .features = BIT(DPU_PINGPONG_DITHER), 257 .sblk = &sc7280_pp_sblk, 258 .merge_3d = MERGE_3D_3, 259 }, { 260 .name = "pingpong_7", .id = PINGPONG_7, 261 .base = 0x66400, .len = 0, 262 .features = BIT(DPU_PINGPONG_DITHER), 263 .sblk = &sc7280_pp_sblk, 264 .merge_3d = MERGE_3D_3, 265 }, 266 }; 267 268 static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = { 269 { 270 .name = "merge_3d_0", .id = MERGE_3D_0, 271 .base = 0x4e000, .len = 0x8, 272 }, { 273 .name = "merge_3d_1", .id = MERGE_3D_1, 274 .base = 0x4f000, .len = 0x8, 275 }, { 276 .name = "merge_3d_2", .id = MERGE_3D_2, 277 .base = 0x50000, .len = 0x8, 278 }, { 279 .name = "merge_3d_3", .id = MERGE_3D_3, 280 .base = 0x66700, .len = 0x8, 281 }, 282 }; 283 284 /* 285 * NOTE: Each display compression engine (DCE) contains dual hard 286 * slice DSC encoders so both share same base address but with 287 * its own different sub block address. 288 */ 289 static const struct dpu_dsc_cfg sm8550_dsc[] = { 290 { 291 .name = "dce_0_0", .id = DSC_0, 292 .base = 0x80000, .len = 0x4, 293 .features = BIT(DPU_DSC_HW_REV_1_2), 294 .sblk = &dsc_sblk_0, 295 }, { 296 .name = "dce_0_1", .id = DSC_1, 297 .base = 0x80000, .len = 0x4, 298 .features = BIT(DPU_DSC_HW_REV_1_2), 299 .sblk = &dsc_sblk_1, 300 }, { 301 .name = "dce_1_0", .id = DSC_2, 302 .base = 0x81000, .len = 0x4, 303 .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), 304 .sblk = &dsc_sblk_0, 305 }, { 306 .name = "dce_1_1", .id = DSC_3, 307 .base = 0x81000, .len = 0x4, 308 .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), 309 .sblk = &dsc_sblk_1, 310 }, 311 }; 312 313 static const struct dpu_wb_cfg sm8550_wb[] = { 314 { 315 .name = "wb_2", .id = WB_2, 316 .base = 0x65000, .len = 0x2c8, 317 .features = WB_SM8250_MASK, 318 .format_list = wb2_formats_rgb, 319 .num_formats = ARRAY_SIZE(wb2_formats_rgb), 320 .xin_id = 6, 321 .vbif_idx = VBIF_RT, 322 .maxlinewidth = 4096, 323 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 324 }, 325 }; 326 327 static const struct dpu_intf_cfg sm8550_intf[] = { 328 { 329 .name = "intf_0", .id = INTF_0, 330 .base = 0x34000, .len = 0x280, 331 .features = INTF_SC7280_MASK, 332 .type = INTF_DP, 333 .controller_id = MSM_DP_CONTROLLER_0, 334 .prog_fetch_lines_worst_case = 24, 335 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 336 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 337 }, { 338 .name = "intf_1", .id = INTF_1, 339 .base = 0x35000, .len = 0x300, 340 .features = INTF_SC7280_MASK, 341 .type = INTF_DSI, 342 .controller_id = MSM_DSI_CONTROLLER_0, 343 .prog_fetch_lines_worst_case = 24, 344 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 345 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 346 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), 347 }, { 348 .name = "intf_2", .id = INTF_2, 349 .base = 0x36000, .len = 0x300, 350 .features = INTF_SC7280_MASK, 351 .type = INTF_DSI, 352 .controller_id = MSM_DSI_CONTROLLER_1, 353 .prog_fetch_lines_worst_case = 24, 354 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), 355 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), 356 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), 357 }, { 358 .name = "intf_3", .id = INTF_3, 359 .base = 0x37000, .len = 0x280, 360 .features = INTF_SC7280_MASK, 361 .type = INTF_DP, 362 .controller_id = MSM_DP_CONTROLLER_1, 363 .prog_fetch_lines_worst_case = 24, 364 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), 365 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), 366 }, 367 }; 368 369 static const struct dpu_perf_cfg sm8550_perf_data = { 370 .max_bw_low = 13600000, 371 .max_bw_high = 18200000, 372 .min_core_ib = 2500000, 373 .min_llcc_ib = 0, 374 .min_dram_ib = 800000, 375 .min_prefill_lines = 35, 376 /* FIXME: lut tables */ 377 .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0}, 378 .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, 379 .qos_lut_tbl = { 380 {.nentry = ARRAY_SIZE(sc7180_qos_linear), 381 .entries = sc7180_qos_linear 382 }, 383 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 384 .entries = sc7180_qos_macrotile 385 }, 386 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 387 .entries = sc7180_qos_nrt 388 }, 389 /* TODO: macrotile-qseed is different from macrotile */ 390 }, 391 .cdp_cfg = { 392 {.rd_enable = 1, .wr_enable = 1}, 393 {.rd_enable = 1, .wr_enable = 0} 394 }, 395 .clk_inefficiency_factor = 105, 396 .bw_inefficiency_factor = 120, 397 }; 398 399 static const struct dpu_mdss_version sm8550_mdss_ver = { 400 .core_major_ver = 9, 401 .core_minor_ver = 0, 402 }; 403 404 const struct dpu_mdss_cfg dpu_sm8550_cfg = { 405 .mdss_ver = &sm8550_mdss_ver, 406 .caps = &sm8550_dpu_caps, 407 .mdp = &sm8550_mdp, 408 .ctl_count = ARRAY_SIZE(sm8550_ctl), 409 .ctl = sm8550_ctl, 410 .sspp_count = ARRAY_SIZE(sm8550_sspp), 411 .sspp = sm8550_sspp, 412 .mixer_count = ARRAY_SIZE(sm8550_lm), 413 .mixer = sm8550_lm, 414 .dspp_count = ARRAY_SIZE(sm8550_dspp), 415 .dspp = sm8550_dspp, 416 .pingpong_count = ARRAY_SIZE(sm8550_pp), 417 .pingpong = sm8550_pp, 418 .dsc_count = ARRAY_SIZE(sm8550_dsc), 419 .dsc = sm8550_dsc, 420 .merge_3d_count = ARRAY_SIZE(sm8550_merge_3d), 421 .merge_3d = sm8550_merge_3d, 422 .wb_count = ARRAY_SIZE(sm8550_wb), 423 .wb = sm8550_wb, 424 .intf_count = ARRAY_SIZE(sm8550_intf), 425 .intf = sm8550_intf, 426 .vbif_count = ARRAY_SIZE(sm8550_vbif), 427 .vbif = sm8550_vbif, 428 .perf = &sm8550_perf_data, 429 }; 430 431 #endif 432