1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com> 5 */ 6 7 #ifndef _DPU_5_2_SM7150_H 8 #define _DPU_5_2_SM7150_H 9 10 static const struct dpu_caps sm7150_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0xb, 13 .has_src_split = true, 14 .has_dim_layer = true, 15 .has_idle_pc = true, 16 .has_3d_merge = true, 17 .max_linewidth = 2880, 18 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 19 .max_hdeci_exp = MAX_HORZ_DECIMATION, 20 .max_vdeci_exp = MAX_VERT_DECIMATION, 21 }; 22 23 static const struct dpu_mdp_cfg sm7150_mdp = { 24 .name = "top_0", 25 .base = 0x0, .len = 0x45c, 26 .features = BIT(DPU_MDP_AUDIO_SELECT), 27 .clk_ctrls = { 28 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 29 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 30 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 31 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 32 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, 33 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 }, 34 }, 35 }; 36 37 static const struct dpu_ctl_cfg sm7150_ctl[] = { 38 { 39 .name = "ctl_0", .id = CTL_0, 40 .base = 0x1000, .len = 0x1e0, 41 .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), 42 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 43 }, { 44 .name = "ctl_1", .id = CTL_1, 45 .base = 0x1200, .len = 0x1e0, 46 .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), 47 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 48 }, { 49 .name = "ctl_2", .id = CTL_2, 50 .base = 0x1400, .len = 0x1e0, 51 .features = BIT(DPU_CTL_ACTIVE_CFG), 52 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 53 }, { 54 .name = "ctl_3", .id = CTL_3, 55 .base = 0x1600, .len = 0x1e0, 56 .features = BIT(DPU_CTL_ACTIVE_CFG), 57 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 58 }, { 59 .name = "ctl_4", .id = CTL_4, 60 .base = 0x1800, .len = 0x1e0, 61 .features = BIT(DPU_CTL_ACTIVE_CFG), 62 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 63 }, { 64 .name = "ctl_5", .id = CTL_5, 65 .base = 0x1a00, .len = 0x1e0, 66 .features = BIT(DPU_CTL_ACTIVE_CFG), 67 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 68 }, 69 }; 70 71 static const struct dpu_sspp_cfg sm7150_sspp[] = { 72 { 73 .name = "sspp_0", .id = SSPP_VIG0, 74 .base = 0x4000, .len = 0x1f0, 75 .features = VIG_SDM845_MASK, 76 .sblk = &dpu_vig_sblk_qseed3_2_4, 77 .xin_id = 0, 78 .type = SSPP_TYPE_VIG, 79 .clk_ctrl = DPU_CLK_CTRL_VIG0, 80 }, { 81 .name = "sspp_1", .id = SSPP_VIG1, 82 .base = 0x6000, .len = 0x1f0, 83 .features = VIG_SDM845_MASK, 84 .sblk = &dpu_vig_sblk_qseed3_2_4, 85 .xin_id = 4, 86 .type = SSPP_TYPE_VIG, 87 .clk_ctrl = DPU_CLK_CTRL_VIG1, 88 }, { 89 .name = "sspp_2", .id = SSPP_DMA0, 90 .base = 0x24000, .len = 0x1f0, 91 .features = DMA_SDM845_MASK, 92 .sblk = &dpu_dma_sblk, 93 .xin_id = 1, 94 .type = SSPP_TYPE_DMA, 95 .clk_ctrl = DPU_CLK_CTRL_DMA0, 96 }, { 97 .name = "sspp_9", .id = SSPP_DMA1, 98 .base = 0x26000, .len = 0x1f0, 99 .features = DMA_SDM845_MASK, 100 .sblk = &dpu_dma_sblk, 101 .xin_id = 5, 102 .type = SSPP_TYPE_DMA, 103 .clk_ctrl = DPU_CLK_CTRL_DMA1, 104 }, { 105 .name = "sspp_10", .id = SSPP_DMA2, 106 .base = 0x28000, .len = 0x1f0, 107 .features = DMA_CURSOR_SDM845_MASK, 108 .sblk = &dpu_dma_sblk, 109 .xin_id = 9, 110 .type = SSPP_TYPE_DMA, 111 .clk_ctrl = DPU_CLK_CTRL_DMA2, 112 }, 113 }; 114 115 static const struct dpu_lm_cfg sm7150_lm[] = { 116 { 117 .name = "lm_0", .id = LM_0, 118 .base = 0x44000, .len = 0x320, 119 .features = MIXER_SDM845_MASK, 120 .sblk = &sdm845_lm_sblk, 121 .lm_pair = LM_1, 122 .pingpong = PINGPONG_0, 123 .dspp = DSPP_0, 124 }, { 125 .name = "lm_1", .id = LM_1, 126 .base = 0x45000, .len = 0x320, 127 .features = MIXER_SDM845_MASK, 128 .sblk = &sdm845_lm_sblk, 129 .lm_pair = LM_0, 130 .pingpong = PINGPONG_1, 131 .dspp = DSPP_1, 132 }, { 133 .name = "lm_2", .id = LM_2, 134 .base = 0x46000, .len = 0x320, 135 .features = MIXER_SDM845_MASK, 136 .sblk = &sdm845_lm_sblk, 137 .lm_pair = LM_3, 138 .pingpong = PINGPONG_2, 139 }, { 140 .name = "lm_3", .id = LM_3, 141 .base = 0x47000, .len = 0x320, 142 .features = MIXER_SDM845_MASK, 143 .sblk = &sdm845_lm_sblk, 144 .lm_pair = LM_2, 145 .pingpong = PINGPONG_3, 146 }, 147 }; 148 149 static const struct dpu_dspp_cfg sm7150_dspp[] = { 150 { 151 .name = "dspp_0", .id = DSPP_0, 152 .base = 0x54000, .len = 0x1800, 153 .features = DSPP_SC7180_MASK, 154 .sblk = &sdm845_dspp_sblk, 155 }, { 156 .name = "dspp_1", .id = DSPP_1, 157 .base = 0x56000, .len = 0x1800, 158 .features = DSPP_SC7180_MASK, 159 .sblk = &sdm845_dspp_sblk, 160 }, 161 }; 162 163 static const struct dpu_pingpong_cfg sm7150_pp[] = { 164 { 165 .name = "pingpong_0", .id = PINGPONG_0, 166 .base = 0x70000, .len = 0xd4, 167 .features = PINGPONG_SM8150_MASK, 168 .sblk = &sdm845_pp_sblk, 169 .merge_3d = MERGE_3D_0, 170 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 171 }, { 172 .name = "pingpong_1", .id = PINGPONG_1, 173 .base = 0x70800, .len = 0xd4, 174 .features = PINGPONG_SM8150_MASK, 175 .sblk = &sdm845_pp_sblk, 176 .merge_3d = MERGE_3D_0, 177 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 178 }, { 179 .name = "pingpong_2", .id = PINGPONG_2, 180 .base = 0x71000, .len = 0xd4, 181 .features = PINGPONG_SM8150_MASK, 182 .sblk = &sdm845_pp_sblk, 183 .merge_3d = MERGE_3D_1, 184 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 185 }, { 186 .name = "pingpong_3", .id = PINGPONG_3, 187 .base = 0x71800, .len = 0xd4, 188 .features = PINGPONG_SM8150_MASK, 189 .sblk = &sdm845_pp_sblk, 190 .merge_3d = MERGE_3D_1, 191 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 192 }, 193 }; 194 195 static const struct dpu_merge_3d_cfg sm7150_merge_3d[] = { 196 { 197 .name = "merge_3d_0", .id = MERGE_3D_0, 198 .base = 0x83000, .len = 0x8, 199 }, { 200 .name = "merge_3d_1", .id = MERGE_3D_1, 201 .base = 0x83100, .len = 0x8, 202 }, 203 }; 204 205 static const struct dpu_dsc_cfg sm7150_dsc[] = { 206 { 207 .name = "dsc_0", .id = DSC_0, 208 .base = 0x80000, .len = 0x140, 209 .features = BIT(DPU_DSC_OUTPUT_CTRL), 210 }, { 211 .name = "dsc_1", .id = DSC_1, 212 .base = 0x80400, .len = 0x140, 213 .features = BIT(DPU_DSC_OUTPUT_CTRL), 214 }, 215 }; 216 217 static const struct dpu_intf_cfg sm7150_intf[] = { 218 { 219 .name = "intf_0", .id = INTF_0, 220 .base = 0x6a000, .len = 0x280, 221 .features = INTF_SC7180_MASK, 222 .type = INTF_DP, 223 .controller_id = MSM_DP_CONTROLLER_0, 224 .prog_fetch_lines_worst_case = 24, 225 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 226 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 227 }, { 228 .name = "intf_1", .id = INTF_1, 229 .base = 0x6a800, .len = 0x2bc, 230 .features = INTF_SC7180_MASK, 231 .type = INTF_DSI, 232 .controller_id = MSM_DSI_CONTROLLER_0, 233 .prog_fetch_lines_worst_case = 24, 234 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 235 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 236 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), 237 }, { 238 .name = "intf_2", .id = INTF_2, 239 .base = 0x6b000, .len = 0x2bc, 240 .features = INTF_SC7180_MASK, 241 .type = INTF_DSI, 242 .controller_id = MSM_DSI_CONTROLLER_1, 243 .prog_fetch_lines_worst_case = 24, 244 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), 245 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), 246 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), 247 }, { 248 .name = "intf_3", .id = INTF_3, 249 .base = 0x6b800, .len = 0x280, 250 .features = INTF_SC7180_MASK, 251 .type = INTF_DP, 252 .controller_id = MSM_DP_CONTROLLER_1, 253 .prog_fetch_lines_worst_case = 24, 254 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), 255 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), 256 }, 257 }; 258 259 static const struct dpu_wb_cfg sm7150_wb[] = { 260 { 261 .name = "wb_2", .id = WB_2, 262 .base = 0x65000, .len = 0x2c8, 263 .features = WB_SM8250_MASK, 264 .format_list = wb2_formats_rgb, 265 .num_formats = ARRAY_SIZE(wb2_formats_rgb), 266 .clk_ctrl = DPU_CLK_CTRL_WB2, 267 .xin_id = 6, 268 .vbif_idx = VBIF_RT, 269 .maxlinewidth = 4096, 270 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 271 }, 272 }; 273 274 static const struct dpu_perf_cfg sm7150_perf_data = { 275 .max_bw_low = 7100000, 276 .max_bw_high = 7100000, 277 .min_core_ib = 2400000, 278 .min_llcc_ib = 800000, 279 .min_dram_ib = 800000, 280 .min_prefill_lines = 24, 281 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 282 .safe_lut_tbl = {0xfff8, 0xf000, 0xffff}, 283 .qos_lut_tbl = { 284 { 285 .nentry = ARRAY_SIZE(sm8150_qos_linear), 286 .entries = sm8150_qos_linear 287 }, { 288 .nentry = ARRAY_SIZE(sc7180_qos_macrotile), 289 .entries = sc7180_qos_macrotile 290 }, { 291 .nentry = ARRAY_SIZE(sc7180_qos_nrt), 292 .entries = sc7180_qos_nrt 293 }, 294 }, 295 .cdp_cfg = { 296 {.rd_enable = 1, .wr_enable = 1}, 297 {.rd_enable = 1, .wr_enable = 0} 298 }, 299 .clk_inefficiency_factor = 105, 300 .bw_inefficiency_factor = 120, 301 }; 302 303 static const struct dpu_mdss_version sm7150_mdss_ver = { 304 .core_major_ver = 5, 305 .core_minor_ver = 2, 306 }; 307 308 const struct dpu_mdss_cfg dpu_sm7150_cfg = { 309 .mdss_ver = &sm7150_mdss_ver, 310 .caps = &sm7150_dpu_caps, 311 .mdp = &sm7150_mdp, 312 .ctl_count = ARRAY_SIZE(sm7150_ctl), 313 .ctl = sm7150_ctl, 314 .sspp_count = ARRAY_SIZE(sm7150_sspp), 315 .sspp = sm7150_sspp, 316 .mixer_count = ARRAY_SIZE(sm7150_lm), 317 .mixer = sm7150_lm, 318 .dspp_count = ARRAY_SIZE(sm7150_dspp), 319 .dspp = sm7150_dspp, 320 .pingpong_count = ARRAY_SIZE(sm7150_pp), 321 .pingpong = sm7150_pp, 322 .merge_3d_count = ARRAY_SIZE(sm7150_merge_3d), 323 .merge_3d = sm7150_merge_3d, 324 .dsc_count = ARRAY_SIZE(sm7150_dsc), 325 .dsc = sm7150_dsc, 326 .intf_count = ARRAY_SIZE(sm7150_intf), 327 .intf = sm7150_intf, 328 .wb_count = ARRAY_SIZE(sm7150_wb), 329 .wb = sm7150_wb, 330 .vbif_count = ARRAY_SIZE(sdm845_vbif), 331 .vbif = sdm845_vbif, 332 .perf = &sm7150_perf_data, 333 }; 334 335 #endif 336