1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights reserved. 5 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 6 * 7 * Author: Rob Clark <robdclark@gmail.com> 8 */ 9 10 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 11 #include <linux/debugfs.h> 12 #include <linux/kthread.h> 13 #include <linux/seq_file.h> 14 15 #include <drm/drm_atomic.h> 16 #include <drm/drm_crtc.h> 17 #include <drm/drm_file.h> 18 #include <drm/drm_probe_helper.h> 19 #include <drm/drm_framebuffer.h> 20 21 #include "msm_drv.h" 22 #include "dpu_kms.h" 23 #include "dpu_hwio.h" 24 #include "dpu_hw_catalog.h" 25 #include "dpu_hw_intf.h" 26 #include "dpu_hw_ctl.h" 27 #include "dpu_hw_cwb.h" 28 #include "dpu_hw_dspp.h" 29 #include "dpu_hw_dsc.h" 30 #include "dpu_hw_merge3d.h" 31 #include "dpu_hw_cdm.h" 32 #include "dpu_formats.h" 33 #include "dpu_encoder_phys.h" 34 #include "dpu_crtc.h" 35 #include "dpu_trace.h" 36 #include "dpu_core_irq.h" 37 #include "disp/msm_disp_snapshot.h" 38 39 #define DPU_DEBUG_ENC(e, fmt, ...) DRM_DEBUG_ATOMIC("enc%d " fmt,\ 40 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) 41 42 #define DPU_ERROR_ENC(e, fmt, ...) DPU_ERROR("enc%d " fmt,\ 43 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) 44 45 #define DPU_ERROR_ENC_RATELIMITED(e, fmt, ...) DPU_ERROR_RATELIMITED("enc%d " fmt,\ 46 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) 47 48 /* 49 * Two to anticipate panels that can do cmd/vid dynamic switching 50 * plan is to create all possible physical encoder types, and switch between 51 * them at runtime 52 */ 53 #define NUM_PHYS_ENCODER_TYPES 2 54 55 #define MAX_PHYS_ENCODERS_PER_VIRTUAL \ 56 (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES) 57 58 #define MAX_CHANNELS_PER_ENC 2 59 #define MAX_CWB_PER_ENC 2 60 61 #define IDLE_SHORT_TIMEOUT 1 62 63 /* timeout in frames waiting for frame done */ 64 #define DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES 5 65 66 /** 67 * enum dpu_enc_rc_events - events for resource control state machine 68 * @DPU_ENC_RC_EVENT_KICKOFF: 69 * This event happens at NORMAL priority. 70 * Event that signals the start of the transfer. When this event is 71 * received, enable MDP/DSI core clocks. Regardless of the previous 72 * state, the resource should be in ON state at the end of this event. 73 * @DPU_ENC_RC_EVENT_FRAME_DONE: 74 * This event happens at INTERRUPT level. 75 * Event signals the end of the data transfer after the PP FRAME_DONE 76 * event. At the end of this event, a delayed work is scheduled to go to 77 * IDLE_PC state after IDLE_TIMEOUT time. 78 * @DPU_ENC_RC_EVENT_PRE_STOP: 79 * This event happens at NORMAL priority. 80 * This event, when received during the ON state, leave the RC STATE 81 * in the PRE_OFF state. It should be followed by the STOP event as 82 * part of encoder disable. 83 * If received during IDLE or OFF states, it will do nothing. 84 * @DPU_ENC_RC_EVENT_STOP: 85 * This event happens at NORMAL priority. 86 * When this event is received, disable all the MDP/DSI core clocks, and 87 * disable IRQs. It should be called from the PRE_OFF or IDLE states. 88 * IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing. 89 * PRE_OFF is expected when PRE_STOP was executed during the ON state. 90 * Resource state should be in OFF at the end of the event. 91 * @DPU_ENC_RC_EVENT_ENTER_IDLE: 92 * This event happens at NORMAL priority from a work item. 93 * Event signals that there were no frame updates for IDLE_TIMEOUT time. 94 * This would disable MDP/DSI core clocks and change the resource state 95 * to IDLE. 96 */ 97 enum dpu_enc_rc_events { 98 DPU_ENC_RC_EVENT_KICKOFF = 1, 99 DPU_ENC_RC_EVENT_FRAME_DONE, 100 DPU_ENC_RC_EVENT_PRE_STOP, 101 DPU_ENC_RC_EVENT_STOP, 102 DPU_ENC_RC_EVENT_ENTER_IDLE 103 }; 104 105 /* 106 * enum dpu_enc_rc_states - states that the resource control maintains 107 * @DPU_ENC_RC_STATE_OFF: Resource is in OFF state 108 * @DPU_ENC_RC_STATE_PRE_OFF: Resource is transitioning to OFF state 109 * @DPU_ENC_RC_STATE_ON: Resource is in ON state 110 * @DPU_ENC_RC_STATE_MODESET: Resource is in modeset state 111 * @DPU_ENC_RC_STATE_IDLE: Resource is in IDLE state 112 */ 113 enum dpu_enc_rc_states { 114 DPU_ENC_RC_STATE_OFF, 115 DPU_ENC_RC_STATE_PRE_OFF, 116 DPU_ENC_RC_STATE_ON, 117 DPU_ENC_RC_STATE_IDLE 118 }; 119 120 /** 121 * struct dpu_encoder_virt - virtual encoder. Container of one or more physical 122 * encoders. Virtual encoder manages one "logical" display. Physical 123 * encoders manage one intf block, tied to a specific panel/sub-panel. 124 * Virtual encoder defers as much as possible to the physical encoders. 125 * Virtual encoder registers itself with the DRM Framework as the encoder. 126 * @base: drm_encoder base class for registration with DRM 127 * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes 128 * @enabled: True if the encoder is active, protected by enc_lock 129 * @commit_done_timedout: True if there has been a timeout on commit after 130 * enabling the encoder. 131 * @num_phys_encs: Actual number of physical encoders contained. 132 * @phys_encs: Container of physical encoders managed. 133 * @cur_master: Pointer to the current master in this mode. Optimization 134 * Only valid after enable. Cleared as disable. 135 * @cur_slave: As above but for the slave encoder. 136 * @hw_pp: Handle to the pingpong blocks used for the display. No. 137 * pingpong blocks can be different than num_phys_encs. 138 * @hw_cwb: Handle to the CWB muxes used for concurrent writeback 139 * display. Number of CWB muxes can be different than 140 * num_phys_encs. 141 * @hw_dsc: Handle to the DSC blocks used for the display. 142 * @dsc_mask: Bitmask of used DSC blocks. 143 * @cwb_mask: Bitmask of used CWB muxes 144 * @intfs_swapped: Whether or not the phys_enc interfaces have been swapped 145 * for partial update right-only cases, such as pingpong 146 * split where virtual pingpong does not generate IRQs 147 * @crtc: Pointer to the currently assigned crtc. Normally you 148 * would use crtc->state->encoder_mask to determine the 149 * link between encoder/crtc. However in this case we need 150 * to track crtc in the disable() hook which is called 151 * _after_ encoder_mask is cleared. 152 * @connector: If a mode is set, cached pointer to the active connector 153 * @enc_lock: Lock around physical encoder 154 * create/destroy/enable/disable 155 * @frame_busy_mask: Bitmask tracking which phys_enc we are still 156 * busy processing current command. 157 * Bit0 = phys_encs[0] etc. 158 * @frame_done_timeout_ms: frame done timeout in ms 159 * @frame_done_timeout_cnt: atomic counter tracking the number of frame 160 * done timeouts 161 * @frame_done_timer: watchdog timer for frame done event 162 * @disp_info: local copy of msm_display_info struct 163 * @idle_pc_supported: indicate if idle power collaps is supported 164 * @rc_lock: resource control mutex lock to protect 165 * virt encoder over various state changes 166 * @rc_state: resource controller state 167 * @delayed_off_work: delayed worker to schedule disabling of 168 * clks and resources after IDLE_TIMEOUT time. 169 * @topology: topology of the display 170 * @idle_timeout: idle timeout duration in milliseconds 171 * @wide_bus_en: wide bus is enabled on this interface 172 * @dsc: drm_dsc_config pointer, for DSC-enabled encoders 173 */ 174 struct dpu_encoder_virt { 175 struct drm_encoder base; 176 spinlock_t enc_spinlock; 177 178 bool enabled; 179 bool commit_done_timedout; 180 181 unsigned int num_phys_encs; 182 struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL]; 183 struct dpu_encoder_phys *cur_master; 184 struct dpu_encoder_phys *cur_slave; 185 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; 186 struct dpu_hw_cwb *hw_cwb[MAX_CWB_PER_ENC]; 187 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC]; 188 189 unsigned int dsc_mask; 190 unsigned int cwb_mask; 191 192 bool intfs_swapped; 193 194 struct drm_crtc *crtc; 195 struct drm_connector *connector; 196 197 struct mutex enc_lock; 198 DECLARE_BITMAP(frame_busy_mask, MAX_PHYS_ENCODERS_PER_VIRTUAL); 199 200 atomic_t frame_done_timeout_ms; 201 atomic_t frame_done_timeout_cnt; 202 struct timer_list frame_done_timer; 203 204 struct msm_display_info disp_info; 205 206 bool idle_pc_supported; 207 struct mutex rc_lock; 208 enum dpu_enc_rc_states rc_state; 209 struct delayed_work delayed_off_work; 210 struct msm_display_topology topology; 211 212 u32 idle_timeout; 213 214 bool wide_bus_en; 215 216 /* DSC configuration */ 217 struct drm_dsc_config *dsc; 218 }; 219 220 #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base) 221 222 static u32 dither_matrix[DITHER_MATRIX_SZ] = { 223 15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10 224 }; 225 226 /** 227 * dpu_encoder_get_drm_fmt - return DRM fourcc format 228 * @phys_enc: Pointer to physical encoder structure 229 */ 230 u32 dpu_encoder_get_drm_fmt(struct dpu_encoder_phys *phys_enc) 231 { 232 struct drm_encoder *drm_enc; 233 struct dpu_encoder_virt *dpu_enc; 234 struct drm_display_info *info; 235 struct drm_display_mode *mode; 236 237 drm_enc = phys_enc->parent; 238 dpu_enc = to_dpu_encoder_virt(drm_enc); 239 info = &dpu_enc->connector->display_info; 240 mode = &phys_enc->cached_mode; 241 242 if (drm_mode_is_420_only(info, mode)) 243 return DRM_FORMAT_YUV420; 244 245 return DRM_FORMAT_RGB888; 246 } 247 248 /** 249 * dpu_encoder_needs_periph_flush - return true if physical encoder requires 250 * peripheral flush 251 * @phys_enc: Pointer to physical encoder structure 252 */ 253 bool dpu_encoder_needs_periph_flush(struct dpu_encoder_phys *phys_enc) 254 { 255 struct drm_encoder *drm_enc; 256 struct dpu_encoder_virt *dpu_enc; 257 struct msm_display_info *disp_info; 258 struct msm_drm_private *priv; 259 struct drm_display_mode *mode; 260 261 drm_enc = phys_enc->parent; 262 dpu_enc = to_dpu_encoder_virt(drm_enc); 263 disp_info = &dpu_enc->disp_info; 264 priv = drm_enc->dev->dev_private; 265 mode = &phys_enc->cached_mode; 266 267 return phys_enc->hw_intf->cap->type == INTF_DP && 268 msm_dp_needs_periph_flush(priv->kms->dp[disp_info->h_tile_instance[0]], mode); 269 } 270 271 /** 272 * dpu_encoder_is_widebus_enabled - return bool value if widebus is enabled 273 * @drm_enc: Pointer to previously created drm encoder structure 274 */ 275 bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc) 276 { 277 const struct dpu_encoder_virt *dpu_enc; 278 struct msm_drm_private *priv = drm_enc->dev->dev_private; 279 const struct msm_display_info *disp_info; 280 int index; 281 282 dpu_enc = to_dpu_encoder_virt(drm_enc); 283 disp_info = &dpu_enc->disp_info; 284 index = disp_info->h_tile_instance[0]; 285 286 if (disp_info->intf_type == INTF_DP) 287 return msm_dp_wide_bus_available(priv->kms->dp[index]); 288 else if (disp_info->intf_type == INTF_DSI) 289 return msm_dsi_wide_bus_enabled(priv->kms->dsi[index]); 290 291 return false; 292 } 293 294 /** 295 * dpu_encoder_is_dsc_enabled - indicate whether dsc is enabled 296 * for the encoder. 297 * @drm_enc: Pointer to previously created drm encoder structure 298 */ 299 bool dpu_encoder_is_dsc_enabled(const struct drm_encoder *drm_enc) 300 { 301 const struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 302 303 return dpu_enc->dsc ? true : false; 304 } 305 306 /** 307 * dpu_encoder_get_crc_values_cnt - get number of physical encoders contained 308 * in virtual encoder that can collect CRC values 309 * @drm_enc: Pointer to previously created drm encoder structure 310 * Returns: Number of physical encoders for given drm encoder 311 */ 312 int dpu_encoder_get_crc_values_cnt(const struct drm_encoder *drm_enc) 313 { 314 struct dpu_encoder_virt *dpu_enc; 315 int i, num_intf = 0; 316 317 dpu_enc = to_dpu_encoder_virt(drm_enc); 318 319 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 320 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 321 322 if (phys->hw_intf && phys->hw_intf->ops.setup_misr 323 && phys->hw_intf->ops.collect_misr) 324 num_intf++; 325 } 326 327 return num_intf; 328 } 329 330 /** 331 * dpu_encoder_setup_misr - enable misr calculations 332 * @drm_enc: Pointer to previously created drm encoder structure 333 */ 334 void dpu_encoder_setup_misr(const struct drm_encoder *drm_enc) 335 { 336 struct dpu_encoder_virt *dpu_enc; 337 338 int i; 339 340 dpu_enc = to_dpu_encoder_virt(drm_enc); 341 342 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 343 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 344 345 if (!phys->hw_intf || !phys->hw_intf->ops.setup_misr) 346 continue; 347 348 phys->hw_intf->ops.setup_misr(phys->hw_intf); 349 } 350 } 351 352 /** 353 * dpu_encoder_get_crc - get the crc value from interface blocks 354 * @drm_enc: Pointer to previously created drm encoder structure 355 * @crcs: array to fill with CRC data 356 * @pos: offset into the @crcs array 357 * Returns: 0 on success, error otherwise 358 */ 359 int dpu_encoder_get_crc(const struct drm_encoder *drm_enc, u32 *crcs, int pos) 360 { 361 struct dpu_encoder_virt *dpu_enc; 362 363 int i, rc = 0, entries_added = 0; 364 365 if (!drm_enc->crtc) { 366 DRM_ERROR("no crtc found for encoder %d\n", drm_enc->index); 367 return -EINVAL; 368 } 369 370 dpu_enc = to_dpu_encoder_virt(drm_enc); 371 372 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 373 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 374 375 if (!phys->hw_intf || !phys->hw_intf->ops.collect_misr) 376 continue; 377 378 rc = phys->hw_intf->ops.collect_misr(phys->hw_intf, &crcs[pos + entries_added]); 379 if (rc) 380 return rc; 381 entries_added++; 382 } 383 384 return entries_added; 385 } 386 387 static void _dpu_encoder_setup_dither(struct dpu_hw_pingpong *hw_pp, unsigned bpc) 388 { 389 struct dpu_hw_dither_cfg dither_cfg = { 0 }; 390 391 if (!hw_pp->ops.setup_dither) 392 return; 393 394 switch (bpc) { 395 case 6: 396 dither_cfg.c0_bitdepth = 6; 397 dither_cfg.c1_bitdepth = 6; 398 dither_cfg.c2_bitdepth = 6; 399 dither_cfg.c3_bitdepth = 6; 400 dither_cfg.temporal_en = 0; 401 break; 402 default: 403 hw_pp->ops.setup_dither(hw_pp, NULL); 404 return; 405 } 406 407 memcpy(&dither_cfg.matrix, dither_matrix, 408 sizeof(u32) * DITHER_MATRIX_SZ); 409 410 hw_pp->ops.setup_dither(hw_pp, &dither_cfg); 411 } 412 413 static char *dpu_encoder_helper_get_intf_type(enum dpu_intf_mode intf_mode) 414 { 415 switch (intf_mode) { 416 case INTF_MODE_VIDEO: 417 return "INTF_MODE_VIDEO"; 418 case INTF_MODE_CMD: 419 return "INTF_MODE_CMD"; 420 case INTF_MODE_WB_BLOCK: 421 return "INTF_MODE_WB_BLOCK"; 422 case INTF_MODE_WB_LINE: 423 return "INTF_MODE_WB_LINE"; 424 default: 425 return "INTF_MODE_UNKNOWN"; 426 } 427 } 428 429 /** 430 * dpu_encoder_helper_report_irq_timeout - utility to report error that irq has 431 * timed out, including reporting frame error event to crtc and debug dump 432 * @phys_enc: Pointer to physical encoder structure 433 * @intr_idx: Failing interrupt index 434 */ 435 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc, 436 enum dpu_intr_idx intr_idx) 437 { 438 DRM_ERROR("irq timeout id=%u, intf_mode=%s intf=%d wb=%d, pp=%d, intr=%d\n", 439 DRMID(phys_enc->parent), 440 dpu_encoder_helper_get_intf_type(phys_enc->intf_mode), 441 phys_enc->hw_intf ? phys_enc->hw_intf->idx - INTF_0 : -1, 442 phys_enc->hw_wb ? phys_enc->hw_wb->idx - WB_0 : -1, 443 phys_enc->hw_pp->idx - PINGPONG_0, intr_idx); 444 445 dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc, 446 DPU_ENCODER_FRAME_EVENT_ERROR); 447 } 448 449 static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id, 450 u32 irq_idx, struct dpu_encoder_wait_info *info); 451 452 /** 453 * dpu_encoder_helper_wait_for_irq - utility to wait on an irq. 454 * note: will call dpu_encoder_helper_wait_for_irq on timeout 455 * @phys_enc: Pointer to physical encoder structure 456 * @irq_idx: IRQ index 457 * @func: IRQ callback to be called in case of timeout 458 * @wait_info: wait info struct 459 * @return: 0 or -ERROR 460 */ 461 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, 462 unsigned int irq_idx, 463 void (*func)(void *arg), 464 struct dpu_encoder_wait_info *wait_info) 465 { 466 u32 irq_status; 467 int ret; 468 469 if (!wait_info) { 470 DPU_ERROR("invalid params\n"); 471 return -EINVAL; 472 } 473 /* note: do master / slave checking outside */ 474 475 /* return EWOULDBLOCK since we know the wait isn't necessary */ 476 if (phys_enc->enable_state == DPU_ENC_DISABLED) { 477 DRM_ERROR("encoder is disabled id=%u, callback=%ps, IRQ=[%d, %d]\n", 478 DRMID(phys_enc->parent), func, 479 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx)); 480 return -EWOULDBLOCK; 481 } 482 483 if (irq_idx == 0) { 484 DRM_DEBUG_KMS("skip irq wait id=%u, callback=%ps\n", 485 DRMID(phys_enc->parent), func); 486 return 0; 487 } 488 489 DRM_DEBUG_KMS("id=%u, callback=%ps, IRQ=[%d, %d], pp=%d, pending_cnt=%d\n", 490 DRMID(phys_enc->parent), func, 491 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), phys_enc->hw_pp->idx - PINGPONG_0, 492 atomic_read(wait_info->atomic_cnt)); 493 494 ret = dpu_encoder_helper_wait_event_timeout( 495 DRMID(phys_enc->parent), 496 irq_idx, 497 wait_info); 498 499 if (ret <= 0) { 500 irq_status = dpu_core_irq_read(phys_enc->dpu_kms, irq_idx); 501 if (irq_status) { 502 unsigned long flags; 503 504 DRM_DEBUG_KMS("IRQ=[%d, %d] not triggered id=%u, callback=%ps, pp=%d, atomic_cnt=%d\n", 505 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), 506 DRMID(phys_enc->parent), func, 507 phys_enc->hw_pp->idx - PINGPONG_0, 508 atomic_read(wait_info->atomic_cnt)); 509 local_irq_save(flags); 510 func(phys_enc); 511 local_irq_restore(flags); 512 ret = 0; 513 } else { 514 ret = -ETIMEDOUT; 515 DRM_DEBUG_KMS("IRQ=[%d, %d] timeout id=%u, callback=%ps, pp=%d, atomic_cnt=%d\n", 516 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), 517 DRMID(phys_enc->parent), func, 518 phys_enc->hw_pp->idx - PINGPONG_0, 519 atomic_read(wait_info->atomic_cnt)); 520 } 521 } else { 522 ret = 0; 523 trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent), 524 func, DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), 525 phys_enc->hw_pp->idx - PINGPONG_0, 526 atomic_read(wait_info->atomic_cnt)); 527 } 528 529 return ret; 530 } 531 532 /** 533 * dpu_encoder_get_vsync_count - get vsync count for the encoder. 534 * @drm_enc: Pointer to previously created drm encoder structure 535 */ 536 int dpu_encoder_get_vsync_count(struct drm_encoder *drm_enc) 537 { 538 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 539 struct dpu_encoder_phys *phys = dpu_enc ? dpu_enc->cur_master : NULL; 540 return phys ? atomic_read(&phys->vsync_cnt) : 0; 541 } 542 543 /** 544 * dpu_encoder_get_linecount - get interface line count for the encoder. 545 * @drm_enc: Pointer to previously created drm encoder structure 546 */ 547 int dpu_encoder_get_linecount(struct drm_encoder *drm_enc) 548 { 549 struct dpu_encoder_virt *dpu_enc; 550 struct dpu_encoder_phys *phys; 551 int linecount = 0; 552 553 dpu_enc = to_dpu_encoder_virt(drm_enc); 554 phys = dpu_enc ? dpu_enc->cur_master : NULL; 555 556 if (phys && phys->ops.get_line_count) 557 linecount = phys->ops.get_line_count(phys); 558 559 return linecount; 560 } 561 562 /** 563 * dpu_encoder_helper_split_config - split display configuration helper function 564 * This helper function may be used by physical encoders to configure 565 * the split display related registers. 566 * @phys_enc: Pointer to physical encoder structure 567 * @interface: enum dpu_intf setting 568 */ 569 void dpu_encoder_helper_split_config( 570 struct dpu_encoder_phys *phys_enc, 571 enum dpu_intf interface) 572 { 573 struct dpu_encoder_virt *dpu_enc; 574 struct split_pipe_cfg cfg = { 0 }; 575 struct dpu_hw_mdp *hw_mdptop; 576 struct msm_display_info *disp_info; 577 578 if (!phys_enc->hw_mdptop || !phys_enc->parent) { 579 DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != NULL); 580 return; 581 } 582 583 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); 584 hw_mdptop = phys_enc->hw_mdptop; 585 disp_info = &dpu_enc->disp_info; 586 587 if (disp_info->intf_type != INTF_DSI) 588 return; 589 590 /** 591 * disable split modes since encoder will be operating in as the only 592 * encoder, either for the entire use case in the case of, for example, 593 * single DSI, or for this frame in the case of left/right only partial 594 * update. 595 */ 596 if (phys_enc->split_role == ENC_ROLE_SOLO) { 597 if (hw_mdptop->ops.setup_split_pipe) 598 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg); 599 return; 600 } 601 602 cfg.en = true; 603 cfg.mode = phys_enc->intf_mode; 604 cfg.intf = interface; 605 606 if (cfg.en && phys_enc->ops.needs_single_flush && 607 phys_enc->ops.needs_single_flush(phys_enc)) 608 cfg.split_flush_en = true; 609 610 if (phys_enc->split_role == ENC_ROLE_MASTER) { 611 DPU_DEBUG_ENC(dpu_enc, "enable %d\n", cfg.en); 612 613 if (hw_mdptop->ops.setup_split_pipe) 614 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg); 615 } 616 } 617 618 /** 619 * dpu_encoder_use_dsc_merge - returns true if the encoder uses DSC merge topology. 620 * @drm_enc: Pointer to previously created drm encoder structure 621 */ 622 bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc) 623 { 624 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 625 int i, intf_count = 0, num_dsc = 0; 626 627 for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++) 628 if (dpu_enc->phys_encs[i]) 629 intf_count++; 630 631 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) 632 if (dpu_enc->hw_dsc[i]) 633 num_dsc++; 634 635 return (num_dsc > 0) && (num_dsc > intf_count); 636 } 637 638 /** 639 * dpu_encoder_get_dsc_config - get DSC config for the DPU encoder 640 * This helper function is used by physical encoder to get DSC config 641 * used for this encoder. 642 * @drm_enc: Pointer to encoder structure 643 */ 644 struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc) 645 { 646 struct msm_drm_private *priv = drm_enc->dev->dev_private; 647 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 648 int index = dpu_enc->disp_info.h_tile_instance[0]; 649 650 if (dpu_enc->disp_info.intf_type == INTF_DSI) 651 return msm_dsi_get_dsc_config(priv->kms->dsi[index]); 652 653 return NULL; 654 } 655 656 void dpu_encoder_update_topology(struct drm_encoder *drm_enc, 657 struct msm_display_topology *topology, 658 struct drm_atomic_commit *state, 659 const struct drm_display_mode *adj_mode) 660 { 661 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 662 struct msm_drm_private *priv = dpu_enc->base.dev->dev_private; 663 struct msm_display_info *disp_info = &dpu_enc->disp_info; 664 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); 665 struct drm_connector *connector; 666 struct drm_connector_state *conn_state; 667 struct drm_framebuffer *fb; 668 struct drm_dsc_config *dsc; 669 670 int i; 671 672 for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++) 673 if (dpu_enc->phys_encs[i]) 674 topology->num_intf++; 675 676 dsc = dpu_encoder_get_dsc_config(drm_enc); 677 678 /* We only support 2 DSC mode (with 2 LM and 1 INTF) */ 679 if (dsc) { 680 /* 681 * Use 2 DSC encoders, 2 layer mixers and 1 or 2 interfaces 682 * when Display Stream Compression (DSC) is enabled, 683 * and when enough DSC blocks are available. 684 * This is power-optimal and can drive up to (including) 4k 685 * screens. 686 */ 687 WARN(topology->num_intf > 2, 688 "DSC topology cannot support more than 2 interfaces\n"); 689 if (topology->num_intf >= 2 || dpu_kms->catalog->dsc_count >= 2) 690 topology->num_dsc = 2; 691 else 692 topology->num_dsc = 1; 693 } 694 695 connector = drm_atomic_get_new_connector_for_encoder(state, drm_enc); 696 if (!connector) 697 return; 698 conn_state = drm_atomic_get_new_connector_state(state, connector); 699 if (!conn_state) 700 return; 701 702 /* 703 * Use CDM only for writeback or DP at the moment as other interfaces cannot handle it. 704 * If writeback itself cannot handle cdm for some reason it will fail in its atomic_check() 705 * earlier. 706 */ 707 if (disp_info->intf_type == INTF_WB && conn_state->writeback_job) { 708 fb = conn_state->writeback_job->fb; 709 710 if (fb && MSM_FORMAT_IS_YUV(msm_framebuffer_format(fb))) 711 topology->num_cdm++; 712 } else if (disp_info->intf_type == INTF_DP) { 713 if (drm_mode_is_420_only(&connector->display_info, adj_mode)) 714 topology->num_cdm++; 715 } 716 } 717 718 bool dpu_encoder_needs_modeset(struct drm_encoder *drm_enc, struct drm_atomic_commit *state) 719 { 720 struct drm_connector *connector; 721 struct drm_connector_state *conn_state; 722 struct drm_framebuffer *fb; 723 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 724 725 if (!drm_enc || !state) 726 return false; 727 728 connector = drm_atomic_get_new_connector_for_encoder(state, drm_enc); 729 if (!connector) 730 return false; 731 732 conn_state = drm_atomic_get_new_connector_state(state, connector); 733 if (!conn_state) 734 return false; 735 736 /** 737 * These checks are duplicated from dpu_encoder_update_topology() since 738 * CRTC and encoder don't hold topology information 739 */ 740 if (dpu_enc->disp_info.intf_type == INTF_WB && conn_state->writeback_job) { 741 fb = conn_state->writeback_job->fb; 742 if (fb && MSM_FORMAT_IS_YUV(msm_framebuffer_format(fb))) { 743 if (!dpu_enc->cur_master->hw_cdm) 744 return true; 745 } else { 746 if (dpu_enc->cur_master->hw_cdm) 747 return true; 748 } 749 } 750 751 return false; 752 } 753 754 static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc, 755 struct msm_display_info *disp_info) 756 { 757 struct dpu_vsync_source_cfg vsync_cfg = { 0 }; 758 struct msm_drm_private *priv; 759 struct dpu_kms *dpu_kms; 760 struct dpu_hw_mdp *hw_mdptop; 761 struct drm_encoder *drm_enc; 762 struct dpu_encoder_phys *phys_enc; 763 int i; 764 765 if (!dpu_enc || !disp_info) { 766 DPU_ERROR("invalid param dpu_enc:%d or disp_info:%d\n", 767 dpu_enc != NULL, disp_info != NULL); 768 return; 769 } else if (dpu_enc->num_phys_encs > ARRAY_SIZE(dpu_enc->hw_pp)) { 770 DPU_ERROR("invalid num phys enc %d/%d\n", 771 dpu_enc->num_phys_encs, 772 (int) ARRAY_SIZE(dpu_enc->hw_pp)); 773 return; 774 } 775 776 drm_enc = &dpu_enc->base; 777 /* this pointers are checked in virt_enable_helper */ 778 priv = drm_enc->dev->dev_private; 779 780 dpu_kms = to_dpu_kms(priv->kms); 781 hw_mdptop = dpu_kms->hw_mdp; 782 if (!hw_mdptop) { 783 DPU_ERROR("invalid mdptop\n"); 784 return; 785 } 786 787 vsync_cfg.vsync_source = disp_info->vsync_source; 788 vsync_cfg.frame_rate = drm_mode_vrefresh(&dpu_enc->base.crtc->state->adjusted_mode); 789 790 if (hw_mdptop->ops.setup_vsync_source) { 791 for (i = 0; i < dpu_enc->num_phys_encs; i++) 792 vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx; 793 794 vsync_cfg.pp_count = dpu_enc->num_phys_encs; 795 796 hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg); 797 } 798 799 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 800 phys_enc = dpu_enc->phys_encs[i]; 801 802 if (phys_enc->has_intf_te && phys_enc->hw_intf->ops.vsync_sel) 803 phys_enc->hw_intf->ops.vsync_sel(phys_enc->hw_intf, 804 &vsync_cfg); 805 } 806 } 807 808 static void _dpu_encoder_irq_enable(struct drm_encoder *drm_enc) 809 { 810 struct dpu_encoder_virt *dpu_enc; 811 int i; 812 813 if (!drm_enc) { 814 DPU_ERROR("invalid encoder\n"); 815 return; 816 } 817 818 dpu_enc = to_dpu_encoder_virt(drm_enc); 819 820 DPU_DEBUG_ENC(dpu_enc, "\n"); 821 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 822 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 823 824 phys->ops.irq_enable(phys); 825 } 826 } 827 828 static void _dpu_encoder_irq_disable(struct drm_encoder *drm_enc) 829 { 830 struct dpu_encoder_virt *dpu_enc; 831 int i; 832 833 if (!drm_enc) { 834 DPU_ERROR("invalid encoder\n"); 835 return; 836 } 837 838 dpu_enc = to_dpu_encoder_virt(drm_enc); 839 840 DPU_DEBUG_ENC(dpu_enc, "\n"); 841 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 842 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 843 844 phys->ops.irq_disable(phys); 845 } 846 } 847 848 static void _dpu_encoder_resource_enable(struct drm_encoder *drm_enc) 849 { 850 struct msm_drm_private *priv; 851 struct dpu_kms *dpu_kms; 852 struct dpu_encoder_virt *dpu_enc; 853 854 dpu_enc = to_dpu_encoder_virt(drm_enc); 855 priv = drm_enc->dev->dev_private; 856 dpu_kms = to_dpu_kms(priv->kms); 857 858 trace_dpu_enc_rc_enable(DRMID(drm_enc)); 859 860 if (!dpu_enc->cur_master) { 861 DPU_ERROR("encoder master not set\n"); 862 return; 863 } 864 865 /* enable DPU core clks */ 866 pm_runtime_get_sync(&dpu_kms->pdev->dev); 867 868 /* enable all the irq */ 869 _dpu_encoder_irq_enable(drm_enc); 870 } 871 872 static void _dpu_encoder_resource_disable(struct drm_encoder *drm_enc) 873 { 874 struct msm_drm_private *priv; 875 struct dpu_kms *dpu_kms; 876 struct dpu_encoder_virt *dpu_enc; 877 878 dpu_enc = to_dpu_encoder_virt(drm_enc); 879 priv = drm_enc->dev->dev_private; 880 dpu_kms = to_dpu_kms(priv->kms); 881 882 trace_dpu_enc_rc_disable(DRMID(drm_enc)); 883 884 if (!dpu_enc->cur_master) { 885 DPU_ERROR("encoder master not set\n"); 886 return; 887 } 888 889 /* disable all the irq */ 890 _dpu_encoder_irq_disable(drm_enc); 891 892 /* disable DPU core clks */ 893 pm_runtime_put_sync(&dpu_kms->pdev->dev); 894 } 895 896 static int dpu_encoder_resource_control(struct drm_encoder *drm_enc, 897 u32 sw_event) 898 { 899 struct dpu_encoder_virt *dpu_enc; 900 struct msm_drm_private *priv; 901 bool is_vid_mode = false; 902 903 if (!drm_enc || !drm_enc->dev || !drm_enc->crtc) { 904 DPU_ERROR("invalid parameters\n"); 905 return -EINVAL; 906 } 907 dpu_enc = to_dpu_encoder_virt(drm_enc); 908 priv = drm_enc->dev->dev_private; 909 is_vid_mode = !dpu_enc->disp_info.is_cmd_mode; 910 911 /* 912 * when idle_pc is not supported, process only KICKOFF, STOP and MODESET 913 * events and return early for other events (ie wb display). 914 */ 915 if (!dpu_enc->idle_pc_supported && 916 (sw_event != DPU_ENC_RC_EVENT_KICKOFF && 917 sw_event != DPU_ENC_RC_EVENT_STOP && 918 sw_event != DPU_ENC_RC_EVENT_PRE_STOP)) 919 return 0; 920 921 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, dpu_enc->idle_pc_supported, 922 dpu_enc->rc_state, "begin"); 923 924 switch (sw_event) { 925 case DPU_ENC_RC_EVENT_KICKOFF: 926 /* cancel delayed off work, if any */ 927 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work)) 928 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n", 929 sw_event); 930 931 mutex_lock(&dpu_enc->rc_lock); 932 933 /* return if the resource control is already in ON state */ 934 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) { 935 DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in ON state\n", 936 DRMID(drm_enc), sw_event); 937 mutex_unlock(&dpu_enc->rc_lock); 938 return 0; 939 } else if (dpu_enc->rc_state != DPU_ENC_RC_STATE_OFF && 940 dpu_enc->rc_state != DPU_ENC_RC_STATE_IDLE) { 941 DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in state %d\n", 942 DRMID(drm_enc), sw_event, 943 dpu_enc->rc_state); 944 mutex_unlock(&dpu_enc->rc_lock); 945 return -EINVAL; 946 } 947 948 if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) 949 _dpu_encoder_irq_enable(drm_enc); 950 else 951 _dpu_encoder_resource_enable(drm_enc); 952 953 dpu_enc->rc_state = DPU_ENC_RC_STATE_ON; 954 955 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 956 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 957 "kickoff"); 958 959 mutex_unlock(&dpu_enc->rc_lock); 960 break; 961 962 case DPU_ENC_RC_EVENT_FRAME_DONE: 963 /* 964 * mutex lock is not used as this event happens at interrupt 965 * context. And locking is not required as, the other events 966 * like KICKOFF and STOP does a wait-for-idle before executing 967 * the resource_control 968 */ 969 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) { 970 DRM_DEBUG_KMS("id:%d, sw_event:%d,rc:%d-unexpected\n", 971 DRMID(drm_enc), sw_event, 972 dpu_enc->rc_state); 973 return -EINVAL; 974 } 975 976 /* 977 * schedule off work item only when there are no 978 * frames pending 979 */ 980 if (dpu_crtc_frame_pending(drm_enc->crtc) > 1) { 981 DRM_DEBUG_KMS("id:%d skip schedule work\n", 982 DRMID(drm_enc)); 983 return 0; 984 } 985 986 queue_delayed_work(priv->kms->wq, &dpu_enc->delayed_off_work, 987 msecs_to_jiffies(dpu_enc->idle_timeout)); 988 989 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 990 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 991 "frame done"); 992 break; 993 994 case DPU_ENC_RC_EVENT_PRE_STOP: 995 /* cancel delayed off work, if any */ 996 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work)) 997 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n", 998 sw_event); 999 1000 mutex_lock(&dpu_enc->rc_lock); 1001 1002 if (is_vid_mode && 1003 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) { 1004 _dpu_encoder_irq_enable(drm_enc); 1005 } 1006 /* skip if is already OFF or IDLE, resources are off already */ 1007 else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF || 1008 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) { 1009 DRM_DEBUG_KMS("id:%u, sw_event:%d, rc in %d state\n", 1010 DRMID(drm_enc), sw_event, 1011 dpu_enc->rc_state); 1012 mutex_unlock(&dpu_enc->rc_lock); 1013 return 0; 1014 } 1015 1016 dpu_enc->rc_state = DPU_ENC_RC_STATE_PRE_OFF; 1017 1018 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 1019 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 1020 "pre stop"); 1021 1022 mutex_unlock(&dpu_enc->rc_lock); 1023 break; 1024 1025 case DPU_ENC_RC_EVENT_STOP: 1026 mutex_lock(&dpu_enc->rc_lock); 1027 1028 /* return if the resource control is already in OFF state */ 1029 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF) { 1030 DRM_DEBUG_KMS("id: %u, sw_event:%d, rc in OFF state\n", 1031 DRMID(drm_enc), sw_event); 1032 mutex_unlock(&dpu_enc->rc_lock); 1033 return 0; 1034 } else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) { 1035 DRM_ERROR("id: %u, sw_event:%d, rc in state %d\n", 1036 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 1037 mutex_unlock(&dpu_enc->rc_lock); 1038 return -EINVAL; 1039 } 1040 1041 /** 1042 * expect to arrive here only if in either idle state or pre-off 1043 * and in IDLE state the resources are already disabled 1044 */ 1045 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_PRE_OFF) 1046 _dpu_encoder_resource_disable(drm_enc); 1047 1048 dpu_enc->rc_state = DPU_ENC_RC_STATE_OFF; 1049 1050 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 1051 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 1052 "stop"); 1053 1054 mutex_unlock(&dpu_enc->rc_lock); 1055 break; 1056 1057 case DPU_ENC_RC_EVENT_ENTER_IDLE: 1058 mutex_lock(&dpu_enc->rc_lock); 1059 1060 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) { 1061 DRM_ERROR("id: %u, sw_event:%d, rc:%d !ON state\n", 1062 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 1063 mutex_unlock(&dpu_enc->rc_lock); 1064 return 0; 1065 } 1066 1067 /* 1068 * if we are in ON but a frame was just kicked off, 1069 * ignore the IDLE event, it's probably a stale timer event 1070 */ 1071 if (dpu_enc->frame_busy_mask[0]) { 1072 DRM_ERROR("id:%u, sw_event:%d, rc:%d frame pending\n", 1073 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 1074 mutex_unlock(&dpu_enc->rc_lock); 1075 return 0; 1076 } 1077 1078 if (is_vid_mode) 1079 _dpu_encoder_irq_disable(drm_enc); 1080 else 1081 _dpu_encoder_resource_disable(drm_enc); 1082 1083 dpu_enc->rc_state = DPU_ENC_RC_STATE_IDLE; 1084 1085 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 1086 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 1087 "idle"); 1088 1089 mutex_unlock(&dpu_enc->rc_lock); 1090 break; 1091 1092 default: 1093 DRM_ERROR("id:%u, unexpected sw_event: %d\n", DRMID(drm_enc), 1094 sw_event); 1095 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 1096 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 1097 "error"); 1098 break; 1099 } 1100 1101 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 1102 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 1103 "end"); 1104 return 0; 1105 } 1106 1107 /** 1108 * dpu_encoder_prepare_wb_job - prepare writeback job for the encoder. 1109 * @drm_enc: Pointer to previously created drm encoder structure 1110 * @job: Pointer to the current drm writeback job 1111 */ 1112 void dpu_encoder_prepare_wb_job(struct drm_encoder *drm_enc, 1113 struct drm_writeback_job *job) 1114 { 1115 struct dpu_encoder_virt *dpu_enc; 1116 int i; 1117 1118 dpu_enc = to_dpu_encoder_virt(drm_enc); 1119 1120 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1121 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1122 1123 if (phys->ops.prepare_wb_job) 1124 phys->ops.prepare_wb_job(phys, job); 1125 1126 } 1127 } 1128 1129 /** 1130 * dpu_encoder_cleanup_wb_job - cleanup writeback job for the encoder. 1131 * @drm_enc: Pointer to previously created drm encoder structure 1132 * @job: Pointer to the current drm writeback job 1133 */ 1134 void dpu_encoder_cleanup_wb_job(struct drm_encoder *drm_enc, 1135 struct drm_writeback_job *job) 1136 { 1137 struct dpu_encoder_virt *dpu_enc; 1138 int i; 1139 1140 dpu_enc = to_dpu_encoder_virt(drm_enc); 1141 1142 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1143 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1144 1145 if (phys->ops.cleanup_wb_job) 1146 phys->ops.cleanup_wb_job(phys, job); 1147 1148 } 1149 } 1150 1151 static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, 1152 struct drm_crtc_state *crtc_state, 1153 struct drm_connector_state *conn_state) 1154 { 1155 struct dpu_encoder_virt *dpu_enc; 1156 struct msm_drm_private *priv; 1157 struct dpu_kms *dpu_kms; 1158 struct dpu_global_state *global_state; 1159 struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC]; 1160 struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC]; 1161 struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC]; 1162 struct dpu_hw_blk *hw_cwb[MAX_CHANNELS_PER_ENC]; 1163 int num_ctl, num_pp, num_dsc, num_pp_per_intf; 1164 int num_cwb = 0; 1165 bool is_cwb_encoder; 1166 unsigned int dsc_mask = 0; 1167 unsigned int cwb_mask = 0; 1168 int i; 1169 1170 if (!drm_enc) { 1171 DPU_ERROR("invalid encoder\n"); 1172 return; 1173 } 1174 1175 dpu_enc = to_dpu_encoder_virt(drm_enc); 1176 DPU_DEBUG_ENC(dpu_enc, "\n"); 1177 1178 priv = drm_enc->dev->dev_private; 1179 dpu_kms = to_dpu_kms(priv->kms); 1180 is_cwb_encoder = drm_crtc_in_clone_mode(crtc_state) && 1181 dpu_enc->disp_info.intf_type == INTF_WB; 1182 1183 global_state = dpu_kms_get_existing_global_state(dpu_kms); 1184 if (IS_ERR_OR_NULL(global_state)) { 1185 DPU_ERROR("Failed to get global state"); 1186 return; 1187 } 1188 1189 trace_dpu_enc_mode_set(DRMID(drm_enc)); 1190 1191 /* Query resource that have been reserved in atomic check step. */ 1192 if (is_cwb_encoder) { 1193 num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1194 drm_enc->crtc, 1195 DPU_HW_BLK_DCWB_PINGPONG, 1196 hw_pp, ARRAY_SIZE(hw_pp)); 1197 num_cwb = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1198 drm_enc->crtc, 1199 DPU_HW_BLK_CWB, 1200 hw_cwb, ARRAY_SIZE(hw_cwb)); 1201 } else { 1202 num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1203 drm_enc->crtc, 1204 DPU_HW_BLK_PINGPONG, hw_pp, 1205 ARRAY_SIZE(hw_pp)); 1206 } 1207 1208 for (i = 0; i < num_cwb; i++) { 1209 dpu_enc->hw_cwb[i] = to_dpu_hw_cwb(hw_cwb[i]); 1210 cwb_mask |= BIT(dpu_enc->hw_cwb[i]->idx - CWB_0); 1211 } 1212 1213 dpu_enc->cwb_mask = cwb_mask; 1214 1215 num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1216 drm_enc->crtc, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); 1217 1218 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) 1219 dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i]) 1220 : NULL; 1221 1222 num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1223 drm_enc->crtc, DPU_HW_BLK_DSC, 1224 hw_dsc, ARRAY_SIZE(hw_dsc)); 1225 for (i = 0; i < num_dsc; i++) { 1226 dpu_enc->hw_dsc[i] = to_dpu_hw_dsc(hw_dsc[i]); 1227 dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0); 1228 } 1229 1230 dpu_enc->dsc_mask = dsc_mask; 1231 1232 if ((dpu_enc->disp_info.intf_type == INTF_WB && conn_state->writeback_job) || 1233 dpu_enc->disp_info.intf_type == INTF_DP) { 1234 struct dpu_hw_blk *hw_cdm = NULL; 1235 1236 dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1237 drm_enc->crtc, DPU_HW_BLK_CDM, 1238 &hw_cdm, 1); 1239 dpu_enc->cur_master->hw_cdm = hw_cdm ? to_dpu_hw_cdm(hw_cdm) : NULL; 1240 } 1241 1242 /* 1243 * There may be 4 PP and 2 INTF for quad pipe case, so INTF is not 1244 * mapped to PP 1:1. Let's calculate the stride with pipe/INTF 1245 */ 1246 num_pp_per_intf = num_pp / dpu_enc->num_phys_encs; 1247 1248 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1249 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1250 1251 phys->hw_pp = dpu_enc->hw_pp[num_pp_per_intf * i]; 1252 if (!phys->hw_pp) { 1253 DPU_ERROR_ENC(dpu_enc, 1254 "no pp block assigned at idx: %d\n", i); 1255 return; 1256 } 1257 1258 /* Use first (and only) CTL if active CTLs are supported */ 1259 if (num_ctl == 1) 1260 phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[0]); 1261 else 1262 phys->hw_ctl = i < num_ctl ? to_dpu_hw_ctl(hw_ctl[i]) : NULL; 1263 if (!phys->hw_ctl) { 1264 DPU_ERROR_ENC(dpu_enc, 1265 "no ctl block assigned at idx: %d\n", i); 1266 return; 1267 } 1268 1269 phys->cached_mode = crtc_state->adjusted_mode; 1270 if (phys->ops.atomic_mode_set) 1271 phys->ops.atomic_mode_set(phys, crtc_state, conn_state); 1272 } 1273 } 1274 1275 static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc) 1276 { 1277 struct dpu_encoder_virt *dpu_enc = NULL; 1278 int i; 1279 1280 if (!drm_enc || !drm_enc->dev) { 1281 DPU_ERROR("invalid parameters\n"); 1282 return; 1283 } 1284 1285 dpu_enc = to_dpu_encoder_virt(drm_enc); 1286 if (!dpu_enc || !dpu_enc->cur_master) { 1287 DPU_ERROR("invalid dpu encoder/master\n"); 1288 return; 1289 } 1290 1291 1292 if (dpu_enc->disp_info.intf_type == INTF_DP && 1293 dpu_enc->cur_master->hw_mdptop && 1294 dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select) 1295 dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select( 1296 dpu_enc->cur_master->hw_mdptop); 1297 1298 if (dpu_enc->disp_info.is_cmd_mode) 1299 _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info); 1300 1301 if (dpu_enc->disp_info.intf_type == INTF_DSI && 1302 !WARN_ON(dpu_enc->num_phys_encs == 0)) { 1303 unsigned bpc = dpu_enc->connector->display_info.bpc; 1304 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) { 1305 if (!dpu_enc->hw_pp[i]) 1306 continue; 1307 _dpu_encoder_setup_dither(dpu_enc->hw_pp[i], bpc); 1308 } 1309 } 1310 } 1311 1312 /** 1313 * dpu_encoder_virt_runtime_resume - pm runtime resume the encoder configs 1314 * @drm_enc: encoder pointer 1315 */ 1316 void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc) 1317 { 1318 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1319 1320 mutex_lock(&dpu_enc->enc_lock); 1321 1322 if (!dpu_enc->enabled) 1323 goto out; 1324 1325 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.restore) 1326 dpu_enc->cur_slave->ops.restore(dpu_enc->cur_slave); 1327 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.restore) 1328 dpu_enc->cur_master->ops.restore(dpu_enc->cur_master); 1329 1330 _dpu_encoder_virt_enable_helper(drm_enc); 1331 1332 out: 1333 mutex_unlock(&dpu_enc->enc_lock); 1334 } 1335 1336 static void dpu_encoder_virt_atomic_enable(struct drm_encoder *drm_enc, 1337 struct drm_atomic_commit *state) 1338 { 1339 struct dpu_encoder_virt *dpu_enc = NULL; 1340 int ret = 0; 1341 struct drm_display_mode *cur_mode = NULL; 1342 1343 dpu_enc = to_dpu_encoder_virt(drm_enc); 1344 dpu_enc->dsc = dpu_encoder_get_dsc_config(drm_enc); 1345 1346 atomic_set(&dpu_enc->frame_done_timeout_cnt, 0); 1347 1348 mutex_lock(&dpu_enc->enc_lock); 1349 1350 dpu_enc->commit_done_timedout = false; 1351 1352 dpu_enc->connector = drm_atomic_get_new_connector_for_encoder(state, drm_enc); 1353 1354 cur_mode = &dpu_enc->base.crtc->state->adjusted_mode; 1355 1356 dpu_enc->wide_bus_en = dpu_encoder_is_widebus_enabled(drm_enc); 1357 1358 trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay, 1359 cur_mode->vdisplay); 1360 1361 /* always enable slave encoder before master */ 1362 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.enable) 1363 dpu_enc->cur_slave->ops.enable(dpu_enc->cur_slave); 1364 1365 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.enable) 1366 dpu_enc->cur_master->ops.enable(dpu_enc->cur_master); 1367 1368 ret = dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF); 1369 if (ret) { 1370 DPU_ERROR_ENC(dpu_enc, "dpu resource control failed: %d\n", 1371 ret); 1372 goto out; 1373 } 1374 1375 _dpu_encoder_virt_enable_helper(drm_enc); 1376 1377 dpu_enc->enabled = true; 1378 1379 out: 1380 mutex_unlock(&dpu_enc->enc_lock); 1381 } 1382 1383 static void dpu_encoder_virt_atomic_disable(struct drm_encoder *drm_enc, 1384 struct drm_atomic_commit *state) 1385 { 1386 struct dpu_encoder_virt *dpu_enc = NULL; 1387 struct drm_crtc *crtc; 1388 struct drm_crtc_state *old_state = NULL; 1389 1390 dpu_enc = to_dpu_encoder_virt(drm_enc); 1391 DPU_DEBUG_ENC(dpu_enc, "\n"); 1392 1393 crtc = drm_atomic_get_old_crtc_for_encoder(state, drm_enc); 1394 if (crtc) 1395 old_state = drm_atomic_get_old_crtc_state(state, crtc); 1396 1397 /* 1398 * The encoder is already disabled if self refresh mode was set earlier, 1399 * in the old_state for the corresponding crtc. 1400 */ 1401 if (old_state && old_state->self_refresh_active) 1402 return; 1403 1404 mutex_lock(&dpu_enc->enc_lock); 1405 dpu_enc->enabled = false; 1406 1407 trace_dpu_enc_disable(DRMID(drm_enc)); 1408 1409 /* wait for idle */ 1410 dpu_encoder_wait_for_tx_complete(drm_enc); 1411 1412 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP); 1413 1414 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.disable) 1415 dpu_enc->cur_slave->ops.disable(dpu_enc->cur_slave); 1416 1417 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.disable) 1418 dpu_enc->cur_master->ops.disable(dpu_enc->cur_master); 1419 1420 1421 /* after phys waits for frame-done, should be no more frames pending */ 1422 if (atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) { 1423 DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id); 1424 timer_delete_sync(&dpu_enc->frame_done_timer); 1425 } 1426 1427 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_STOP); 1428 1429 dpu_enc->connector = NULL; 1430 1431 DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n"); 1432 1433 mutex_unlock(&dpu_enc->enc_lock); 1434 } 1435 1436 static struct dpu_hw_intf *dpu_encoder_get_intf(const struct dpu_mdss_cfg *catalog, 1437 struct dpu_rm *dpu_rm, 1438 enum dpu_intf_type type, u32 controller_id) 1439 { 1440 int i = 0; 1441 1442 if (type == INTF_WB) 1443 return NULL; 1444 1445 for (i = 0; i < catalog->intf_count; i++) { 1446 if (catalog->intf[i].type == type 1447 && catalog->intf[i].controller_id == controller_id) { 1448 return dpu_rm_get_intf(dpu_rm, catalog->intf[i].id); 1449 } 1450 } 1451 1452 return NULL; 1453 } 1454 1455 /** 1456 * dpu_encoder_vblank_callback - Notify virtual encoder of vblank IRQ reception 1457 * @drm_enc: Pointer to drm encoder structure 1458 * @phy_enc: Pointer to physical encoder 1459 * Note: This is called from IRQ handler context. 1460 */ 1461 void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc, 1462 struct dpu_encoder_phys *phy_enc) 1463 { 1464 struct dpu_encoder_virt *dpu_enc = NULL; 1465 unsigned long lock_flags; 1466 1467 if (!drm_enc || !phy_enc) 1468 return; 1469 1470 DPU_ATRACE_BEGIN("encoder_vblank_callback"); 1471 dpu_enc = to_dpu_encoder_virt(drm_enc); 1472 1473 atomic_inc(&phy_enc->vsync_cnt); 1474 1475 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1476 if (dpu_enc->crtc) 1477 dpu_crtc_vblank_callback(dpu_enc->crtc); 1478 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1479 1480 DPU_ATRACE_END("encoder_vblank_callback"); 1481 } 1482 1483 /** 1484 * dpu_encoder_underrun_callback - Notify virtual encoder of underrun IRQ reception 1485 * @drm_enc: Pointer to drm encoder structure 1486 * @phy_enc: Pointer to physical encoder 1487 * Note: This is called from IRQ handler context. 1488 */ 1489 void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc, 1490 struct dpu_encoder_phys *phy_enc) 1491 { 1492 if (!phy_enc) 1493 return; 1494 1495 DPU_ATRACE_BEGIN("encoder_underrun_callback"); 1496 atomic_inc(&phy_enc->underrun_cnt); 1497 1498 /* trigger dump only on the first underrun */ 1499 if (atomic_read(&phy_enc->underrun_cnt) == 1) 1500 msm_disp_snapshot_state(drm_enc->dev); 1501 1502 trace_dpu_enc_underrun_cb(DRMID(drm_enc), 1503 atomic_read(&phy_enc->underrun_cnt)); 1504 DPU_ATRACE_END("encoder_underrun_callback"); 1505 } 1506 1507 /** 1508 * dpu_encoder_assign_crtc - Link the encoder to the crtc it's assigned to 1509 * @drm_enc: encoder pointer 1510 * @crtc: crtc pointer 1511 */ 1512 void dpu_encoder_assign_crtc(struct drm_encoder *drm_enc, struct drm_crtc *crtc) 1513 { 1514 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1515 unsigned long lock_flags; 1516 1517 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1518 /* crtc should always be cleared before re-assigning */ 1519 WARN_ON(crtc && dpu_enc->crtc); 1520 dpu_enc->crtc = crtc; 1521 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1522 } 1523 1524 /** 1525 * dpu_encoder_toggle_vblank_for_crtc - Toggles vblank interrupts on or off if 1526 * the encoder is assigned to the given crtc 1527 * @drm_enc: encoder pointer 1528 * @crtc: crtc pointer 1529 * @enable: true if vblank should be enabled 1530 */ 1531 void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *drm_enc, 1532 struct drm_crtc *crtc, bool enable) 1533 { 1534 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1535 unsigned long lock_flags; 1536 int i; 1537 1538 trace_dpu_enc_vblank_cb(DRMID(drm_enc), enable); 1539 1540 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1541 if (dpu_enc->crtc != crtc) { 1542 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1543 return; 1544 } 1545 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1546 1547 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1548 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1549 1550 if (phys->ops.control_vblank_irq) 1551 phys->ops.control_vblank_irq(phys, enable); 1552 } 1553 } 1554 1555 /** 1556 * dpu_encoder_frame_done_callback - Notify virtual encoder that this phys 1557 * encoder completes last request frame 1558 * @drm_enc: Pointer to drm encoder structure 1559 * @ready_phys: Pointer to physical encoder 1560 * @event: Event to process 1561 */ 1562 void dpu_encoder_frame_done_callback( 1563 struct drm_encoder *drm_enc, 1564 struct dpu_encoder_phys *ready_phys, u32 event) 1565 { 1566 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1567 unsigned int i; 1568 1569 if (event & (DPU_ENCODER_FRAME_EVENT_DONE 1570 | DPU_ENCODER_FRAME_EVENT_ERROR 1571 | DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) { 1572 1573 if (!dpu_enc->frame_busy_mask[0]) { 1574 /** 1575 * suppress frame_done without waiter, 1576 * likely autorefresh 1577 */ 1578 trace_dpu_enc_frame_done_cb_not_busy(DRMID(drm_enc), event, 1579 dpu_encoder_helper_get_intf_type(ready_phys->intf_mode), 1580 ready_phys->hw_intf ? ready_phys->hw_intf->idx : -1, 1581 ready_phys->hw_wb ? ready_phys->hw_wb->idx : -1); 1582 return; 1583 } 1584 1585 /* One of the physical encoders has become idle */ 1586 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1587 if (dpu_enc->phys_encs[i] == ready_phys) { 1588 trace_dpu_enc_frame_done_cb(DRMID(drm_enc), i, 1589 dpu_enc->frame_busy_mask[0]); 1590 clear_bit(i, dpu_enc->frame_busy_mask); 1591 } 1592 } 1593 1594 if (!dpu_enc->frame_busy_mask[0]) { 1595 atomic_set(&dpu_enc->frame_done_timeout_ms, 0); 1596 timer_delete(&dpu_enc->frame_done_timer); 1597 1598 dpu_encoder_resource_control(drm_enc, 1599 DPU_ENC_RC_EVENT_FRAME_DONE); 1600 1601 if (dpu_enc->crtc) 1602 dpu_crtc_frame_event_cb(dpu_enc->crtc, event); 1603 } 1604 } else { 1605 if (dpu_enc->crtc) 1606 dpu_crtc_frame_event_cb(dpu_enc->crtc, event); 1607 } 1608 } 1609 1610 static void dpu_encoder_off_work(struct work_struct *work) 1611 { 1612 struct dpu_encoder_virt *dpu_enc = container_of(work, 1613 struct dpu_encoder_virt, delayed_off_work.work); 1614 1615 dpu_encoder_resource_control(&dpu_enc->base, 1616 DPU_ENC_RC_EVENT_ENTER_IDLE); 1617 1618 dpu_encoder_frame_done_callback(&dpu_enc->base, NULL, 1619 DPU_ENCODER_FRAME_EVENT_IDLE); 1620 } 1621 1622 /** 1623 * _dpu_encoder_trigger_flush - trigger flush for a physical encoder 1624 * @drm_enc: Pointer to drm encoder structure 1625 * @phys: Pointer to physical encoder structure 1626 * @extra_flush_bits: Additional bit mask to include in flush trigger 1627 */ 1628 static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc, 1629 struct dpu_encoder_phys *phys, uint32_t extra_flush_bits) 1630 { 1631 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1632 struct dpu_hw_ctl *ctl; 1633 int pending_kickoff_cnt; 1634 u32 ret = UINT_MAX; 1635 1636 if (!phys->hw_pp) { 1637 DPU_ERROR("invalid pingpong hw\n"); 1638 return; 1639 } 1640 1641 ctl = phys->hw_ctl; 1642 if (!ctl->ops.trigger_flush) { 1643 DPU_ERROR("missing trigger cb\n"); 1644 return; 1645 } 1646 1647 pending_kickoff_cnt = dpu_encoder_phys_inc_pending(phys); 1648 1649 /* Return early if encoder is writeback and in clone mode */ 1650 if (drm_enc->encoder_type == DRM_MODE_ENCODER_VIRTUAL && 1651 dpu_enc->cwb_mask) { 1652 DPU_DEBUG("encoder %d skip flush for concurrent writeback encoder\n", 1653 DRMID(drm_enc)); 1654 return; 1655 } 1656 1657 1658 if (extra_flush_bits && ctl->ops.update_pending_flush) 1659 ctl->ops.update_pending_flush(ctl, extra_flush_bits); 1660 1661 ctl->ops.trigger_flush(ctl); 1662 1663 if (ctl->ops.get_pending_flush) 1664 ret = ctl->ops.get_pending_flush(ctl); 1665 1666 trace_dpu_enc_trigger_flush(DRMID(drm_enc), 1667 dpu_encoder_helper_get_intf_type(phys->intf_mode), 1668 phys->hw_intf ? phys->hw_intf->idx : -1, 1669 phys->hw_wb ? phys->hw_wb->idx : -1, 1670 pending_kickoff_cnt, ctl->idx, 1671 extra_flush_bits, ret); 1672 } 1673 1674 /** 1675 * _dpu_encoder_trigger_start - trigger start for a physical encoder 1676 * @phys: Pointer to physical encoder structure 1677 */ 1678 static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys) 1679 { 1680 struct dpu_encoder_virt *dpu_enc; 1681 1682 if (!phys) { 1683 DPU_ERROR("invalid argument(s)\n"); 1684 return; 1685 } 1686 1687 if (!phys->hw_pp) { 1688 DPU_ERROR("invalid pingpong hw\n"); 1689 return; 1690 } 1691 1692 dpu_enc = to_dpu_encoder_virt(phys->parent); 1693 1694 if (phys->parent->encoder_type == DRM_MODE_ENCODER_VIRTUAL && 1695 dpu_enc->cwb_mask) { 1696 DPU_DEBUG("encoder %d CWB enabled, skipping\n", DRMID(phys->parent)); 1697 return; 1698 } 1699 1700 if (phys->ops.trigger_start && phys->enable_state != DPU_ENC_DISABLED) 1701 phys->ops.trigger_start(phys); 1702 } 1703 1704 /** 1705 * dpu_encoder_helper_trigger_start - control start helper function 1706 * This helper function may be optionally specified by physical 1707 * encoders if they require ctl_start triggering. 1708 * @phys_enc: Pointer to physical encoder structure 1709 */ 1710 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc) 1711 { 1712 struct dpu_hw_ctl *ctl; 1713 1714 ctl = phys_enc->hw_ctl; 1715 if (ctl->ops.trigger_start) { 1716 ctl->ops.trigger_start(ctl); 1717 trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx); 1718 } 1719 } 1720 1721 static int dpu_encoder_helper_wait_event_timeout( 1722 int32_t drm_id, 1723 unsigned int irq_idx, 1724 struct dpu_encoder_wait_info *info) 1725 { 1726 int rc = 0; 1727 s64 expected_time = ktime_to_ms(ktime_get()) + info->timeout_ms; 1728 s64 jiffies = msecs_to_jiffies(info->timeout_ms); 1729 s64 time; 1730 1731 do { 1732 rc = wait_event_timeout(*(info->wq), 1733 atomic_read(info->atomic_cnt) == 0, jiffies); 1734 time = ktime_to_ms(ktime_get()); 1735 1736 trace_dpu_enc_wait_event_timeout(drm_id, 1737 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), 1738 rc, time, 1739 expected_time, 1740 atomic_read(info->atomic_cnt)); 1741 /* If we timed out, counter is valid and time is less, wait again */ 1742 } while (atomic_read(info->atomic_cnt) && (rc == 0) && 1743 (time < expected_time)); 1744 1745 return rc; 1746 } 1747 1748 static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc) 1749 { 1750 struct dpu_encoder_virt *dpu_enc; 1751 struct dpu_hw_ctl *ctl; 1752 int rc; 1753 struct drm_encoder *drm_enc; 1754 1755 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); 1756 ctl = phys_enc->hw_ctl; 1757 drm_enc = phys_enc->parent; 1758 1759 if (!ctl->ops.reset) 1760 return; 1761 1762 DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(drm_enc), 1763 ctl->idx); 1764 1765 rc = ctl->ops.reset(ctl); 1766 if (rc) { 1767 DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx); 1768 msm_disp_snapshot_state(drm_enc->dev); 1769 } 1770 1771 phys_enc->enable_state = DPU_ENC_ENABLED; 1772 } 1773 1774 /** 1775 * _dpu_encoder_kickoff_phys - handle physical encoder kickoff 1776 * Iterate through the physical encoders and perform consolidated flush 1777 * and/or control start triggering as needed. This is done in the virtual 1778 * encoder rather than the individual physical ones in order to handle 1779 * use cases that require visibility into multiple physical encoders at 1780 * a time. 1781 * @dpu_enc: Pointer to virtual encoder structure 1782 */ 1783 static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc) 1784 { 1785 struct dpu_hw_ctl *ctl; 1786 uint32_t i, pending_flush; 1787 unsigned long lock_flags; 1788 1789 pending_flush = 0x0; 1790 1791 /* update pending counts and trigger kickoff ctl flush atomically */ 1792 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1793 1794 /* don't perform flush/start operations for slave encoders */ 1795 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1796 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1797 1798 if (phys->enable_state == DPU_ENC_DISABLED) 1799 continue; 1800 1801 ctl = phys->hw_ctl; 1802 1803 /* 1804 * This is cleared in frame_done worker, which isn't invoked 1805 * for async commits. So don't set this for async, since it'll 1806 * roll over to the next commit. 1807 */ 1808 if (phys->split_role != ENC_ROLE_SLAVE) 1809 set_bit(i, dpu_enc->frame_busy_mask); 1810 1811 if (!phys->ops.needs_single_flush || 1812 !phys->ops.needs_single_flush(phys)) 1813 _dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0); 1814 else if (ctl->ops.get_pending_flush) 1815 pending_flush |= ctl->ops.get_pending_flush(ctl); 1816 } 1817 1818 /* for split flush, combine pending flush masks and send to master */ 1819 if (pending_flush && dpu_enc->cur_master) { 1820 _dpu_encoder_trigger_flush( 1821 &dpu_enc->base, 1822 dpu_enc->cur_master, 1823 pending_flush); 1824 } 1825 1826 _dpu_encoder_trigger_start(dpu_enc->cur_master); 1827 1828 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1829 } 1830 1831 /** 1832 * dpu_encoder_trigger_kickoff_pending - Clear the flush bits from previous 1833 * kickoff and trigger the ctl prepare progress for command mode display. 1834 * @drm_enc: encoder pointer 1835 */ 1836 void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc) 1837 { 1838 struct dpu_encoder_virt *dpu_enc; 1839 struct dpu_encoder_phys *phys; 1840 unsigned int i; 1841 struct dpu_hw_ctl *ctl; 1842 struct msm_display_info *disp_info; 1843 1844 if (!drm_enc) { 1845 DPU_ERROR("invalid encoder\n"); 1846 return; 1847 } 1848 dpu_enc = to_dpu_encoder_virt(drm_enc); 1849 disp_info = &dpu_enc->disp_info; 1850 1851 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1852 phys = dpu_enc->phys_encs[i]; 1853 1854 ctl = phys->hw_ctl; 1855 ctl->ops.clear_pending_flush(ctl); 1856 1857 /* update only for command mode primary ctl */ 1858 if ((phys == dpu_enc->cur_master) && 1859 disp_info->is_cmd_mode 1860 && ctl->ops.trigger_pending) 1861 ctl->ops.trigger_pending(ctl); 1862 } 1863 } 1864 1865 static u32 _dpu_encoder_calculate_linetime(struct dpu_encoder_virt *dpu_enc, 1866 struct drm_display_mode *mode) 1867 { 1868 u64 pclk_rate; 1869 u32 pclk_period; 1870 u32 line_time; 1871 1872 /* 1873 * For linetime calculation, only operate on master encoder. 1874 */ 1875 if (!dpu_enc->cur_master) 1876 return 0; 1877 1878 if (!dpu_enc->cur_master->ops.get_line_count) { 1879 DPU_ERROR("get_line_count function not defined\n"); 1880 return 0; 1881 } 1882 1883 pclk_rate = mode->clock; /* pixel clock in kHz */ 1884 if (pclk_rate == 0) { 1885 DPU_ERROR("pclk is 0, cannot calculate line time\n"); 1886 return 0; 1887 } 1888 1889 pclk_period = DIV_ROUND_UP_ULL(1000000000ull, pclk_rate); 1890 if (pclk_period == 0) { 1891 DPU_ERROR("pclk period is 0\n"); 1892 return 0; 1893 } 1894 1895 /* 1896 * Line time calculation based on Pixel clock and HTOTAL. 1897 * Final unit is in ns. 1898 */ 1899 line_time = (pclk_period * mode->htotal) / 1000; 1900 if (line_time == 0) { 1901 DPU_ERROR("line time calculation is 0\n"); 1902 return 0; 1903 } 1904 1905 DPU_DEBUG_ENC(dpu_enc, 1906 "clk_rate=%lldkHz, clk_period=%d, linetime=%dns\n", 1907 pclk_rate, pclk_period, line_time); 1908 1909 return line_time; 1910 } 1911 1912 /** 1913 * dpu_encoder_vsync_time - get the time of the next vsync 1914 * @drm_enc: encoder pointer 1915 * @wakeup_time: pointer to ktime_t to write the vsync time to 1916 */ 1917 int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time) 1918 { 1919 struct drm_display_mode *mode; 1920 struct dpu_encoder_virt *dpu_enc; 1921 u32 cur_line; 1922 u32 line_time; 1923 u32 vtotal, time_to_vsync; 1924 ktime_t cur_time; 1925 1926 dpu_enc = to_dpu_encoder_virt(drm_enc); 1927 1928 if (!drm_enc->crtc || !drm_enc->crtc->state) { 1929 DPU_ERROR("crtc/crtc state object is NULL\n"); 1930 return -EINVAL; 1931 } 1932 mode = &drm_enc->crtc->state->adjusted_mode; 1933 1934 line_time = _dpu_encoder_calculate_linetime(dpu_enc, mode); 1935 if (!line_time) 1936 return -EINVAL; 1937 1938 cur_line = dpu_enc->cur_master->ops.get_line_count(dpu_enc->cur_master); 1939 1940 vtotal = mode->vtotal; 1941 if (cur_line >= vtotal) 1942 time_to_vsync = line_time * vtotal; 1943 else 1944 time_to_vsync = line_time * (vtotal - cur_line); 1945 1946 if (time_to_vsync == 0) { 1947 DPU_ERROR("time to vsync should not be zero, vtotal=%d\n", 1948 vtotal); 1949 return -EINVAL; 1950 } 1951 1952 cur_time = ktime_get(); 1953 *wakeup_time = ktime_add_ns(cur_time, time_to_vsync); 1954 1955 DPU_DEBUG_ENC(dpu_enc, 1956 "cur_line=%u vtotal=%u time_to_vsync=%u, cur_time=%lld, wakeup_time=%lld\n", 1957 cur_line, vtotal, time_to_vsync, 1958 ktime_to_ms(cur_time), 1959 ktime_to_ms(*wakeup_time)); 1960 return 0; 1961 } 1962 1963 static u32 1964 dpu_encoder_dsc_initial_line_calc(struct drm_dsc_config *dsc, 1965 u32 enc_ip_width) 1966 { 1967 int ssm_delay, total_pixels, soft_slice_per_enc; 1968 1969 soft_slice_per_enc = enc_ip_width / dsc->slice_width; 1970 1971 /* 1972 * minimum number of initial line pixels is a sum of: 1973 * 1. sub-stream multiplexer delay (83 groups for 8bpc, 1974 * 91 for 10 bpc) * 3 1975 * 2. for two soft slice cases, add extra sub-stream multiplexer * 3 1976 * 3. the initial xmit delay 1977 * 4. total pipeline delay through the "lock step" of encoder (47) 1978 * 5. 6 additional pixels as the output of the rate buffer is 1979 * 48 bits wide 1980 */ 1981 ssm_delay = ((dsc->bits_per_component < 10) ? 84 : 92); 1982 total_pixels = ssm_delay * 3 + dsc->initial_xmit_delay + 47; 1983 if (soft_slice_per_enc > 1) 1984 total_pixels += (ssm_delay * 3); 1985 return DIV_ROUND_UP(total_pixels, dsc->slice_width); 1986 } 1987 1988 static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_ctl *ctl, 1989 struct dpu_hw_dsc *hw_dsc, 1990 struct dpu_hw_pingpong *hw_pp, 1991 struct drm_dsc_config *dsc, 1992 u32 common_mode, 1993 u32 initial_lines) 1994 { 1995 if (hw_dsc->ops.dsc_config) 1996 hw_dsc->ops.dsc_config(hw_dsc, dsc, common_mode, initial_lines); 1997 1998 if (hw_dsc->ops.dsc_config_thresh) 1999 hw_dsc->ops.dsc_config_thresh(hw_dsc, dsc); 2000 2001 if (hw_pp->ops.setup_dsc) 2002 hw_pp->ops.setup_dsc(hw_pp); 2003 2004 if (hw_dsc->ops.dsc_bind_pingpong_blk) 2005 hw_dsc->ops.dsc_bind_pingpong_blk(hw_dsc, hw_pp->idx); 2006 2007 if (hw_pp->ops.enable_dsc) 2008 hw_pp->ops.enable_dsc(hw_pp); 2009 2010 if (ctl->ops.update_pending_flush_dsc) 2011 ctl->ops.update_pending_flush_dsc(ctl, hw_dsc->idx); 2012 } 2013 2014 static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc, 2015 struct drm_dsc_config *dsc) 2016 { 2017 struct dpu_encoder_phys *enc_master = dpu_enc->cur_master; 2018 struct dpu_hw_ctl *ctl = enc_master->hw_ctl; 2019 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC]; 2020 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; 2021 int this_frame_slices; 2022 int intf_ip_w, enc_ip_w; 2023 int dsc_common_mode; 2024 int pic_width; 2025 u32 initial_lines; 2026 int num_dsc = 0; 2027 int i; 2028 2029 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) { 2030 hw_pp[i] = dpu_enc->hw_pp[i]; 2031 hw_dsc[i] = dpu_enc->hw_dsc[i]; 2032 2033 if (!hw_pp[i] || !hw_dsc[i]) 2034 break; 2035 2036 num_dsc++; 2037 } 2038 2039 pic_width = dsc->pic_width; 2040 2041 dsc_common_mode = 0; 2042 if (num_dsc > 1) 2043 dsc_common_mode |= DSC_MODE_SPLIT_PANEL; 2044 if (dpu_encoder_use_dsc_merge(enc_master->parent)) 2045 dsc_common_mode |= DSC_MODE_MULTIPLEX; 2046 if (enc_master->intf_mode == INTF_MODE_VIDEO) 2047 dsc_common_mode |= DSC_MODE_VIDEO; 2048 2049 this_frame_slices = pic_width / dsc->slice_width; 2050 intf_ip_w = this_frame_slices * dsc->slice_width; 2051 2052 enc_ip_w = intf_ip_w / num_dsc; 2053 initial_lines = dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w); 2054 2055 for (i = 0; i < num_dsc; i++) 2056 dpu_encoder_dsc_pipe_cfg(ctl, hw_dsc[i], hw_pp[i], 2057 dsc, dsc_common_mode, initial_lines); 2058 } 2059 2060 /** 2061 * dpu_encoder_prepare_for_kickoff - schedule double buffer flip of the ctl 2062 * path (i.e. ctl flush and start) at next appropriate time. 2063 * Immediately: if no previous commit is outstanding. 2064 * Delayed: Block until next trigger can be issued. 2065 * @drm_enc: encoder pointer 2066 */ 2067 void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc) 2068 { 2069 struct dpu_encoder_virt *dpu_enc; 2070 struct dpu_encoder_phys *phys; 2071 bool needs_hw_reset = false; 2072 unsigned int i; 2073 2074 dpu_enc = to_dpu_encoder_virt(drm_enc); 2075 2076 trace_dpu_enc_prepare_kickoff(DRMID(drm_enc)); 2077 2078 /* prepare for next kickoff, may include waiting on previous kickoff */ 2079 DPU_ATRACE_BEGIN("enc_prepare_for_kickoff"); 2080 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2081 phys = dpu_enc->phys_encs[i]; 2082 if (phys->ops.prepare_for_kickoff) 2083 phys->ops.prepare_for_kickoff(phys); 2084 if (phys->enable_state == DPU_ENC_ERR_NEEDS_HW_RESET) 2085 needs_hw_reset = true; 2086 } 2087 DPU_ATRACE_END("enc_prepare_for_kickoff"); 2088 2089 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF); 2090 2091 /* if any phys needs reset, reset all phys, in-order */ 2092 if (needs_hw_reset) { 2093 trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc)); 2094 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2095 dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]); 2096 } 2097 } 2098 2099 if (dpu_enc->dsc) 2100 dpu_encoder_prep_dsc(dpu_enc, dpu_enc->dsc); 2101 } 2102 2103 /** 2104 * dpu_encoder_is_valid_for_commit - check if encode has valid parameters for commit. 2105 * @drm_enc: Pointer to drm encoder structure 2106 */ 2107 bool dpu_encoder_is_valid_for_commit(struct drm_encoder *drm_enc) 2108 { 2109 struct dpu_encoder_virt *dpu_enc; 2110 unsigned int i; 2111 struct dpu_encoder_phys *phys; 2112 2113 dpu_enc = to_dpu_encoder_virt(drm_enc); 2114 2115 if (drm_enc->encoder_type == DRM_MODE_ENCODER_VIRTUAL) { 2116 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2117 phys = dpu_enc->phys_encs[i]; 2118 if (phys->ops.is_valid_for_commit && !phys->ops.is_valid_for_commit(phys)) { 2119 DPU_DEBUG("invalid FB not kicking off\n"); 2120 return false; 2121 } 2122 } 2123 } 2124 2125 return true; 2126 } 2127 2128 /** 2129 * dpu_encoder_start_frame_done_timer - Start the encoder frame done timer 2130 * @drm_enc: Pointer to drm encoder structure 2131 */ 2132 void dpu_encoder_start_frame_done_timer(struct drm_encoder *drm_enc) 2133 { 2134 struct dpu_encoder_virt *dpu_enc; 2135 unsigned long timeout_ms; 2136 2137 dpu_enc = to_dpu_encoder_virt(drm_enc); 2138 timeout_ms = DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES * 1000 / 2139 drm_mode_vrefresh(&drm_enc->crtc->state->adjusted_mode); 2140 2141 atomic_set(&dpu_enc->frame_done_timeout_ms, timeout_ms); 2142 mod_timer(&dpu_enc->frame_done_timer, 2143 jiffies + msecs_to_jiffies(timeout_ms)); 2144 2145 } 2146 2147 /** 2148 * dpu_encoder_kickoff - trigger a double buffer flip of the ctl path 2149 * (i.e. ctl flush and start) immediately. 2150 * @drm_enc: encoder pointer 2151 */ 2152 void dpu_encoder_kickoff(struct drm_encoder *drm_enc) 2153 { 2154 struct dpu_encoder_virt *dpu_enc; 2155 struct dpu_encoder_phys *phys; 2156 unsigned int i; 2157 2158 DPU_ATRACE_BEGIN("encoder_kickoff"); 2159 dpu_enc = to_dpu_encoder_virt(drm_enc); 2160 2161 trace_dpu_enc_kickoff(DRMID(drm_enc)); 2162 2163 /* All phys encs are ready to go, trigger the kickoff */ 2164 _dpu_encoder_kickoff_phys(dpu_enc); 2165 2166 /* allow phys encs to handle any post-kickoff business */ 2167 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2168 phys = dpu_enc->phys_encs[i]; 2169 if (phys->ops.handle_post_kickoff) 2170 phys->ops.handle_post_kickoff(phys); 2171 } 2172 2173 DPU_ATRACE_END("encoder_kickoff"); 2174 } 2175 2176 static void dpu_encoder_helper_reset_mixers(struct dpu_encoder_phys *phys_enc) 2177 { 2178 int i, num_lm; 2179 struct dpu_global_state *global_state; 2180 struct dpu_hw_blk *hw_lm[2]; 2181 struct dpu_hw_mixer *hw_mixer[2]; 2182 struct dpu_hw_ctl *ctl = phys_enc->hw_ctl; 2183 2184 /* reset all mixers for this encoder */ 2185 if (ctl->ops.clear_all_blendstages) 2186 ctl->ops.clear_all_blendstages(ctl); 2187 2188 global_state = dpu_kms_get_existing_global_state(phys_enc->dpu_kms); 2189 2190 num_lm = dpu_rm_get_assigned_resources(&phys_enc->dpu_kms->rm, global_state, 2191 phys_enc->parent->crtc, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); 2192 2193 for (i = 0; i < num_lm; i++) { 2194 hw_mixer[i] = to_dpu_hw_mixer(hw_lm[i]); 2195 if (ctl->ops.update_pending_flush_mixer) 2196 ctl->ops.update_pending_flush_mixer(ctl, hw_mixer[i]->idx); 2197 2198 /* clear all blendstages */ 2199 if (ctl->ops.setup_blendstage) 2200 ctl->ops.setup_blendstage(ctl, hw_mixer[i]->idx, NULL); 2201 2202 if (hw_mixer[i]->ops.clear_all_blendstages) 2203 hw_mixer[i]->ops.clear_all_blendstages(hw_mixer[i]); 2204 2205 if (ctl->ops.set_active_lms) 2206 ctl->ops.set_active_lms(ctl, NULL); 2207 2208 if (ctl->ops.set_active_fetch_pipes) 2209 ctl->ops.set_active_fetch_pipes(ctl, NULL); 2210 2211 if (ctl->ops.set_active_pipes) 2212 ctl->ops.set_active_pipes(ctl, NULL); 2213 } 2214 } 2215 2216 static void dpu_encoder_dsc_pipe_clr(struct dpu_hw_ctl *ctl, 2217 struct dpu_hw_dsc *hw_dsc, 2218 struct dpu_hw_pingpong *hw_pp) 2219 { 2220 if (hw_dsc->ops.dsc_disable) 2221 hw_dsc->ops.dsc_disable(hw_dsc); 2222 2223 if (hw_pp->ops.disable_dsc) 2224 hw_pp->ops.disable_dsc(hw_pp); 2225 2226 if (hw_dsc->ops.dsc_bind_pingpong_blk) 2227 hw_dsc->ops.dsc_bind_pingpong_blk(hw_dsc, PINGPONG_NONE); 2228 2229 if (ctl->ops.update_pending_flush_dsc) 2230 ctl->ops.update_pending_flush_dsc(ctl, hw_dsc->idx); 2231 } 2232 2233 static void dpu_encoder_unprep_dsc(struct dpu_encoder_virt *dpu_enc) 2234 { 2235 /* coding only for 2LM, 2enc, 1 dsc config */ 2236 struct dpu_encoder_phys *enc_master = dpu_enc->cur_master; 2237 struct dpu_hw_ctl *ctl = enc_master->hw_ctl; 2238 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC]; 2239 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; 2240 int i; 2241 2242 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) { 2243 hw_pp[i] = dpu_enc->hw_pp[i]; 2244 hw_dsc[i] = dpu_enc->hw_dsc[i]; 2245 2246 if (hw_pp[i] && hw_dsc[i]) 2247 dpu_encoder_dsc_pipe_clr(ctl, hw_dsc[i], hw_pp[i]); 2248 } 2249 } 2250 2251 /** 2252 * dpu_encoder_helper_phys_cleanup - helper to cleanup dpu pipeline 2253 * @phys_enc: Pointer to physical encoder structure 2254 */ 2255 void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc) 2256 { 2257 struct dpu_hw_ctl *ctl = phys_enc->hw_ctl; 2258 struct dpu_hw_intf_cfg intf_cfg = { 0 }; 2259 int i; 2260 struct dpu_encoder_virt *dpu_enc; 2261 2262 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); 2263 2264 ctl->ops.reset(ctl); 2265 2266 dpu_encoder_helper_reset_mixers(phys_enc); 2267 2268 /* 2269 * TODO: move the once-only operation like CTL flush/trigger 2270 * into dpu_encoder_virt_disable() and all operations which need 2271 * to be done per phys encoder into the phys_disable() op. 2272 */ 2273 if (phys_enc->hw_wb) { 2274 /* disable the PP block */ 2275 if (phys_enc->hw_wb->ops.bind_pingpong_blk) 2276 phys_enc->hw_wb->ops.bind_pingpong_blk(phys_enc->hw_wb, PINGPONG_NONE); 2277 2278 /* mark WB flush as pending */ 2279 if (ctl->ops.update_pending_flush_wb) 2280 ctl->ops.update_pending_flush_wb(ctl, phys_enc->hw_wb->idx); 2281 } else { 2282 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2283 if (dpu_enc->phys_encs[i] && phys_enc->hw_intf->ops.bind_pingpong_blk) 2284 phys_enc->hw_intf->ops.bind_pingpong_blk( 2285 dpu_enc->phys_encs[i]->hw_intf, 2286 PINGPONG_NONE); 2287 2288 /* mark INTF flush as pending */ 2289 if (ctl->ops.update_pending_flush_intf) 2290 ctl->ops.update_pending_flush_intf(ctl, 2291 dpu_enc->phys_encs[i]->hw_intf->idx); 2292 } 2293 } 2294 2295 if (phys_enc->hw_pp && phys_enc->hw_pp->ops.setup_dither) 2296 phys_enc->hw_pp->ops.setup_dither(phys_enc->hw_pp, NULL); 2297 2298 if (dpu_enc->cwb_mask) 2299 dpu_encoder_helper_phys_setup_cwb(phys_enc, false); 2300 2301 /* reset the merge 3D HW block */ 2302 if (phys_enc->hw_pp && phys_enc->hw_pp->merge_3d) { 2303 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, 2304 BLEND_3D_NONE); 2305 if (ctl->ops.update_pending_flush_merge_3d) 2306 ctl->ops.update_pending_flush_merge_3d(ctl, 2307 phys_enc->hw_pp->merge_3d->idx); 2308 } 2309 2310 if (phys_enc->hw_cdm) { 2311 if (phys_enc->hw_cdm->ops.bind_pingpong_blk && phys_enc->hw_pp) 2312 phys_enc->hw_cdm->ops.bind_pingpong_blk(phys_enc->hw_cdm, 2313 PINGPONG_NONE); 2314 if (ctl->ops.update_pending_flush_cdm) 2315 ctl->ops.update_pending_flush_cdm(ctl, 2316 phys_enc->hw_cdm->idx); 2317 } 2318 2319 if (dpu_enc->dsc) { 2320 dpu_encoder_unprep_dsc(dpu_enc); 2321 dpu_enc->dsc = NULL; 2322 } 2323 2324 intf_cfg.stream_sel = 0; /* Don't care value for video mode */ 2325 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); 2326 intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); 2327 intf_cfg.cwb = dpu_enc->cwb_mask; 2328 2329 if (phys_enc->hw_intf) 2330 intf_cfg.intf = phys_enc->hw_intf->idx; 2331 if (phys_enc->hw_wb) 2332 intf_cfg.wb = phys_enc->hw_wb->idx; 2333 2334 if (phys_enc->hw_pp && phys_enc->hw_pp->merge_3d) 2335 intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx; 2336 2337 if (ctl->ops.reset_intf_cfg) 2338 ctl->ops.reset_intf_cfg(ctl, &intf_cfg); 2339 2340 ctl->ops.trigger_flush(ctl); 2341 ctl->ops.trigger_start(ctl); 2342 ctl->ops.clear_pending_flush(ctl); 2343 } 2344 2345 void dpu_encoder_helper_phys_setup_cwb(struct dpu_encoder_phys *phys_enc, 2346 bool enable) 2347 { 2348 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(phys_enc->parent); 2349 struct dpu_hw_cwb *hw_cwb; 2350 struct dpu_hw_ctl *hw_ctl; 2351 struct dpu_hw_cwb_setup_cfg cwb_cfg; 2352 2353 struct dpu_kms *dpu_kms; 2354 struct dpu_global_state *global_state; 2355 struct dpu_hw_blk *rt_pp_list[MAX_CHANNELS_PER_ENC]; 2356 int num_pp; 2357 2358 if (!phys_enc->hw_wb) 2359 return; 2360 2361 hw_ctl = phys_enc->hw_ctl; 2362 2363 if (!phys_enc->hw_ctl) { 2364 DPU_DEBUG("[wb:%d] no ctl assigned\n", 2365 phys_enc->hw_wb->idx - WB_0); 2366 return; 2367 } 2368 2369 dpu_kms = phys_enc->dpu_kms; 2370 global_state = dpu_kms_get_existing_global_state(dpu_kms); 2371 num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 2372 phys_enc->parent->crtc, 2373 DPU_HW_BLK_PINGPONG, rt_pp_list, 2374 ARRAY_SIZE(rt_pp_list)); 2375 2376 if (num_pp == 0 || num_pp > MAX_CHANNELS_PER_ENC) { 2377 DPU_DEBUG_ENC(dpu_enc, "invalid num_pp %d\n", num_pp); 2378 return; 2379 } 2380 2381 /* 2382 * The CWB mux supports using LM or DSPP as tap points. For now, 2383 * always use LM tap point 2384 */ 2385 cwb_cfg.input = INPUT_MODE_LM_OUT; 2386 2387 for (int i = 0; i < MAX_CWB_PER_ENC; i++) { 2388 hw_cwb = dpu_enc->hw_cwb[i]; 2389 if (!hw_cwb) 2390 continue; 2391 2392 if (enable) { 2393 struct dpu_hw_pingpong *hw_pp = 2394 to_dpu_hw_pingpong(rt_pp_list[i]); 2395 cwb_cfg.pp_idx = hw_pp->idx; 2396 } else { 2397 cwb_cfg.pp_idx = PINGPONG_NONE; 2398 } 2399 2400 hw_cwb->ops.config_cwb(hw_cwb, &cwb_cfg); 2401 2402 if (hw_ctl->ops.update_pending_flush_cwb) 2403 hw_ctl->ops.update_pending_flush_cwb(hw_ctl, hw_cwb->idx); 2404 } 2405 } 2406 2407 /** 2408 * dpu_encoder_helper_phys_setup_cdm - setup chroma down sampling block 2409 * @phys_enc: Pointer to physical encoder 2410 * @dpu_fmt: Pinter to the format description 2411 * @output_type: HDMI/WB 2412 */ 2413 void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc, 2414 const struct msm_format *dpu_fmt, 2415 u32 output_type) 2416 { 2417 struct dpu_hw_cdm *hw_cdm; 2418 struct dpu_hw_cdm_cfg *cdm_cfg; 2419 struct dpu_hw_pingpong *hw_pp; 2420 int ret; 2421 2422 if (!phys_enc) 2423 return; 2424 2425 cdm_cfg = &phys_enc->cdm_cfg; 2426 hw_pp = phys_enc->hw_pp; 2427 hw_cdm = phys_enc->hw_cdm; 2428 2429 if (!hw_cdm) 2430 return; 2431 2432 if (!MSM_FORMAT_IS_YUV(dpu_fmt)) { 2433 DPU_DEBUG("[enc:%d] cdm_disable fmt:%p4cc\n", DRMID(phys_enc->parent), 2434 &dpu_fmt->pixel_format); 2435 if (hw_cdm->ops.bind_pingpong_blk) 2436 hw_cdm->ops.bind_pingpong_blk(hw_cdm, PINGPONG_NONE); 2437 2438 return; 2439 } 2440 2441 memset(cdm_cfg, 0, sizeof(struct dpu_hw_cdm_cfg)); 2442 2443 cdm_cfg->output_width = phys_enc->cached_mode.hdisplay; 2444 cdm_cfg->output_height = phys_enc->cached_mode.vdisplay; 2445 cdm_cfg->output_fmt = dpu_fmt; 2446 cdm_cfg->output_type = output_type; 2447 cdm_cfg->output_bit_depth = MSM_FORMAT_IS_DX(dpu_fmt) ? 2448 CDM_CDWN_OUTPUT_10BIT : CDM_CDWN_OUTPUT_8BIT; 2449 cdm_cfg->csc_cfg = &dpu_csc10_rgb2yuv_601l; 2450 2451 /* enable 10 bit logic */ 2452 switch (cdm_cfg->output_fmt->chroma_sample) { 2453 case CHROMA_FULL: 2454 cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE; 2455 cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE; 2456 break; 2457 case CHROMA_H2V1: 2458 cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE; 2459 cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE; 2460 break; 2461 case CHROMA_420: 2462 cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE; 2463 cdm_cfg->v_cdwn_type = CDM_CDWN_OFFSITE; 2464 break; 2465 case CHROMA_H1V2: 2466 default: 2467 DPU_ERROR("[enc:%d] unsupported chroma sampling type\n", 2468 DRMID(phys_enc->parent)); 2469 cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE; 2470 cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE; 2471 break; 2472 } 2473 2474 DPU_DEBUG("[enc:%d] cdm_enable:%d,%d,%p4cc,%d,%d,%d,%d]\n", 2475 DRMID(phys_enc->parent), cdm_cfg->output_width, 2476 cdm_cfg->output_height, &cdm_cfg->output_fmt->pixel_format, 2477 cdm_cfg->output_type, cdm_cfg->output_bit_depth, 2478 cdm_cfg->h_cdwn_type, cdm_cfg->v_cdwn_type); 2479 2480 if (hw_cdm->ops.enable) { 2481 cdm_cfg->pp_id = hw_pp->idx; 2482 ret = hw_cdm->ops.enable(hw_cdm, cdm_cfg); 2483 if (ret < 0) { 2484 DPU_ERROR("[enc:%d] failed to enable CDM; ret:%d\n", 2485 DRMID(phys_enc->parent), ret); 2486 return; 2487 } 2488 } 2489 } 2490 2491 #ifdef CONFIG_DEBUG_FS 2492 static int _dpu_encoder_status_show(struct seq_file *s, void *data) 2493 { 2494 struct drm_encoder *drm_enc = s->private; 2495 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 2496 int i; 2497 2498 mutex_lock(&dpu_enc->enc_lock); 2499 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2500 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 2501 2502 seq_printf(s, "intf:%d wb:%d vsync:%8d underrun:%8d frame_done_cnt:%d", 2503 phys->hw_intf ? phys->hw_intf->idx - INTF_0 : -1, 2504 phys->hw_wb ? phys->hw_wb->idx - WB_0 : -1, 2505 atomic_read(&phys->vsync_cnt), 2506 atomic_read(&phys->underrun_cnt), 2507 atomic_read(&dpu_enc->frame_done_timeout_cnt)); 2508 2509 seq_printf(s, "mode: %s\n", dpu_encoder_helper_get_intf_type(phys->intf_mode)); 2510 } 2511 mutex_unlock(&dpu_enc->enc_lock); 2512 2513 return 0; 2514 } 2515 2516 DEFINE_SHOW_ATTRIBUTE(_dpu_encoder_status); 2517 2518 static void dpu_encoder_debugfs_init(struct drm_encoder *drm_enc, struct dentry *root) 2519 { 2520 /* don't error check these */ 2521 debugfs_create_file("status", 0600, 2522 root, drm_enc, &_dpu_encoder_status_fops); 2523 } 2524 #else 2525 #define dpu_encoder_debugfs_init NULL 2526 #endif 2527 2528 static int dpu_encoder_virt_add_phys_encs( 2529 struct drm_device *dev, 2530 struct msm_display_info *disp_info, 2531 struct dpu_encoder_virt *dpu_enc, 2532 struct dpu_enc_phys_init_params *params) 2533 { 2534 struct dpu_encoder_phys *enc = NULL; 2535 2536 DPU_DEBUG_ENC(dpu_enc, "\n"); 2537 2538 /* 2539 * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types 2540 * in this function, check up-front. 2541 */ 2542 if (dpu_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >= 2543 ARRAY_SIZE(dpu_enc->phys_encs)) { 2544 DPU_ERROR_ENC(dpu_enc, "too many physical encoders %d\n", 2545 dpu_enc->num_phys_encs); 2546 return -EINVAL; 2547 } 2548 2549 2550 if (disp_info->intf_type == INTF_WB) { 2551 enc = dpu_encoder_phys_wb_init(dev, params); 2552 2553 if (IS_ERR(enc)) { 2554 DPU_ERROR_ENC(dpu_enc, "failed to init wb enc: %ld\n", 2555 PTR_ERR(enc)); 2556 return PTR_ERR(enc); 2557 } 2558 2559 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; 2560 ++dpu_enc->num_phys_encs; 2561 } else if (disp_info->is_cmd_mode) { 2562 enc = dpu_encoder_phys_cmd_init(dev, params); 2563 2564 if (IS_ERR(enc)) { 2565 DPU_ERROR_ENC(dpu_enc, "failed to init cmd enc: %ld\n", 2566 PTR_ERR(enc)); 2567 return PTR_ERR(enc); 2568 } 2569 2570 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; 2571 ++dpu_enc->num_phys_encs; 2572 } else { 2573 enc = dpu_encoder_phys_vid_init(dev, params); 2574 2575 if (IS_ERR(enc)) { 2576 DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n", 2577 PTR_ERR(enc)); 2578 return PTR_ERR(enc); 2579 } 2580 2581 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; 2582 ++dpu_enc->num_phys_encs; 2583 } 2584 2585 if (params->split_role == ENC_ROLE_SLAVE) 2586 dpu_enc->cur_slave = enc; 2587 else 2588 dpu_enc->cur_master = enc; 2589 2590 return 0; 2591 } 2592 2593 /** 2594 * dpu_encoder_get_clones - Calculate the possible_clones for DPU encoder 2595 * @drm_enc: DRM encoder pointer 2596 * Returns: possible_clones mask 2597 */ 2598 uint32_t dpu_encoder_get_clones(struct drm_encoder *drm_enc) 2599 { 2600 struct drm_encoder *curr; 2601 int type = drm_enc->encoder_type; 2602 uint32_t clone_mask = drm_encoder_mask(drm_enc); 2603 2604 /* 2605 * Set writeback as possible clones of real-time DSI encoders and vice 2606 * versa 2607 * 2608 * Writeback encoders can't be clones of each other and DSI 2609 * encoders can't be clones of each other. 2610 * 2611 * TODO: Add DP encoders as valid possible clones for writeback encoders 2612 * (and vice versa) once concurrent writeback has been validated for DP 2613 */ 2614 drm_for_each_encoder(curr, drm_enc->dev) { 2615 if ((type == DRM_MODE_ENCODER_VIRTUAL && 2616 curr->encoder_type == DRM_MODE_ENCODER_DSI) || 2617 (type == DRM_MODE_ENCODER_DSI && 2618 curr->encoder_type == DRM_MODE_ENCODER_VIRTUAL)) 2619 clone_mask |= drm_encoder_mask(curr); 2620 } 2621 2622 return clone_mask; 2623 } 2624 2625 static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, 2626 struct dpu_kms *dpu_kms, 2627 struct msm_display_info *disp_info) 2628 { 2629 int ret = 0; 2630 int i = 0; 2631 struct dpu_enc_phys_init_params phys_params; 2632 2633 if (!dpu_enc) { 2634 DPU_ERROR("invalid arg(s), enc %d\n", dpu_enc != NULL); 2635 return -EINVAL; 2636 } 2637 2638 dpu_enc->cur_master = NULL; 2639 2640 memset(&phys_params, 0, sizeof(phys_params)); 2641 phys_params.dpu_kms = dpu_kms; 2642 phys_params.parent = &dpu_enc->base; 2643 phys_params.enc_spinlock = &dpu_enc->enc_spinlock; 2644 2645 WARN_ON(disp_info->num_of_h_tiles < 1); 2646 2647 DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles); 2648 2649 if (disp_info->intf_type != INTF_WB) 2650 dpu_enc->idle_pc_supported = 2651 dpu_kms->catalog->caps->has_idle_pc; 2652 2653 mutex_lock(&dpu_enc->enc_lock); 2654 for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) { 2655 /* 2656 * Left-most tile is at index 0, content is controller id 2657 * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right 2658 * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right 2659 */ 2660 u32 controller_id = disp_info->h_tile_instance[i]; 2661 2662 if (disp_info->num_of_h_tiles > 1) { 2663 if (i == 0) 2664 phys_params.split_role = ENC_ROLE_MASTER; 2665 else 2666 phys_params.split_role = ENC_ROLE_SLAVE; 2667 } else { 2668 phys_params.split_role = ENC_ROLE_SOLO; 2669 } 2670 2671 DPU_DEBUG("h_tile_instance %d = %d, split_role %d\n", 2672 i, controller_id, phys_params.split_role); 2673 2674 phys_params.hw_intf = dpu_encoder_get_intf(dpu_kms->catalog, &dpu_kms->rm, 2675 disp_info->intf_type, 2676 controller_id); 2677 2678 if (disp_info->intf_type == INTF_WB && controller_id < WB_MAX) 2679 phys_params.hw_wb = dpu_rm_get_wb(&dpu_kms->rm, controller_id); 2680 2681 if (!phys_params.hw_intf && !phys_params.hw_wb) { 2682 DPU_ERROR_ENC(dpu_enc, "no intf or wb block assigned at idx: %d\n", i); 2683 ret = -EINVAL; 2684 break; 2685 } 2686 2687 if (phys_params.hw_intf && phys_params.hw_wb) { 2688 DPU_ERROR_ENC(dpu_enc, 2689 "invalid phys both intf and wb block at idx: %d\n", i); 2690 ret = -EINVAL; 2691 break; 2692 } 2693 2694 ret = dpu_encoder_virt_add_phys_encs(dpu_kms->dev, disp_info, 2695 dpu_enc, &phys_params); 2696 if (ret) { 2697 DPU_ERROR_ENC(dpu_enc, "failed to add phys encs\n"); 2698 break; 2699 } 2700 } 2701 2702 mutex_unlock(&dpu_enc->enc_lock); 2703 2704 return ret; 2705 } 2706 2707 static void dpu_encoder_frame_done_timeout(struct timer_list *t) 2708 { 2709 struct dpu_encoder_virt *dpu_enc = timer_container_of(dpu_enc, t, 2710 frame_done_timer); 2711 struct drm_encoder *drm_enc = &dpu_enc->base; 2712 u32 event; 2713 2714 if (!drm_enc->dev) { 2715 DPU_ERROR("invalid parameters\n"); 2716 return; 2717 } 2718 2719 if (!dpu_enc->frame_busy_mask[0] || !dpu_enc->crtc) { 2720 DRM_DEBUG_KMS("id:%u invalid timeout frame_busy_mask=%lu\n", 2721 DRMID(drm_enc), dpu_enc->frame_busy_mask[0]); 2722 return; 2723 } else if (!atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) { 2724 DRM_DEBUG_KMS("id:%u invalid timeout\n", DRMID(drm_enc)); 2725 return; 2726 } 2727 2728 DPU_ERROR_ENC_RATELIMITED(dpu_enc, "frame done timeout\n"); 2729 2730 if (atomic_inc_return(&dpu_enc->frame_done_timeout_cnt) == 1) 2731 msm_disp_snapshot_state(drm_enc->dev); 2732 2733 event = DPU_ENCODER_FRAME_EVENT_ERROR; 2734 trace_dpu_enc_frame_done_timeout(DRMID(drm_enc), event); 2735 dpu_crtc_frame_event_cb(dpu_enc->crtc, event); 2736 } 2737 2738 static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = { 2739 .atomic_mode_set = dpu_encoder_virt_atomic_mode_set, 2740 .atomic_disable = dpu_encoder_virt_atomic_disable, 2741 .atomic_enable = dpu_encoder_virt_atomic_enable, 2742 }; 2743 2744 static const struct drm_encoder_funcs dpu_encoder_funcs = { 2745 .debugfs_init = dpu_encoder_debugfs_init, 2746 }; 2747 2748 /** 2749 * dpu_encoder_init - initialize virtual encoder object 2750 * @dev: Pointer to drm device structure 2751 * @drm_enc_mode: corresponding DRM_MODE_ENCODER_* constant 2752 * @disp_info: Pointer to display information structure 2753 * Returns: Pointer to newly created drm encoder 2754 */ 2755 struct drm_encoder *dpu_encoder_init(struct drm_device *dev, 2756 int drm_enc_mode, 2757 struct msm_display_info *disp_info) 2758 { 2759 struct msm_drm_private *priv = dev->dev_private; 2760 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); 2761 struct dpu_encoder_virt *dpu_enc; 2762 int ret; 2763 2764 dpu_enc = drmm_encoder_alloc(dev, struct dpu_encoder_virt, base, 2765 &dpu_encoder_funcs, drm_enc_mode, NULL); 2766 if (IS_ERR(dpu_enc)) 2767 return ERR_CAST(dpu_enc); 2768 2769 drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs); 2770 2771 spin_lock_init(&dpu_enc->enc_spinlock); 2772 dpu_enc->enabled = false; 2773 mutex_init(&dpu_enc->enc_lock); 2774 mutex_init(&dpu_enc->rc_lock); 2775 2776 ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info); 2777 if (ret) { 2778 DPU_ERROR("failed to setup encoder\n"); 2779 return ERR_PTR(-ENOMEM); 2780 } 2781 2782 atomic_set(&dpu_enc->frame_done_timeout_ms, 0); 2783 atomic_set(&dpu_enc->frame_done_timeout_cnt, 0); 2784 timer_setup(&dpu_enc->frame_done_timer, 2785 dpu_encoder_frame_done_timeout, 0); 2786 2787 INIT_DELAYED_WORK(&dpu_enc->delayed_off_work, 2788 dpu_encoder_off_work); 2789 dpu_enc->idle_timeout = IDLE_TIMEOUT; 2790 2791 memcpy(&dpu_enc->disp_info, disp_info, sizeof(*disp_info)); 2792 2793 DPU_DEBUG_ENC(dpu_enc, "created\n"); 2794 2795 return &dpu_enc->base; 2796 } 2797 2798 /** 2799 * dpu_encoder_wait_for_commit_done() - Wait for encoder to flush pending state 2800 * @drm_enc: encoder pointer 2801 * 2802 * Wait for hardware to have flushed the current pending changes to hardware at 2803 * a vblank or CTL_START. Physical encoders will map this differently depending 2804 * on the type: vid mode -> vsync_irq, cmd mode -> CTL_START. 2805 * 2806 * Return: 0 on success, -EWOULDBLOCK if already signaled, error otherwise 2807 */ 2808 int dpu_encoder_wait_for_commit_done(struct drm_encoder *drm_enc) 2809 { 2810 struct dpu_encoder_virt *dpu_enc = NULL; 2811 int i, ret = 0; 2812 2813 if (!drm_enc) { 2814 DPU_ERROR("invalid encoder\n"); 2815 return -EINVAL; 2816 } 2817 dpu_enc = to_dpu_encoder_virt(drm_enc); 2818 DPU_DEBUG_ENC(dpu_enc, "\n"); 2819 2820 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2821 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 2822 2823 if (phys->ops.wait_for_commit_done) { 2824 DPU_ATRACE_BEGIN("wait_for_commit_done"); 2825 ret = phys->ops.wait_for_commit_done(phys); 2826 DPU_ATRACE_END("wait_for_commit_done"); 2827 if (ret == -ETIMEDOUT && !dpu_enc->commit_done_timedout) { 2828 dpu_enc->commit_done_timedout = true; 2829 msm_disp_snapshot_state(drm_enc->dev); 2830 } 2831 if (ret) 2832 return ret; 2833 } 2834 } 2835 2836 return ret; 2837 } 2838 2839 /** 2840 * dpu_encoder_wait_for_tx_complete() - Wait for encoder to transfer pixels to panel 2841 * @drm_enc: encoder pointer 2842 * 2843 * Wait for the hardware to transfer all the pixels to the panel. Physical 2844 * encoders will map this differently depending on the type: vid mode -> vsync_irq, 2845 * cmd mode -> pp_done. 2846 * 2847 * Return: 0 on success, -EWOULDBLOCK if already signaled, error otherwise 2848 */ 2849 int dpu_encoder_wait_for_tx_complete(struct drm_encoder *drm_enc) 2850 { 2851 struct dpu_encoder_virt *dpu_enc = NULL; 2852 int i, ret = 0; 2853 2854 if (!drm_enc) { 2855 DPU_ERROR("invalid encoder\n"); 2856 return -EINVAL; 2857 } 2858 dpu_enc = to_dpu_encoder_virt(drm_enc); 2859 DPU_DEBUG_ENC(dpu_enc, "\n"); 2860 2861 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2862 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 2863 2864 if (phys->ops.wait_for_tx_complete) { 2865 DPU_ATRACE_BEGIN("wait_for_tx_complete"); 2866 ret = phys->ops.wait_for_tx_complete(phys); 2867 DPU_ATRACE_END("wait_for_tx_complete"); 2868 if (ret) 2869 return ret; 2870 } 2871 } 2872 2873 return ret; 2874 } 2875 2876 /** 2877 * dpu_encoder_get_intf_mode - get interface mode of the given encoder 2878 * @encoder: Pointer to drm encoder object 2879 */ 2880 enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder) 2881 { 2882 struct dpu_encoder_virt *dpu_enc = NULL; 2883 2884 if (!encoder) { 2885 DPU_ERROR("invalid encoder\n"); 2886 return INTF_MODE_NONE; 2887 } 2888 dpu_enc = to_dpu_encoder_virt(encoder); 2889 2890 if (dpu_enc->cur_master) 2891 return dpu_enc->cur_master->intf_mode; 2892 2893 if (dpu_enc->num_phys_encs) 2894 return dpu_enc->phys_encs[0]->intf_mode; 2895 2896 return INTF_MODE_NONE; 2897 } 2898 2899 /** 2900 * dpu_encoder_helper_get_cwb_mask - get CWB blocks mask for the DPU encoder 2901 * @phys_enc: Pointer to physical encoder structure 2902 */ 2903 unsigned int dpu_encoder_helper_get_cwb_mask(struct dpu_encoder_phys *phys_enc) 2904 { 2905 struct drm_encoder *encoder = phys_enc->parent; 2906 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder); 2907 2908 return dpu_enc->cwb_mask; 2909 } 2910 2911 /** 2912 * dpu_encoder_helper_get_dsc - get DSC blocks mask for the DPU encoder 2913 * This helper function is used by physical encoder to get DSC blocks mask 2914 * used for this encoder. 2915 * @phys_enc: Pointer to physical encoder structure 2916 */ 2917 unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc) 2918 { 2919 struct drm_encoder *encoder = phys_enc->parent; 2920 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder); 2921 2922 return dpu_enc->dsc_mask; 2923 } 2924 2925 void dpu_encoder_phys_init(struct dpu_encoder_phys *phys_enc, 2926 struct dpu_enc_phys_init_params *p) 2927 { 2928 phys_enc->hw_mdptop = p->dpu_kms->hw_mdp; 2929 phys_enc->hw_intf = p->hw_intf; 2930 phys_enc->hw_wb = p->hw_wb; 2931 phys_enc->parent = p->parent; 2932 phys_enc->dpu_kms = p->dpu_kms; 2933 phys_enc->split_role = p->split_role; 2934 phys_enc->enc_spinlock = p->enc_spinlock; 2935 phys_enc->enable_state = DPU_ENC_DISABLED; 2936 2937 atomic_set(&phys_enc->pending_kickoff_cnt, 0); 2938 atomic_set(&phys_enc->pending_ctlstart_cnt, 0); 2939 2940 atomic_set(&phys_enc->vsync_cnt, 0); 2941 atomic_set(&phys_enc->underrun_cnt, 0); 2942 2943 init_waitqueue_head(&phys_enc->pending_kickoff_wq); 2944 } 2945