1// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 2/* 3 * Copyright (c) 2021-2024, Arm Limited. All rights reserved. 4 */ 5 6/dts-v1/; 7#include "morello.dtsi" 8 9/ { 10 model = "Arm Morello System Development Platform"; 11 compatible = "arm,morello-sdp", "arm,morello"; 12 13 aliases { 14 serial0 = &uart0; 15 }; 16 17 chosen { 18 stdout-path = "serial0:115200n8"; 19 }; 20 21 dpu_aclk: clock-350000000 { 22 /* 77.1 MHz derived from 24 MHz reference clock */ 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <350000000>; 26 clock-output-names = "aclk"; 27 }; 28 29 dpu_pixel_clk: clock-148500000 { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <148500000>; 33 clock-output-names = "pxclk"; 34 }; 35 36 i2c0: i2c@1c0f0000 { 37 compatible = "cdns,i2c-r1p14"; 38 reg = <0x0 0x1c0f0000 0x0 0x1000>; 39 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 40 clocks = <&dpu_aclk>; 41 42 #address-cells = <1>; 43 #size-cells = <0>; 44 45 clock-frequency = <100000>; 46 47 hdmi_tx: hdmi-transmitter@70 { 48 compatible = "nxp,tda998x"; 49 reg = <0x70>; 50 video-ports = <0x234501>; 51 port { 52 tda998x_0_input: endpoint { 53 remote-endpoint = <&dp_pl0_out0>; 54 }; 55 }; 56 }; 57 }; 58 59 dp0: display@2cc00000 { 60 compatible = "arm,mali-d32", "arm,mali-d71"; 61 reg = <0x0 0x2cc00000 0x0 0x20000>; 62 interrupts = <0 69 4>; 63 clocks = <&dpu_aclk>; 64 clock-names = "aclk"; 65 iommus = <&smmu_dp 0>, <&smmu_dp 1>, <&smmu_dp 2>, <&smmu_dp 3>, 66 <&smmu_dp 8>; 67 68 #address-cells = <1>; 69 #size-cells = <0>; 70 71 pl0: pipeline@0 { 72 reg = <0>; 73 clocks = <&dpu_pixel_clk>; 74 clock-names = "pxclk"; 75 port { 76 dp_pl0_out0: endpoint { 77 remote-endpoint = <&tda998x_0_input>; 78 }; 79 }; 80 }; 81 }; 82 83 smmu_ccix: iommu@4f000000 { 84 compatible = "arm,smmu-v3"; 85 reg = <0x0 0x4f000000 0x0 0x40000>; 86 87 interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>, 88 <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>, 89 <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>, 90 <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>; 91 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 92 msi-parent = <&its1 0>; 93 #iommu-cells = <1>; 94 dma-coherent; 95 }; 96 97 smmu_pcie: iommu@4f400000 { 98 compatible = "arm,smmu-v3"; 99 reg = <0x0 0x4f400000 0x0 0x40000>; 100 101 interrupts = <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>, 102 <GIC_SPI 237 IRQ_TYPE_EDGE_RISING>, 103 <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>, 104 <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>; 105 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 106 msi-parent = <&its2 0>; 107 #iommu-cells = <1>; 108 dma-coherent; 109 }; 110 111 pcie_ctlr: pcie@28c0000000 { 112 device_type = "pci"; 113 compatible = "pci-host-ecam-generic"; 114 reg = <0x28 0xC0000000 0 0x10000000>; 115 ranges = <0x01000000 0x00 0x00000000 0x00 0x6f000000 0x00 0x00800000>, 116 <0x02000000 0x00 0x60000000 0x00 0x60000000 0x00 0x0f000000>, 117 <0x42000000 0x09 0x00000000 0x09 0x00000000 0x1f 0xc0000000>; 118 bus-range = <0 255>; 119 linux,pci-domain = <0>; 120 #address-cells = <3>; 121 #size-cells = <2>; 122 dma-coherent; 123 #interrupt-cells = <1>; 124 interrupt-map-mask = <0 0 0 7>; 125 interrupt-map = <0 0 0 1 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>, 126 <0 0 0 2 &gic 0 0 0 170 IRQ_TYPE_LEVEL_HIGH>, 127 <0 0 0 3 &gic 0 0 0 171 IRQ_TYPE_LEVEL_HIGH>, 128 <0 0 0 4 &gic 0 0 0 172 IRQ_TYPE_LEVEL_HIGH>; 129 msi-map = <0 &its_pcie 0 0x10000>; 130 iommu-map = <0 &smmu_pcie 0 0x10000>; 131 }; 132 133 ccix_pcie_ctlr: pcie@4fc0000000 { 134 device_type = "pci"; 135 compatible = "pci-host-ecam-generic"; 136 reg = <0x4f 0xC0000000 0 0x10000000>; 137 ranges = <0x01000000 0x00 0x00000000 0x00 0x7f000000 0x00 0x00800000>, 138 <0x02000000 0x00 0x70000000 0x00 0x70000000 0x00 0x0f000000>, 139 <0x42000000 0x30 0x00000000 0x30 0x00000000 0x1f 0xc0000000>; 140 linux,pci-domain = <1>; 141 #address-cells = <3>; 142 #size-cells = <2>; 143 dma-coherent; 144 #interrupt-cells = <1>; 145 interrupt-map-mask = <0 0 0 7>; 146 interrupt-map = <0 0 0 1 &gic 0 0 0 201 IRQ_TYPE_LEVEL_HIGH>, 147 <0 0 0 2 &gic 0 0 0 202 IRQ_TYPE_LEVEL_HIGH>, 148 <0 0 0 3 &gic 0 0 0 203 IRQ_TYPE_LEVEL_HIGH>, 149 <0 0 0 4 &gic 0 0 0 204 IRQ_TYPE_LEVEL_HIGH>; 150 msi-map = <0 &its_ccix 0 0x10000>; 151 iommu-map = <0 &smmu_ccix 0 0x10000>; 152 }; 153}; 154 155&uart0 { 156 status = "okay"; 157}; 158