1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "core_types.h"
28 #include "reg_helper.h"
29 #include "dcn30/dcn30_dpp.h"
30 #include "basics/conversion.h"
31 #include "dcn30/dcn30_cm_common.h"
32
33 #define REG(reg)\
34 dpp->tf_regs->reg
35
36 #define CTX \
37 dpp->base.ctx
38
39 #undef FN
40 #define FN(reg_name, field_name) \
41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
42
43
dpp30_read_state(struct dpp * dpp_base,struct dcn_dpp_state * s)44 void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s)
45 {
46 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
47 uint32_t gamcor_lut_mode, rgam_lut_mode;
48
49 REG_GET(DPP_CONTROL,
50 DPP_CLOCK_ENABLE, &s->is_enabled);
51
52 // Pre-degamma (ROM)
53 REG_GET_2(PRE_DEGAM,
54 PRE_DEGAM_MODE, &s->pre_dgam_mode,
55 PRE_DEGAM_SELECT, &s->pre_dgam_select);
56
57 // Gamma Correction (RAM)
58 REG_GET(CM_GAMCOR_CONTROL,
59 CM_GAMCOR_MODE_CURRENT, &s->gamcor_mode);
60 if (s->gamcor_mode) {
61 REG_GET(CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT_CURRENT, &gamcor_lut_mode);
62 if (!gamcor_lut_mode)
63 s->gamcor_mode = LUT_RAM_A; // Otherwise, LUT_RAM_B
64 }
65
66 // Shaper LUT (RAM), 3D LUT (mode, bit-depth, size)
67 if (REG(CM_SHAPER_CONTROL))
68 REG_GET(CM_SHAPER_CONTROL, CM_SHAPER_LUT_MODE, &s->shaper_lut_mode);
69 if (REG(CM_3DLUT_MODE))
70 REG_GET(CM_3DLUT_MODE, CM_3DLUT_MODE_CURRENT, &s->lut3d_mode);
71 if (REG(CM_3DLUT_READ_WRITE_CONTROL))
72 REG_GET(CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_30BIT_EN, &s->lut3d_bit_depth);
73 if (REG(CM_3DLUT_MODE))
74 REG_GET(CM_3DLUT_MODE, CM_3DLUT_SIZE, &s->lut3d_size);
75
76 // Blend/Out Gamma (RAM)
77 if (REG(CM_BLNDGAM_CONTROL)) {
78 REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE_CURRENT, &s->rgam_lut_mode);
79 if (s->rgam_lut_mode) {
80 REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_SELECT_CURRENT, &rgam_lut_mode);
81 if (!rgam_lut_mode)
82 s->rgam_lut_mode = LUT_RAM_A; // Otherwise, LUT_RAM_B
83 }
84 }
85 }
86
87 /*program post scaler scs block in dpp CM*/
dpp3_program_post_csc(struct dpp * dpp_base,enum dc_color_space color_space,enum dcn10_input_csc_select input_select,const struct out_csc_color_matrix * tbl_entry)88 void dpp3_program_post_csc(
89 struct dpp *dpp_base,
90 enum dc_color_space color_space,
91 enum dcn10_input_csc_select input_select,
92 const struct out_csc_color_matrix *tbl_entry)
93 {
94 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
95 int i;
96 int arr_size = sizeof(dpp_input_csc_matrix)/sizeof(struct dpp_input_csc_matrix);
97 const uint16_t *regval = NULL;
98 uint32_t cur_select = 0;
99 enum dcn10_input_csc_select select;
100 struct color_matrices_reg gam_regs;
101
102 if (input_select == INPUT_CSC_SELECT_BYPASS) {
103 REG_SET(CM_POST_CSC_CONTROL, 0, CM_POST_CSC_MODE, 0);
104 return;
105 }
106
107 if (tbl_entry == NULL) {
108 for (i = 0; i < arr_size; i++)
109 if (dpp_input_csc_matrix[i].color_space == color_space) {
110 regval = dpp_input_csc_matrix[i].regval;
111 break;
112 }
113
114 if (regval == NULL) {
115 BREAK_TO_DEBUGGER();
116 return;
117 }
118 } else {
119 regval = tbl_entry->regval;
120 }
121
122 /* determine which CSC matrix (icsc or coma) we are using
123 * currently. select the alternate set to double buffer
124 * the CSC update so CSC is updated on frame boundary
125 */
126 REG_GET(CM_POST_CSC_CONTROL,
127 CM_POST_CSC_MODE_CURRENT, &cur_select);
128
129 if (cur_select != INPUT_CSC_SELECT_ICSC)
130 select = INPUT_CSC_SELECT_ICSC;
131 else
132 select = INPUT_CSC_SELECT_COMA;
133
134 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_POST_CSC_C11;
135 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_POST_CSC_C11;
136 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_POST_CSC_C12;
137 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_POST_CSC_C12;
138
139 if (select == INPUT_CSC_SELECT_ICSC) {
140
141 gam_regs.csc_c11_c12 = REG(CM_POST_CSC_C11_C12);
142 gam_regs.csc_c33_c34 = REG(CM_POST_CSC_C33_C34);
143
144 } else {
145
146 gam_regs.csc_c11_c12 = REG(CM_POST_CSC_B_C11_C12);
147 gam_regs.csc_c33_c34 = REG(CM_POST_CSC_B_C33_C34);
148
149 }
150
151 cm_helper_program_color_matrices(
152 dpp->base.ctx,
153 regval,
154 &gam_regs);
155
156 REG_SET(CM_POST_CSC_CONTROL, 0,
157 CM_POST_CSC_MODE, select);
158 }
159
160
161 /*CNVC degam unit has read only LUTs*/
dpp3_set_pre_degam(struct dpp * dpp_base,enum dc_transfer_func_predefined tr)162 void dpp3_set_pre_degam(struct dpp *dpp_base, enum dc_transfer_func_predefined tr)
163 {
164 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
165 int pre_degam_en = 1;
166 int degamma_lut_selection = 0;
167
168 switch (tr) {
169 case TRANSFER_FUNCTION_LINEAR:
170 case TRANSFER_FUNCTION_UNITY:
171 pre_degam_en = 0; //bypass
172 break;
173 case TRANSFER_FUNCTION_SRGB:
174 degamma_lut_selection = 0;
175 break;
176 case TRANSFER_FUNCTION_BT709:
177 degamma_lut_selection = 4;
178 break;
179 case TRANSFER_FUNCTION_PQ:
180 degamma_lut_selection = 5;
181 break;
182 case TRANSFER_FUNCTION_HLG:
183 degamma_lut_selection = 6;
184 break;
185 case TRANSFER_FUNCTION_GAMMA22:
186 degamma_lut_selection = 1;
187 break;
188 case TRANSFER_FUNCTION_GAMMA24:
189 degamma_lut_selection = 2;
190 break;
191 case TRANSFER_FUNCTION_GAMMA26:
192 degamma_lut_selection = 3;
193 break;
194 default:
195 pre_degam_en = 0;
196 break;
197 }
198
199 REG_SET_2(PRE_DEGAM, 0,
200 PRE_DEGAM_MODE, pre_degam_en,
201 PRE_DEGAM_SELECT, degamma_lut_selection);
202 }
203
dpp3_cnv_setup(struct dpp * dpp_base,enum surface_pixel_format format,enum expansion_mode mode,struct dc_csc_transform input_csc_color_matrix,enum dc_color_space input_color_space,struct cnv_alpha_2bit_lut * alpha_2bit_lut)204 void dpp3_cnv_setup (
205 struct dpp *dpp_base,
206 enum surface_pixel_format format,
207 enum expansion_mode mode,
208 struct dc_csc_transform input_csc_color_matrix,
209 enum dc_color_space input_color_space,
210 struct cnv_alpha_2bit_lut *alpha_2bit_lut)
211 {
212 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
213 uint32_t pixel_format = 0;
214 uint32_t alpha_en = 1;
215 enum dc_color_space color_space = COLOR_SPACE_SRGB;
216 enum dcn10_input_csc_select select = INPUT_CSC_SELECT_BYPASS;
217 bool force_disable_cursor = false;
218 uint32_t is_2bit = 0;
219 uint32_t alpha_plane_enable = 0;
220 uint32_t dealpha_en = 0, dealpha_ablnd_en = 0;
221 uint32_t realpha_en = 0, realpha_ablnd_en = 0;
222 struct out_csc_color_matrix tbl_entry;
223 int i;
224
225 REG_SET_2(FORMAT_CONTROL, 0,
226 CNVC_BYPASS, 0,
227 FORMAT_EXPANSION_MODE, mode);
228
229 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0);
230 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0);
231 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0);
232 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0);
233
234 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_R, 0);
235 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_G, 1);
236 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_B, 2);
237
238 switch (format) {
239 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
240 pixel_format = 1;
241 break;
242 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
243 pixel_format = 3;
244 alpha_en = 0;
245 break;
246 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
247 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
248 pixel_format = 8;
249 break;
250 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
251 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
252 pixel_format = 10;
253 is_2bit = 1;
254 break;
255 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
256 force_disable_cursor = false;
257 pixel_format = 65;
258 color_space = COLOR_SPACE_YCBCR709;
259 select = INPUT_CSC_SELECT_ICSC;
260 break;
261 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
262 force_disable_cursor = true;
263 pixel_format = 64;
264 color_space = COLOR_SPACE_YCBCR709;
265 select = INPUT_CSC_SELECT_ICSC;
266 break;
267 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
268 force_disable_cursor = true;
269 pixel_format = 67;
270 color_space = COLOR_SPACE_YCBCR709;
271 select = INPUT_CSC_SELECT_ICSC;
272 break;
273 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
274 force_disable_cursor = true;
275 pixel_format = 66;
276 color_space = COLOR_SPACE_YCBCR709;
277 select = INPUT_CSC_SELECT_ICSC;
278 break;
279 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
280 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
281 pixel_format = 26; /* ARGB16161616_UNORM */
282 break;
283 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
284 pixel_format = 24;
285 break;
286 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
287 pixel_format = 25;
288 break;
289 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:
290 pixel_format = 12;
291 color_space = COLOR_SPACE_YCBCR709;
292 select = INPUT_CSC_SELECT_ICSC;
293 break;
294 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
295 pixel_format = 112;
296 alpha_en = 0;
297 break;
298 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
299 pixel_format = 113;
300 alpha_en = 0;
301 break;
302 case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:
303 pixel_format = 114;
304 color_space = COLOR_SPACE_YCBCR709;
305 select = INPUT_CSC_SELECT_ICSC;
306 is_2bit = 1;
307 break;
308 case SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102:
309 pixel_format = 115;
310 color_space = COLOR_SPACE_YCBCR709;
311 select = INPUT_CSC_SELECT_ICSC;
312 is_2bit = 1;
313 break;
314 case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
315 pixel_format = 116;
316 alpha_plane_enable = 0;
317 break;
318 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
319 pixel_format = 116;
320 alpha_plane_enable = 1;
321 break;
322 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
323 pixel_format = 118;
324 alpha_en = 0;
325 break;
326 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
327 pixel_format = 119;
328 alpha_en = 0;
329 break;
330 default:
331 break;
332 }
333
334 /* Set default color space based on format if none is given. */
335 color_space = input_color_space ? input_color_space : color_space;
336
337 if (is_2bit == 1 && alpha_2bit_lut != NULL) {
338 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
339 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);
340 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2);
341 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3);
342 }
343
344 REG_SET_2(CNVC_SURFACE_PIXEL_FORMAT, 0,
345 CNVC_SURFACE_PIXEL_FORMAT, pixel_format,
346 CNVC_ALPHA_PLANE_ENABLE, alpha_plane_enable);
347 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
348
349 REG_SET_2(PRE_DEALPHA, 0,
350 PRE_DEALPHA_EN, dealpha_en,
351 PRE_DEALPHA_ABLND_EN, dealpha_ablnd_en);
352 REG_SET_2(PRE_REALPHA, 0,
353 PRE_REALPHA_EN, realpha_en,
354 PRE_REALPHA_ABLND_EN, realpha_ablnd_en);
355
356 /* If input adjustment exists, program the ICSC with those values. */
357 if (input_csc_color_matrix.enable_adjustment == true) {
358 for (i = 0; i < 12; i++)
359 tbl_entry.regval[i] = input_csc_color_matrix.matrix[i];
360
361 tbl_entry.color_space = input_color_space;
362
363 if (color_space >= COLOR_SPACE_YCBCR601)
364 select = INPUT_CSC_SELECT_ICSC;
365 else
366 select = INPUT_CSC_SELECT_BYPASS;
367
368 dpp3_program_post_csc(dpp_base, color_space, select,
369 &tbl_entry);
370 } else {
371 dpp3_program_post_csc(dpp_base, color_space, select, NULL);
372 }
373
374 if (force_disable_cursor) {
375 REG_UPDATE(CURSOR_CONTROL,
376 CURSOR_ENABLE, 0);
377 REG_UPDATE(CURSOR0_CONTROL,
378 CUR0_ENABLE, 0);
379 }
380 }
381
382 #define IDENTITY_RATIO(ratio) (dc_fixpt_u3d19(ratio) == (1 << 19))
383
dpp3_set_cursor_attributes(struct dpp * dpp_base,struct dc_cursor_attributes * cursor_attributes)384 void dpp3_set_cursor_attributes(
385 struct dpp *dpp_base,
386 struct dc_cursor_attributes *cursor_attributes)
387 {
388 enum dc_cursor_color_format color_format = cursor_attributes->color_format;
389 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
390 int cur_rom_en = 0;
391
392 if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA ||
393 color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) {
394 if (cursor_attributes->attribute_flags.bits.ENABLE_CURSOR_DEGAMMA) {
395 cur_rom_en = 1;
396 }
397 }
398
399 REG_UPDATE_3(CURSOR0_CONTROL,
400 CUR0_MODE, color_format,
401 CUR0_EXPANSION_MODE, 0,
402 CUR0_ROM_EN, cur_rom_en);
403
404 if (color_format == CURSOR_MODE_MONO) {
405 /* todo: clarify what to program these to */
406 REG_UPDATE(CURSOR0_COLOR0,
407 CUR0_COLOR0, 0x00000000);
408 REG_UPDATE(CURSOR0_COLOR1,
409 CUR0_COLOR1, 0xFFFFFFFF);
410 }
411
412 dpp_base->att.cur0_ctl.bits.expansion_mode = 0;
413 dpp_base->att.cur0_ctl.bits.cur0_rom_en = cur_rom_en;
414 dpp_base->att.cur0_ctl.bits.mode = color_format;
415 }
416
417
dpp3_get_optimal_number_of_taps(struct dpp * dpp,struct scaler_data * scl_data,const struct scaling_taps * in_taps)418 bool dpp3_get_optimal_number_of_taps(
419 struct dpp *dpp,
420 struct scaler_data *scl_data,
421 const struct scaling_taps *in_taps)
422 {
423 int num_part_y, num_part_c;
424 int max_taps_y, max_taps_c;
425 int min_taps_y, min_taps_c;
426 enum lb_memory_config lb_config;
427
428 /*
429 * Set default taps if none are provided
430 * From programming guide: taps = min{ ceil(2*H_RATIO,1), 8} for downscaling
431 * taps = 4 for upscaling
432 */
433 if (in_taps->h_taps == 0) {
434 if (dc_fixpt_ceil(scl_data->ratios.horz) > 1)
435 scl_data->taps.h_taps = min(2 * dc_fixpt_ceil(scl_data->ratios.horz), 8);
436 else
437 scl_data->taps.h_taps = 4;
438 } else
439 scl_data->taps.h_taps = in_taps->h_taps;
440 if (in_taps->v_taps == 0) {
441 if (dc_fixpt_ceil(scl_data->ratios.vert) > 1)
442 scl_data->taps.v_taps = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert, 2)), 8);
443 else
444 scl_data->taps.v_taps = 4;
445 } else
446 scl_data->taps.v_taps = in_taps->v_taps;
447 if (in_taps->v_taps_c == 0) {
448 if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 1)
449 scl_data->taps.v_taps_c = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert_c, 2)), 8);
450 else
451 scl_data->taps.v_taps_c = 4;
452 } else
453 scl_data->taps.v_taps_c = in_taps->v_taps_c;
454 if (in_taps->h_taps_c == 0) {
455 if (dc_fixpt_ceil(scl_data->ratios.horz_c) > 1)
456 scl_data->taps.h_taps_c = min(2 * dc_fixpt_ceil(scl_data->ratios.horz_c), 8);
457 else
458 scl_data->taps.h_taps_c = 4;
459 } else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1)
460 /* Only 1 and even h_taps_c are supported by hw */
461 scl_data->taps.h_taps_c = in_taps->h_taps_c - 1;
462 else
463 scl_data->taps.h_taps_c = in_taps->h_taps_c;
464
465 // Avoid null data in the scl data with this early return, proceed non-adaptive calcualtion first
466 if (scl_data->viewport.width > scl_data->h_active &&
467 dpp->ctx->dc->debug.max_downscale_src_width != 0 &&
468 scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)
469 return false;
470
471 /*Ensure we can support the requested number of vtaps*/
472 min_taps_y = dc_fixpt_ceil(scl_data->ratios.vert);
473 min_taps_c = dc_fixpt_ceil(scl_data->ratios.vert_c);
474
475 /* Use LB_MEMORY_CONFIG_3 for 4:2:0 */
476 if ((scl_data->format == PIXEL_FORMAT_420BPP8) || (scl_data->format == PIXEL_FORMAT_420BPP10))
477 lb_config = LB_MEMORY_CONFIG_3;
478 else
479 lb_config = LB_MEMORY_CONFIG_0;
480
481 dpp->caps->dscl_calc_lb_num_partitions(
482 scl_data, lb_config, &num_part_y, &num_part_c);
483
484 /* MAX_V_TAPS = MIN (NUM_LINES - MAX(CEILING(V_RATIO,1)-2, 0), 8) */
485 if (dc_fixpt_ceil(scl_data->ratios.vert) > 2)
486 max_taps_y = num_part_y - (dc_fixpt_ceil(scl_data->ratios.vert) - 2);
487 else
488 max_taps_y = num_part_y;
489
490 if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 2)
491 max_taps_c = num_part_c - (dc_fixpt_ceil(scl_data->ratios.vert_c) - 2);
492 else
493 max_taps_c = num_part_c;
494
495 if (max_taps_y < min_taps_y)
496 return false;
497 else if (max_taps_c < min_taps_c)
498 return false;
499
500 if (scl_data->taps.v_taps > max_taps_y)
501 scl_data->taps.v_taps = max_taps_y;
502
503 if (scl_data->taps.v_taps_c > max_taps_c)
504 scl_data->taps.v_taps_c = max_taps_c;
505
506 if (!dpp->ctx->dc->debug.always_scale) {
507 if (IDENTITY_RATIO(scl_data->ratios.horz))
508 scl_data->taps.h_taps = 1;
509 if (IDENTITY_RATIO(scl_data->ratios.vert))
510 scl_data->taps.v_taps = 1;
511 if (IDENTITY_RATIO(scl_data->ratios.horz_c))
512 scl_data->taps.h_taps_c = 1;
513 if (IDENTITY_RATIO(scl_data->ratios.vert_c))
514 scl_data->taps.v_taps_c = 1;
515 }
516
517 return true;
518 }
519
dpp3_deferred_update(struct dpp * dpp_base)520 static void dpp3_deferred_update(struct dpp *dpp_base)
521 {
522 int bypass_state;
523 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
524
525 if (dpp_base->deferred_reg_writes.bits.disable_dscl) {
526 REG_UPDATE(DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, 3);
527 dpp_base->deferred_reg_writes.bits.disable_dscl = false;
528 }
529
530 if (dpp_base->deferred_reg_writes.bits.disable_gamcor) {
531 REG_GET(CM_GAMCOR_CONTROL, CM_GAMCOR_MODE_CURRENT, &bypass_state);
532 if (bypass_state == 0) { // only program if bypass was latched
533 REG_UPDATE(CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_FORCE, 3);
534 } else
535 ASSERT(0); // LUT select was updated again before vupdate
536 dpp_base->deferred_reg_writes.bits.disable_gamcor = false;
537 }
538
539 if (dpp_base->deferred_reg_writes.bits.disable_blnd_lut) {
540 REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE_CURRENT, &bypass_state);
541 if (bypass_state == 0) { // only program if bypass was latched
542 REG_UPDATE(CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, 3);
543 } else
544 ASSERT(0); // LUT select was updated again before vupdate
545 dpp_base->deferred_reg_writes.bits.disable_blnd_lut = false;
546 }
547
548 if (dpp_base->deferred_reg_writes.bits.disable_3dlut) {
549 REG_GET(CM_3DLUT_MODE, CM_3DLUT_MODE_CURRENT, &bypass_state);
550 if (bypass_state == 0) { // only program if bypass was latched
551 REG_UPDATE(CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, 3);
552 } else
553 ASSERT(0); // LUT select was updated again before vupdate
554 dpp_base->deferred_reg_writes.bits.disable_3dlut = false;
555 }
556
557 if (dpp_base->deferred_reg_writes.bits.disable_shaper) {
558 REG_GET(CM_SHAPER_CONTROL, CM_SHAPER_MODE_CURRENT, &bypass_state);
559 if (bypass_state == 0) { // only program if bypass was latched
560 REG_UPDATE(CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, 3);
561 } else
562 ASSERT(0); // LUT select was updated again before vupdate
563 dpp_base->deferred_reg_writes.bits.disable_shaper = false;
564 }
565 }
566
dpp3_power_on_blnd_lut(struct dpp * dpp_base,bool power_on)567 static void dpp3_power_on_blnd_lut(
568 struct dpp *dpp_base,
569 bool power_on)
570 {
571 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
572
573 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
574 if (power_on) {
575 REG_UPDATE(CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, 0);
576 REG_WAIT(CM_MEM_PWR_STATUS, BLNDGAM_MEM_PWR_STATE, 0, 1, 5);
577 } else {
578 dpp_base->ctx->dc->optimized_required = true;
579 dpp_base->deferred_reg_writes.bits.disable_blnd_lut = true;
580 }
581 }
582 }
583
dpp3_power_on_hdr3dlut(struct dpp * dpp_base,bool power_on)584 static void dpp3_power_on_hdr3dlut(
585 struct dpp *dpp_base,
586 bool power_on)
587 {
588 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
589
590 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
591 if (power_on) {
592 REG_UPDATE(CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, 0);
593 REG_WAIT(CM_MEM_PWR_STATUS2, HDR3DLUT_MEM_PWR_STATE, 0, 1, 5);
594 } else {
595 dpp_base->ctx->dc->optimized_required = true;
596 dpp_base->deferred_reg_writes.bits.disable_3dlut = true;
597 }
598 }
599 }
600
dpp3_power_on_shaper(struct dpp * dpp_base,bool power_on)601 static void dpp3_power_on_shaper(
602 struct dpp *dpp_base,
603 bool power_on)
604 {
605 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
606
607 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
608 if (power_on) {
609 REG_UPDATE(CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, 0);
610 REG_WAIT(CM_MEM_PWR_STATUS2, SHAPER_MEM_PWR_STATE, 0, 1, 5);
611 } else {
612 dpp_base->ctx->dc->optimized_required = true;
613 dpp_base->deferred_reg_writes.bits.disable_shaper = true;
614 }
615 }
616 }
617
dpp3_configure_blnd_lut(struct dpp * dpp_base,bool is_ram_a)618 static void dpp3_configure_blnd_lut(
619 struct dpp *dpp_base,
620 bool is_ram_a)
621 {
622 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
623
624 REG_UPDATE_2(CM_BLNDGAM_LUT_CONTROL,
625 CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 7,
626 CM_BLNDGAM_LUT_HOST_SEL, is_ram_a == true ? 0 : 1);
627
628 REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0);
629 }
630
dpp3_program_blnd_pwl(struct dpp * dpp_base,const struct pwl_result_data * rgb,uint32_t num)631 static void dpp3_program_blnd_pwl(
632 struct dpp *dpp_base,
633 const struct pwl_result_data *rgb,
634 uint32_t num)
635 {
636 uint32_t i;
637 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
638 uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg;
639 uint32_t last_base_value_green = rgb[num-1].green_reg + rgb[num-1].delta_green_reg;
640 uint32_t last_base_value_blue = rgb[num-1].blue_reg + rgb[num-1].delta_blue_reg;
641
642 if (is_rgb_equal(rgb, num)) {
643 for (i = 0 ; i < num; i++)
644 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg);
645 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red);
646 } else {
647 REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0);
648 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 4);
649 for (i = 0 ; i < num; i++)
650 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg);
651 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red);
652
653 REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0);
654 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 2);
655 for (i = 0 ; i < num; i++)
656 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].green_reg);
657 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_green);
658
659 REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0);
660 REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 1);
661 for (i = 0 ; i < num; i++)
662 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].blue_reg);
663 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_blue);
664 }
665 }
666
dcn3_dpp_cm_get_reg_field(struct dcn3_dpp * dpp,struct dcn3_xfer_func_reg * reg)667 static void dcn3_dpp_cm_get_reg_field(
668 struct dcn3_dpp *dpp,
669 struct dcn3_xfer_func_reg *reg)
670 {
671 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;
672 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;
673 reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
674 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
675 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;
676 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;
677 reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
678 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
679
680 reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B;
681 reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B;
682 reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;
683 reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;
684 reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;
685 reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;
686 reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B;
687 reg->masks.field_region_linear_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B;
688 reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B;
689 reg->masks.exp_region_start = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_B;
690 reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;
691 reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;
692 }
693
694 /*program blnd lut RAM A*/
dpp3_program_blnd_luta_settings(struct dpp * dpp_base,const struct pwl_params * params)695 static void dpp3_program_blnd_luta_settings(
696 struct dpp *dpp_base,
697 const struct pwl_params *params)
698 {
699 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
700 struct dcn3_xfer_func_reg gam_regs;
701
702 dcn3_dpp_cm_get_reg_field(dpp, &gam_regs);
703
704 gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMA_START_CNTL_B);
705 gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMA_START_CNTL_G);
706 gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMA_START_CNTL_R);
707 gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B);
708 gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G);
709 gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R);
710 gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMA_END_CNTL1_B);
711 gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMA_END_CNTL2_B);
712 gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMA_END_CNTL1_G);
713 gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMA_END_CNTL2_G);
714 gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMA_END_CNTL1_R);
715 gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMA_END_CNTL2_R);
716 gam_regs.region_start = REG(CM_BLNDGAM_RAMA_REGION_0_1);
717 gam_regs.region_end = REG(CM_BLNDGAM_RAMA_REGION_32_33);
718
719 cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs);
720 }
721
722 /*program blnd lut RAM B*/
dpp3_program_blnd_lutb_settings(struct dpp * dpp_base,const struct pwl_params * params)723 static void dpp3_program_blnd_lutb_settings(
724 struct dpp *dpp_base,
725 const struct pwl_params *params)
726 {
727 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
728 struct dcn3_xfer_func_reg gam_regs;
729
730 dcn3_dpp_cm_get_reg_field(dpp, &gam_regs);
731
732 gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMB_START_CNTL_B);
733 gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMB_START_CNTL_G);
734 gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMB_START_CNTL_R);
735 gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B);
736 gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G);
737 gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R);
738 gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMB_END_CNTL1_B);
739 gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMB_END_CNTL2_B);
740 gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMB_END_CNTL1_G);
741 gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMB_END_CNTL2_G);
742 gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMB_END_CNTL1_R);
743 gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMB_END_CNTL2_R);
744 gam_regs.region_start = REG(CM_BLNDGAM_RAMB_REGION_0_1);
745 gam_regs.region_end = REG(CM_BLNDGAM_RAMB_REGION_32_33);
746
747 cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs);
748 }
749
dpp3_get_blndgam_current(struct dpp * dpp_base)750 static enum dc_lut_mode dpp3_get_blndgam_current(struct dpp *dpp_base)
751 {
752 enum dc_lut_mode mode;
753 uint32_t mode_current = 0;
754 uint32_t in_use = 0;
755
756 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
757
758 REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE_CURRENT, &mode_current);
759 REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_SELECT_CURRENT, &in_use);
760
761 switch (mode_current) {
762 case 0:
763 case 1:
764 mode = LUT_BYPASS;
765 break;
766
767 case 2:
768 if (in_use == 0)
769 mode = LUT_RAM_A;
770 else
771 mode = LUT_RAM_B;
772 break;
773 default:
774 mode = LUT_BYPASS;
775 break;
776 }
777
778 return mode;
779 }
780
dpp3_program_blnd_lut(struct dpp * dpp_base,const struct pwl_params * params)781 static bool dpp3_program_blnd_lut(struct dpp *dpp_base,
782 const struct pwl_params *params)
783 {
784 enum dc_lut_mode current_mode;
785 enum dc_lut_mode next_mode;
786 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
787
788 if (params == NULL) {
789 REG_SET(CM_BLNDGAM_CONTROL, 0, CM_BLNDGAM_MODE, 0);
790 dpp3_power_on_blnd_lut(dpp_base, false);
791 return false;
792 }
793
794 current_mode = dpp3_get_blndgam_current(dpp_base);
795 if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_B)
796 next_mode = LUT_RAM_A;
797 else
798 next_mode = LUT_RAM_B;
799
800 dpp3_power_on_blnd_lut(dpp_base, true);
801 dpp3_configure_blnd_lut(dpp_base, next_mode == LUT_RAM_A);
802
803 if (next_mode == LUT_RAM_A)
804 dpp3_program_blnd_luta_settings(dpp_base, params);
805 else
806 dpp3_program_blnd_lutb_settings(dpp_base, params);
807
808 dpp3_program_blnd_pwl(
809 dpp_base, params->rgb_resulted, params->hw_points_num);
810
811 REG_UPDATE_2(CM_BLNDGAM_CONTROL,
812 CM_BLNDGAM_MODE, 2,
813 CM_BLNDGAM_SELECT, next_mode == LUT_RAM_A ? 0 : 1);
814
815 return true;
816 }
817
818
dpp3_program_shaper_lut(struct dpp * dpp_base,const struct pwl_result_data * rgb,uint32_t num)819 static void dpp3_program_shaper_lut(
820 struct dpp *dpp_base,
821 const struct pwl_result_data *rgb,
822 uint32_t num)
823 {
824 uint32_t i, red, green, blue;
825 uint32_t red_delta, green_delta, blue_delta;
826 uint32_t red_value, green_value, blue_value;
827
828 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
829
830 for (i = 0 ; i < num; i++) {
831
832 red = rgb[i].red_reg;
833 green = rgb[i].green_reg;
834 blue = rgb[i].blue_reg;
835
836 red_delta = rgb[i].delta_red_reg;
837 green_delta = rgb[i].delta_green_reg;
838 blue_delta = rgb[i].delta_blue_reg;
839
840 red_value = ((red_delta & 0x3ff) << 14) | (red & 0x3fff);
841 green_value = ((green_delta & 0x3ff) << 14) | (green & 0x3fff);
842 blue_value = ((blue_delta & 0x3ff) << 14) | (blue & 0x3fff);
843
844 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, red_value);
845 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, green_value);
846 REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, blue_value);
847 }
848
849 }
850
dpp3_get_shaper_current(struct dpp * dpp_base)851 static enum dc_lut_mode dpp3_get_shaper_current(struct dpp *dpp_base)
852 {
853 enum dc_lut_mode mode;
854 uint32_t state_mode;
855 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
856
857 REG_GET(CM_SHAPER_CONTROL, CM_SHAPER_MODE_CURRENT, &state_mode);
858
859 switch (state_mode) {
860 case 0:
861 mode = LUT_BYPASS;
862 break;
863 case 1:
864 mode = LUT_RAM_A;
865 break;
866 case 2:
867 mode = LUT_RAM_B;
868 break;
869 default:
870 mode = LUT_BYPASS;
871 break;
872 }
873
874 return mode;
875 }
876
dpp3_configure_shaper_lut(struct dpp * dpp_base,bool is_ram_a)877 static void dpp3_configure_shaper_lut(
878 struct dpp *dpp_base,
879 bool is_ram_a)
880 {
881 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
882
883 REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK,
884 CM_SHAPER_LUT_WRITE_EN_MASK, 7);
885 REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK,
886 CM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1);
887 REG_SET(CM_SHAPER_LUT_INDEX, 0, CM_SHAPER_LUT_INDEX, 0);
888 }
889
890 /*program shaper RAM A*/
891
dpp3_program_shaper_luta_settings(struct dpp * dpp_base,const struct pwl_params * params)892 static void dpp3_program_shaper_luta_settings(
893 struct dpp *dpp_base,
894 const struct pwl_params *params)
895 {
896 const struct gamma_curve *curve;
897 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
898
899 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_B, 0,
900 CM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
901 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
902 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_G, 0,
903 CM_SHAPER_RAMA_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x,
904 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G, 0);
905 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_R, 0,
906 CM_SHAPER_RAMA_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x,
907 CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R, 0);
908
909 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_B, 0,
910 CM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
911 CM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
912
913 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_G, 0,
914 CM_SHAPER_RAMA_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x,
915 CM_SHAPER_RAMA_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y);
916
917 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_R, 0,
918 CM_SHAPER_RAMA_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x,
919 CM_SHAPER_RAMA_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y);
920
921 curve = params->arr_curve_points;
922 REG_SET_4(CM_SHAPER_RAMA_REGION_0_1, 0,
923 CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
924 CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
925 CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
926 CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
927
928 curve += 2;
929 REG_SET_4(CM_SHAPER_RAMA_REGION_2_3, 0,
930 CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET, curve[0].offset,
931 CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,
932 CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET, curve[1].offset,
933 CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);
934
935 curve += 2;
936 REG_SET_4(CM_SHAPER_RAMA_REGION_4_5, 0,
937 CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET, curve[0].offset,
938 CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,
939 CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET, curve[1].offset,
940 CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);
941
942 curve += 2;
943 REG_SET_4(CM_SHAPER_RAMA_REGION_6_7, 0,
944 CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET, curve[0].offset,
945 CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,
946 CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET, curve[1].offset,
947 CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);
948
949 curve += 2;
950 REG_SET_4(CM_SHAPER_RAMA_REGION_8_9, 0,
951 CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET, curve[0].offset,
952 CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,
953 CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET, curve[1].offset,
954 CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);
955
956 curve += 2;
957 REG_SET_4(CM_SHAPER_RAMA_REGION_10_11, 0,
958 CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET, curve[0].offset,
959 CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,
960 CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET, curve[1].offset,
961 CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);
962
963 curve += 2;
964 REG_SET_4(CM_SHAPER_RAMA_REGION_12_13, 0,
965 CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET, curve[0].offset,
966 CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,
967 CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET, curve[1].offset,
968 CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);
969
970 curve += 2;
971 REG_SET_4(CM_SHAPER_RAMA_REGION_14_15, 0,
972 CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET, curve[0].offset,
973 CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,
974 CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET, curve[1].offset,
975 CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);
976
977 curve += 2;
978 REG_SET_4(CM_SHAPER_RAMA_REGION_16_17, 0,
979 CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET, curve[0].offset,
980 CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num,
981 CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET, curve[1].offset,
982 CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num);
983
984 curve += 2;
985 REG_SET_4(CM_SHAPER_RAMA_REGION_18_19, 0,
986 CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET, curve[0].offset,
987 CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num,
988 CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET, curve[1].offset,
989 CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num);
990
991 curve += 2;
992 REG_SET_4(CM_SHAPER_RAMA_REGION_20_21, 0,
993 CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET, curve[0].offset,
994 CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num,
995 CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET, curve[1].offset,
996 CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num);
997
998 curve += 2;
999 REG_SET_4(CM_SHAPER_RAMA_REGION_22_23, 0,
1000 CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET, curve[0].offset,
1001 CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num,
1002 CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET, curve[1].offset,
1003 CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num);
1004
1005 curve += 2;
1006 REG_SET_4(CM_SHAPER_RAMA_REGION_24_25, 0,
1007 CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET, curve[0].offset,
1008 CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num,
1009 CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET, curve[1].offset,
1010 CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num);
1011
1012 curve += 2;
1013 REG_SET_4(CM_SHAPER_RAMA_REGION_26_27, 0,
1014 CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET, curve[0].offset,
1015 CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num,
1016 CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET, curve[1].offset,
1017 CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num);
1018
1019 curve += 2;
1020 REG_SET_4(CM_SHAPER_RAMA_REGION_28_29, 0,
1021 CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET, curve[0].offset,
1022 CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num,
1023 CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET, curve[1].offset,
1024 CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num);
1025
1026 curve += 2;
1027 REG_SET_4(CM_SHAPER_RAMA_REGION_30_31, 0,
1028 CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET, curve[0].offset,
1029 CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num,
1030 CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET, curve[1].offset,
1031 CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num);
1032
1033 curve += 2;
1034 REG_SET_4(CM_SHAPER_RAMA_REGION_32_33, 0,
1035 CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET, curve[0].offset,
1036 CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num,
1037 CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET, curve[1].offset,
1038 CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num);
1039 }
1040
1041 /*program shaper RAM B*/
dpp3_program_shaper_lutb_settings(struct dpp * dpp_base,const struct pwl_params * params)1042 static void dpp3_program_shaper_lutb_settings(
1043 struct dpp *dpp_base,
1044 const struct pwl_params *params)
1045 {
1046 const struct gamma_curve *curve;
1047 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1048
1049 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_B, 0,
1050 CM_SHAPER_RAMB_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
1051 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B, 0);
1052 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_G, 0,
1053 CM_SHAPER_RAMB_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x,
1054 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G, 0);
1055 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_R, 0,
1056 CM_SHAPER_RAMB_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x,
1057 CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R, 0);
1058
1059 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_B, 0,
1060 CM_SHAPER_RAMB_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
1061 CM_SHAPER_RAMB_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
1062
1063 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_G, 0,
1064 CM_SHAPER_RAMB_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x,
1065 CM_SHAPER_RAMB_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y);
1066
1067 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_R, 0,
1068 CM_SHAPER_RAMB_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x,
1069 CM_SHAPER_RAMB_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y);
1070
1071 curve = params->arr_curve_points;
1072 REG_SET_4(CM_SHAPER_RAMB_REGION_0_1, 0,
1073 CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset,
1074 CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
1075 CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset,
1076 CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
1077
1078 curve += 2;
1079 REG_SET_4(CM_SHAPER_RAMB_REGION_2_3, 0,
1080 CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET, curve[0].offset,
1081 CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,
1082 CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET, curve[1].offset,
1083 CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);
1084
1085 curve += 2;
1086 REG_SET_4(CM_SHAPER_RAMB_REGION_4_5, 0,
1087 CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET, curve[0].offset,
1088 CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,
1089 CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET, curve[1].offset,
1090 CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);
1091
1092 curve += 2;
1093 REG_SET_4(CM_SHAPER_RAMB_REGION_6_7, 0,
1094 CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET, curve[0].offset,
1095 CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,
1096 CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET, curve[1].offset,
1097 CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);
1098
1099 curve += 2;
1100 REG_SET_4(CM_SHAPER_RAMB_REGION_8_9, 0,
1101 CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET, curve[0].offset,
1102 CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,
1103 CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET, curve[1].offset,
1104 CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);
1105
1106 curve += 2;
1107 REG_SET_4(CM_SHAPER_RAMB_REGION_10_11, 0,
1108 CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET, curve[0].offset,
1109 CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,
1110 CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET, curve[1].offset,
1111 CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);
1112
1113 curve += 2;
1114 REG_SET_4(CM_SHAPER_RAMB_REGION_12_13, 0,
1115 CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET, curve[0].offset,
1116 CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,
1117 CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET, curve[1].offset,
1118 CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);
1119
1120 curve += 2;
1121 REG_SET_4(CM_SHAPER_RAMB_REGION_14_15, 0,
1122 CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET, curve[0].offset,
1123 CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,
1124 CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET, curve[1].offset,
1125 CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);
1126
1127 curve += 2;
1128 REG_SET_4(CM_SHAPER_RAMB_REGION_16_17, 0,
1129 CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET, curve[0].offset,
1130 CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num,
1131 CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET, curve[1].offset,
1132 CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num);
1133
1134 curve += 2;
1135 REG_SET_4(CM_SHAPER_RAMB_REGION_18_19, 0,
1136 CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET, curve[0].offset,
1137 CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num,
1138 CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET, curve[1].offset,
1139 CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num);
1140
1141 curve += 2;
1142 REG_SET_4(CM_SHAPER_RAMB_REGION_20_21, 0,
1143 CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET, curve[0].offset,
1144 CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num,
1145 CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET, curve[1].offset,
1146 CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num);
1147
1148 curve += 2;
1149 REG_SET_4(CM_SHAPER_RAMB_REGION_22_23, 0,
1150 CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET, curve[0].offset,
1151 CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num,
1152 CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET, curve[1].offset,
1153 CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num);
1154
1155 curve += 2;
1156 REG_SET_4(CM_SHAPER_RAMB_REGION_24_25, 0,
1157 CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET, curve[0].offset,
1158 CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num,
1159 CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET, curve[1].offset,
1160 CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num);
1161
1162 curve += 2;
1163 REG_SET_4(CM_SHAPER_RAMB_REGION_26_27, 0,
1164 CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET, curve[0].offset,
1165 CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num,
1166 CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET, curve[1].offset,
1167 CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num);
1168
1169 curve += 2;
1170 REG_SET_4(CM_SHAPER_RAMB_REGION_28_29, 0,
1171 CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET, curve[0].offset,
1172 CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num,
1173 CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET, curve[1].offset,
1174 CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num);
1175
1176 curve += 2;
1177 REG_SET_4(CM_SHAPER_RAMB_REGION_30_31, 0,
1178 CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET, curve[0].offset,
1179 CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num,
1180 CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET, curve[1].offset,
1181 CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num);
1182
1183 curve += 2;
1184 REG_SET_4(CM_SHAPER_RAMB_REGION_32_33, 0,
1185 CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET, curve[0].offset,
1186 CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num,
1187 CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET, curve[1].offset,
1188 CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num);
1189
1190 }
1191
1192
dpp3_program_shaper(struct dpp * dpp_base,const struct pwl_params * params)1193 static bool dpp3_program_shaper(struct dpp *dpp_base,
1194 const struct pwl_params *params)
1195 {
1196 enum dc_lut_mode current_mode;
1197 enum dc_lut_mode next_mode;
1198
1199 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1200
1201 if (params == NULL) {
1202 REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, 0);
1203 dpp3_power_on_shaper(dpp_base, false);
1204 return false;
1205 }
1206
1207 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
1208 dpp3_power_on_shaper(dpp_base, true);
1209
1210 current_mode = dpp3_get_shaper_current(dpp_base);
1211
1212 if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
1213 next_mode = LUT_RAM_B;
1214 else
1215 next_mode = LUT_RAM_A;
1216
1217 dpp3_configure_shaper_lut(dpp_base, next_mode == LUT_RAM_A);
1218
1219 if (next_mode == LUT_RAM_A)
1220 dpp3_program_shaper_luta_settings(dpp_base, params);
1221 else
1222 dpp3_program_shaper_lutb_settings(dpp_base, params);
1223
1224 dpp3_program_shaper_lut(
1225 dpp_base, params->rgb_resulted, params->hw_points_num);
1226
1227 REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2);
1228
1229 return true;
1230
1231 }
1232
get3dlut_config(struct dpp * dpp_base,bool * is_17x17x17,bool * is_12bits_color_channel)1233 static enum dc_lut_mode get3dlut_config(
1234 struct dpp *dpp_base,
1235 bool *is_17x17x17,
1236 bool *is_12bits_color_channel)
1237 {
1238 uint32_t i_mode, i_enable_10bits, lut_size;
1239 enum dc_lut_mode mode;
1240 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1241
1242 REG_GET(CM_3DLUT_READ_WRITE_CONTROL,
1243 CM_3DLUT_30BIT_EN, &i_enable_10bits);
1244 REG_GET(CM_3DLUT_MODE,
1245 CM_3DLUT_MODE_CURRENT, &i_mode);
1246
1247 switch (i_mode) {
1248 case 0:
1249 mode = LUT_BYPASS;
1250 break;
1251 case 1:
1252 mode = LUT_RAM_A;
1253 break;
1254 case 2:
1255 mode = LUT_RAM_B;
1256 break;
1257 default:
1258 mode = LUT_BYPASS;
1259 break;
1260 }
1261 if (i_enable_10bits > 0)
1262 *is_12bits_color_channel = false;
1263 else
1264 *is_12bits_color_channel = true;
1265
1266 REG_GET(CM_3DLUT_MODE, CM_3DLUT_SIZE, &lut_size);
1267
1268 if (lut_size == 0)
1269 *is_17x17x17 = true;
1270 else
1271 *is_17x17x17 = false;
1272
1273 return mode;
1274 }
1275 /*
1276 * select ramA or ramB, or bypass
1277 * select color channel size 10 or 12 bits
1278 * select 3dlut size 17x17x17 or 9x9x9
1279 */
dpp3_set_3dlut_mode(struct dpp * dpp_base,enum dc_lut_mode mode,bool is_color_channel_12bits,bool is_lut_size17x17x17)1280 static void dpp3_set_3dlut_mode(
1281 struct dpp *dpp_base,
1282 enum dc_lut_mode mode,
1283 bool is_color_channel_12bits,
1284 bool is_lut_size17x17x17)
1285 {
1286 uint32_t lut_mode;
1287 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1288
1289 if (mode == LUT_BYPASS)
1290 lut_mode = 0;
1291 else if (mode == LUT_RAM_A)
1292 lut_mode = 1;
1293 else
1294 lut_mode = 2;
1295
1296 REG_UPDATE_2(CM_3DLUT_MODE,
1297 CM_3DLUT_MODE, lut_mode,
1298 CM_3DLUT_SIZE, is_lut_size17x17x17 == true ? 0 : 1);
1299 }
1300
dpp3_select_3dlut_ram(struct dpp * dpp_base,enum dc_lut_mode mode,bool is_color_channel_12bits)1301 static void dpp3_select_3dlut_ram(
1302 struct dpp *dpp_base,
1303 enum dc_lut_mode mode,
1304 bool is_color_channel_12bits)
1305 {
1306 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1307
1308 REG_UPDATE_2(CM_3DLUT_READ_WRITE_CONTROL,
1309 CM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1,
1310 CM_3DLUT_30BIT_EN,
1311 is_color_channel_12bits == true ? 0:1);
1312 }
1313
1314
1315
dpp3_set3dlut_ram12(struct dpp * dpp_base,const struct dc_rgb * lut,uint32_t entries)1316 static void dpp3_set3dlut_ram12(
1317 struct dpp *dpp_base,
1318 const struct dc_rgb *lut,
1319 uint32_t entries)
1320 {
1321 uint32_t i, red, green, blue, red1, green1, blue1;
1322 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1323
1324 for (i = 0 ; i < entries; i += 2) {
1325 red = lut[i].red<<4;
1326 green = lut[i].green<<4;
1327 blue = lut[i].blue<<4;
1328 red1 = lut[i+1].red<<4;
1329 green1 = lut[i+1].green<<4;
1330 blue1 = lut[i+1].blue<<4;
1331
1332 REG_SET_2(CM_3DLUT_DATA, 0,
1333 CM_3DLUT_DATA0, red,
1334 CM_3DLUT_DATA1, red1);
1335
1336 REG_SET_2(CM_3DLUT_DATA, 0,
1337 CM_3DLUT_DATA0, green,
1338 CM_3DLUT_DATA1, green1);
1339
1340 REG_SET_2(CM_3DLUT_DATA, 0,
1341 CM_3DLUT_DATA0, blue,
1342 CM_3DLUT_DATA1, blue1);
1343
1344 }
1345 }
1346
1347 /*
1348 * load selected lut with 10 bits color channels
1349 */
dpp3_set3dlut_ram10(struct dpp * dpp_base,const struct dc_rgb * lut,uint32_t entries)1350 static void dpp3_set3dlut_ram10(
1351 struct dpp *dpp_base,
1352 const struct dc_rgb *lut,
1353 uint32_t entries)
1354 {
1355 uint32_t i, red, green, blue, value;
1356 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1357
1358 for (i = 0; i < entries; i++) {
1359 red = lut[i].red;
1360 green = lut[i].green;
1361 blue = lut[i].blue;
1362
1363 value = (red<<20) | (green<<10) | blue;
1364
1365 REG_SET(CM_3DLUT_DATA_30BIT, 0, CM_3DLUT_DATA_30BIT, value);
1366 }
1367
1368 }
1369
1370
dpp3_select_3dlut_ram_mask(struct dpp * dpp_base,uint32_t ram_selection_mask)1371 static void dpp3_select_3dlut_ram_mask(
1372 struct dpp *dpp_base,
1373 uint32_t ram_selection_mask)
1374 {
1375 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1376
1377 REG_UPDATE(CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_WRITE_EN_MASK,
1378 ram_selection_mask);
1379 REG_SET(CM_3DLUT_INDEX, 0, CM_3DLUT_INDEX, 0);
1380 }
1381
dpp3_program_3dlut(struct dpp * dpp_base,const struct tetrahedral_params * params)1382 static bool dpp3_program_3dlut(struct dpp *dpp_base,
1383 const struct tetrahedral_params *params)
1384 {
1385 enum dc_lut_mode mode;
1386 bool is_17x17x17;
1387 bool is_12bits_color_channel;
1388 const struct dc_rgb *lut0;
1389 const struct dc_rgb *lut1;
1390 const struct dc_rgb *lut2;
1391 const struct dc_rgb *lut3;
1392 int lut_size0;
1393 int lut_size;
1394
1395 if (params == NULL) {
1396 dpp3_set_3dlut_mode(dpp_base, LUT_BYPASS, false, false);
1397 dpp3_power_on_hdr3dlut(dpp_base, false);
1398 return false;
1399 }
1400
1401 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
1402 dpp3_power_on_hdr3dlut(dpp_base, true);
1403
1404 mode = get3dlut_config(dpp_base, &is_17x17x17, &is_12bits_color_channel);
1405
1406 if (mode == LUT_BYPASS || mode == LUT_RAM_B)
1407 mode = LUT_RAM_A;
1408 else
1409 mode = LUT_RAM_B;
1410
1411 is_17x17x17 = !params->use_tetrahedral_9;
1412 is_12bits_color_channel = params->use_12bits;
1413 if (is_17x17x17) {
1414 lut0 = params->tetrahedral_17.lut0;
1415 lut1 = params->tetrahedral_17.lut1;
1416 lut2 = params->tetrahedral_17.lut2;
1417 lut3 = params->tetrahedral_17.lut3;
1418 lut_size0 = sizeof(params->tetrahedral_17.lut0)/
1419 sizeof(params->tetrahedral_17.lut0[0]);
1420 lut_size = sizeof(params->tetrahedral_17.lut1)/
1421 sizeof(params->tetrahedral_17.lut1[0]);
1422 } else {
1423 lut0 = params->tetrahedral_9.lut0;
1424 lut1 = params->tetrahedral_9.lut1;
1425 lut2 = params->tetrahedral_9.lut2;
1426 lut3 = params->tetrahedral_9.lut3;
1427 lut_size0 = sizeof(params->tetrahedral_9.lut0)/
1428 sizeof(params->tetrahedral_9.lut0[0]);
1429 lut_size = sizeof(params->tetrahedral_9.lut1)/
1430 sizeof(params->tetrahedral_9.lut1[0]);
1431 }
1432
1433 dpp3_select_3dlut_ram(dpp_base, mode,
1434 is_12bits_color_channel);
1435 dpp3_select_3dlut_ram_mask(dpp_base, 0x1);
1436 if (is_12bits_color_channel)
1437 dpp3_set3dlut_ram12(dpp_base, lut0, lut_size0);
1438 else
1439 dpp3_set3dlut_ram10(dpp_base, lut0, lut_size0);
1440
1441 dpp3_select_3dlut_ram_mask(dpp_base, 0x2);
1442 if (is_12bits_color_channel)
1443 dpp3_set3dlut_ram12(dpp_base, lut1, lut_size);
1444 else
1445 dpp3_set3dlut_ram10(dpp_base, lut1, lut_size);
1446
1447 dpp3_select_3dlut_ram_mask(dpp_base, 0x4);
1448 if (is_12bits_color_channel)
1449 dpp3_set3dlut_ram12(dpp_base, lut2, lut_size);
1450 else
1451 dpp3_set3dlut_ram10(dpp_base, lut2, lut_size);
1452
1453 dpp3_select_3dlut_ram_mask(dpp_base, 0x8);
1454 if (is_12bits_color_channel)
1455 dpp3_set3dlut_ram12(dpp_base, lut3, lut_size);
1456 else
1457 dpp3_set3dlut_ram10(dpp_base, lut3, lut_size);
1458
1459
1460 dpp3_set_3dlut_mode(dpp_base, mode, is_12bits_color_channel,
1461 is_17x17x17);
1462
1463 return true;
1464 }
1465 static struct dpp_funcs dcn30_dpp_funcs = {
1466 .dpp_program_gamcor_lut = dpp3_program_gamcor_lut,
1467 .dpp_read_state = dpp30_read_state,
1468 .dpp_reset = dpp_reset,
1469 .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,
1470 .dpp_get_optimal_number_of_taps = dpp3_get_optimal_number_of_taps,
1471 .dpp_set_gamut_remap = dpp3_cm_set_gamut_remap,
1472 .dpp_set_csc_adjustment = NULL,
1473 .dpp_set_csc_default = NULL,
1474 .dpp_program_regamma_pwl = NULL,
1475 .dpp_set_pre_degam = dpp3_set_pre_degam,
1476 .dpp_program_input_lut = NULL,
1477 .dpp_full_bypass = dpp1_full_bypass,
1478 .dpp_setup = dpp3_cnv_setup,
1479 .dpp_program_degamma_pwl = NULL,
1480 .dpp_program_cm_dealpha = dpp3_program_cm_dealpha,
1481 .dpp_program_cm_bias = dpp3_program_cm_bias,
1482 .dpp_program_blnd_lut = dpp3_program_blnd_lut,
1483 .dpp_program_shaper_lut = dpp3_program_shaper,
1484 .dpp_program_3dlut = dpp3_program_3dlut,
1485 .dpp_deferred_update = dpp3_deferred_update,
1486 .dpp_program_bias_and_scale = NULL,
1487 .dpp_cnv_set_alpha_keyer = dpp2_cnv_set_alpha_keyer,
1488 .set_cursor_attributes = dpp3_set_cursor_attributes,
1489 .set_cursor_position = dpp1_set_cursor_position,
1490 .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes,
1491 .dpp_dppclk_control = dpp1_dppclk_control,
1492 .dpp_set_hdr_multiplier = dpp3_set_hdr_multiplier,
1493 .dpp_get_gamut_remap = dpp3_cm_get_gamut_remap,
1494 .dpp_force_disable_cursor = dpp_force_disable_cursor,
1495 };
1496
1497
1498 static struct dpp_caps dcn30_dpp_cap = {
1499 .dscl_data_proc_format = DSCL_DATA_PRCESSING_FLOAT_FORMAT,
1500 .dscl_calc_lb_num_partitions = dscl2_calc_lb_num_partitions,
1501 };
1502
dpp3_construct(struct dcn3_dpp * dpp,struct dc_context * ctx,uint32_t inst,const struct dcn3_dpp_registers * tf_regs,const struct dcn3_dpp_shift * tf_shift,const struct dcn3_dpp_mask * tf_mask)1503 bool dpp3_construct(
1504 struct dcn3_dpp *dpp,
1505 struct dc_context *ctx,
1506 uint32_t inst,
1507 const struct dcn3_dpp_registers *tf_regs,
1508 const struct dcn3_dpp_shift *tf_shift,
1509 const struct dcn3_dpp_mask *tf_mask)
1510 {
1511 dpp->base.ctx = ctx;
1512
1513 dpp->base.inst = inst;
1514 dpp->base.funcs = &dcn30_dpp_funcs;
1515 dpp->base.caps = &dcn30_dpp_cap;
1516
1517 dpp->tf_regs = tf_regs;
1518 dpp->tf_shift = tf_shift;
1519 dpp->tf_mask = tf_mask;
1520
1521 return true;
1522 }
1523
1524