1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "core_types.h" 29 30 #include "reg_helper.h" 31 #include "dcn10/dcn10_dpp.h" 32 #include "basics/conversion.h" 33 34 #define NUM_PHASES 64 35 #define HORZ_MAX_TAPS 8 36 #define VERT_MAX_TAPS 8 37 38 #define BLACK_OFFSET_RGB_Y 0x0 39 #define BLACK_OFFSET_CBCR 0x8000 40 41 #define REG(reg)\ 42 dpp->tf_regs->reg 43 44 #define CTX \ 45 dpp->base.ctx 46 47 #undef FN 48 #define FN(reg_name, field_name) \ 49 dpp->tf_shift->field_name, dpp->tf_mask->field_name 50 51 enum pixel_format_description { 52 PIXEL_FORMAT_FIXED = 0, 53 PIXEL_FORMAT_FIXED16, 54 PIXEL_FORMAT_FLOAT 55 56 }; 57 58 enum dcn10_coef_filter_type_sel { 59 SCL_COEF_LUMA_VERT_FILTER = 0, 60 SCL_COEF_LUMA_HORZ_FILTER = 1, 61 SCL_COEF_CHROMA_VERT_FILTER = 2, 62 SCL_COEF_CHROMA_HORZ_FILTER = 3, 63 SCL_COEF_ALPHA_VERT_FILTER = 4, 64 SCL_COEF_ALPHA_HORZ_FILTER = 5 65 }; 66 67 enum dscl_autocal_mode { 68 AUTOCAL_MODE_OFF = 0, 69 70 /* Autocal calculate the scaling ratio and initial phase and the 71 * DSCL_MODE_SEL must be set to 1 72 */ 73 AUTOCAL_MODE_AUTOSCALE = 1, 74 /* Autocal perform auto centering without replication and the 75 * DSCL_MODE_SEL must be set to 0 76 */ 77 AUTOCAL_MODE_AUTOCENTER = 2, 78 /* Autocal perform auto centering and auto replication and the 79 * DSCL_MODE_SEL must be set to 0 80 */ 81 AUTOCAL_MODE_AUTOREPLICATE = 3 82 }; 83 84 enum dscl_mode_sel { 85 DSCL_MODE_SCALING_444_BYPASS = 0, 86 DSCL_MODE_SCALING_444_RGB_ENABLE = 1, 87 DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2, 88 DSCL_MODE_SCALING_420_YCBCR_ENABLE = 3, 89 DSCL_MODE_SCALING_420_LUMA_BYPASS = 4, 90 DSCL_MODE_SCALING_420_CHROMA_BYPASS = 5, 91 DSCL_MODE_DSCL_BYPASS = 6 92 }; 93 94 void dpp_read_state(struct dpp *dpp_base, 95 struct dcn_dpp_state *s) 96 { 97 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 98 99 REG_GET(DPP_CONTROL, 100 DPP_CLOCK_ENABLE, &s->is_enabled); 101 REG_GET(CM_IGAM_CONTROL, 102 CM_IGAM_LUT_MODE, &s->igam_lut_mode); 103 REG_GET(CM_IGAM_CONTROL, 104 CM_IGAM_INPUT_FORMAT, &s->igam_input_format); 105 REG_GET(CM_DGAM_CONTROL, 106 CM_DGAM_LUT_MODE, &s->dgam_lut_mode); 107 REG_GET(CM_RGAM_CONTROL, 108 CM_RGAM_LUT_MODE, &s->rgam_lut_mode); 109 REG_GET(CM_GAMUT_REMAP_CONTROL, 110 CM_GAMUT_REMAP_MODE, &s->gamut_remap_mode); 111 112 if (s->gamut_remap_mode) { 113 s->gamut_remap_c11_c12 = REG_READ(CM_GAMUT_REMAP_C11_C12); 114 s->gamut_remap_c13_c14 = REG_READ(CM_GAMUT_REMAP_C13_C14); 115 s->gamut_remap_c21_c22 = REG_READ(CM_GAMUT_REMAP_C21_C22); 116 s->gamut_remap_c23_c24 = REG_READ(CM_GAMUT_REMAP_C23_C24); 117 s->gamut_remap_c31_c32 = REG_READ(CM_GAMUT_REMAP_C31_C32); 118 s->gamut_remap_c33_c34 = REG_READ(CM_GAMUT_REMAP_C33_C34); 119 } 120 } 121 122 #define IDENTITY_RATIO(ratio) (dc_fixpt_u2d19(ratio) == (1 << 19)) 123 124 bool dpp1_get_optimal_number_of_taps( 125 struct dpp *dpp, 126 struct scaler_data *scl_data, 127 const struct scaling_taps *in_taps) 128 { 129 /* Some ASICs does not support FP16 scaling, so we reject modes require this*/ 130 if (scl_data->format == PIXEL_FORMAT_FP16 && 131 dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT && 132 scl_data->ratios.horz.value != dc_fixpt_one.value && 133 scl_data->ratios.vert.value != dc_fixpt_one.value) 134 return false; 135 136 if (scl_data->viewport.width > scl_data->h_active && 137 dpp->ctx->dc->debug.max_downscale_src_width != 0 && 138 scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width) 139 return false; 140 141 /* TODO: add lb check */ 142 143 /* No support for programming ratio of 4, drop to 3.99999.. */ 144 if (scl_data->ratios.horz.value == (4ll << 32)) 145 scl_data->ratios.horz.value--; 146 if (scl_data->ratios.vert.value == (4ll << 32)) 147 scl_data->ratios.vert.value--; 148 if (scl_data->ratios.horz_c.value == (4ll << 32)) 149 scl_data->ratios.horz_c.value--; 150 if (scl_data->ratios.vert_c.value == (4ll << 32)) 151 scl_data->ratios.vert_c.value--; 152 153 /* Set default taps if none are provided */ 154 if (in_taps->h_taps == 0) 155 scl_data->taps.h_taps = 4; 156 else 157 scl_data->taps.h_taps = in_taps->h_taps; 158 if (in_taps->v_taps == 0) 159 scl_data->taps.v_taps = 4; 160 else 161 scl_data->taps.v_taps = in_taps->v_taps; 162 if (in_taps->v_taps_c == 0) 163 scl_data->taps.v_taps_c = 2; 164 else 165 scl_data->taps.v_taps_c = in_taps->v_taps_c; 166 if (in_taps->h_taps_c == 0) 167 scl_data->taps.h_taps_c = 2; 168 /* Only 1 and even h_taps_c are supported by hw */ 169 else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1) 170 scl_data->taps.h_taps_c = in_taps->h_taps_c - 1; 171 else 172 scl_data->taps.h_taps_c = in_taps->h_taps_c; 173 174 if (!dpp->ctx->dc->debug.always_scale) { 175 if (IDENTITY_RATIO(scl_data->ratios.horz)) 176 scl_data->taps.h_taps = 1; 177 if (IDENTITY_RATIO(scl_data->ratios.vert)) 178 scl_data->taps.v_taps = 1; 179 if (IDENTITY_RATIO(scl_data->ratios.horz_c)) 180 scl_data->taps.h_taps_c = 1; 181 if (IDENTITY_RATIO(scl_data->ratios.vert_c)) 182 scl_data->taps.v_taps_c = 1; 183 } 184 185 return true; 186 } 187 188 void dpp_reset(struct dpp *dpp_base) 189 { 190 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 191 192 dpp->filter_h_c = NULL; 193 dpp->filter_v_c = NULL; 194 dpp->filter_h = NULL; 195 dpp->filter_v = NULL; 196 197 memset(&dpp_base->pos, 0, sizeof(dpp_base->pos)); 198 memset(&dpp_base->att, 0, sizeof(dpp_base->att)); 199 200 memset(&dpp->scl_data, 0, sizeof(dpp->scl_data)); 201 memset(&dpp->pwl_data, 0, sizeof(dpp->pwl_data)); 202 } 203 204 205 206 static void dpp1_cm_set_regamma_pwl( 207 struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode) 208 { 209 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 210 uint32_t re_mode = 0; 211 212 switch (mode) { 213 case OPP_REGAMMA_BYPASS: 214 re_mode = 0; 215 break; 216 case OPP_REGAMMA_SRGB: 217 re_mode = 1; 218 break; 219 case OPP_REGAMMA_XVYCC: 220 re_mode = 2; 221 break; 222 case OPP_REGAMMA_USER: 223 re_mode = dpp->is_write_to_ram_a_safe ? 4 : 3; 224 if (memcmp(&dpp->pwl_data, params, sizeof(*params)) == 0) 225 break; 226 227 dpp1_cm_power_on_regamma_lut(dpp_base, true); 228 dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe); 229 230 if (dpp->is_write_to_ram_a_safe) 231 dpp1_cm_program_regamma_luta_settings(dpp_base, params); 232 else 233 dpp1_cm_program_regamma_lutb_settings(dpp_base, params); 234 235 dpp1_cm_program_regamma_lut(dpp_base, params->rgb_resulted, 236 params->hw_points_num); 237 dpp->pwl_data = *params; 238 239 re_mode = dpp->is_write_to_ram_a_safe ? 3 : 4; 240 dpp->is_write_to_ram_a_safe = !dpp->is_write_to_ram_a_safe; 241 break; 242 default: 243 break; 244 } 245 REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode); 246 } 247 248 static void dpp1_setup_format_flags(enum surface_pixel_format input_format,\ 249 enum pixel_format_description *fmt) 250 { 251 252 if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F || 253 input_format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) 254 *fmt = PIXEL_FORMAT_FLOAT; 255 else if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 || 256 input_format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616) 257 *fmt = PIXEL_FORMAT_FIXED16; 258 else 259 *fmt = PIXEL_FORMAT_FIXED; 260 } 261 262 static void dpp1_set_degamma_format_float( 263 struct dpp *dpp_base, 264 bool is_float) 265 { 266 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 267 268 if (is_float) { 269 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 3); 270 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 1); 271 } else { 272 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 2); 273 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 0); 274 } 275 } 276 277 void dpp1_cnv_setup ( 278 struct dpp *dpp_base, 279 enum surface_pixel_format format, 280 enum expansion_mode mode, 281 struct dc_csc_transform input_csc_color_matrix, 282 enum dc_color_space input_color_space, 283 struct cnv_alpha_2bit_lut *alpha_2bit_lut) 284 { 285 uint32_t pixel_format; 286 uint32_t alpha_en; 287 enum pixel_format_description fmt ; 288 enum dc_color_space color_space; 289 enum dcn10_input_csc_select select; 290 bool is_float; 291 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 292 bool force_disable_cursor = false; 293 struct out_csc_color_matrix tbl_entry; 294 int i = 0; 295 296 dpp1_setup_format_flags(format, &fmt); 297 alpha_en = 1; 298 pixel_format = 0; 299 color_space = COLOR_SPACE_SRGB; 300 select = INPUT_CSC_SELECT_BYPASS; 301 is_float = false; 302 303 switch (fmt) { 304 case PIXEL_FORMAT_FIXED: 305 case PIXEL_FORMAT_FIXED16: 306 /*when output is float then FORMAT_CONTROL__OUTPUT_FP=1*/ 307 REG_SET_3(FORMAT_CONTROL, 0, 308 CNVC_BYPASS, 0, 309 FORMAT_EXPANSION_MODE, mode, 310 OUTPUT_FP, 0); 311 break; 312 case PIXEL_FORMAT_FLOAT: 313 REG_SET_3(FORMAT_CONTROL, 0, 314 CNVC_BYPASS, 0, 315 FORMAT_EXPANSION_MODE, mode, 316 OUTPUT_FP, 1); 317 is_float = true; 318 break; 319 default: 320 321 break; 322 } 323 324 dpp1_set_degamma_format_float(dpp_base, is_float); 325 326 switch (format) { 327 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 328 pixel_format = 1; 329 break; 330 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 331 pixel_format = 3; 332 alpha_en = 0; 333 break; 334 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 335 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 336 pixel_format = 8; 337 break; 338 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 339 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 340 pixel_format = 10; 341 break; 342 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 343 force_disable_cursor = false; 344 pixel_format = 65; 345 color_space = COLOR_SPACE_YCBCR709; 346 select = INPUT_CSC_SELECT_ICSC; 347 break; 348 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 349 force_disable_cursor = true; 350 pixel_format = 64; 351 color_space = COLOR_SPACE_YCBCR709; 352 select = INPUT_CSC_SELECT_ICSC; 353 break; 354 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 355 force_disable_cursor = true; 356 pixel_format = 67; 357 color_space = COLOR_SPACE_YCBCR709; 358 select = INPUT_CSC_SELECT_ICSC; 359 break; 360 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 361 force_disable_cursor = true; 362 pixel_format = 66; 363 color_space = COLOR_SPACE_YCBCR709; 364 select = INPUT_CSC_SELECT_ICSC; 365 break; 366 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 367 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: 368 pixel_format = 26; /* ARGB16161616_UNORM */ 369 break; 370 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 371 pixel_format = 24; 372 break; 373 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 374 pixel_format = 25; 375 break; 376 default: 377 break; 378 } 379 380 /* Set default color space based on format if none is given. */ 381 color_space = input_color_space ? input_color_space : color_space; 382 383 REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0, 384 CNVC_SURFACE_PIXEL_FORMAT, pixel_format); 385 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); 386 387 // if input adjustments exist, program icsc with those values 388 389 if (input_csc_color_matrix.enable_adjustment 390 == true) { 391 for (i = 0; i < 12; i++) 392 tbl_entry.regval[i] = input_csc_color_matrix.matrix[i]; 393 394 tbl_entry.color_space = color_space; 395 396 if (color_space >= COLOR_SPACE_YCBCR601) 397 select = INPUT_CSC_SELECT_ICSC; 398 else 399 select = INPUT_CSC_SELECT_BYPASS; 400 401 dpp1_program_input_csc(dpp_base, color_space, select, &tbl_entry); 402 } else 403 dpp1_program_input_csc(dpp_base, color_space, select, NULL); 404 405 if (force_disable_cursor) { 406 REG_UPDATE(CURSOR_CONTROL, 407 CURSOR_ENABLE, 0); 408 REG_UPDATE(CURSOR0_CONTROL, 409 CUR0_ENABLE, 0); 410 } 411 } 412 413 void dpp1_set_cursor_attributes( 414 struct dpp *dpp_base, 415 struct dc_cursor_attributes *cursor_attributes) 416 { 417 enum dc_cursor_color_format color_format = cursor_attributes->color_format; 418 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 419 420 REG_UPDATE_2(CURSOR0_CONTROL, 421 CUR0_MODE, color_format, 422 CUR0_EXPANSION_MODE, 0); 423 424 if (color_format == CURSOR_MODE_MONO) { 425 /* todo: clarify what to program these to */ 426 REG_UPDATE(CURSOR0_COLOR0, 427 CUR0_COLOR0, 0x00000000); 428 REG_UPDATE(CURSOR0_COLOR1, 429 CUR0_COLOR1, 0xFFFFFFFF); 430 } 431 } 432 433 434 void dpp1_set_cursor_position( 435 struct dpp *dpp_base, 436 const struct dc_cursor_position *pos, 437 const struct dc_cursor_mi_param *param, 438 uint32_t width, 439 uint32_t height) 440 { 441 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 442 int x_pos = pos->x - param->viewport.x; 443 int y_pos = pos->y - param->viewport.y; 444 int x_hotspot = pos->x_hotspot; 445 int y_hotspot = pos->y_hotspot; 446 int src_x_offset = x_pos - pos->x_hotspot; 447 int src_y_offset = y_pos - pos->y_hotspot; 448 int cursor_height = (int)height; 449 int cursor_width = (int)width; 450 uint32_t cur_en = pos->enable ? 1 : 0; 451 452 // Transform cursor width / height and hotspots for offset calculations 453 if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) { 454 swap(cursor_height, cursor_width); 455 swap(x_hotspot, y_hotspot); 456 457 if (param->rotation == ROTATION_ANGLE_90) { 458 // hotspot = (-y, x) 459 src_x_offset = x_pos - (cursor_width - x_hotspot); 460 src_y_offset = y_pos - y_hotspot; 461 } else if (param->rotation == ROTATION_ANGLE_270) { 462 // hotspot = (y, -x) 463 src_x_offset = x_pos - x_hotspot; 464 src_y_offset = y_pos - (cursor_height - y_hotspot); 465 } 466 } else if (param->rotation == ROTATION_ANGLE_180) { 467 // hotspot = (-x, -y) 468 if (!param->mirror) 469 src_x_offset = x_pos - (cursor_width - x_hotspot); 470 471 src_y_offset = y_pos - (cursor_height - y_hotspot); 472 } 473 474 if (src_x_offset >= (int)param->viewport.width) 475 cur_en = 0; /* not visible beyond right edge*/ 476 477 if (src_x_offset + cursor_width <= 0) 478 cur_en = 0; /* not visible beyond left edge*/ 479 480 if (src_y_offset >= (int)param->viewport.height) 481 cur_en = 0; /* not visible beyond bottom edge*/ 482 483 if (src_y_offset + cursor_height <= 0) 484 cur_en = 0; /* not visible beyond top edge*/ 485 486 if (dpp_base->pos.cur0_ctl.bits.cur0_enable != cur_en) { 487 REG_UPDATE(CURSOR0_CONTROL, CUR0_ENABLE, cur_en); 488 489 dpp_base->pos.cur0_ctl.bits.cur0_enable = cur_en; 490 } 491 } 492 493 void dpp1_cnv_set_optional_cursor_attributes( 494 struct dpp *dpp_base, 495 struct dpp_cursor_attributes *attr) 496 { 497 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 498 499 if (attr) { 500 REG_UPDATE(CURSOR0_FP_SCALE_BIAS, CUR0_FP_BIAS, attr->bias); 501 REG_UPDATE(CURSOR0_FP_SCALE_BIAS, CUR0_FP_SCALE, attr->scale); 502 } 503 } 504 505 void dpp1_dppclk_control( 506 struct dpp *dpp_base, 507 bool dppclk_div, 508 bool enable) 509 { 510 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 511 512 if (enable) { 513 if (dpp->tf_mask->DPPCLK_RATE_CONTROL) 514 REG_UPDATE_2(DPP_CONTROL, 515 DPPCLK_RATE_CONTROL, dppclk_div, 516 DPP_CLOCK_ENABLE, 1); 517 else 518 REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 1); 519 } else 520 REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 0); 521 } 522 523 static const struct dpp_funcs dcn10_dpp_funcs = { 524 .dpp_read_state = dpp_read_state, 525 .dpp_reset = dpp_reset, 526 .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale, 527 .dpp_get_optimal_number_of_taps = dpp1_get_optimal_number_of_taps, 528 .dpp_set_gamut_remap = dpp1_cm_set_gamut_remap, 529 .dpp_set_csc_adjustment = dpp1_cm_set_output_csc_adjustment, 530 .dpp_set_csc_default = dpp1_cm_set_output_csc_default, 531 .dpp_power_on_regamma_lut = dpp1_cm_power_on_regamma_lut, 532 .dpp_program_regamma_lut = dpp1_cm_program_regamma_lut, 533 .dpp_configure_regamma_lut = dpp1_cm_configure_regamma_lut, 534 .dpp_program_regamma_lutb_settings = dpp1_cm_program_regamma_lutb_settings, 535 .dpp_program_regamma_luta_settings = dpp1_cm_program_regamma_luta_settings, 536 .dpp_program_regamma_pwl = dpp1_cm_set_regamma_pwl, 537 .dpp_program_bias_and_scale = dpp1_program_bias_and_scale, 538 .dpp_set_degamma = dpp1_set_degamma, 539 .dpp_program_input_lut = dpp1_program_input_lut, 540 .dpp_program_degamma_pwl = dpp1_set_degamma_pwl, 541 .dpp_setup = dpp1_cnv_setup, 542 .dpp_full_bypass = dpp1_full_bypass, 543 .set_cursor_attributes = dpp1_set_cursor_attributes, 544 .set_cursor_position = dpp1_set_cursor_position, 545 .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes, 546 .dpp_dppclk_control = dpp1_dppclk_control, 547 .dpp_set_hdr_multiplier = dpp1_set_hdr_multiplier, 548 .dpp_program_blnd_lut = NULL, 549 .dpp_program_shaper_lut = NULL, 550 .dpp_program_3dlut = NULL, 551 .dpp_get_gamut_remap = dpp1_cm_get_gamut_remap, 552 }; 553 554 static struct dpp_caps dcn10_dpp_cap = { 555 .dscl_data_proc_format = DSCL_DATA_PRCESSING_FIXED_FORMAT, 556 .dscl_calc_lb_num_partitions = dpp1_dscl_calc_lb_num_partitions, 557 }; 558 559 /*****************************************/ 560 /* Constructor, Destructor */ 561 /*****************************************/ 562 563 void dpp1_construct( 564 struct dcn10_dpp *dpp, 565 struct dc_context *ctx, 566 uint32_t inst, 567 const struct dcn_dpp_registers *tf_regs, 568 const struct dcn_dpp_shift *tf_shift, 569 const struct dcn_dpp_mask *tf_mask) 570 { 571 dpp->base.ctx = ctx; 572 573 dpp->base.inst = inst; 574 dpp->base.funcs = &dcn10_dpp_funcs; 575 dpp->base.caps = &dcn10_dpp_cap; 576 577 dpp->tf_regs = tf_regs; 578 dpp->tf_shift = tf_shift; 579 dpp->tf_mask = tf_mask; 580 581 dpp->lb_pixel_depth_supported = 582 LB_PIXEL_DEPTH_18BPP | 583 LB_PIXEL_DEPTH_24BPP | 584 LB_PIXEL_DEPTH_30BPP | 585 LB_PIXEL_DEPTH_36BPP; 586 587 dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY; 588 dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/ 589 } 590