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Searched defs:dpp (Results 1 – 25 of 42) sorted by relevance

12

/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
H A Ddcn10_dpp_cm.c92 struct dcn10_dpp *dpp, in program_gamut_remap()
164 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_set_gamut_remap() local
184 static void read_gamut_remap(struct dcn10_dpp *dpp, in read_gamut_remap()
236 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_get_gamut_remap() local
253 struct dcn10_dpp *dpp, in dpp1_cm_program_color_matrix()
311 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_set_output_csc_default() local
325 struct dcn10_dpp *dpp, in dpp1_cm_get_reg_field()
352 struct dcn10_dpp *dpp, in dpp1_cm_get_degamma_reg_field()
381 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_set_output_csc_adjustment() local
389 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_power_on_regamma_lut() local
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H A Ddcn10_dpp_dscl.c161 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_power_on_dscl() local
180 dpp1_dscl_set_lb(struct dcn10_dpp * dpp,const struct line_buffer_params * lb_params,enum lb_memory_config mem_size_config) dpp1_dscl_set_lb() argument
241 dpp1_dscl_set_scaler_filter(struct dcn10_dpp * dpp,uint32_t taps,enum dcn10_coef_filter_type_sel filter_type,const uint16_t * filter) dpp1_dscl_set_scaler_filter() argument
279 dpp1_dscl_set_scl_filter(struct dcn10_dpp * dpp,const struct scaler_data * scl_data,bool chroma_coef_mode) dpp1_dscl_set_scl_filter() argument
459 dpp1_dscl_find_lb_memory_config(struct dcn10_dpp * dpp,const struct scaler_data * scl_data) dpp1_dscl_find_lb_memory_config() argument
511 dpp1_dscl_set_manual_ratio_init(struct dcn10_dpp * dpp,const struct scaler_data * data) dpp1_dscl_set_manual_ratio_init() argument
587 dpp1_dscl_set_recout(struct dcn10_dpp * dpp,const struct rect * recout) dpp1_dscl_set_recout() argument
617 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_dscl_set_scaler_manual_scale() local
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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn20/
H A Ddcn20_dpp_cm.c53 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_enable_cm_block() local
70 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_degamma_ram_inuse() local
93 struct dcn20_dpp *dpp in dpp2_program_degamma_lut() local
138 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp2_set_degamma() local
162 program_gamut_remap(struct dcn20_dpp * dpp,const uint16_t * regval,enum dcn20_gamut_remap_select select) program_gamut_remap() argument
217 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp2_cm_set_gamut_remap() local
237 read_gamut_remap(struct dcn20_dpp * dpp,uint16_t * regval,enum dcn20_gamut_remap_select * select) read_gamut_remap() argument
276 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp2_cm_get_gamut_remap() local
298 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp2_program_input_csc() local
369 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_power_on_blnd_lut() local
380 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_configure_blnd_lut() local
395 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_program_blnd_pwl() local
414 dcn20_dpp_cm_get_reg_field(struct dcn20_dpp * dpp,struct xfer_func_reg * reg) dcn20_dpp_cm_get_reg_field() argument
445 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_program_blnd_luta_settings() local
473 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_program_blnd_lutb_settings() local
500 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_get_blndgam_current() local
527 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_program_blnd_lut() local
566 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_program_shaper_lut() local
593 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_get_shaper_current() local
619 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_configure_shaper_lut() local
635 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_program_shaper_luta_settings() local
785 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_program_shaper_lutb_settings() local
938 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_program_shaper() local
974 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); get3dlut_config() local
1020 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_set_3dlut_mode() local
1039 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_select_3dlut_ram() local
1055 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_set3dlut_ram12() local
1089 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_set3dlut_ram10() local
1108 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_select_3dlut_ram_mask() local
1199 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp2_set_hdr_multiplier() local
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H A Ddcn20_dpp.c54 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp20_read_state() local
81 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_power_on_obuf() local
105 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp2_cnv_setup() local
320 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp2_cnv_set_alpha_keyer() local
344 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp2_set_cursor_attributes() local
369 oppn20_dummy_program_regamma_pwl(struct dpp * dpp,const struct pwl_params * params,enum opp_regamma mode) oppn20_dummy_program_regamma_pwl() argument
407 dpp2_construct(struct dcn20_dpp * dpp,struct dc_context * ctx,uint32_t inst,const struct dcn2_dpp_registers * tf_regs,const struct dcn2_dpp_shift * tf_shift,const struct dcn2_dpp_mask * tf_mask) dpp2_construct() argument
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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
H A Ddcn30_dpp.c46 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp30_read_state() local
89 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp30_read_reg_state() local
110 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_program_post_csc() local
180 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_set_pre_degam() local
228 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_cnv_setup() local
405 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_set_cursor_attributes() local
439 dpp3_get_optimal_number_of_taps(struct dpp * dpp,struct scaler_data * scl_data,const struct scaling_taps * in_taps) dpp3_get_optimal_number_of_taps() argument
543 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_deferred_update() local
591 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_power_on_blnd_lut() local
608 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_power_on_hdr3dlut() local
625 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_power_on_shaper() local
642 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_configure_blnd_lut() local
657 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_program_blnd_pwl() local
688 dcn3_dpp_cm_get_reg_field(struct dcn3_dpp * dpp,struct dcn3_xfer_func_reg * reg) dcn3_dpp_cm_get_reg_field() argument
719 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_program_blnd_luta_settings() local
747 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_program_blnd_lutb_settings() local
776 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_get_blndgam_current() local
806 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_program_blnd_lut() local
848 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_program_shaper_lut() local
875 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_get_shaper_current() local
901 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_configure_shaper_lut() local
917 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_program_shaper_luta_settings() local
1067 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_program_shaper_lutb_settings() local
1219 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_program_shaper() local
1260 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); get3dlut_config() local
1307 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_set_3dlut_mode() local
1326 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_select_3dlut_ram() local
1342 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_set3dlut_ram12() local
1376 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_set3dlut_ram10() local
1395 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_select_3dlut_ram_mask() local
1524 dpp3_construct(struct dcn3_dpp * dpp,struct dc_context * ctx,uint32_t inst,const struct dcn3_dpp_registers * tf_regs,const struct dcn3_dpp_shift * tf_shift,const struct dcn3_dpp_mask * tf_mask) dpp3_construct() argument
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H A Ddcn30_dpp_cm.c46 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_enable_cm_block() local
62 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp30_get_gamcor_current() local
84 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_program_gammcor_lut() local
130 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_power_on_gamcor_lut() local
149 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_program_cm_dealpha() local
160 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_program_cm_bias() local
169 dpp3_gamcor_reg_field(struct dcn3_dpp * dpp,struct dcn3_xfer_func_reg * reg) dpp3_gamcor_reg_field() argument
205 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_configure_gamcor_lut() local
220 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_program_gamcor_lut() local
308 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_set_hdr_multiplier() local
315 program_gamut_remap(struct dcn3_dpp * dpp,const uint16_t * regval,int select) program_gamut_remap() argument
377 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_cm_set_gamut_remap() local
409 read_gamut_remap(struct dcn3_dpp * dpp,uint16_t * regval,int * select) read_gamut_remap() argument
447 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_cm_get_gamut_remap() local
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H A Ddcn30_dpp.h30 #define TO_DCN30_DPP(dpp)\ argument
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn201/
H A Ddcn201_dpp.c52 struct dcn201_dpp *dpp = TO_DCN201_DPP(dpp_base); in dpp201_cnv_setup() local
191 struct dpp *dpp, in dpp201_get_optimal_number_of_taps()
298 struct dcn201_dpp *dpp, in dpp201_construct()
H A Ddcn201_dpp.h30 #define TO_DCN201_DPP(dpp)\ argument
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn401/
H A Ddcn401_dpp.c47 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp401_read_state() local
63 struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); in dpp401_dpp_setup() local
263 struct dcn401_dpp *dpp, in dpp401_construct()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c291 struct dpp *dpp = res_pool->dpps[i]; in dcn201_init_hw() local
311 struct dpp *dpp = res_pool->dpps[i]; in dcn201_init_hw() local
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_hwseq.c695 struct dpp *dpp = dc->res_pool->dpps[i]; dcn35_init_pipes() local
819 struct dpp *dpp = pipe_ctx->plane_res.dpp; dcn35_enable_plane() local
859 struct dpp *dpp = pipe_ctx->plane_res.dpp; dcn35_plane_atomic_disable() local
1677 const struct dpp *dpp = pipe->plane_res.dpp; dcn35_update_cursor_offload_pipe() local
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c464 struct dpp *dpp = pool->dpps[i]; dcn10_log_color_state() local
1489 dcn10_plane_atomic_power_down(struct dc * dc,struct dpp * dpp,struct hubp * hubp) dcn10_plane_atomic_power_down() argument
1525 struct dpp *dpp = pipe_ctx->plane_res.dpp; dcn10_plane_atomic_disable() local
1643 struct dpp *dpp = dc->res_pool->dpps[i]; dcn10_init_pipes() local
2113 struct dpp *dpp = pipe_ctx->plane_res.dpp; dcn10_set_output_transfer_func() local
2858 dcn10_update_dpp(struct dpp * dpp,struct dc_plane_state * plane_state) dcn10_update_dpp() argument
2984 struct dpp *dpp = pipe_ctx->plane_res.dpp; dcn10_update_dchubp_dpp() local
3650 struct dpp *dpp = pipe_ctx->plane_res.dpp; dcn10_set_cursor_position() local
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/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_hw_sequencer.c1968 if (dpp in hwss_program_bias_and_scale() local
1740 hwss_add_dpp_set_hdr_multiplier(struct block_sequence_state * seq_state,struct dpp * dpp,uint32_t hw_mult) hwss_add_dpp_set_hdr_multiplier() argument
1948 struct dpp *dpp = pipe_ctx->plane_res.dpp; hwss_setup_dpp() local
2407 struct dpp *dpp = params->dpp_set_hdr_multiplier_params.dpp; hwss_dpp_set_hdr_multiplier() local
2820 struct dpp *dpp = params->dpp_dppclk_control_params.dpp; hwss_dpp_dppclk_control() local
2915 struct dpp *dpp = params->dpp_reset_params.dpp; hwss_dpp_reset() local
3013 struct dpp *dpp = params->dpp_set_cursor_matrix_params.dpp; hwss_dpp_set_cursor_matrix() local
3067 struct dpp *dpp = params->dpp_set_scaler_params.dpp; hwss_dpp_set_scaler() local
3594 hwss_add_dpp_dppclk_control(struct block_sequence_state * seq_state,struct dpp * dpp,bool dppclk_div,bool enable) hwss_add_dpp_dppclk_control() argument
3732 hwss_add_dpp_reset(struct block_sequence_state * seq_state,struct dpp * dpp) hwss_add_dpp_reset() argument
3912 hwss_add_dpp_set_cursor_matrix(struct block_sequence_state * seq_state,struct dpp * dpp,enum dc_color_space color_space,struct dc_csc_transform * cursor_csc_color_matrix) hwss_add_dpp_set_cursor_matrix() argument
3926 hwss_add_dpp_set_scaler(struct block_sequence_state * seq_state,struct dpp * dpp,const struct scaler_data * scl_data) hwss_add_dpp_set_scaler() argument
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.c90 struct dpp *dpp = pool->dpps[i]; dcn20_log_color_state() local
699 struct dpp *dpp = pipe_ctx->plane_res.dpp; dcn20_plane_atomic_disable() local
1671 struct dpp *dpp = pipe_ctx->plane_res.dpp; dcn20_update_dchubp_dpp() local
3167 struct dpp *dpp = res_pool->dpps[i]; dcn20_fpga_init_hw() local
3187 struct dpp *dpp = dc->res_pool->dpps[i]; dcn20_fpga_init_hw() local
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.c91 struct dpp *dpp = pool->dpps[i]; dcn30_log_color_state() local
1250 struct dpp *dpp = dc->res_pool->dpps[i]; dcn30_get_underflow_debug_data() local
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c1085 struct dpp *dpp = pipe_ctx->plane_res.dpp; dcn401_set_cursor_position() local
2951 dcn401_plane_atomic_power_down(struct dc * dc,struct dpp * dpp,struct hubp * hubp) dcn401_plane_atomic_power_down() argument
2991 const struct dpp *dpp = pipe->plane_res.dpp; dcn401_update_cursor_offload_pipe() local
3043 dcn401_plane_atomic_power_down_sequence(struct dc * dc,struct dpp * dpp,struct hubp * hubp,struct block_sequence_state * seq_state) dcn401_plane_atomic_power_down_sequence() argument
3592 struct dpp *dpp = pipe_ctx->plane_res.dpp; dcn401_update_dchubp_dpp_sequence() local
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/
H A Ddcn201_resource.c625 static void dcn201_dpp_destroy(struct dpp **dpp) in dcn201_dpp_destroy() argument
635 struct dcn201_dpp *dpp = in dcn201_dpp_create() local
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn10/
H A Ddcn10_resource.c594 static void dcn10_dpp_destroy(struct dpp **dpp) in dcn10_dpp_destroy() argument
604 struct dcn10_dpp *dpp = in dcn10_dpp_create() local
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/linux/arch/sparc/vdso/
H A Dvma.c251 struct page *dp, **dpp = NULL; init_vdso_image() local
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn301/
H A Ddcn301_resource.c712 static void dcn301_dpp_destroy(struct dpp **dpp) in dcn301_dpp_destroy() argument
720 struct dcn3_dpp *dpp = in dcn301_dpp_create() local
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/linux/fs/xfs/scrub/
H A Dparent.c414 struct xfs_inode **dpp) in xchk_parent_iget()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/
H A Ddcn316_resource.c919 static void dcn31_dpp_destroy(struct dpp **dpp) in dcn31_dpp_destroy() argument
929 struct dcn3_dpp *dpp = in dcn31_dpp_create() local
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/
H A Ddcn314_resource.c963 static void dcn31_dpp_destroy(struct dpp **dpp) in dcn31_dpp_destroy() argument
973 struct dcn3_dpp *dpp = in dcn31_dpp_create() local
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/
H A Ddcn31_resource.c927 static void dcn31_dpp_destroy(struct dpp **dpp) in dcn31_dpp_destroy() argument
937 struct dcn3_dpp *dpp = in dcn31_dpp_create() local
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