1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */ 2 /* Do not edit directly, auto-generated from: */ 3 /* Documentation/netlink/specs/dpll.yaml */ 4 /* YNL-GEN uapi header */ 5 /* To regenerate run: tools/net/ynl/ynl-regen.sh */ 6 7 #ifndef _UAPI_LINUX_DPLL_H 8 #define _UAPI_LINUX_DPLL_H 9 10 #define DPLL_FAMILY_NAME "dpll" 11 #define DPLL_FAMILY_VERSION 1 12 13 /** 14 * enum dpll_mode - working modes a dpll can support, differentiates if and how 15 * dpll selects one of its inputs to syntonize with it, valid values for 16 * DPLL_A_MODE attribute 17 * @DPLL_MODE_MANUAL: input can be only selected by sending a request to dpll 18 * @DPLL_MODE_AUTOMATIC: highest prio input pin auto selected by dpll 19 */ 20 enum dpll_mode { 21 DPLL_MODE_MANUAL = 1, 22 DPLL_MODE_AUTOMATIC, 23 24 /* private: */ 25 __DPLL_MODE_MAX, 26 DPLL_MODE_MAX = (__DPLL_MODE_MAX - 1) 27 }; 28 29 /** 30 * enum dpll_lock_status - provides information of dpll device lock status, 31 * valid values for DPLL_A_LOCK_STATUS attribute 32 * @DPLL_LOCK_STATUS_UNLOCKED: dpll was not yet locked to any valid input 33 * @DPLL_LOCK_STATUS_LOCKED: dpll is locked to a valid signal, but no holdover 34 * available 35 * @DPLL_LOCK_STATUS_LOCKED_HO_ACQ: dpll is locked and holdover acquired 36 * @DPLL_LOCK_STATUS_HOLDOVER: dpll is in holdover state - lost a valid lock or 37 * was forced by disconnecting all the pins (latter possible only when dpll 38 * lock-state was already DPLL_LOCK_STATUS_LOCKED_HO_ACQ, if dpll lock-state 39 * was not DPLL_LOCK_STATUS_LOCKED_HO_ACQ, the dpll's lock-state shall remain 40 * DPLL_LOCK_STATUS_UNLOCKED) 41 */ 42 enum dpll_lock_status { 43 DPLL_LOCK_STATUS_UNLOCKED = 1, 44 DPLL_LOCK_STATUS_LOCKED, 45 DPLL_LOCK_STATUS_LOCKED_HO_ACQ, 46 DPLL_LOCK_STATUS_HOLDOVER, 47 48 /* private: */ 49 __DPLL_LOCK_STATUS_MAX, 50 DPLL_LOCK_STATUS_MAX = (__DPLL_LOCK_STATUS_MAX - 1) 51 }; 52 53 /** 54 * enum dpll_lock_status_error - if previous status change was done due to a 55 * failure, this provides information of dpll device lock status error. Valid 56 * values for DPLL_A_LOCK_STATUS_ERROR attribute 57 * @DPLL_LOCK_STATUS_ERROR_NONE: dpll device lock status was changed without 58 * any error 59 * @DPLL_LOCK_STATUS_ERROR_UNDEFINED: dpll device lock status was changed due 60 * to undefined error. Driver fills this value up in case it is not able to 61 * obtain suitable exact error type. 62 * @DPLL_LOCK_STATUS_ERROR_MEDIA_DOWN: dpll device lock status was changed 63 * because of associated media got down. This may happen for example if dpll 64 * device was previously locked on an input pin of type 65 * PIN_TYPE_SYNCE_ETH_PORT. 66 * @DPLL_LOCK_STATUS_ERROR_FRACTIONAL_FREQUENCY_OFFSET_TOO_HIGH: the FFO 67 * (Fractional Frequency Offset) between the RX and TX symbol rate on the 68 * media got too high. This may happen for example if dpll device was 69 * previously locked on an input pin of type PIN_TYPE_SYNCE_ETH_PORT. 70 */ 71 enum dpll_lock_status_error { 72 DPLL_LOCK_STATUS_ERROR_NONE = 1, 73 DPLL_LOCK_STATUS_ERROR_UNDEFINED, 74 DPLL_LOCK_STATUS_ERROR_MEDIA_DOWN, 75 DPLL_LOCK_STATUS_ERROR_FRACTIONAL_FREQUENCY_OFFSET_TOO_HIGH, 76 77 /* private: */ 78 __DPLL_LOCK_STATUS_ERROR_MAX, 79 DPLL_LOCK_STATUS_ERROR_MAX = (__DPLL_LOCK_STATUS_ERROR_MAX - 1) 80 }; 81 82 /* 83 * level of quality of a clock device. This mainly applies when the dpll 84 * lock-status is DPLL_LOCK_STATUS_HOLDOVER. The current list is defined 85 * according to the table 11-7 contained in ITU-T G.8264/Y.1364 document. One 86 * may extend this list freely by other ITU-T defined clock qualities, or 87 * different ones defined by another standardization body (for those, please 88 * use different prefix). 89 */ 90 enum dpll_clock_quality_level { 91 DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_PRC = 1, 92 DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_SSU_A, 93 DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_SSU_B, 94 DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_EEC1, 95 DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_PRTC, 96 DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_EPRTC, 97 DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_EEEC, 98 DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_EPRC, 99 100 /* private: */ 101 __DPLL_CLOCK_QUALITY_LEVEL_MAX, 102 DPLL_CLOCK_QUALITY_LEVEL_MAX = (__DPLL_CLOCK_QUALITY_LEVEL_MAX - 1) 103 }; 104 105 #define DPLL_TEMP_DIVIDER 1000 106 107 /** 108 * enum dpll_type - type of dpll, valid values for DPLL_A_TYPE attribute 109 * @DPLL_TYPE_PPS: dpll produces Pulse-Per-Second signal 110 * @DPLL_TYPE_EEC: dpll drives the Ethernet Equipment Clock 111 * @DPLL_TYPE_GENERIC: generic dpll type for devices outside PPS/EEC classes 112 */ 113 enum dpll_type { 114 DPLL_TYPE_PPS = 1, 115 DPLL_TYPE_EEC, 116 DPLL_TYPE_GENERIC, 117 118 /* private: */ 119 __DPLL_TYPE_MAX, 120 DPLL_TYPE_MAX = (__DPLL_TYPE_MAX - 1) 121 }; 122 123 /** 124 * enum dpll_pin_type - defines possible types of a pin, valid values for 125 * DPLL_A_PIN_TYPE attribute 126 * @DPLL_PIN_TYPE_MUX: aggregates another layer of selectable pins 127 * @DPLL_PIN_TYPE_EXT: external input 128 * @DPLL_PIN_TYPE_SYNCE_ETH_PORT: ethernet port PHY's recovered clock 129 * @DPLL_PIN_TYPE_INT_OSCILLATOR: device internal oscillator 130 * @DPLL_PIN_TYPE_GNSS: GNSS recovered clock 131 * @DPLL_PIN_TYPE_INT_NCO: Device internal numerically controlled oscillator. 132 * When connected as a DPLL input, the DPLL enters NCO mode where the output 133 * frequency is adjusted by the host via the PTP clock interface. 134 */ 135 enum dpll_pin_type { 136 DPLL_PIN_TYPE_MUX = 1, 137 DPLL_PIN_TYPE_EXT, 138 DPLL_PIN_TYPE_SYNCE_ETH_PORT, 139 DPLL_PIN_TYPE_INT_OSCILLATOR, 140 DPLL_PIN_TYPE_GNSS, 141 DPLL_PIN_TYPE_INT_NCO, 142 143 /* private: */ 144 __DPLL_PIN_TYPE_MAX, 145 DPLL_PIN_TYPE_MAX = (__DPLL_PIN_TYPE_MAX - 1) 146 }; 147 148 /** 149 * enum dpll_pin_direction - defines possible direction of a pin, valid values 150 * for DPLL_A_PIN_DIRECTION attribute 151 * @DPLL_PIN_DIRECTION_INPUT: pin used as a input of a signal 152 * @DPLL_PIN_DIRECTION_OUTPUT: pin used to output the signal 153 */ 154 enum dpll_pin_direction { 155 DPLL_PIN_DIRECTION_INPUT = 1, 156 DPLL_PIN_DIRECTION_OUTPUT, 157 158 /* private: */ 159 __DPLL_PIN_DIRECTION_MAX, 160 DPLL_PIN_DIRECTION_MAX = (__DPLL_PIN_DIRECTION_MAX - 1) 161 }; 162 163 #define DPLL_PIN_FREQUENCY_1_HZ 1 164 #define DPLL_PIN_FREQUENCY_10_KHZ 10000 165 #define DPLL_PIN_FREQUENCY_77_5_KHZ 77500 166 #define DPLL_PIN_FREQUENCY_10_MHZ 10000000 167 168 /** 169 * enum dpll_pin_state - defines possible states of a pin, valid values for 170 * DPLL_A_PIN_STATE attribute 171 * @DPLL_PIN_STATE_CONNECTED: pin connected, active input of phase locked loop 172 * @DPLL_PIN_STATE_DISCONNECTED: pin disconnected, not considered as a valid 173 * input 174 * @DPLL_PIN_STATE_SELECTABLE: pin enabled for automatic input selection 175 */ 176 enum dpll_pin_state { 177 DPLL_PIN_STATE_CONNECTED = 1, 178 DPLL_PIN_STATE_DISCONNECTED, 179 DPLL_PIN_STATE_SELECTABLE, 180 181 /* private: */ 182 __DPLL_PIN_STATE_MAX, 183 DPLL_PIN_STATE_MAX = (__DPLL_PIN_STATE_MAX - 1) 184 }; 185 186 /** 187 * enum dpll_pin_operstate - defines possible operational states of a pin with 188 * respect to its parent DPLL device, valid values for DPLL_A_PIN_OPERSTATE 189 * attribute 190 * @DPLL_PIN_OPERSTATE_ACTIVE: pin is qualified and actively used by the DPLL 191 * @DPLL_PIN_OPERSTATE_STANDBY: pin is qualified but not actively used by the 192 * DPLL 193 * @DPLL_PIN_OPERSTATE_NO_SIGNAL: pin does not have a valid signal 194 * @DPLL_PIN_OPERSTATE_QUAL_FAILED: pin signal failed qualification (e.g. 195 * frequency or phase monitor) 196 */ 197 enum dpll_pin_operstate { 198 DPLL_PIN_OPERSTATE_ACTIVE = 1, 199 DPLL_PIN_OPERSTATE_STANDBY, 200 DPLL_PIN_OPERSTATE_NO_SIGNAL, 201 DPLL_PIN_OPERSTATE_QUAL_FAILED, 202 203 /* private: */ 204 __DPLL_PIN_OPERSTATE_MAX, 205 DPLL_PIN_OPERSTATE_MAX = (__DPLL_PIN_OPERSTATE_MAX - 1) 206 }; 207 208 /** 209 * enum dpll_pin_capabilities - defines possible capabilities of a pin, valid 210 * flags on DPLL_A_PIN_CAPABILITIES attribute 211 * @DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE: pin direction can be changed 212 * @DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE: pin priority can be changed 213 * @DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE: pin state can be changed 214 * @DPLL_PIN_CAPABILITIES_STATE_CONNECTED_OVERRIDE: pin state can be set to 215 * connected regardless of current DPLL device mode, overriding the active 216 * input selection. Requires state-can-change to be set as well. 217 */ 218 enum dpll_pin_capabilities { 219 DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE = 1, 220 DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE = 2, 221 DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE = 4, 222 DPLL_PIN_CAPABILITIES_STATE_CONNECTED_OVERRIDE = 8, 223 }; 224 225 #define DPLL_PHASE_OFFSET_DIVIDER 1000 226 #define DPLL_PIN_MEASURED_FREQUENCY_DIVIDER 1000 227 228 /** 229 * enum dpll_feature_state - Allow control (enable/disable) and status checking 230 * over features. 231 * @DPLL_FEATURE_STATE_DISABLE: feature shall be disabled 232 * @DPLL_FEATURE_STATE_ENABLE: feature shall be enabled 233 */ 234 enum dpll_feature_state { 235 DPLL_FEATURE_STATE_DISABLE, 236 DPLL_FEATURE_STATE_ENABLE, 237 }; 238 239 enum dpll_a { 240 DPLL_A_ID = 1, 241 DPLL_A_MODULE_NAME, 242 DPLL_A_PAD, 243 DPLL_A_CLOCK_ID, 244 DPLL_A_MODE, 245 DPLL_A_MODE_SUPPORTED, 246 DPLL_A_LOCK_STATUS, 247 DPLL_A_TEMP, 248 DPLL_A_TYPE, 249 DPLL_A_LOCK_STATUS_ERROR, 250 DPLL_A_CLOCK_QUALITY_LEVEL, 251 DPLL_A_PHASE_OFFSET_MONITOR, 252 DPLL_A_PHASE_OFFSET_AVG_FACTOR, 253 DPLL_A_FREQUENCY_MONITOR, 254 255 __DPLL_A_MAX, 256 DPLL_A_MAX = (__DPLL_A_MAX - 1) 257 }; 258 259 enum dpll_a_pin { 260 DPLL_A_PIN_ID = 1, 261 DPLL_A_PIN_PARENT_ID, 262 DPLL_A_PIN_MODULE_NAME, 263 DPLL_A_PIN_PAD, 264 DPLL_A_PIN_CLOCK_ID, 265 DPLL_A_PIN_BOARD_LABEL, 266 DPLL_A_PIN_PANEL_LABEL, 267 DPLL_A_PIN_PACKAGE_LABEL, 268 DPLL_A_PIN_TYPE, 269 DPLL_A_PIN_DIRECTION, 270 DPLL_A_PIN_FREQUENCY, 271 DPLL_A_PIN_FREQUENCY_SUPPORTED, 272 DPLL_A_PIN_FREQUENCY_MIN, 273 DPLL_A_PIN_FREQUENCY_MAX, 274 DPLL_A_PIN_PRIO, 275 DPLL_A_PIN_STATE, 276 DPLL_A_PIN_CAPABILITIES, 277 DPLL_A_PIN_PARENT_DEVICE, 278 DPLL_A_PIN_PARENT_PIN, 279 DPLL_A_PIN_PHASE_ADJUST_MIN, 280 DPLL_A_PIN_PHASE_ADJUST_MAX, 281 DPLL_A_PIN_PHASE_ADJUST, 282 DPLL_A_PIN_PHASE_OFFSET, 283 DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET, 284 DPLL_A_PIN_ESYNC_FREQUENCY, 285 DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED, 286 DPLL_A_PIN_ESYNC_PULSE, 287 DPLL_A_PIN_REFERENCE_SYNC, 288 DPLL_A_PIN_PHASE_ADJUST_GRAN, 289 DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET_PPT, 290 DPLL_A_PIN_MEASURED_FREQUENCY, 291 DPLL_A_PIN_OPERSTATE, 292 293 __DPLL_A_PIN_MAX, 294 DPLL_A_PIN_MAX = (__DPLL_A_PIN_MAX - 1) 295 }; 296 297 enum dpll_cmd { 298 DPLL_CMD_DEVICE_ID_GET = 1, 299 DPLL_CMD_DEVICE_GET, 300 DPLL_CMD_DEVICE_SET, 301 DPLL_CMD_DEVICE_CREATE_NTF, 302 DPLL_CMD_DEVICE_DELETE_NTF, 303 DPLL_CMD_DEVICE_CHANGE_NTF, 304 DPLL_CMD_PIN_ID_GET, 305 DPLL_CMD_PIN_GET, 306 DPLL_CMD_PIN_SET, 307 DPLL_CMD_PIN_CREATE_NTF, 308 DPLL_CMD_PIN_DELETE_NTF, 309 DPLL_CMD_PIN_CHANGE_NTF, 310 311 __DPLL_CMD_MAX, 312 DPLL_CMD_MAX = (__DPLL_CMD_MAX - 1) 313 }; 314 315 #define DPLL_MCGRP_MONITOR "monitor" 316 317 #endif /* _UAPI_LINUX_DPLL_H */ 318