1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * RZ/G2L MIPI DSI Encoder Driver
4 *
5 * Copyright (C) 2022 Renesas Electronics Corporation
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/clk.h>
10 #include <linux/clk/renesas.h>
11 #include <linux/delay.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/io.h>
14 #include <linux/iopoll.h>
15 #include <linux/math.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/of_graph.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/reset.h>
22 #include <linux/slab.h>
23 #include <linux/units.h>
24
25 #include <drm/drm_atomic.h>
26 #include <drm/drm_atomic_helper.h>
27 #include <drm/drm_bridge.h>
28 #include <drm/drm_mipi_dsi.h>
29 #include <drm/drm_of.h>
30 #include <drm/drm_panel.h>
31 #include <drm/drm_probe_helper.h>
32 #include <video/mipi_display.h>
33
34 #include "rzg2l_mipi_dsi_regs.h"
35
36 MODULE_IMPORT_NS("RZV2H_CPG");
37
38 #define RZG2L_DCS_BUF_SIZE 128 /* Maximum DCS buffer size in external memory. */
39
40 #define RZ_MIPI_DSI_FEATURE_16BPP BIT(0)
41
42 struct rzg2l_mipi_dsi;
43
44 struct rzg2l_mipi_dsi_hw_info {
45 int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, u64 hsfreq_millihz);
46 void (*dphy_startup_late_init)(struct rzg2l_mipi_dsi *dsi);
47 void (*dphy_exit)(struct rzg2l_mipi_dsi *dsi);
48 int (*dphy_conf_clks)(struct rzg2l_mipi_dsi *dsi, unsigned long mode_freq,
49 u64 *hsfreq_millihz);
50 unsigned int (*dphy_mode_clk_check)(struct rzg2l_mipi_dsi *dsi,
51 unsigned long mode_freq);
52 struct {
53 const struct rzv2h_pll_limits **limits;
54 const u8 *table;
55 const u8 table_size;
56 } cpg_plldsi;
57 u32 phy_reg_offset;
58 u32 link_reg_offset;
59 unsigned long min_dclk;
60 unsigned long max_dclk;
61 u8 features;
62 };
63
64 struct rzv2h_dsi_mode_calc {
65 unsigned long mode_freq_khz;
66 struct rzv2h_pll_pars dsi_parameters;
67 };
68
69 struct rzg2l_mipi_dsi {
70 struct device *dev;
71 void __iomem *mmio;
72
73 const struct rzg2l_mipi_dsi_hw_info *info;
74
75 struct reset_control *rstc;
76 struct reset_control *arstc;
77 struct reset_control *prstc;
78
79 struct mipi_dsi_host host;
80 struct drm_bridge bridge;
81 struct drm_bridge *next_bridge;
82
83 struct clk *vclk;
84 struct clk *lpclk;
85
86 enum mipi_dsi_pixel_format format;
87 unsigned int num_data_lanes;
88 unsigned int lanes;
89 unsigned long mode_flags;
90
91 struct rzv2h_dsi_mode_calc mode_calc;
92
93 /* DCS buffer pointers when using external memory. */
94 dma_addr_t dcs_buf_phys;
95 u8 *dcs_buf_virt;
96 };
97
98 static const struct rzv2h_pll_limits rzv2h_plldsi_div_limits = {
99 .fout = { .min = 80 * MEGA, .max = 1500 * MEGA },
100 .fvco = { .min = 1050 * MEGA, .max = 2100 * MEGA },
101 .m = { .min = 64, .max = 1023 },
102 .p = { .min = 1, .max = 4 },
103 .s = { .min = 0, .max = 5 },
104 .k = { .min = -32768, .max = 32767 },
105 };
106
107 static inline struct rzg2l_mipi_dsi *
bridge_to_rzg2l_mipi_dsi(struct drm_bridge * bridge)108 bridge_to_rzg2l_mipi_dsi(struct drm_bridge *bridge)
109 {
110 return container_of(bridge, struct rzg2l_mipi_dsi, bridge);
111 }
112
113 static inline struct rzg2l_mipi_dsi *
host_to_rzg2l_mipi_dsi(struct mipi_dsi_host * host)114 host_to_rzg2l_mipi_dsi(struct mipi_dsi_host *host)
115 {
116 return container_of(host, struct rzg2l_mipi_dsi, host);
117 }
118
119 struct rzg2l_mipi_dsi_timings {
120 unsigned long hsfreq_max;
121 u32 t_init;
122 u32 tclk_prepare;
123 u32 ths_prepare;
124 u32 tclk_zero;
125 u32 tclk_pre;
126 u32 tclk_post;
127 u32 tclk_trail;
128 u32 ths_zero;
129 u32 ths_trail;
130 u32 ths_exit;
131 u32 tlpx;
132 };
133
134 static const struct rzg2l_mipi_dsi_timings rzg2l_mipi_dsi_global_timings[] = {
135 {
136 .hsfreq_max = 80000000,
137 .t_init = 79801,
138 .tclk_prepare = 8,
139 .ths_prepare = 13,
140 .tclk_zero = 33,
141 .tclk_pre = 24,
142 .tclk_post = 94,
143 .tclk_trail = 10,
144 .ths_zero = 23,
145 .ths_trail = 17,
146 .ths_exit = 13,
147 .tlpx = 6,
148 },
149 {
150 .hsfreq_max = 125000000,
151 .t_init = 79801,
152 .tclk_prepare = 8,
153 .ths_prepare = 12,
154 .tclk_zero = 33,
155 .tclk_pre = 15,
156 .tclk_post = 94,
157 .tclk_trail = 10,
158 .ths_zero = 23,
159 .ths_trail = 17,
160 .ths_exit = 13,
161 .tlpx = 6,
162 },
163 {
164 .hsfreq_max = 250000000,
165 .t_init = 79801,
166 .tclk_prepare = 8,
167 .ths_prepare = 12,
168 .tclk_zero = 33,
169 .tclk_pre = 13,
170 .tclk_post = 94,
171 .tclk_trail = 10,
172 .ths_zero = 23,
173 .ths_trail = 16,
174 .ths_exit = 13,
175 .tlpx = 6,
176 },
177 {
178 .hsfreq_max = 360000000,
179 .t_init = 79801,
180 .tclk_prepare = 8,
181 .ths_prepare = 10,
182 .tclk_zero = 33,
183 .tclk_pre = 4,
184 .tclk_post = 35,
185 .tclk_trail = 7,
186 .ths_zero = 16,
187 .ths_trail = 9,
188 .ths_exit = 13,
189 .tlpx = 6,
190 },
191 {
192 .hsfreq_max = 720000000,
193 .t_init = 79801,
194 .tclk_prepare = 8,
195 .ths_prepare = 9,
196 .tclk_zero = 33,
197 .tclk_pre = 4,
198 .tclk_post = 35,
199 .tclk_trail = 7,
200 .ths_zero = 16,
201 .ths_trail = 9,
202 .ths_exit = 13,
203 .tlpx = 6,
204 },
205 {
206 .hsfreq_max = 1500000000,
207 .t_init = 79801,
208 .tclk_prepare = 8,
209 .ths_prepare = 9,
210 .tclk_zero = 33,
211 .tclk_pre = 4,
212 .tclk_post = 35,
213 .tclk_trail = 7,
214 .ths_zero = 16,
215 .ths_trail = 9,
216 .ths_exit = 13,
217 .tlpx = 6,
218 },
219 };
220
221 /**
222 * struct rzv2h_mipi_dsi_timings - Timing parameter table structure
223 *
224 * @hsfreq: Pointer to frequency threshold array
225 * @len: Number of entries in the hsfreq array
226 * @base_value: Base register value offset for this timing parameter
227 *
228 * Each timing parameter (TCLK*, THS*, etc.) has its own table with
229 * frequency thresholds and corresponding base register values.
230 */
231 struct rzv2h_mipi_dsi_timings {
232 const u8 *hsfreq;
233 u8 len;
234 u8 base_value;
235 };
236
237 /*
238 * enum rzv2h_dsi_timing_idx - MIPI DSI timing parameter indices
239 *
240 * These enums correspond to different MIPI DSI PHY timing parameters.
241 */
242 enum rzv2h_dsi_timing_idx {
243 TCLKPRPRCTL,
244 TCLKZEROCTL,
245 TCLKPOSTCTL,
246 TCLKTRAILCTL,
247 THSPRPRCTL,
248 THSZEROCTL,
249 THSTRAILCTL,
250 TLPXCTL,
251 THSEXITCTL,
252 };
253
254 /*
255 * RZ/V2H(P) Frequency threshold lookup tables for D-PHY timing parameters
256 *
257 * - Each array contains frequency thresholds (in units of 10 Mbps),
258 * taken directly from the table 9.5-4 hardware manual.
259 * - These thresholds define the frequency ranges for which timing
260 * register values must be programmed.
261 * - The actual register value is calculated in
262 * rzv2h_dphy_find_timings_val():
263 *
264 * register_value = timings->base_value + table_index
265 *
266 * Example (TCLKPRPRCTL, from HW manual):
267 * 0-150 Mbps -> index 0 -> register_value = base + 0 = 0 + 0 = 0
268 * 151-260 Mbps -> index 1 -> register_value = base + 1 = 0 + 1 = 1
269 * 261-370 Mbps -> index 2 -> register_value = base + 2 = 0 + 2 = 2
270 *
271 * Each of the following arrays corresponds to a specific timing
272 * parameter (TCLKPRPRCTL, TCLKZEROCTL, TCLKPOSTCTL, etc.).
273 */
274 static const u8 tclkprprctl[] = {
275 15, 26, 37, 47, 58, 69, 79, 90, 101, 111, 122, 133, 143, 150,
276 };
277
278 static const u8 tclkzeroctl[] = {
279 9, 11, 13, 15, 18, 21, 23, 24, 25, 27, 29, 31, 34, 36, 38,
280 41, 43, 45, 47, 50, 52, 54, 57, 59, 61, 63, 66, 68, 70, 73,
281 75, 77, 79, 82, 84, 86, 89, 91, 93, 95, 98, 100, 102, 105,
282 107, 109, 111, 114, 116, 118, 121, 123, 125, 127, 130, 132,
283 134, 137, 139, 141, 143, 146, 148, 150,
284 };
285
286 static const u8 tclkpostctl[] = {
287 8, 21, 34, 48, 61, 74, 88, 101, 114, 128, 141, 150,
288 };
289
290 static const u8 tclktrailctl[] = {
291 14, 25, 37, 48, 59, 71, 82, 94, 105, 117, 128, 139, 150,
292 };
293
294 static const u8 thsprprctl[] = {
295 11, 19, 29, 40, 50, 61, 72, 82, 93, 103, 114, 125, 135, 146, 150,
296 };
297
298 static const u8 thszeroctl[] = {
299 18, 24, 29, 35, 40, 46, 51, 57, 62, 68, 73, 79, 84, 90,
300 95, 101, 106, 112, 117, 123, 128, 134, 139, 145, 150,
301 };
302
303 static const u8 thstrailctl[] = {
304 10, 21, 32, 42, 53, 64, 75, 85, 96, 107, 118, 128, 139, 150,
305 };
306
307 static const u8 tlpxctl[] = {
308 13, 26, 39, 53, 66, 79, 93, 106, 119, 133, 146, 150,
309 };
310
311 static const u8 thsexitctl[] = {
312 15, 23, 31, 39, 47, 55, 63, 71, 79, 87,
313 95, 103, 111, 119, 127, 135, 143, 150,
314 };
315
316 /*
317 * rzv2h_dsi_timings_tables - main timing parameter lookup table
318 * Maps timing parameter enum to its frequency table, array length and
319 * base register offset value.
320 */
321 static const struct rzv2h_mipi_dsi_timings rzv2h_dsi_timings_tables[] = {
322 [TCLKPRPRCTL] = {
323 .hsfreq = tclkprprctl,
324 .len = ARRAY_SIZE(tclkprprctl),
325 .base_value = 0,
326 },
327 [TCLKZEROCTL] = {
328 .hsfreq = tclkzeroctl,
329 .len = ARRAY_SIZE(tclkzeroctl),
330 .base_value = 2,
331 },
332 [TCLKPOSTCTL] = {
333 .hsfreq = tclkpostctl,
334 .len = ARRAY_SIZE(tclkpostctl),
335 .base_value = 6,
336 },
337 [TCLKTRAILCTL] = {
338 .hsfreq = tclktrailctl,
339 .len = ARRAY_SIZE(tclktrailctl),
340 .base_value = 1,
341 },
342 [THSPRPRCTL] = {
343 .hsfreq = thsprprctl,
344 .len = ARRAY_SIZE(thsprprctl),
345 .base_value = 0,
346 },
347 [THSZEROCTL] = {
348 .hsfreq = thszeroctl,
349 .len = ARRAY_SIZE(thszeroctl),
350 .base_value = 0,
351 },
352 [THSTRAILCTL] = {
353 .hsfreq = thstrailctl,
354 .len = ARRAY_SIZE(thstrailctl),
355 .base_value = 3,
356 },
357 [TLPXCTL] = {
358 .hsfreq = tlpxctl,
359 .len = ARRAY_SIZE(tlpxctl),
360 .base_value = 0,
361 },
362 [THSEXITCTL] = {
363 .hsfreq = thsexitctl,
364 .len = ARRAY_SIZE(thsexitctl),
365 .base_value = 1,
366 },
367 };
368
369 /**
370 * rzv2h_dphy_find_ulpsexit - Find ULP Exit timing value based on frequency
371 * The function maps frequency ranges to ULP exit timing values.
372 * Thresholds in the local hsfreq[] are expressed in Hz already.
373 *
374 * @freq: Input frequency in Hz
375 *
376 * Return: ULP exit timing value
377 */
rzv2h_dphy_find_ulpsexit(unsigned long freq)378 static u16 rzv2h_dphy_find_ulpsexit(unsigned long freq)
379 {
380 /* Frequency thresholds in Hz for ULP exit timing selection */
381 static const unsigned long hsfreq[] = {
382 1953125UL,
383 3906250UL,
384 7812500UL,
385 15625000UL,
386 };
387 /* Corresponding ULP exit timing values for each frequency range */
388 static const u16 ulpsexit[] = {49, 98, 195, 391};
389 unsigned int i;
390
391 /* Find the appropriate frequency range */
392 for (i = 0; i < ARRAY_SIZE(hsfreq); i++) {
393 if (freq <= hsfreq[i])
394 break;
395 }
396
397 /* If frequency exceeds all thresholds, use the highest range */
398 if (i == ARRAY_SIZE(hsfreq))
399 i--;
400
401 return ulpsexit[i];
402 }
403
404 /**
405 * rzv2h_dphy_find_timings_val - Find timing parameter value from lookup tables
406 * @freq: Input frequency in Hz
407 * @index: Index to select timing parameter table (see enum rzv2h_dsi_timing_idx)
408 *
409 * Selects the timing table for the requested parameter, finds the
410 * frequency range entry and returns the register value to program:
411 *
412 * register_value = timings->base_value + table_index
413 *
414 * Note: frequency table entries are stored as small integers (units of 10):
415 * threshold_in_hz = (unsigned long)table_entry * 10 * MEGA
416 *
417 * Return: timing register value to be programmed into hardware
418 */
rzv2h_dphy_find_timings_val(unsigned long freq,u8 index)419 static u16 rzv2h_dphy_find_timings_val(unsigned long freq, u8 index)
420 {
421 const struct rzv2h_mipi_dsi_timings *timings;
422 u16 i;
423
424 /* Get the timing table structure for the requested parameter */
425 timings = &rzv2h_dsi_timings_tables[index];
426
427 /*
428 * Search through frequency table to find appropriate range
429 * timings->hsfreq[i] contains frequency values from HW manual
430 * Convert to Hz by multiplying by 10 * MEGA.
431 */
432 for (i = 0; i < timings->len; i++) {
433 unsigned long hsfreq = timings->hsfreq[i] * 10 * MEGA;
434
435 if (freq <= hsfreq)
436 break;
437 }
438
439 /* If frequency exceeds table range, use the last entry */
440 if (i == timings->len)
441 i--;
442
443 /*
444 * Calculate final register value:
445 * - timings->base_value: base value for this timing parameter
446 * - i: index into frequency table (0-based)
447 * Combined they give the exact register value to program
448 */
449 return timings->base_value + i;
450 };
451
rzg2l_mipi_dsi_phy_write(struct rzg2l_mipi_dsi * dsi,u32 reg,u32 data)452 static void rzg2l_mipi_dsi_phy_write(struct rzg2l_mipi_dsi *dsi, u32 reg, u32 data)
453 {
454 iowrite32(data, dsi->mmio + dsi->info->phy_reg_offset + reg);
455 }
456
rzg2l_mipi_dsi_link_write(struct rzg2l_mipi_dsi * dsi,u32 reg,u32 data)457 static void rzg2l_mipi_dsi_link_write(struct rzg2l_mipi_dsi *dsi, u32 reg, u32 data)
458 {
459 iowrite32(data, dsi->mmio + dsi->info->link_reg_offset + reg);
460 }
461
rzg2l_mipi_dsi_phy_read(struct rzg2l_mipi_dsi * dsi,u32 reg)462 static u32 rzg2l_mipi_dsi_phy_read(struct rzg2l_mipi_dsi *dsi, u32 reg)
463 {
464 return ioread32(dsi->mmio + dsi->info->phy_reg_offset + reg);
465 }
466
rzg2l_mipi_dsi_link_read(struct rzg2l_mipi_dsi * dsi,u32 reg)467 static u32 rzg2l_mipi_dsi_link_read(struct rzg2l_mipi_dsi *dsi, u32 reg)
468 {
469 return ioread32(dsi->mmio + dsi->info->link_reg_offset + reg);
470 }
471
472 /* -----------------------------------------------------------------------------
473 * Hardware Setup
474 */
475
rzg2l_mipi_dsi_dphy_init(struct rzg2l_mipi_dsi * dsi,u64 hsfreq_millihz)476 static int rzg2l_mipi_dsi_dphy_init(struct rzg2l_mipi_dsi *dsi,
477 u64 hsfreq_millihz)
478 {
479 unsigned long hsfreq = DIV_ROUND_CLOSEST_ULL(hsfreq_millihz, MILLI);
480 const struct rzg2l_mipi_dsi_timings *dphy_timings;
481 unsigned int i;
482 u32 dphyctrl0;
483 u32 dphytim0;
484 u32 dphytim1;
485 u32 dphytim2;
486 u32 dphytim3;
487 int ret;
488
489 /* All DSI global operation timings are set with recommended setting */
490 for (i = 0; i < ARRAY_SIZE(rzg2l_mipi_dsi_global_timings); ++i) {
491 dphy_timings = &rzg2l_mipi_dsi_global_timings[i];
492 if (hsfreq <= dphy_timings->hsfreq_max)
493 break;
494 }
495
496 /* Initializing DPHY before accessing LINK */
497 dphyctrl0 = DSIDPHYCTRL0_CAL_EN_HSRX_OFS | DSIDPHYCTRL0_CMN_MASTER_EN |
498 DSIDPHYCTRL0_RE_VDD_DETVCCQLV18 | DSIDPHYCTRL0_EN_BGR;
499
500 rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYCTRL0, dphyctrl0);
501 usleep_range(20, 30);
502
503 dphyctrl0 |= DSIDPHYCTRL0_EN_LDO1200;
504 rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYCTRL0, dphyctrl0);
505 usleep_range(10, 20);
506
507 dphytim0 = DSIDPHYTIM0_TCLK_MISS(0) |
508 DSIDPHYTIM0_T_INIT(dphy_timings->t_init);
509 dphytim1 = DSIDPHYTIM1_THS_PREPARE(dphy_timings->ths_prepare) |
510 DSIDPHYTIM1_TCLK_PREPARE(dphy_timings->tclk_prepare) |
511 DSIDPHYTIM1_THS_SETTLE(0) |
512 DSIDPHYTIM1_TCLK_SETTLE(0);
513 dphytim2 = DSIDPHYTIM2_TCLK_TRAIL(dphy_timings->tclk_trail) |
514 DSIDPHYTIM2_TCLK_POST(dphy_timings->tclk_post) |
515 DSIDPHYTIM2_TCLK_PRE(dphy_timings->tclk_pre) |
516 DSIDPHYTIM2_TCLK_ZERO(dphy_timings->tclk_zero);
517 dphytim3 = DSIDPHYTIM3_TLPX(dphy_timings->tlpx) |
518 DSIDPHYTIM3_THS_EXIT(dphy_timings->ths_exit) |
519 DSIDPHYTIM3_THS_TRAIL(dphy_timings->ths_trail) |
520 DSIDPHYTIM3_THS_ZERO(dphy_timings->ths_zero);
521
522 rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYTIM0, dphytim0);
523 rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYTIM1, dphytim1);
524 rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYTIM2, dphytim2);
525 rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYTIM3, dphytim3);
526
527 ret = reset_control_deassert(dsi->rstc);
528 if (ret < 0)
529 return ret;
530
531 udelay(1);
532
533 return 0;
534 }
535
rzg2l_mipi_dsi_dphy_exit(struct rzg2l_mipi_dsi * dsi)536 static void rzg2l_mipi_dsi_dphy_exit(struct rzg2l_mipi_dsi *dsi)
537 {
538 u32 dphyctrl0;
539
540 dphyctrl0 = rzg2l_mipi_dsi_phy_read(dsi, DSIDPHYCTRL0);
541
542 dphyctrl0 &= ~(DSIDPHYCTRL0_EN_LDO1200 | DSIDPHYCTRL0_EN_BGR);
543 rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYCTRL0, dphyctrl0);
544
545 reset_control_assert(dsi->rstc);
546 }
547
rzg2l_dphy_conf_clks(struct rzg2l_mipi_dsi * dsi,unsigned long mode_freq,u64 * hsfreq_millihz)548 static int rzg2l_dphy_conf_clks(struct rzg2l_mipi_dsi *dsi, unsigned long mode_freq,
549 u64 *hsfreq_millihz)
550 {
551 unsigned long vclk_rate;
552 unsigned int bpp;
553
554 clk_set_rate(dsi->vclk, mode_freq * KILO);
555 vclk_rate = clk_get_rate(dsi->vclk);
556 if (vclk_rate != mode_freq * KILO)
557 dev_dbg(dsi->dev, "Requested vclk rate %lu, actual %lu mismatch\n",
558 mode_freq * KILO, vclk_rate);
559 /*
560 * Relationship between hsclk and vclk must follow
561 * vclk * bpp = hsclk * 8 * lanes
562 * where vclk: video clock (Hz)
563 * bpp: video pixel bit depth
564 * hsclk: DSI HS Byte clock frequency (Hz)
565 * lanes: number of data lanes
566 *
567 * hsclk(bit) = hsclk(byte) * 8 = hsfreq
568 */
569 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
570 *hsfreq_millihz = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(vclk_rate, bpp * MILLI),
571 dsi->lanes);
572
573 return 0;
574 }
575
rzv2h_dphy_mode_clk_check(struct rzg2l_mipi_dsi * dsi,unsigned long mode_freq)576 static unsigned int rzv2h_dphy_mode_clk_check(struct rzg2l_mipi_dsi *dsi,
577 unsigned long mode_freq)
578 {
579 u64 hsfreq_millihz, mode_freq_hz, mode_freq_millihz;
580 struct rzv2h_pll_div_pars cpg_dsi_parameters;
581 struct rzv2h_pll_pars dsi_parameters;
582 bool parameters_found;
583 unsigned int bpp;
584
585 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
586 mode_freq_hz = mul_u32_u32(mode_freq, KILO);
587 mode_freq_millihz = mode_freq_hz * MILLI;
588 parameters_found =
589 rzv2h_get_pll_divs_pars(dsi->info->cpg_plldsi.limits[0],
590 &cpg_dsi_parameters,
591 dsi->info->cpg_plldsi.table,
592 dsi->info->cpg_plldsi.table_size,
593 mode_freq_millihz);
594 if (!parameters_found)
595 return MODE_CLOCK_RANGE;
596
597 hsfreq_millihz = DIV_ROUND_CLOSEST_ULL(cpg_dsi_parameters.div.freq_millihz * bpp,
598 dsi->lanes);
599 parameters_found = rzv2h_get_pll_pars(&rzv2h_plldsi_div_limits,
600 &dsi_parameters, hsfreq_millihz);
601 if (!parameters_found)
602 return MODE_CLOCK_RANGE;
603
604 if (abs(dsi_parameters.error_millihz) >= 500)
605 return MODE_CLOCK_RANGE;
606
607 memcpy(&dsi->mode_calc.dsi_parameters, &dsi_parameters, sizeof(dsi_parameters));
608 dsi->mode_calc.mode_freq_khz = mode_freq;
609
610 return MODE_OK;
611 }
612
rzv2h_dphy_conf_clks(struct rzg2l_mipi_dsi * dsi,unsigned long mode_freq,u64 * hsfreq_millihz)613 static int rzv2h_dphy_conf_clks(struct rzg2l_mipi_dsi *dsi, unsigned long mode_freq,
614 u64 *hsfreq_millihz)
615 {
616 struct rzv2h_pll_pars *dsi_parameters = &dsi->mode_calc.dsi_parameters;
617 unsigned long status;
618
619 if (dsi->mode_calc.mode_freq_khz != mode_freq) {
620 status = rzv2h_dphy_mode_clk_check(dsi, mode_freq);
621 if (status != MODE_OK) {
622 dev_err(dsi->dev, "No PLL parameters found for mode clk %lu\n",
623 mode_freq);
624 return -EINVAL;
625 }
626 }
627
628 *hsfreq_millihz = dsi_parameters->freq_millihz;
629
630 return 0;
631 }
632
rzv2h_mipi_dsi_dphy_init(struct rzg2l_mipi_dsi * dsi,u64 hsfreq_millihz)633 static int rzv2h_mipi_dsi_dphy_init(struct rzg2l_mipi_dsi *dsi,
634 u64 hsfreq_millihz)
635 {
636 struct rzv2h_pll_pars *dsi_parameters = &dsi->mode_calc.dsi_parameters;
637 unsigned long lpclk_rate = clk_get_rate(dsi->lpclk);
638 u32 phytclksetr, phythssetr, phytlpxsetr, phycr;
639 struct rzg2l_mipi_dsi_timings dphy_timings;
640 u16 ulpsexit;
641 u64 hsfreq;
642
643 hsfreq = DIV_ROUND_CLOSEST_ULL(hsfreq_millihz, MILLI);
644
645 if (dsi_parameters->freq_millihz != hsfreq_millihz &&
646 !rzv2h_get_pll_pars(&rzv2h_plldsi_div_limits, dsi_parameters,
647 hsfreq_millihz)) {
648 dev_err(dsi->dev, "No PLL parameters found for HSFREQ %lluHz\n", hsfreq);
649 return -EINVAL;
650 }
651
652 dphy_timings.tclk_trail =
653 rzv2h_dphy_find_timings_val(hsfreq, TCLKTRAILCTL);
654 dphy_timings.tclk_post =
655 rzv2h_dphy_find_timings_val(hsfreq, TCLKPOSTCTL);
656 dphy_timings.tclk_zero =
657 rzv2h_dphy_find_timings_val(hsfreq, TCLKZEROCTL);
658 dphy_timings.tclk_prepare =
659 rzv2h_dphy_find_timings_val(hsfreq, TCLKPRPRCTL);
660 dphy_timings.ths_exit =
661 rzv2h_dphy_find_timings_val(hsfreq, THSEXITCTL);
662 dphy_timings.ths_trail =
663 rzv2h_dphy_find_timings_val(hsfreq, THSTRAILCTL);
664 dphy_timings.ths_zero =
665 rzv2h_dphy_find_timings_val(hsfreq, THSZEROCTL);
666 dphy_timings.ths_prepare =
667 rzv2h_dphy_find_timings_val(hsfreq, THSPRPRCTL);
668 dphy_timings.tlpx =
669 rzv2h_dphy_find_timings_val(hsfreq, TLPXCTL);
670 ulpsexit = rzv2h_dphy_find_ulpsexit(lpclk_rate);
671
672 phytclksetr = FIELD_PREP(PHYTCLKSETR_TCLKTRAILCTL, dphy_timings.tclk_trail) |
673 FIELD_PREP(PHYTCLKSETR_TCLKPOSTCTL, dphy_timings.tclk_post) |
674 FIELD_PREP(PHYTCLKSETR_TCLKZEROCTL, dphy_timings.tclk_zero) |
675 FIELD_PREP(PHYTCLKSETR_TCLKPRPRCTL, dphy_timings.tclk_prepare);
676 phythssetr = FIELD_PREP(PHYTHSSETR_THSEXITCTL, dphy_timings.ths_exit) |
677 FIELD_PREP(PHYTHSSETR_THSTRAILCTL, dphy_timings.ths_trail) |
678 FIELD_PREP(PHYTHSSETR_THSZEROCTL, dphy_timings.ths_zero) |
679 FIELD_PREP(PHYTHSSETR_THSPRPRCTL, dphy_timings.ths_prepare);
680 phytlpxsetr = rzg2l_mipi_dsi_phy_read(dsi, PHYTLPXSETR) & ~PHYTLPXSETR_TLPXCTL;
681 phytlpxsetr |= FIELD_PREP(PHYTLPXSETR_TLPXCTL, dphy_timings.tlpx);
682 phycr = rzg2l_mipi_dsi_phy_read(dsi, PHYCR) & ~GENMASK(9, 0);
683 phycr |= FIELD_PREP(PHYCR_ULPSEXIT, ulpsexit);
684
685 /* Setting all D-PHY Timings Registers */
686 rzg2l_mipi_dsi_phy_write(dsi, PHYTCLKSETR, phytclksetr);
687 rzg2l_mipi_dsi_phy_write(dsi, PHYTHSSETR, phythssetr);
688 rzg2l_mipi_dsi_phy_write(dsi, PHYTLPXSETR, phytlpxsetr);
689 rzg2l_mipi_dsi_phy_write(dsi, PHYCR, phycr);
690
691 rzg2l_mipi_dsi_phy_write(dsi, PLLCLKSET0R,
692 FIELD_PREP(PLLCLKSET0R_PLL_S, dsi_parameters->s) |
693 FIELD_PREP(PLLCLKSET0R_PLL_P, dsi_parameters->p) |
694 FIELD_PREP(PLLCLKSET0R_PLL_M, dsi_parameters->m));
695 rzg2l_mipi_dsi_phy_write(dsi, PLLCLKSET1R,
696 FIELD_PREP(PLLCLKSET1R_PLL_K, dsi_parameters->k));
697
698 /*
699 * From RZ/V2H HW manual (Rev.1.20) section 9.5.3 Operation,
700 * (C) After write to D-PHY registers we need to wait for more than 1 x tp
701 *
702 * tp = 1 / (PLLREFCLK / PLLCLKSET0R.PLL_P)
703 * PLLREFCLK = 24MHz
704 * PLLCLKSET0R.PLL_P = {1, 2, 3, 4}
705 *
706 * To handle all the cases lets use PLLCLKSET0R.PLL_P = 4
707 * tp = 1 / (24MHz / 4) = 1 / 6MHz = 166.67ns
708 */
709 ndelay(200);
710
711 rzg2l_mipi_dsi_phy_write(dsi, PLLENR, PLLENR_PLLEN);
712 /*
713 * From RZ/V2H HW manual (Rev.1.20) section 9.5.3 Operation,
714 * (D) After write to PLLENR.PLLEN we need to wait for more than 3000 x tp
715 *
716 * 3000 x tp = 3000 x 0.16667 ns = 500.01 microseconds
717 */
718 usleep_range(510, 520);
719
720 return 0;
721 }
722
rzv2h_mipi_dsi_dphy_startup_late_init(struct rzg2l_mipi_dsi * dsi)723 static void rzv2h_mipi_dsi_dphy_startup_late_init(struct rzg2l_mipi_dsi *dsi)
724 {
725 /*
726 * From RZ/V2H HW manual (Rev.1.20) section 9.5.3 Operation,
727 * (E) After write to TXSETR we need to wait for more than 200 microseconds
728 * and then write to PHYRSTR
729 */
730 usleep_range(210, 220);
731 rzg2l_mipi_dsi_phy_write(dsi, PHYRSTR, PHYRSTR_PHYMRSTN);
732 }
733
rzv2h_mipi_dsi_dphy_exit(struct rzg2l_mipi_dsi * dsi)734 static void rzv2h_mipi_dsi_dphy_exit(struct rzg2l_mipi_dsi *dsi)
735 {
736 rzg2l_mipi_dsi_phy_write(dsi, PLLENR, 0);
737 }
738
rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi * dsi,const struct drm_display_mode * mode)739 static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi,
740 const struct drm_display_mode *mode)
741 {
742 unsigned long hsfreq;
743 u64 hsfreq_millihz;
744 u32 txsetr;
745 u32 clstptsetr;
746 u32 lptrnstsetr;
747 u32 clkkpt;
748 u32 clkbfht;
749 u32 clkstpt;
750 u32 golpbkt;
751 u32 dsisetr;
752 int ret;
753
754 ret = pm_runtime_resume_and_get(dsi->dev);
755 if (ret < 0)
756 return ret;
757
758 ret = dsi->info->dphy_conf_clks(dsi, mode->clock, &hsfreq_millihz);
759 if (ret < 0)
760 goto err_phy;
761
762 ret = dsi->info->dphy_init(dsi, hsfreq_millihz);
763 if (ret < 0)
764 goto err_phy;
765
766 /* Enable Data lanes and Clock lanes */
767 txsetr = TXSETR_DLEN | TXSETR_NUMLANEUSE(dsi->lanes - 1) | TXSETR_CLEN;
768 rzg2l_mipi_dsi_link_write(dsi, TXSETR, txsetr);
769
770 if (dsi->info->dphy_startup_late_init)
771 dsi->info->dphy_startup_late_init(dsi);
772
773 hsfreq = DIV_ROUND_CLOSEST_ULL(hsfreq_millihz, MILLI);
774 /*
775 * Global timings characteristic depends on high speed Clock Frequency
776 * Currently MIPI DSI-IF just supports maximum FHD@60 with:
777 * - videoclock = 148.5 (MHz)
778 * - bpp: maximum 24bpp
779 * - data lanes: maximum 4 lanes
780 * Therefore maximum hsclk will be 891 Mbps.
781 */
782 if (hsfreq > 445500000) {
783 clkkpt = 12;
784 clkbfht = 15;
785 clkstpt = 48;
786 golpbkt = 75;
787 } else if (hsfreq > 250000000) {
788 clkkpt = 7;
789 clkbfht = 8;
790 clkstpt = 27;
791 golpbkt = 40;
792 } else {
793 clkkpt = 8;
794 clkbfht = 6;
795 clkstpt = 24;
796 golpbkt = 29;
797 }
798
799 clstptsetr = CLSTPTSETR_CLKKPT(clkkpt) | CLSTPTSETR_CLKBFHT(clkbfht) |
800 CLSTPTSETR_CLKSTPT(clkstpt);
801 rzg2l_mipi_dsi_link_write(dsi, CLSTPTSETR, clstptsetr);
802
803 lptrnstsetr = LPTRNSTSETR_GOLPBKT(golpbkt);
804 rzg2l_mipi_dsi_link_write(dsi, LPTRNSTSETR, lptrnstsetr);
805
806 /*
807 * Increase MRPSZ as the default value of 1 will result in long read
808 * commands payload not being saved to memory.
809 */
810 dsisetr = rzg2l_mipi_dsi_link_read(dsi, DSISETR);
811 dsisetr &= ~DSISETR_MRPSZ;
812 dsisetr |= FIELD_PREP(DSISETR_MRPSZ, RZG2L_DCS_BUF_SIZE);
813 rzg2l_mipi_dsi_link_write(dsi, DSISETR, dsisetr);
814
815 return 0;
816
817 err_phy:
818 dsi->info->dphy_exit(dsi);
819 pm_runtime_put(dsi->dev);
820
821 return ret;
822 }
823
rzg2l_mipi_dsi_stop(struct rzg2l_mipi_dsi * dsi)824 static void rzg2l_mipi_dsi_stop(struct rzg2l_mipi_dsi *dsi)
825 {
826 dsi->info->dphy_exit(dsi);
827 pm_runtime_put(dsi->dev);
828 }
829
rzg2l_mipi_dsi_set_display_timing(struct rzg2l_mipi_dsi * dsi,const struct drm_display_mode * mode)830 static void rzg2l_mipi_dsi_set_display_timing(struct rzg2l_mipi_dsi *dsi,
831 const struct drm_display_mode *mode)
832 {
833 u32 vich1ppsetr;
834 u32 vich1vssetr;
835 u32 vich1vpsetr;
836 u32 vich1hssetr;
837 u32 vich1hpsetr;
838 int dsi_format;
839 u32 delay[2];
840 u8 index;
841
842 /* Configuration for Pixel Packet */
843 dsi_format = mipi_dsi_pixel_format_to_bpp(dsi->format);
844 switch (dsi_format) {
845 case 24:
846 vich1ppsetr = VICH1PPSETR_DT_RGB24;
847 break;
848 case 18:
849 vich1ppsetr = VICH1PPSETR_DT_RGB18;
850 break;
851 case 16:
852 vich1ppsetr = VICH1PPSETR_DT_RGB16;
853 break;
854 }
855
856 if ((dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) &&
857 !(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST))
858 vich1ppsetr |= VICH1PPSETR_TXESYNC_PULSE;
859
860 rzg2l_mipi_dsi_link_write(dsi, VICH1PPSETR, vich1ppsetr);
861
862 /* Configuration for Video Parameters */
863 vich1vssetr = VICH1VSSETR_VACTIVE(mode->vdisplay) |
864 VICH1VSSETR_VSA(mode->vsync_end - mode->vsync_start);
865 vich1vssetr |= (mode->flags & DRM_MODE_FLAG_PVSYNC) ?
866 VICH1VSSETR_VSPOL_HIGH : VICH1VSSETR_VSPOL_LOW;
867
868 vich1vpsetr = VICH1VPSETR_VFP(mode->vsync_start - mode->vdisplay) |
869 VICH1VPSETR_VBP(mode->vtotal - mode->vsync_end);
870
871 vich1hssetr = VICH1HSSETR_HACTIVE(mode->hdisplay) |
872 VICH1HSSETR_HSA(mode->hsync_end - mode->hsync_start);
873 vich1hssetr |= (mode->flags & DRM_MODE_FLAG_PHSYNC) ?
874 VICH1HSSETR_HSPOL_HIGH : VICH1HSSETR_HSPOL_LOW;
875
876 vich1hpsetr = VICH1HPSETR_HFP(mode->hsync_start - mode->hdisplay) |
877 VICH1HPSETR_HBP(mode->htotal - mode->hsync_end);
878
879 rzg2l_mipi_dsi_link_write(dsi, VICH1VSSETR, vich1vssetr);
880 rzg2l_mipi_dsi_link_write(dsi, VICH1VPSETR, vich1vpsetr);
881 rzg2l_mipi_dsi_link_write(dsi, VICH1HSSETR, vich1hssetr);
882 rzg2l_mipi_dsi_link_write(dsi, VICH1HPSETR, vich1hpsetr);
883
884 /*
885 * Configuration for Delay Value
886 * Delay value based on 2 ranges of video clock.
887 * 74.25MHz is videoclock of HD@60p or FHD@30p
888 */
889 if (mode->clock > 74250) {
890 delay[0] = 231;
891 delay[1] = 216;
892 } else {
893 delay[0] = 220;
894 delay[1] = 212;
895 }
896
897 if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
898 index = 0;
899 else
900 index = 1;
901
902 rzg2l_mipi_dsi_link_write(dsi, VICH1SET1R,
903 VICH1SET1R_DLY(delay[index]));
904 }
905
rzg2l_mipi_dsi_start_hs_clock(struct rzg2l_mipi_dsi * dsi)906 static int rzg2l_mipi_dsi_start_hs_clock(struct rzg2l_mipi_dsi *dsi)
907 {
908 bool is_clk_cont;
909 u32 hsclksetr;
910 u32 status;
911 int ret;
912
913 is_clk_cont = !(dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS);
914
915 /* Start HS clock */
916 hsclksetr = HSCLKSETR_HSCLKRUN_HS | (is_clk_cont ?
917 HSCLKSETR_HSCLKMODE_CONT :
918 HSCLKSETR_HSCLKMODE_NON_CONT);
919 rzg2l_mipi_dsi_link_write(dsi, HSCLKSETR, hsclksetr);
920
921 if (is_clk_cont) {
922 ret = read_poll_timeout(rzg2l_mipi_dsi_link_read, status,
923 status & PLSR_CLLP2HS,
924 2000, 20000, false, dsi, PLSR);
925 if (ret < 0) {
926 dev_err(dsi->dev, "failed to start HS clock\n");
927 return ret;
928 }
929 }
930
931 dev_dbg(dsi->dev, "Start High Speed Clock with %s clock mode",
932 is_clk_cont ? "continuous" : "non-continuous");
933
934 return 0;
935 }
936
rzg2l_mipi_dsi_stop_hs_clock(struct rzg2l_mipi_dsi * dsi)937 static int rzg2l_mipi_dsi_stop_hs_clock(struct rzg2l_mipi_dsi *dsi)
938 {
939 bool is_clk_cont;
940 u32 status;
941 int ret;
942
943 is_clk_cont = !(dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS);
944
945 /* Stop HS clock */
946 rzg2l_mipi_dsi_link_write(dsi, HSCLKSETR,
947 is_clk_cont ? HSCLKSETR_HSCLKMODE_CONT :
948 HSCLKSETR_HSCLKMODE_NON_CONT);
949
950 if (is_clk_cont) {
951 ret = read_poll_timeout(rzg2l_mipi_dsi_link_read, status,
952 status & PLSR_CLHS2LP,
953 2000, 20000, false, dsi, PLSR);
954 if (ret < 0) {
955 dev_err(dsi->dev, "failed to stop HS clock\n");
956 return ret;
957 }
958 }
959
960 return 0;
961 }
962
rzg2l_mipi_dsi_start_video(struct rzg2l_mipi_dsi * dsi)963 static int rzg2l_mipi_dsi_start_video(struct rzg2l_mipi_dsi *dsi)
964 {
965 u32 vich1set0r;
966 u32 status;
967 int ret;
968
969 /* Configuration for Blanking sequence and start video input */
970 vich1set0r = VICH1SET0R_HFPNOLP | VICH1SET0R_HBPNOLP |
971 VICH1SET0R_HSANOLP | VICH1SET0R_VSTART;
972 rzg2l_mipi_dsi_link_write(dsi, VICH1SET0R, vich1set0r);
973
974 ret = read_poll_timeout(rzg2l_mipi_dsi_link_read, status,
975 status & VICH1SR_VIRDY,
976 2000, 20000, false, dsi, VICH1SR);
977 if (ret < 0)
978 dev_err(dsi->dev, "Failed to start video signal input\n");
979
980 return ret;
981 }
982
rzg2l_mipi_dsi_stop_video(struct rzg2l_mipi_dsi * dsi)983 static int rzg2l_mipi_dsi_stop_video(struct rzg2l_mipi_dsi *dsi)
984 {
985 u32 status;
986 int ret;
987
988 rzg2l_mipi_dsi_link_write(dsi, VICH1SET0R, VICH1SET0R_VSTPAFT);
989 ret = read_poll_timeout(rzg2l_mipi_dsi_link_read, status,
990 (status & VICH1SR_STOP) && (!(status & VICH1SR_RUNNING)),
991 2000, 20000, false, dsi, VICH1SR);
992 if (ret < 0)
993 goto err;
994
995 ret = read_poll_timeout(rzg2l_mipi_dsi_link_read, status,
996 !(status & LINKSR_HSBUSY),
997 2000, 20000, false, dsi, LINKSR);
998 if (ret < 0)
999 goto err;
1000
1001 return 0;
1002
1003 err:
1004 dev_err(dsi->dev, "Failed to stop video signal input\n");
1005 return ret;
1006 }
1007
1008 /* -----------------------------------------------------------------------------
1009 * Bridge
1010 */
1011
rzg2l_mipi_dsi_attach(struct drm_bridge * bridge,struct drm_encoder * encoder,enum drm_bridge_attach_flags flags)1012 static int rzg2l_mipi_dsi_attach(struct drm_bridge *bridge,
1013 struct drm_encoder *encoder,
1014 enum drm_bridge_attach_flags flags)
1015 {
1016 struct rzg2l_mipi_dsi *dsi = bridge_to_rzg2l_mipi_dsi(bridge);
1017
1018 return drm_bridge_attach(encoder, dsi->next_bridge, bridge,
1019 flags);
1020 }
1021
rzg2l_mipi_dsi_atomic_pre_enable(struct drm_bridge * bridge,struct drm_atomic_state * state)1022 static void rzg2l_mipi_dsi_atomic_pre_enable(struct drm_bridge *bridge,
1023 struct drm_atomic_state *state)
1024 {
1025 struct rzg2l_mipi_dsi *dsi = bridge_to_rzg2l_mipi_dsi(bridge);
1026 const struct drm_display_mode *mode;
1027 struct drm_connector *connector;
1028 struct drm_crtc *crtc;
1029 int ret;
1030
1031 connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
1032 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
1033 mode = &drm_atomic_get_new_crtc_state(state, crtc)->adjusted_mode;
1034
1035 ret = rzg2l_mipi_dsi_startup(dsi, mode);
1036 if (ret < 0)
1037 return;
1038
1039 rzg2l_mipi_dsi_set_display_timing(dsi, mode);
1040 }
1041
rzg2l_mipi_dsi_atomic_enable(struct drm_bridge * bridge,struct drm_atomic_state * state)1042 static void rzg2l_mipi_dsi_atomic_enable(struct drm_bridge *bridge,
1043 struct drm_atomic_state *state)
1044 {
1045 struct rzg2l_mipi_dsi *dsi = bridge_to_rzg2l_mipi_dsi(bridge);
1046 int ret;
1047
1048 ret = rzg2l_mipi_dsi_start_hs_clock(dsi);
1049 if (ret < 0)
1050 goto err_stop;
1051
1052 ret = rzg2l_mipi_dsi_start_video(dsi);
1053 if (ret < 0)
1054 goto err_stop_clock;
1055
1056 return;
1057
1058 err_stop_clock:
1059 rzg2l_mipi_dsi_stop_hs_clock(dsi);
1060 err_stop:
1061 rzg2l_mipi_dsi_stop(dsi);
1062 }
1063
rzg2l_mipi_dsi_atomic_disable(struct drm_bridge * bridge,struct drm_atomic_state * state)1064 static void rzg2l_mipi_dsi_atomic_disable(struct drm_bridge *bridge,
1065 struct drm_atomic_state *state)
1066 {
1067 struct rzg2l_mipi_dsi *dsi = bridge_to_rzg2l_mipi_dsi(bridge);
1068
1069 rzg2l_mipi_dsi_stop_video(dsi);
1070 rzg2l_mipi_dsi_stop_hs_clock(dsi);
1071 }
1072
rzg2l_mipi_dsi_atomic_post_disable(struct drm_bridge * bridge,struct drm_atomic_state * state)1073 static void rzg2l_mipi_dsi_atomic_post_disable(struct drm_bridge *bridge,
1074 struct drm_atomic_state *state)
1075 {
1076 struct rzg2l_mipi_dsi *dsi = bridge_to_rzg2l_mipi_dsi(bridge);
1077
1078 rzg2l_mipi_dsi_stop(dsi);
1079 }
1080
1081 static enum drm_mode_status
rzg2l_mipi_dsi_bridge_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)1082 rzg2l_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge,
1083 const struct drm_display_info *info,
1084 const struct drm_display_mode *mode)
1085 {
1086 struct rzg2l_mipi_dsi *dsi = bridge_to_rzg2l_mipi_dsi(bridge);
1087
1088 if (mode->clock > dsi->info->max_dclk)
1089 return MODE_CLOCK_HIGH;
1090
1091 if (mode->clock < dsi->info->min_dclk)
1092 return MODE_CLOCK_LOW;
1093
1094 if (dsi->info->dphy_mode_clk_check) {
1095 enum drm_mode_status status;
1096
1097 status = dsi->info->dphy_mode_clk_check(dsi, mode->clock);
1098 if (status != MODE_OK)
1099 return status;
1100 }
1101
1102 return MODE_OK;
1103 }
1104
1105 static const struct drm_bridge_funcs rzg2l_mipi_dsi_bridge_ops = {
1106 .attach = rzg2l_mipi_dsi_attach,
1107 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1108 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1109 .atomic_reset = drm_atomic_helper_bridge_reset,
1110 .atomic_pre_enable = rzg2l_mipi_dsi_atomic_pre_enable,
1111 .atomic_enable = rzg2l_mipi_dsi_atomic_enable,
1112 .atomic_disable = rzg2l_mipi_dsi_atomic_disable,
1113 .atomic_post_disable = rzg2l_mipi_dsi_atomic_post_disable,
1114 .mode_valid = rzg2l_mipi_dsi_bridge_mode_valid,
1115 };
1116
1117 /* -----------------------------------------------------------------------------
1118 * Host setting
1119 */
1120
rzg2l_mipi_dsi_host_attach(struct mipi_dsi_host * host,struct mipi_dsi_device * device)1121 static int rzg2l_mipi_dsi_host_attach(struct mipi_dsi_host *host,
1122 struct mipi_dsi_device *device)
1123 {
1124 struct rzg2l_mipi_dsi *dsi = host_to_rzg2l_mipi_dsi(host);
1125 int bpp;
1126 int ret;
1127
1128 if (device->lanes > dsi->num_data_lanes) {
1129 dev_err(dsi->dev,
1130 "Number of lines of device (%u) exceeds host (%u)\n",
1131 device->lanes, dsi->num_data_lanes);
1132 return -EINVAL;
1133 }
1134
1135 bpp = mipi_dsi_pixel_format_to_bpp(device->format);
1136 switch (bpp) {
1137 case 24:
1138 break;
1139 case 18:
1140 break;
1141 case 16:
1142 if (!(dsi->info->features & RZ_MIPI_DSI_FEATURE_16BPP)) {
1143 dev_err(dsi->dev, "Unsupported format 0x%04x\n",
1144 device->format);
1145 return -EINVAL;
1146 }
1147 break;
1148 default:
1149 dev_err(dsi->dev, "Unsupported format 0x%04x\n", device->format);
1150 return -EINVAL;
1151 }
1152
1153 dsi->lanes = device->lanes;
1154 dsi->format = device->format;
1155 dsi->mode_flags = device->mode_flags;
1156
1157 dsi->next_bridge = devm_drm_of_get_bridge(dsi->dev, dsi->dev->of_node,
1158 1, 0);
1159 if (IS_ERR(dsi->next_bridge)) {
1160 ret = PTR_ERR(dsi->next_bridge);
1161 dev_err(dsi->dev, "failed to get next bridge: %d\n", ret);
1162 return ret;
1163 }
1164
1165 drm_bridge_add(&dsi->bridge);
1166
1167 /*
1168 * Report the required division ratio setting for the MIPI clock dividers.
1169 *
1170 * vclk * bpp = hsclk * 8 * num_lanes
1171 *
1172 * vclk * DSI_AB_divider = hsclk * 16
1173 *
1174 * which simplifies to...
1175 * DSI_AB_divider = bpp * 2 / num_lanes
1176 */
1177 rzg2l_cpg_dsi_div_set_divider(bpp * 2 / dsi->lanes, PLL5_TARGET_DSI);
1178
1179 return 0;
1180 }
1181
rzg2l_mipi_dsi_host_detach(struct mipi_dsi_host * host,struct mipi_dsi_device * device)1182 static int rzg2l_mipi_dsi_host_detach(struct mipi_dsi_host *host,
1183 struct mipi_dsi_device *device)
1184 {
1185 struct rzg2l_mipi_dsi *dsi = host_to_rzg2l_mipi_dsi(host);
1186
1187 drm_bridge_remove(&dsi->bridge);
1188
1189 return 0;
1190 }
1191
rzg2l_mipi_dsi_read_response(struct rzg2l_mipi_dsi * dsi,const struct mipi_dsi_msg * msg)1192 static ssize_t rzg2l_mipi_dsi_read_response(struct rzg2l_mipi_dsi *dsi,
1193 const struct mipi_dsi_msg *msg)
1194 {
1195 u8 *msg_rx = msg->rx_buf;
1196 u8 datatype;
1197 u32 result;
1198 u16 size;
1199
1200 result = rzg2l_mipi_dsi_link_read(dsi, RXRSS0R);
1201 if (result & RXRSS0R_RXPKTDFAIL) {
1202 dev_err(dsi->dev, "packet rx data did not save correctly\n");
1203 return -EPROTO;
1204 }
1205
1206 if (result & RXRSS0R_RXFAIL) {
1207 dev_err(dsi->dev, "packet rx failure\n");
1208 return -EPROTO;
1209 }
1210
1211 if (!(result & RXRSS0R_RXSUC))
1212 return -EPROTO;
1213
1214 datatype = FIELD_GET(RXRSS0R_DT, result);
1215
1216 switch (datatype) {
1217 case 0:
1218 dev_dbg(dsi->dev, "ACK\n");
1219 return 0;
1220 case MIPI_DSI_RX_END_OF_TRANSMISSION:
1221 dev_dbg(dsi->dev, "EoTp\n");
1222 return 0;
1223 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1224 dev_dbg(dsi->dev, "Acknowledge and error report: $%02x%02x\n",
1225 (u8)FIELD_GET(RXRSS0R_DATA1, result),
1226 (u8)FIELD_GET(RXRSS0R_DATA0, result));
1227 return 0;
1228 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1229 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
1230 msg_rx[0] = FIELD_GET(RXRSS0R_DATA0, result);
1231 return 1;
1232 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1233 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
1234 msg_rx[0] = FIELD_GET(RXRSS0R_DATA0, result);
1235 msg_rx[1] = FIELD_GET(RXRSS0R_DATA1, result);
1236 return 2;
1237 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
1238 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
1239 size = FIELD_GET(RXRSS0R_WC, result);
1240
1241 if (size > msg->rx_len) {
1242 dev_err(dsi->dev, "rx buffer too small");
1243 return -ENOSPC;
1244 }
1245
1246 memcpy(msg_rx, dsi->dcs_buf_virt, size);
1247 return size;
1248 default:
1249 dev_err(dsi->dev, "unhandled response type: %02x\n", datatype);
1250 return -EPROTO;
1251 }
1252 }
1253
rzg2l_mipi_dsi_host_transfer(struct mipi_dsi_host * host,const struct mipi_dsi_msg * msg)1254 static ssize_t rzg2l_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
1255 const struct mipi_dsi_msg *msg)
1256 {
1257 struct rzg2l_mipi_dsi *dsi = host_to_rzg2l_mipi_dsi(host);
1258 struct mipi_dsi_packet packet;
1259 bool need_bta;
1260 u32 value;
1261 int ret;
1262
1263 ret = mipi_dsi_create_packet(&packet, msg);
1264 if (ret < 0)
1265 return ret;
1266
1267 /* Terminate operation after this descriptor is finished */
1268 value = SQCH0DSC0AR_NXACT_TERM;
1269
1270 if (msg->flags & MIPI_DSI_MSG_REQ_ACK) {
1271 need_bta = true; /* Message with explicitly requested ACK */
1272 value |= FIELD_PREP(SQCH0DSC0AR_BTA, SQCH0DSC0AR_BTA_NON_READ);
1273 } else if (msg->rx_buf && msg->rx_len > 0) {
1274 need_bta = true; /* Read request */
1275 value |= FIELD_PREP(SQCH0DSC0AR_BTA, SQCH0DSC0AR_BTA_READ);
1276 } else {
1277 need_bta = false;
1278 value |= FIELD_PREP(SQCH0DSC0AR_BTA, SQCH0DSC0AR_BTA_NONE);
1279 }
1280
1281 /* Set transmission speed */
1282 if (msg->flags & MIPI_DSI_MSG_USE_LPM)
1283 value |= SQCH0DSC0AR_SPD_LOW;
1284 else
1285 value |= SQCH0DSC0AR_SPD_HIGH;
1286
1287 /* Write TX packet header */
1288 value |= FIELD_PREP(SQCH0DSC0AR_DT, packet.header[0]) |
1289 FIELD_PREP(SQCH0DSC0AR_DATA0, packet.header[1]) |
1290 FIELD_PREP(SQCH0DSC0AR_DATA1, packet.header[2]);
1291
1292 if (mipi_dsi_packet_format_is_long(msg->type)) {
1293 value |= SQCH0DSC0AR_FMT_LONG;
1294
1295 if (packet.payload_length > RZG2L_DCS_BUF_SIZE) {
1296 dev_err(dsi->dev, "Packet Tx payload size (%d) too large",
1297 (unsigned int)packet.payload_length);
1298 return -ENOSPC;
1299 }
1300
1301 /* Copy TX packet payload data to memory space */
1302 memcpy(dsi->dcs_buf_virt, packet.payload, packet.payload_length);
1303 } else {
1304 value |= SQCH0DSC0AR_FMT_SHORT;
1305 }
1306
1307 rzg2l_mipi_dsi_link_write(dsi, SQCH0DSC0AR, value);
1308
1309 /*
1310 * Write: specify payload data source location, only used for
1311 * long packet.
1312 * Read: specify payload data storage location of response
1313 * packet. Note: a read packet is always a short packet.
1314 * If the response packet is a short packet or a long packet
1315 * with WC = 0 (no payload), DTSEL is meaningless.
1316 */
1317 rzg2l_mipi_dsi_link_write(dsi, SQCH0DSC0BR, SQCH0DSC0BR_DTSEL_MEM_SPACE);
1318
1319 /*
1320 * Set SQCHxSR.AACTFIN bit when descriptor actions are finished.
1321 * Read: set Rx result save slot number to 0 (ACTCODE).
1322 */
1323 rzg2l_mipi_dsi_link_write(dsi, SQCH0DSC0CR, SQCH0DSC0CR_FINACT);
1324
1325 /* Set rx/tx payload data address, only relevant for long packet. */
1326 rzg2l_mipi_dsi_link_write(dsi, SQCH0DSC0DR, (u32)dsi->dcs_buf_phys);
1327
1328 /* Start sequence 0 operation */
1329 value = rzg2l_mipi_dsi_link_read(dsi, SQCH0SET0R);
1330 value |= SQCH0SET0R_START;
1331 rzg2l_mipi_dsi_link_write(dsi, SQCH0SET0R, value);
1332
1333 /* Wait for operation to finish */
1334 ret = read_poll_timeout(rzg2l_mipi_dsi_link_read,
1335 value, value & SQCH0SR_ADESFIN,
1336 2000, 20000, false, dsi, SQCH0SR);
1337 if (ret == 0) {
1338 /* Success: clear status bit */
1339 rzg2l_mipi_dsi_link_write(dsi, SQCH0SCR, SQCH0SCR_ADESFIN);
1340
1341 if (need_bta)
1342 ret = rzg2l_mipi_dsi_read_response(dsi, msg);
1343 else
1344 ret = packet.payload_length;
1345 }
1346
1347 return ret;
1348 }
1349
1350 static const struct mipi_dsi_host_ops rzg2l_mipi_dsi_host_ops = {
1351 .attach = rzg2l_mipi_dsi_host_attach,
1352 .detach = rzg2l_mipi_dsi_host_detach,
1353 .transfer = rzg2l_mipi_dsi_host_transfer,
1354 };
1355
1356 /* -----------------------------------------------------------------------------
1357 * Power Management
1358 */
1359
rzg2l_mipi_pm_runtime_suspend(struct device * dev)1360 static int rzg2l_mipi_pm_runtime_suspend(struct device *dev)
1361 {
1362 struct rzg2l_mipi_dsi *dsi = dev_get_drvdata(dev);
1363
1364 reset_control_assert(dsi->prstc);
1365 reset_control_assert(dsi->arstc);
1366
1367 return 0;
1368 }
1369
rzg2l_mipi_pm_runtime_resume(struct device * dev)1370 static int rzg2l_mipi_pm_runtime_resume(struct device *dev)
1371 {
1372 struct rzg2l_mipi_dsi *dsi = dev_get_drvdata(dev);
1373 int ret;
1374
1375 ret = reset_control_deassert(dsi->arstc);
1376 if (ret < 0)
1377 return ret;
1378
1379 ret = reset_control_deassert(dsi->prstc);
1380 if (ret < 0)
1381 reset_control_assert(dsi->arstc);
1382
1383 return ret;
1384 }
1385
1386 static const struct dev_pm_ops rzg2l_mipi_pm_ops = {
1387 RUNTIME_PM_OPS(rzg2l_mipi_pm_runtime_suspend, rzg2l_mipi_pm_runtime_resume, NULL)
1388 };
1389
1390 /* -----------------------------------------------------------------------------
1391 * Probe & Remove
1392 */
1393
rzg2l_mipi_dsi_probe(struct platform_device * pdev)1394 static int rzg2l_mipi_dsi_probe(struct platform_device *pdev)
1395 {
1396 unsigned int num_data_lanes;
1397 struct rzg2l_mipi_dsi *dsi;
1398 u32 txsetr;
1399 int ret;
1400
1401 dsi = devm_drm_bridge_alloc(&pdev->dev, struct rzg2l_mipi_dsi, bridge,
1402 &rzg2l_mipi_dsi_bridge_ops);
1403 if (IS_ERR(dsi))
1404 return PTR_ERR(dsi);
1405
1406 platform_set_drvdata(pdev, dsi);
1407 dsi->dev = &pdev->dev;
1408
1409 dsi->info = of_device_get_match_data(&pdev->dev);
1410
1411 ret = drm_of_get_data_lanes_count_ep(dsi->dev->of_node, 1, 0, 1, 4);
1412 if (ret < 0)
1413 return dev_err_probe(dsi->dev, ret,
1414 "missing or invalid data-lanes property\n");
1415
1416 num_data_lanes = ret;
1417
1418 dsi->mmio = devm_platform_ioremap_resource(pdev, 0);
1419 if (IS_ERR(dsi->mmio))
1420 return PTR_ERR(dsi->mmio);
1421
1422 dsi->vclk = devm_clk_get(dsi->dev, "vclk");
1423 if (IS_ERR(dsi->vclk))
1424 return PTR_ERR(dsi->vclk);
1425
1426 dsi->lpclk = devm_clk_get(dsi->dev, "lpclk");
1427 if (IS_ERR(dsi->lpclk))
1428 return PTR_ERR(dsi->lpclk);
1429
1430 dsi->rstc = devm_reset_control_get_optional_exclusive(dsi->dev, "rst");
1431 if (IS_ERR(dsi->rstc))
1432 return dev_err_probe(dsi->dev, PTR_ERR(dsi->rstc),
1433 "failed to get rst\n");
1434
1435 dsi->arstc = devm_reset_control_get_exclusive(dsi->dev, "arst");
1436 if (IS_ERR(dsi->arstc))
1437 return dev_err_probe(&pdev->dev, PTR_ERR(dsi->arstc),
1438 "failed to get arst\n");
1439
1440 dsi->prstc = devm_reset_control_get_exclusive(dsi->dev, "prst");
1441 if (IS_ERR(dsi->prstc))
1442 return dev_err_probe(dsi->dev, PTR_ERR(dsi->prstc),
1443 "failed to get prst\n");
1444
1445 platform_set_drvdata(pdev, dsi);
1446
1447 pm_runtime_enable(dsi->dev);
1448
1449 ret = pm_runtime_resume_and_get(dsi->dev);
1450 if (ret < 0)
1451 goto err_pm_disable;
1452
1453 /*
1454 * TXSETR register can be read only after DPHY init. But during probe
1455 * mode->clock and format are not available. So initialize DPHY with
1456 * timing parameters for 80Mbps.
1457 */
1458 ret = dsi->info->dphy_init(dsi, 80000000ULL * MILLI);
1459 if (ret < 0)
1460 goto err_phy;
1461
1462 txsetr = rzg2l_mipi_dsi_link_read(dsi, TXSETR);
1463 dsi->num_data_lanes = min(((txsetr >> 16) & 3) + 1, num_data_lanes);
1464 dsi->info->dphy_exit(dsi);
1465 pm_runtime_put(dsi->dev);
1466
1467 /* Initialize the DRM bridge. */
1468 dsi->bridge.of_node = dsi->dev->of_node;
1469
1470 /* Init host device */
1471 dsi->host.dev = dsi->dev;
1472 dsi->host.ops = &rzg2l_mipi_dsi_host_ops;
1473 ret = mipi_dsi_host_register(&dsi->host);
1474 if (ret < 0)
1475 goto err_pm_disable;
1476
1477 dsi->dcs_buf_virt = dma_alloc_coherent(dsi->host.dev, RZG2L_DCS_BUF_SIZE,
1478 &dsi->dcs_buf_phys, GFP_KERNEL);
1479 if (!dsi->dcs_buf_virt)
1480 return -ENOMEM;
1481
1482 return 0;
1483
1484 err_phy:
1485 dsi->info->dphy_exit(dsi);
1486 pm_runtime_put(dsi->dev);
1487 err_pm_disable:
1488 pm_runtime_disable(dsi->dev);
1489 return ret;
1490 }
1491
rzg2l_mipi_dsi_remove(struct platform_device * pdev)1492 static void rzg2l_mipi_dsi_remove(struct platform_device *pdev)
1493 {
1494 struct rzg2l_mipi_dsi *dsi = platform_get_drvdata(pdev);
1495
1496 dma_free_coherent(dsi->host.dev, RZG2L_DCS_BUF_SIZE, dsi->dcs_buf_virt,
1497 dsi->dcs_buf_phys);
1498 mipi_dsi_host_unregister(&dsi->host);
1499 pm_runtime_disable(&pdev->dev);
1500 }
1501
1502 RZV2H_CPG_PLL_DSI_LIMITS(rzv2h_cpg_pll_dsi_limits);
1503
1504 static const struct rzv2h_pll_limits *rzv2h_plldsi_limits[] = {
1505 &rzv2h_cpg_pll_dsi_limits,
1506 };
1507
1508 static const u8 rzv2h_cpg_div_table[] = {
1509 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32,
1510 };
1511
1512 static const struct rzg2l_mipi_dsi_hw_info rzv2h_mipi_dsi_info = {
1513 .dphy_init = rzv2h_mipi_dsi_dphy_init,
1514 .dphy_startup_late_init = rzv2h_mipi_dsi_dphy_startup_late_init,
1515 .dphy_exit = rzv2h_mipi_dsi_dphy_exit,
1516 .dphy_mode_clk_check = rzv2h_dphy_mode_clk_check,
1517 .dphy_conf_clks = rzv2h_dphy_conf_clks,
1518 .cpg_plldsi.limits = rzv2h_plldsi_limits,
1519 .cpg_plldsi.table = rzv2h_cpg_div_table,
1520 .cpg_plldsi.table_size = ARRAY_SIZE(rzv2h_cpg_div_table),
1521 .phy_reg_offset = 0x10000,
1522 .link_reg_offset = 0,
1523 .min_dclk = 5440,
1524 .max_dclk = 187500,
1525 .features = RZ_MIPI_DSI_FEATURE_16BPP,
1526 };
1527
1528 static const struct rzg2l_mipi_dsi_hw_info rzg2l_mipi_dsi_info = {
1529 .dphy_init = rzg2l_mipi_dsi_dphy_init,
1530 .dphy_exit = rzg2l_mipi_dsi_dphy_exit,
1531 .dphy_conf_clks = rzg2l_dphy_conf_clks,
1532 .link_reg_offset = 0x10000,
1533 .min_dclk = 5803,
1534 .max_dclk = 148500,
1535 };
1536
1537 static const struct of_device_id rzg2l_mipi_dsi_of_table[] = {
1538 { .compatible = "renesas,r9a09g057-mipi-dsi", .data = &rzv2h_mipi_dsi_info, },
1539 { .compatible = "renesas,rzg2l-mipi-dsi", .data = &rzg2l_mipi_dsi_info, },
1540 { /* sentinel */ }
1541 };
1542
1543 MODULE_DEVICE_TABLE(of, rzg2l_mipi_dsi_of_table);
1544
1545 static struct platform_driver rzg2l_mipi_dsi_platform_driver = {
1546 .probe = rzg2l_mipi_dsi_probe,
1547 .remove = rzg2l_mipi_dsi_remove,
1548 .driver = {
1549 .name = "rzg2l-mipi-dsi",
1550 .pm = pm_ptr(&rzg2l_mipi_pm_ops),
1551 .of_match_table = rzg2l_mipi_dsi_of_table,
1552 },
1553 };
1554
1555 module_platform_driver(rzg2l_mipi_dsi_platform_driver);
1556
1557 MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
1558 MODULE_DESCRIPTION("Renesas RZ/G2L MIPI DSI Encoder Driver");
1559 MODULE_LICENSE("GPL");
1560