1 /* 2 * Copyright © 2008 Keith Packard 3 * 4 * Permission to use, copy, modify, distribute, and sell this software and its 5 * documentation for any purpose is hereby granted without fee, provided that 6 * the above copyright notice appear in all copies and that both that copyright 7 * notice and this permission notice appear in supporting documentation, and 8 * that the name of the copyright holders not be used in advertising or 9 * publicity pertaining to distribution of the software without specific, 10 * written prior permission. The copyright holders make no representations 11 * about the suitability of this software for any purpose. It is provided "as 12 * is" without express or implied warranty. 13 * 14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE 20 * OF THIS SOFTWARE. 21 */ 22 23 #ifndef _DRM_DP_HELPER_H_ 24 #define _DRM_DP_HELPER_H_ 25 26 #include <linux/delay.h> 27 #include <linux/i2c.h> 28 29 #include <drm/display/drm_dp.h> 30 #include <drm/drm_connector.h> 31 32 struct drm_device; 33 struct drm_dp_aux; 34 struct drm_panel; 35 36 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 37 int lane_count); 38 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 39 int lane_count); 40 bool drm_dp_post_lt_adj_req_in_progress(const u8 link_status[DP_LINK_STATUS_SIZE]); 41 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], 42 int lane); 43 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], 44 int lane); 45 u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE], 46 int lane); 47 48 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 49 enum drm_dp_phy dp_phy, bool uhbr); 50 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 51 enum drm_dp_phy dp_phy, bool uhbr); 52 53 void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, 54 const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 55 void drm_dp_lttpr_link_train_clock_recovery_delay(void); 56 void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 57 const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 58 void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 59 const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 60 61 int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux); 62 bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE], 63 int lane_count); 64 bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE], 65 int lane_count); 66 bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]); 67 bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]); 68 bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE]); 69 70 u8 drm_dp_link_rate_to_bw_code(int link_rate); 71 int drm_dp_bw_code_to_link_rate(u8 link_bw); 72 73 const char *drm_dp_phy_name(enum drm_dp_phy dp_phy); 74 75 /** 76 * struct drm_dp_vsc_sdp - drm DP VSC SDP 77 * 78 * This structure represents a DP VSC SDP of drm 79 * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and 80 * [Table 2-117: VSC SDP Payload for DB16 through DB18] 81 * 82 * @sdp_type: secondary-data packet type 83 * @revision: revision number 84 * @length: number of valid data bytes 85 * @pixelformat: pixel encoding format 86 * @colorimetry: colorimetry format 87 * @bpc: bit per color 88 * @dynamic_range: dynamic range information 89 * @content_type: CTA-861-G defines content types and expected processing by a sink device 90 */ 91 struct drm_dp_vsc_sdp { 92 unsigned char sdp_type; 93 unsigned char revision; 94 unsigned char length; 95 enum dp_pixelformat pixelformat; 96 enum dp_colorimetry colorimetry; 97 int bpc; 98 enum dp_dynamic_range dynamic_range; 99 enum dp_content_type content_type; 100 }; 101 102 /** 103 * struct drm_dp_as_sdp - drm DP Adaptive Sync SDP 104 * 105 * This structure represents a DP AS SDP of drm 106 * It is based on DP 2.1 spec [Table 2-126: Adaptive-Sync SDP Header Bytes] and 107 * [Table 2-127: Adaptive-Sync SDP Payload for DB0 through DB8] 108 * 109 * @sdp_type: Secondary-data packet type 110 * @revision: Revision Number 111 * @length: Number of valid data bytes 112 * @vtotal: Minimum Vertical Vtotal 113 * @target_rr: Target Refresh 114 * @duration_incr_ms: Successive frame duration increase 115 * @duration_decr_ms: Successive frame duration decrease 116 * @target_rr_divider: Target refresh rate divider 117 * @mode: Adaptive Sync Operation Mode 118 * @coasting_vtotal: Coasting vtotal 119 */ 120 struct drm_dp_as_sdp { 121 unsigned char sdp_type; 122 unsigned char revision; 123 unsigned char length; 124 int vtotal; 125 int target_rr; 126 int duration_incr_ms; 127 int duration_decr_ms; 128 bool target_rr_divider; 129 enum operation_mode mode; 130 int coasting_vtotal; 131 }; 132 133 void drm_dp_as_sdp_log(struct drm_printer *p, 134 const struct drm_dp_as_sdp *as_sdp); 135 void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp *vsc); 136 137 bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 138 bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 139 140 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]); 141 142 static inline bool 143 drm_dp_lane_count_is_valid(int lane_count) 144 { 145 return lane_count == 1 || lane_count == 2 || lane_count == 4; 146 } 147 148 static inline int 149 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 150 { 151 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); 152 } 153 154 static inline u8 155 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 156 { 157 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; 158 } 159 160 static inline bool 161 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 162 { 163 return dpcd[DP_DPCD_REV] >= 0x11 && 164 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); 165 } 166 167 static inline bool 168 drm_dp_post_lt_adj_req_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 169 { 170 return dpcd[DP_DPCD_REV] >= 0x13 && 171 (dpcd[DP_MAX_LANE_COUNT] & DP_POST_LT_ADJ_REQ_SUPPORTED); 172 } 173 174 static inline bool 175 drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 176 { 177 return dpcd[DP_DPCD_REV] >= 0x11 && 178 (dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING); 179 } 180 181 static inline bool 182 drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 183 { 184 return dpcd[DP_DPCD_REV] >= 0x12 && 185 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED; 186 } 187 188 static inline bool 189 drm_dp_max_downspread(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 190 { 191 return dpcd[DP_DPCD_REV] >= 0x11 || 192 dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5; 193 } 194 195 static inline bool 196 drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 197 { 198 return dpcd[DP_DPCD_REV] >= 0x14 && 199 dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED; 200 } 201 202 static inline u8 203 drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 204 { 205 return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 : 206 DP_TRAINING_PATTERN_MASK; 207 } 208 209 static inline bool 210 drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 211 { 212 return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT; 213 } 214 215 /* DP/eDP DSC support */ 216 u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); 217 u32 drm_dp_dsc_slice_count_to_mask(int slice_count); 218 u32 drm_dp_dsc_sink_slice_count_mask(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], 219 bool is_edp); 220 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], 221 bool is_edp); 222 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); 223 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE], 224 u8 dsc_bpc[3]); 225 int drm_dp_dsc_sink_max_slice_throughput(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], 226 int peak_pixel_rate, bool is_rgb_yuv444); 227 int drm_dp_dsc_branch_max_overall_throughput(const u8 dsc_branch_dpcd[DP_DSC_BRANCH_CAP_SIZE], 228 bool is_rgb_yuv444); 229 int drm_dp_dsc_branch_max_line_width(const u8 dsc_branch_dpcd[DP_DSC_BRANCH_CAP_SIZE]); 230 231 static inline bool 232 drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 233 { 234 return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] & 235 DP_DSC_DECOMPRESSION_IS_SUPPORTED; 236 } 237 238 static inline u16 239 drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 240 { 241 return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] | 242 ((dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] & 243 DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK) << 8); 244 } 245 246 static inline u32 247 drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 248 { 249 /* Max Slicewidth = Number of Pixels * 320 */ 250 return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] * 251 DP_DSC_SLICE_WIDTH_MULTIPLIER; 252 } 253 254 /** 255 * drm_dp_dsc_sink_supports_format() - check if sink supports DSC with given output format 256 * @dsc_dpcd : DSC-capability DPCDs of the sink 257 * @output_format: output_format which is to be checked 258 * 259 * Returns true if the sink supports DSC with the given output_format, false otherwise. 260 */ 261 static inline bool 262 drm_dp_dsc_sink_supports_format(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 output_format) 263 { 264 return dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & output_format; 265 } 266 267 /* Forward Error Correction Support on DP 1.4 */ 268 static inline bool 269 drm_dp_sink_supports_fec(const u8 fec_capable) 270 { 271 return fec_capable & DP_FEC_CAPABLE; 272 } 273 274 static inline bool 275 drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 276 { 277 return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B; 278 } 279 280 static inline bool 281 drm_dp_128b132b_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 282 { 283 return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B; 284 } 285 286 static inline bool 287 drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 288 { 289 return dpcd[DP_EDP_CONFIGURATION_CAP] & 290 DP_ALTERNATE_SCRAMBLER_RESET_CAP; 291 } 292 293 /* Ignore MSA timing for Adaptive Sync support on DP 1.4 */ 294 static inline bool 295 drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 296 { 297 return dpcd[DP_DOWN_STREAM_PORT_COUNT] & 298 DP_MSA_TIMING_PAR_IGNORED; 299 } 300 301 /** 302 * drm_edp_backlight_supported() - Check an eDP DPCD for VESA backlight support 303 * @edp_dpcd: The DPCD to check 304 * 305 * Note that currently this function will return %false for panels which support various DPCD 306 * backlight features but which require the brightness be set through PWM, and don't support setting 307 * the brightness level via the DPCD. 308 * 309 * Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false 310 * otherwise 311 */ 312 static inline bool 313 drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]) 314 { 315 return !!(edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP); 316 } 317 318 /** 319 * drm_dp_is_uhbr_rate - Determine if a link rate is UHBR 320 * @link_rate: link rate in 10kbits/s units 321 * 322 * Determine if the provided link rate is an UHBR rate. 323 * 324 * Returns: %True if @link_rate is an UHBR rate. 325 */ 326 static inline bool drm_dp_is_uhbr_rate(int link_rate) 327 { 328 return link_rate >= 1000000; 329 } 330 331 /* 332 * DisplayPort AUX channel 333 */ 334 335 /** 336 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction 337 * @address: address of the (first) register to access 338 * @request: contains the type of transaction (see DP_AUX_* macros) 339 * @reply: upon completion, contains the reply type of the transaction 340 * @buffer: pointer to a transmission or reception buffer 341 * @size: size of @buffer 342 */ 343 struct drm_dp_aux_msg { 344 unsigned int address; 345 u8 request; 346 u8 reply; 347 void *buffer; 348 size_t size; 349 }; 350 351 struct cec_adapter; 352 struct drm_connector; 353 struct drm_edid; 354 355 /** 356 * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX 357 * @lock: mutex protecting this struct 358 * @adap: the CEC adapter for CEC-Tunneling-over-AUX support. 359 * @connector: the connector this CEC adapter is associated with 360 * @unregister_work: unregister the CEC adapter 361 */ 362 struct drm_dp_aux_cec { 363 struct mutex lock; 364 struct cec_adapter *adap; 365 struct drm_connector *connector; 366 struct delayed_work unregister_work; 367 }; 368 369 /** 370 * struct drm_dp_aux - DisplayPort AUX channel 371 * 372 * An AUX channel can also be used to transport I2C messages to a sink. A 373 * typical application of that is to access an EDID that's present in the sink 374 * device. The @transfer() function can also be used to execute such 375 * transactions. The drm_dp_aux_register() function registers an I2C adapter 376 * that can be passed to drm_probe_ddc(). Upon removal, drivers should call 377 * drm_dp_aux_unregister() to remove the I2C adapter. The I2C adapter uses long 378 * transfers by default; if a partial response is received, the adapter will 379 * drop down to the size given by the partial response for this transaction 380 * only. 381 */ 382 struct drm_dp_aux { 383 /** 384 * @name: user-visible name of this AUX channel and the 385 * I2C-over-AUX adapter. 386 * 387 * It's also used to specify the name of the I2C adapter. If set 388 * to %NULL, dev_name() of @dev will be used. 389 */ 390 const char *name; 391 392 /** 393 * @ddc: I2C adapter that can be used for I2C-over-AUX 394 * communication 395 */ 396 struct i2c_adapter ddc; 397 398 /** 399 * @dev: pointer to struct device that is the parent for this 400 * AUX channel. 401 */ 402 struct device *dev; 403 404 /** 405 * @drm_dev: pointer to the &drm_device that owns this AUX channel. 406 * Beware, this may be %NULL before drm_dp_aux_register() has been 407 * called. 408 * 409 * It should be set to the &drm_device that will be using this AUX 410 * channel as early as possible. For many graphics drivers this should 411 * happen before drm_dp_aux_init(), however it's perfectly fine to set 412 * this field later so long as it's assigned before calling 413 * drm_dp_aux_register(). 414 */ 415 struct drm_device *drm_dev; 416 417 /** 418 * @crtc: backpointer to the crtc that is currently using this 419 * AUX channel 420 */ 421 struct drm_crtc *crtc; 422 423 /** 424 * @hw_mutex: internal mutex used for locking transfers. 425 * 426 * Note that if the underlying hardware is shared among multiple 427 * channels, the driver needs to do additional locking to 428 * prevent concurrent access. 429 */ 430 struct mutex hw_mutex; 431 432 /** 433 * @crc_work: worker that captures CRCs for each frame 434 */ 435 struct work_struct crc_work; 436 437 /** 438 * @crc_count: counter of captured frame CRCs 439 */ 440 u8 crc_count; 441 442 /** 443 * @transfer: transfers a message representing a single AUX 444 * transaction. 445 * 446 * This is a hardware-specific implementation of how 447 * transactions are executed that the drivers must provide. 448 * 449 * A pointer to a &drm_dp_aux_msg structure describing the 450 * transaction is passed into this function. Upon success, the 451 * implementation should return the number of payload bytes that 452 * were transferred, or a negative error-code on failure. 453 * 454 * Helpers will propagate these errors, with the exception of 455 * the %-EBUSY error, which causes a transaction to be retried. 456 * On a short, helpers will return %-EPROTO to make it simpler 457 * to check for failure. 458 * 459 * The @transfer() function must only modify the reply field of 460 * the &drm_dp_aux_msg structure. The retry logic and i2c 461 * helpers assume this is the case. 462 * 463 * Also note that this callback can be called no matter the 464 * state @dev is in and also no matter what state the panel is 465 * in. It's expected: 466 * 467 * - If the @dev providing the AUX bus is currently unpowered then 468 * it will power itself up for the transfer. 469 * 470 * - If we're on eDP (using a drm_panel) and the panel is not in a 471 * state where it can respond (it's not powered or it's in a 472 * low power state) then this function may return an error, but 473 * not crash. It's up to the caller of this code to make sure that 474 * the panel is powered on if getting an error back is not OK. If a 475 * drm_panel driver is initiating a DP AUX transfer it may power 476 * itself up however it wants. All other code should ensure that 477 * the pre_enable() bridge chain (which eventually calls the 478 * drm_panel prepare function) has powered the panel. 479 */ 480 ssize_t (*transfer)(struct drm_dp_aux *aux, 481 struct drm_dp_aux_msg *msg); 482 483 /** 484 * @wait_hpd_asserted: wait for HPD to be asserted 485 * 486 * This is mainly useful for eDP panels drivers to wait for an eDP 487 * panel to finish powering on. It is optional for DP AUX controllers 488 * to implement this function. It is required for DP AUX endpoints 489 * (panel drivers) to call this function after powering up but before 490 * doing AUX transfers unless the DP AUX endpoint driver knows that 491 * we're not using the AUX controller's HPD. One example of the panel 492 * driver not needing to call this is if HPD is hooked up to a GPIO 493 * that the panel driver can read directly. 494 * 495 * If a DP AUX controller does not implement this function then it 496 * may still support eDP panels that use the AUX controller's built-in 497 * HPD signal by implementing a long wait for HPD in the transfer() 498 * callback, though this is deprecated. 499 * 500 * This function will efficiently wait for the HPD signal to be 501 * asserted. The `wait_us` parameter that is passed in says that we 502 * know that the HPD signal is expected to be asserted within `wait_us` 503 * microseconds. This function could wait for longer than `wait_us` if 504 * the logic in the DP controller has a long debouncing time. The 505 * important thing is that if this function returns success that the 506 * DP controller is ready to send AUX transactions. 507 * 508 * This function returns 0 if HPD was asserted or -ETIMEDOUT if time 509 * expired and HPD wasn't asserted. This function should not print 510 * timeout errors to the log. 511 * 512 * The semantics of this function are designed to match the 513 * readx_poll_timeout() function. That means a `wait_us` of 0 means 514 * to wait forever. Like readx_poll_timeout(), this function may sleep. 515 * 516 * NOTE: this function specifically reports the state of the HPD pin 517 * that's associated with the DP AUX channel. This is different from 518 * the HPD concept in much of the rest of DRM which is more about 519 * physical presence of a display. For eDP, for instance, a display is 520 * assumed always present even if the HPD pin is deasserted. 521 */ 522 int (*wait_hpd_asserted)(struct drm_dp_aux *aux, unsigned long wait_us); 523 524 /** 525 * @i2c_nack_count: Counts I2C NACKs, used for DP validation. 526 */ 527 unsigned i2c_nack_count; 528 /** 529 * @i2c_defer_count: Counts I2C DEFERs, used for DP validation. 530 */ 531 unsigned i2c_defer_count; 532 /** 533 * @cec: struct containing fields used for CEC-Tunneling-over-AUX. 534 */ 535 struct drm_dp_aux_cec cec; 536 /** 537 * @is_remote: Is this AUX CH actually using sideband messaging. 538 */ 539 bool is_remote; 540 541 /** 542 * @powered_down: If true then the remote endpoint is powered down. 543 */ 544 bool powered_down; 545 546 /** 547 * @no_zero_sized: If the hw can't use zero sized transfers (NVIDIA) 548 */ 549 bool no_zero_sized; 550 551 /** 552 * @dpcd_probe_disabled: If probing before a DPCD access is disabled. 553 */ 554 bool dpcd_probe_disabled; 555 }; 556 557 int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset); 558 void drm_dp_dpcd_set_powered(struct drm_dp_aux *aux, bool powered); 559 void drm_dp_dpcd_set_probe(struct drm_dp_aux *aux, bool enable); 560 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, 561 void *buffer, size_t size); 562 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, 563 void *buffer, size_t size); 564 565 /** 566 * drm_dp_dpcd_readb() - read a single byte from the DPCD 567 * @aux: DisplayPort AUX channel 568 * @offset: address of the register to read 569 * @valuep: location where the value of the register will be stored 570 * 571 * Returns the number of bytes transferred (1) on success, or a negative 572 * error code on failure. In most of the cases you should be using 573 * drm_dp_dpcd_read_byte() instead. 574 */ 575 static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux, 576 unsigned int offset, u8 *valuep) 577 { 578 return drm_dp_dpcd_read(aux, offset, valuep, 1); 579 } 580 581 /** 582 * drm_dp_dpcd_read_data() - read a series of bytes from the DPCD 583 * @aux: DisplayPort AUX channel (SST or MST) 584 * @offset: address of the (first) register to read 585 * @buffer: buffer to store the register values 586 * @size: number of bytes in @buffer 587 * 588 * Returns zero (0) on success, or a negative error 589 * code on failure. -EIO is returned if the request was NAKed by the sink or 590 * if the retry count was exceeded. If not all bytes were transferred, this 591 * function returns -EPROTO. Errors from the underlying AUX channel transfer 592 * function, with the exception of -EBUSY (which causes the transaction to 593 * be retried), are propagated to the caller. 594 */ 595 static inline int drm_dp_dpcd_read_data(struct drm_dp_aux *aux, 596 unsigned int offset, 597 void *buffer, size_t size) 598 { 599 int ret; 600 size_t i; 601 u8 *buf = buffer; 602 603 ret = drm_dp_dpcd_read(aux, offset, buffer, size); 604 if (ret >= 0) { 605 if (ret < size) 606 return -EPROTO; 607 return 0; 608 } 609 610 /* 611 * Workaround for USB-C hubs/adapters with buggy firmware that fail 612 * multi-byte AUX reads but work with single-byte reads. 613 * Known affected devices: 614 * - Lenovo USB-C to VGA adapter (VIA VL817, idVendor=17ef, idProduct=7217) 615 * - Dell DA310 USB-C hub (idVendor=413c, idProduct=c010) 616 * Attempt byte-by-byte reading as a fallback. 617 */ 618 for (i = 0; i < size; i++) { 619 ret = drm_dp_dpcd_readb(aux, offset + i, &buf[i]); 620 if (ret < 0) 621 return ret; 622 } 623 624 return 0; 625 } 626 627 /** 628 * drm_dp_dpcd_write_data() - write a series of bytes to the DPCD 629 * @aux: DisplayPort AUX channel (SST or MST) 630 * @offset: address of the (first) register to write 631 * @buffer: buffer containing the values to write 632 * @size: number of bytes in @buffer 633 * 634 * Returns zero (0) on success, or a negative error 635 * code on failure. -EIO is returned if the request was NAKed by the sink or 636 * if the retry count was exceeded. If not all bytes were transferred, this 637 * function returns -EPROTO. Errors from the underlying AUX channel transfer 638 * function, with the exception of -EBUSY (which causes the transaction to 639 * be retried), are propagated to the caller. 640 */ 641 static inline int drm_dp_dpcd_write_data(struct drm_dp_aux *aux, 642 unsigned int offset, 643 void *buffer, size_t size) 644 { 645 int ret; 646 647 ret = drm_dp_dpcd_write(aux, offset, buffer, size); 648 if (ret < 0) 649 return ret; 650 if (ret < size) 651 return -EPROTO; 652 653 return 0; 654 } 655 656 /** 657 * drm_dp_dpcd_writeb() - write a single byte to the DPCD 658 * @aux: DisplayPort AUX channel 659 * @offset: address of the register to write 660 * @value: value to write to the register 661 * 662 * Returns the number of bytes transferred (1) on success, or a negative 663 * error code on failure. In most of the cases you should be using 664 * drm_dp_dpcd_write_byte() instead. 665 */ 666 static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux, 667 unsigned int offset, u8 value) 668 { 669 return drm_dp_dpcd_write(aux, offset, &value, 1); 670 } 671 672 /** 673 * drm_dp_dpcd_read_byte() - read a single byte from the DPCD 674 * @aux: DisplayPort AUX channel 675 * @offset: address of the register to read 676 * @valuep: location where the value of the register will be stored 677 * 678 * Returns zero (0) on success, or a negative error code on failure. 679 */ 680 static inline int drm_dp_dpcd_read_byte(struct drm_dp_aux *aux, 681 unsigned int offset, u8 *valuep) 682 { 683 return drm_dp_dpcd_read_data(aux, offset, valuep, 1); 684 } 685 686 /** 687 * drm_dp_dpcd_write_byte() - write a single byte to the DPCD 688 * @aux: DisplayPort AUX channel 689 * @offset: address of the register to write 690 * @value: value to write to the register 691 * 692 * Returns zero (0) on success, or a negative error code on failure. 693 */ 694 static inline int drm_dp_dpcd_write_byte(struct drm_dp_aux *aux, 695 unsigned int offset, u8 value) 696 { 697 return drm_dp_dpcd_write_data(aux, offset, &value, 1); 698 } 699 700 int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, 701 u8 dpcd[DP_RECEIVER_CAP_SIZE]); 702 703 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, 704 u8 status[DP_LINK_STATUS_SIZE]); 705 706 int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux, 707 enum drm_dp_phy dp_phy, 708 u8 link_status[DP_LINK_STATUS_SIZE]); 709 int drm_dp_link_power_up(struct drm_dp_aux *aux, unsigned char revision); 710 int drm_dp_link_power_down(struct drm_dp_aux *aux, unsigned char revision); 711 712 int drm_dp_dpcd_write_payload(struct drm_dp_aux *aux, 713 int vcpid, u8 start_time_slot, u8 time_slot_count); 714 int drm_dp_dpcd_clear_payload(struct drm_dp_aux *aux); 715 int drm_dp_dpcd_poll_act_handled(struct drm_dp_aux *aux, int timeout_ms); 716 717 bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux, 718 u8 real_edid_checksum); 719 720 int drm_dp_read_downstream_info(struct drm_dp_aux *aux, 721 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 722 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]); 723 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 724 const u8 port_cap[4], u8 type); 725 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 726 const u8 port_cap[4], 727 const struct drm_edid *drm_edid); 728 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 729 const u8 port_cap[4]); 730 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 731 const u8 port_cap[4], 732 const struct drm_edid *drm_edid); 733 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 734 const u8 port_cap[4], 735 const struct drm_edid *drm_edid); 736 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 737 const u8 port_cap[4], 738 const struct drm_edid *drm_edid); 739 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 740 const u8 port_cap[4]); 741 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 742 const u8 port_cap[4]); 743 struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev, 744 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 745 const u8 port_cap[4]); 746 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]); 747 void drm_dp_downstream_debug(struct seq_file *m, 748 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 749 const u8 port_cap[4], 750 const struct drm_edid *drm_edid, 751 struct drm_dp_aux *aux); 752 enum drm_mode_subconnector 753 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 754 const u8 port_cap[4]); 755 void drm_dp_set_subconnector_property(struct drm_connector *connector, 756 enum drm_connector_status status, 757 const u8 *dpcd, 758 const u8 port_cap[4]); 759 760 struct drm_dp_desc; 761 bool drm_dp_read_sink_count_cap(struct drm_connector *connector, 762 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 763 const struct drm_dp_desc *desc); 764 int drm_dp_read_sink_count(struct drm_dp_aux *aux); 765 766 int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux, 767 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 768 u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); 769 int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux, 770 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 771 enum drm_dp_phy dp_phy, 772 u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 773 int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]); 774 int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); 775 int drm_dp_lttpr_set_transparent_mode(struct drm_dp_aux *aux, bool enable); 776 int drm_dp_lttpr_init(struct drm_dp_aux *aux, int lttpr_count); 777 int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); 778 bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 779 bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 780 void drm_dp_lttpr_wake_timeout_setup(struct drm_dp_aux *aux, bool transparent_mode); 781 782 void drm_dp_remote_aux_init(struct drm_dp_aux *aux); 783 void drm_dp_aux_init(struct drm_dp_aux *aux); 784 int drm_dp_aux_register(struct drm_dp_aux *aux); 785 void drm_dp_aux_unregister(struct drm_dp_aux *aux); 786 787 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc); 788 int drm_dp_stop_crc(struct drm_dp_aux *aux); 789 790 struct drm_dp_dpcd_ident { 791 u8 oui[3]; 792 u8 device_id[6]; 793 u8 hw_rev; 794 u8 sw_major_rev; 795 u8 sw_minor_rev; 796 } __packed; 797 798 /** 799 * struct drm_dp_desc - DP branch/sink device descriptor 800 * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch). 801 * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks. 802 */ 803 struct drm_dp_desc { 804 struct drm_dp_dpcd_ident ident; 805 u32 quirks; 806 }; 807 808 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc, 809 bool is_branch); 810 811 int drm_dp_dump_lttpr_desc(struct drm_dp_aux *aux, enum drm_dp_phy dp_phy); 812 813 /** 814 * enum drm_dp_quirk - Display Port sink/branch device specific quirks 815 * 816 * Display Port sink and branch devices in the wild have a variety of bugs, try 817 * to collect them here. The quirks are shared, but it's up to the drivers to 818 * implement workarounds for them. 819 */ 820 enum drm_dp_quirk { 821 /** 822 * @DP_DPCD_QUIRK_CONSTANT_N: 823 * 824 * The device requires main link attributes Mvid and Nvid to be limited 825 * to 16 bits. So will give a constant value (0x8000) for compatability. 826 */ 827 DP_DPCD_QUIRK_CONSTANT_N, 828 /** 829 * @DP_DPCD_QUIRK_NO_PSR: 830 * 831 * The device does not support PSR even if reports that it supports or 832 * driver still need to implement proper handling for such device. 833 */ 834 DP_DPCD_QUIRK_NO_PSR, 835 /** 836 * @DP_DPCD_QUIRK_NO_SINK_COUNT: 837 * 838 * The device does not set SINK_COUNT to a non-zero value. 839 * The driver should ignore SINK_COUNT during detection. Note that 840 * drm_dp_read_sink_count_cap() automatically checks for this quirk. 841 */ 842 DP_DPCD_QUIRK_NO_SINK_COUNT, 843 /** 844 * @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD: 845 * 846 * The device supports MST DSC despite not supporting Virtual DPCD. 847 * The DSC caps can be read from the physical aux instead. 848 */ 849 DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD, 850 /** 851 * @DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS: 852 * 853 * The device supports a link rate of 3.24 Gbps (multiplier 0xc) despite 854 * the DP_MAX_LINK_RATE register reporting a lower max multiplier. 855 */ 856 DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS, 857 /** 858 * @DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC: 859 * 860 * The device applies HBLANK expansion for some modes, but this 861 * requires enabling DSC. 862 */ 863 DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC, 864 /** 865 * @DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT: 866 * 867 * The device doesn't support DSC decompression at the maximum DSC 868 * pixel throughput and compressed bpp it indicates via its DPCD DSC 869 * capabilities. The compressed bpp must be limited above a device 870 * specific DSC pixel throughput. 871 */ 872 DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT, 873 }; 874 875 /** 876 * drm_dp_has_quirk() - does the DP device have a specific quirk 877 * @desc: Device descriptor filled by drm_dp_read_desc() 878 * @quirk: Quirk to query for 879 * 880 * Return true if DP device identified by @desc has @quirk. 881 */ 882 static inline bool 883 drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk) 884 { 885 return desc->quirks & BIT(quirk); 886 } 887 888 /** 889 * struct drm_edp_backlight_info - Probed eDP backlight info struct 890 * @pwmgen_bit_count: The pwmgen bit count 891 * @pwm_freq_pre_divider: The PWM frequency pre-divider value being used for this backlight, if any 892 * @max: The maximum backlight level that may be set 893 * @lsb_reg_used: Do we also write values to the DP_EDP_BACKLIGHT_BRIGHTNESS_LSB register? 894 * @aux_enable: Does the panel support the AUX enable cap? 895 * @aux_set: Does the panel support setting the brightness through AUX? 896 * @luminance_set: Does the panel support setting the brightness through AUX using luminance values? 897 * 898 * This structure contains various data about an eDP backlight, which can be populated by using 899 * drm_edp_backlight_init(). 900 */ 901 struct drm_edp_backlight_info { 902 u8 pwmgen_bit_count; 903 u8 pwm_freq_pre_divider; 904 u32 max; 905 906 bool lsb_reg_used : 1; 907 bool aux_enable : 1; 908 bool aux_set : 1; 909 bool luminance_set : 1; 910 }; 911 912 int 913 drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, 914 u32 max_luminance, 915 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE], 916 u32 *current_level, u8 *current_mode, bool need_luminance); 917 int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 918 u32 level); 919 int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 920 u32 level); 921 int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl); 922 923 #if IS_ENABLED(CONFIG_DRM_KMS_HELPER) && (IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \ 924 (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE))) 925 926 int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux); 927 928 #else 929 930 static inline int drm_panel_dp_aux_backlight(struct drm_panel *panel, 931 struct drm_dp_aux *aux) 932 { 933 return 0; 934 } 935 936 #endif 937 938 #ifdef CONFIG_DRM_DISPLAY_DP_AUX_CEC 939 void drm_dp_cec_irq(struct drm_dp_aux *aux); 940 void drm_dp_cec_register_connector(struct drm_dp_aux *aux, 941 struct drm_connector *connector); 942 void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux); 943 void drm_dp_cec_attach(struct drm_dp_aux *aux, u16 source_physical_address); 944 void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid); 945 void drm_dp_cec_unset_edid(struct drm_dp_aux *aux); 946 #else 947 static inline void drm_dp_cec_irq(struct drm_dp_aux *aux) 948 { 949 } 950 951 static inline void 952 drm_dp_cec_register_connector(struct drm_dp_aux *aux, 953 struct drm_connector *connector) 954 { 955 } 956 957 static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux) 958 { 959 } 960 961 static inline void drm_dp_cec_attach(struct drm_dp_aux *aux, 962 u16 source_physical_address) 963 { 964 } 965 966 static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux, 967 const struct edid *edid) 968 { 969 } 970 971 static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux) 972 { 973 } 974 975 #endif 976 977 /** 978 * struct drm_dp_phy_test_params - DP Phy Compliance parameters 979 * @link_rate: Requested Link rate from DPCD 0x219 980 * @num_lanes: Number of lanes requested by sing through DPCD 0x220 981 * @phy_pattern: DP Phy test pattern from DPCD 0x248 982 * @hbr2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B 983 * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259 984 * @enhanced_frame_cap: flag for enhanced frame capability. 985 */ 986 struct drm_dp_phy_test_params { 987 int link_rate; 988 u8 num_lanes; 989 u8 phy_pattern; 990 u8 hbr2_reset[2]; 991 u8 custom80[10]; 992 bool enhanced_frame_cap; 993 }; 994 995 int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, 996 struct drm_dp_phy_test_params *data); 997 int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux, 998 struct drm_dp_phy_test_params *data, u8 dp_rev); 999 int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1000 const u8 port_cap[4]); 1001 int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd); 1002 bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux); 1003 int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, 1004 u8 frl_mode); 1005 int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, 1006 u8 frl_type); 1007 int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux); 1008 int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux); 1009 1010 bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux); 1011 int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask); 1012 void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux, 1013 struct drm_connector *connector); 1014 bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 1015 int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 1016 int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 1017 int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 1018 int drm_dp_pcon_pps_default(struct drm_dp_aux *aux); 1019 int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]); 1020 int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]); 1021 bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1022 const u8 port_cap[4], u8 color_spc); 1023 int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc); 1024 1025 #define DRM_DP_BW_OVERHEAD_MST BIT(0) 1026 #define DRM_DP_BW_OVERHEAD_UHBR BIT(1) 1027 #define DRM_DP_BW_OVERHEAD_SSC_REF_CLK BIT(2) 1028 #define DRM_DP_BW_OVERHEAD_FEC BIT(3) 1029 #define DRM_DP_BW_OVERHEAD_DSC BIT(4) 1030 1031 int drm_dp_bw_overhead(int lane_count, int hactive, 1032 int dsc_slice_count, 1033 int bpp_x16, unsigned long flags); 1034 int drm_dp_bw_channel_coding_efficiency(bool is_uhbr); 1035 int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes); 1036 1037 ssize_t drm_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, struct dp_sdp *sdp); 1038 int drm_dp_link_symbol_cycles(int lane_count, int pixels, int dsc_slice_count, 1039 int bpp_x16, int symbol_size, bool is_mst); 1040 1041 #endif /* _DRM_DP_HELPER_H_ */ 1042