1 // SPDX-License-Identifier: GPL-2.0 2 /* Driver for the Texas Instruments DP83869 PHY 3 * Copyright (C) 2019 Texas Instruments Inc. 4 */ 5 6 #include <linux/ethtool.h> 7 #include <linux/etherdevice.h> 8 #include <linux/kernel.h> 9 #include <linux/mii.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/phy.h> 13 #include <linux/delay.h> 14 #include <linux/bitfield.h> 15 16 #include <dt-bindings/net/ti-dp83869.h> 17 18 #define DP83869_PHY_ID 0x2000a0f1 19 #define DP83561_PHY_ID 0x2000a1a4 20 #define DP83869_DEVADDR 0x1f 21 22 #define MII_DP83869_PHYCTRL 0x10 23 #define MII_DP83869_MICR 0x12 24 #define MII_DP83869_ISR 0x13 25 #define DP83869_CFG2 0x14 26 #define DP83869_CTRL 0x1f 27 #define DP83869_CFG4 0x1e 28 29 /* Extended Registers */ 30 #define DP83869_GEN_CFG3 0x0031 31 #define DP83869_RGMIICTL 0x0032 32 #define DP83869_STRAP_STS1 0x006e 33 #define DP83869_RGMIIDCTL 0x0086 34 #define DP83869_ANA_PLL_PROG_PI 0x00c6 35 #define DP83869_RXFCFG 0x0134 36 #define DP83869_RXFPMD1 0x0136 37 #define DP83869_RXFPMD2 0x0137 38 #define DP83869_RXFPMD3 0x0138 39 #define DP83869_RXFSOP1 0x0139 40 #define DP83869_RXFSOP2 0x013A 41 #define DP83869_RXFSOP3 0x013B 42 #define DP83869_IO_MUX_CFG 0x0170 43 #define DP83869_OP_MODE 0x01df 44 #define DP83869_FX_CTRL 0x0c00 45 46 #define DP83869_SW_RESET BIT(15) 47 #define DP83869_SW_RESTART BIT(14) 48 49 /* MICR Interrupt bits */ 50 #define MII_DP83869_MICR_AN_ERR_INT_EN BIT(15) 51 #define MII_DP83869_MICR_SPEED_CHNG_INT_EN BIT(14) 52 #define MII_DP83869_MICR_DUP_MODE_CHNG_INT_EN BIT(13) 53 #define MII_DP83869_MICR_PAGE_RXD_INT_EN BIT(12) 54 #define MII_DP83869_MICR_AUTONEG_COMP_INT_EN BIT(11) 55 #define MII_DP83869_MICR_LINK_STS_CHNG_INT_EN BIT(10) 56 #define MII_DP83869_MICR_FALSE_CARRIER_INT_EN BIT(8) 57 #define MII_DP83869_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) 58 #define MII_DP83869_MICR_WOL_INT_EN BIT(3) 59 #define MII_DP83869_MICR_XGMII_ERR_INT_EN BIT(2) 60 #define MII_DP83869_MICR_POL_CHNG_INT_EN BIT(1) 61 #define MII_DP83869_MICR_JABBER_INT_EN BIT(0) 62 63 #define MII_DP83869_BMCR_DEFAULT (BMCR_ANENABLE | \ 64 BMCR_FULLDPLX | \ 65 BMCR_SPEED1000) 66 67 #define MII_DP83869_FIBER_ADVERTISE (ADVERTISED_FIBRE | \ 68 ADVERTISED_Pause | \ 69 ADVERTISED_Asym_Pause) 70 71 /* This is the same bit mask as the BMCR so re-use the BMCR default */ 72 #define DP83869_FX_CTRL_DEFAULT MII_DP83869_BMCR_DEFAULT 73 74 /* CFG1 bits */ 75 #define DP83869_CFG1_DEFAULT (ADVERTISE_1000HALF | \ 76 ADVERTISE_1000FULL | \ 77 CTL1000_AS_MASTER) 78 79 /* RGMIICTL bits */ 80 #define DP83869_RGMII_TX_CLK_DELAY_EN BIT(1) 81 #define DP83869_RGMII_RX_CLK_DELAY_EN BIT(0) 82 83 /* RGMIIDCTL */ 84 #define DP83869_RGMII_CLK_DELAY_SHIFT 4 85 #define DP83869_CLK_DELAY_DEF 7 86 87 /* STRAP_STS1 bits */ 88 #define DP83869_STRAP_OP_MODE_MASK GENMASK(11, 9) 89 #define DP83869_STRAP_STS1_RESERVED BIT(11) 90 #define DP83869_STRAP_MIRROR_ENABLED BIT(12) 91 92 /* PHYCTRL bits */ 93 #define DP83869_RX_FIFO_SHIFT 12 94 #define DP83869_TX_FIFO_SHIFT 14 95 96 /* PHY_CTRL lower bytes 0x48 are declared as reserved */ 97 #define DP83869_PHY_CTRL_DEFAULT 0x48 98 #define DP83869_PHYCR_FIFO_DEPTH_MASK GENMASK(15, 12) 99 #define DP83869_PHYCR_RESERVED_MASK BIT(11) 100 101 /* IO_MUX_CFG bits */ 102 #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f 103 104 #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0 105 #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f 106 #define DP83869_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8) 107 #define DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT 8 108 109 /* CFG3 bits */ 110 #define DP83869_CFG3_PORT_MIRROR_EN BIT(0) 111 112 /* CFG4 bits */ 113 #define DP83869_INT_OE BIT(7) 114 115 /* OP MODE */ 116 #define DP83869_OP_MODE_MII BIT(5) 117 #define DP83869_SGMII_RGMII_BRIDGE BIT(6) 118 119 /* RXFCFG bits*/ 120 #define DP83869_WOL_MAGIC_EN BIT(0) 121 #define DP83869_WOL_PATTERN_EN BIT(1) 122 #define DP83869_WOL_BCAST_EN BIT(2) 123 #define DP83869_WOL_UCAST_EN BIT(4) 124 #define DP83869_WOL_SEC_EN BIT(5) 125 #define DP83869_WOL_ENH_MAC BIT(7) 126 127 /* CFG2 bits */ 128 #define DP83869_DOWNSHIFT_EN (BIT(8) | BIT(9)) 129 #define DP83869_DOWNSHIFT_ATTEMPT_MASK (BIT(10) | BIT(11)) 130 #define DP83869_DOWNSHIFT_1_COUNT_VAL 0 131 #define DP83869_DOWNSHIFT_2_COUNT_VAL 1 132 #define DP83869_DOWNSHIFT_4_COUNT_VAL 2 133 #define DP83869_DOWNSHIFT_8_COUNT_VAL 3 134 #define DP83869_DOWNSHIFT_1_COUNT 1 135 #define DP83869_DOWNSHIFT_2_COUNT 2 136 #define DP83869_DOWNSHIFT_4_COUNT 4 137 #define DP83869_DOWNSHIFT_8_COUNT 8 138 139 enum { 140 DP83869_PORT_MIRRORING_KEEP, 141 DP83869_PORT_MIRRORING_EN, 142 DP83869_PORT_MIRRORING_DIS, 143 }; 144 145 struct dp83869_private { 146 int tx_fifo_depth; 147 int rx_fifo_depth; 148 s32 rx_int_delay; 149 s32 tx_int_delay; 150 int io_impedance; 151 int port_mirroring; 152 bool rxctrl_strap_quirk; 153 int clk_output_sel; 154 int mode; 155 }; 156 157 static int dp83869_config_aneg(struct phy_device *phydev) 158 { 159 struct dp83869_private *dp83869 = phydev->priv; 160 161 if (dp83869->mode != DP83869_RGMII_1000_BASE) 162 return genphy_config_aneg(phydev); 163 164 return genphy_c37_config_aneg(phydev); 165 } 166 167 static int dp83869_read_status(struct phy_device *phydev) 168 { 169 struct dp83869_private *dp83869 = phydev->priv; 170 bool changed; 171 int ret; 172 173 if (dp83869->mode == DP83869_RGMII_1000_BASE) 174 return genphy_c37_read_status(phydev, &changed); 175 176 ret = genphy_read_status(phydev); 177 if (ret) 178 return ret; 179 180 if (dp83869->mode == DP83869_RGMII_100_BASE) { 181 if (phydev->link) { 182 phydev->speed = SPEED_100; 183 } else { 184 phydev->speed = SPEED_UNKNOWN; 185 phydev->duplex = DUPLEX_UNKNOWN; 186 } 187 } 188 189 return 0; 190 } 191 192 static int dp83869_ack_interrupt(struct phy_device *phydev) 193 { 194 int err = phy_read(phydev, MII_DP83869_ISR); 195 196 if (err < 0) 197 return err; 198 199 return 0; 200 } 201 202 static int dp83869_config_intr(struct phy_device *phydev) 203 { 204 int micr_status = 0, err; 205 206 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 207 err = dp83869_ack_interrupt(phydev); 208 if (err) 209 return err; 210 211 micr_status = phy_read(phydev, MII_DP83869_MICR); 212 if (micr_status < 0) 213 return micr_status; 214 215 micr_status |= 216 (MII_DP83869_MICR_AN_ERR_INT_EN | 217 MII_DP83869_MICR_SPEED_CHNG_INT_EN | 218 MII_DP83869_MICR_AUTONEG_COMP_INT_EN | 219 MII_DP83869_MICR_LINK_STS_CHNG_INT_EN | 220 MII_DP83869_MICR_DUP_MODE_CHNG_INT_EN | 221 MII_DP83869_MICR_SLEEP_MODE_CHNG_INT_EN); 222 223 err = phy_write(phydev, MII_DP83869_MICR, micr_status); 224 } else { 225 err = phy_write(phydev, MII_DP83869_MICR, micr_status); 226 if (err) 227 return err; 228 229 err = dp83869_ack_interrupt(phydev); 230 } 231 232 return err; 233 } 234 235 static irqreturn_t dp83869_handle_interrupt(struct phy_device *phydev) 236 { 237 int irq_status, irq_enabled; 238 239 irq_status = phy_read(phydev, MII_DP83869_ISR); 240 if (irq_status < 0) { 241 phy_error(phydev); 242 return IRQ_NONE; 243 } 244 245 irq_enabled = phy_read(phydev, MII_DP83869_MICR); 246 if (irq_enabled < 0) { 247 phy_error(phydev); 248 return IRQ_NONE; 249 } 250 251 if (!(irq_status & irq_enabled)) 252 return IRQ_NONE; 253 254 phy_trigger_machine(phydev); 255 256 return IRQ_HANDLED; 257 } 258 259 static int dp83869_set_wol(struct phy_device *phydev, 260 struct ethtool_wolinfo *wol) 261 { 262 struct net_device *ndev = phydev->attached_dev; 263 int val_rxcfg, val_micr; 264 const u8 *mac; 265 int ret; 266 267 val_rxcfg = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG); 268 if (val_rxcfg < 0) 269 return val_rxcfg; 270 271 val_micr = phy_read(phydev, MII_DP83869_MICR); 272 if (val_micr < 0) 273 return val_micr; 274 275 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | 276 WAKE_BCAST)) { 277 val_rxcfg |= DP83869_WOL_ENH_MAC; 278 val_micr |= MII_DP83869_MICR_WOL_INT_EN; 279 280 if (wol->wolopts & WAKE_MAGIC || 281 wol->wolopts & WAKE_MAGICSECURE) { 282 mac = (const u8 *)ndev->dev_addr; 283 284 if (!is_valid_ether_addr(mac)) 285 return -EINVAL; 286 287 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 288 DP83869_RXFPMD1, 289 mac[1] << 8 | mac[0]); 290 if (ret) 291 return ret; 292 293 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 294 DP83869_RXFPMD2, 295 mac[3] << 8 | mac[2]); 296 if (ret) 297 return ret; 298 299 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 300 DP83869_RXFPMD3, 301 mac[5] << 8 | mac[4]); 302 if (ret) 303 return ret; 304 305 val_rxcfg |= DP83869_WOL_MAGIC_EN; 306 } else { 307 val_rxcfg &= ~DP83869_WOL_MAGIC_EN; 308 } 309 310 if (wol->wolopts & WAKE_MAGICSECURE) { 311 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 312 DP83869_RXFSOP1, 313 (wol->sopass[1] << 8) | wol->sopass[0]); 314 if (ret) 315 return ret; 316 317 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 318 DP83869_RXFSOP2, 319 (wol->sopass[3] << 8) | wol->sopass[2]); 320 if (ret) 321 return ret; 322 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 323 DP83869_RXFSOP3, 324 (wol->sopass[5] << 8) | wol->sopass[4]); 325 if (ret) 326 return ret; 327 328 val_rxcfg |= DP83869_WOL_SEC_EN; 329 } else { 330 val_rxcfg &= ~DP83869_WOL_SEC_EN; 331 } 332 333 if (wol->wolopts & WAKE_UCAST) 334 val_rxcfg |= DP83869_WOL_UCAST_EN; 335 else 336 val_rxcfg &= ~DP83869_WOL_UCAST_EN; 337 338 if (wol->wolopts & WAKE_BCAST) 339 val_rxcfg |= DP83869_WOL_BCAST_EN; 340 else 341 val_rxcfg &= ~DP83869_WOL_BCAST_EN; 342 } else { 343 val_rxcfg &= ~DP83869_WOL_ENH_MAC; 344 val_micr &= ~MII_DP83869_MICR_WOL_INT_EN; 345 } 346 347 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG, val_rxcfg); 348 if (ret) 349 return ret; 350 351 return phy_write(phydev, MII_DP83869_MICR, val_micr); 352 } 353 354 static void dp83869_get_wol(struct phy_device *phydev, 355 struct ethtool_wolinfo *wol) 356 { 357 int value, sopass_val; 358 359 wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC | 360 WAKE_MAGICSECURE); 361 wol->wolopts = 0; 362 363 value = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG); 364 if (value < 0) { 365 phydev_err(phydev, "Failed to read RX CFG\n"); 366 return; 367 } 368 369 if (value & DP83869_WOL_UCAST_EN) 370 wol->wolopts |= WAKE_UCAST; 371 372 if (value & DP83869_WOL_BCAST_EN) 373 wol->wolopts |= WAKE_BCAST; 374 375 if (value & DP83869_WOL_MAGIC_EN) 376 wol->wolopts |= WAKE_MAGIC; 377 378 if (value & DP83869_WOL_SEC_EN) { 379 sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR, 380 DP83869_RXFSOP1); 381 if (sopass_val < 0) { 382 phydev_err(phydev, "Failed to read RX SOP 1\n"); 383 return; 384 } 385 386 wol->sopass[0] = (sopass_val & 0xff); 387 wol->sopass[1] = (sopass_val >> 8); 388 389 sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR, 390 DP83869_RXFSOP2); 391 if (sopass_val < 0) { 392 phydev_err(phydev, "Failed to read RX SOP 2\n"); 393 return; 394 } 395 396 wol->sopass[2] = (sopass_val & 0xff); 397 wol->sopass[3] = (sopass_val >> 8); 398 399 sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR, 400 DP83869_RXFSOP3); 401 if (sopass_val < 0) { 402 phydev_err(phydev, "Failed to read RX SOP 3\n"); 403 return; 404 } 405 406 wol->sopass[4] = (sopass_val & 0xff); 407 wol->sopass[5] = (sopass_val >> 8); 408 409 wol->wolopts |= WAKE_MAGICSECURE; 410 } 411 412 if (!(value & DP83869_WOL_ENH_MAC)) 413 wol->wolopts = 0; 414 } 415 416 static int dp83869_get_downshift(struct phy_device *phydev, u8 *data) 417 { 418 int val, cnt, enable, count; 419 420 val = phy_read(phydev, DP83869_CFG2); 421 if (val < 0) 422 return val; 423 424 enable = FIELD_GET(DP83869_DOWNSHIFT_EN, val); 425 cnt = FIELD_GET(DP83869_DOWNSHIFT_ATTEMPT_MASK, val); 426 427 switch (cnt) { 428 case DP83869_DOWNSHIFT_1_COUNT_VAL: 429 count = DP83869_DOWNSHIFT_1_COUNT; 430 break; 431 case DP83869_DOWNSHIFT_2_COUNT_VAL: 432 count = DP83869_DOWNSHIFT_2_COUNT; 433 break; 434 case DP83869_DOWNSHIFT_4_COUNT_VAL: 435 count = DP83869_DOWNSHIFT_4_COUNT; 436 break; 437 case DP83869_DOWNSHIFT_8_COUNT_VAL: 438 count = DP83869_DOWNSHIFT_8_COUNT; 439 break; 440 default: 441 return -EINVAL; 442 } 443 444 *data = enable ? count : DOWNSHIFT_DEV_DISABLE; 445 446 return 0; 447 } 448 449 static int dp83869_set_downshift(struct phy_device *phydev, u8 cnt) 450 { 451 int val, count; 452 453 if (cnt > DP83869_DOWNSHIFT_8_COUNT) 454 return -EINVAL; 455 456 if (!cnt) 457 return phy_clear_bits(phydev, DP83869_CFG2, 458 DP83869_DOWNSHIFT_EN); 459 460 switch (cnt) { 461 case DP83869_DOWNSHIFT_1_COUNT: 462 count = DP83869_DOWNSHIFT_1_COUNT_VAL; 463 break; 464 case DP83869_DOWNSHIFT_2_COUNT: 465 count = DP83869_DOWNSHIFT_2_COUNT_VAL; 466 break; 467 case DP83869_DOWNSHIFT_4_COUNT: 468 count = DP83869_DOWNSHIFT_4_COUNT_VAL; 469 break; 470 case DP83869_DOWNSHIFT_8_COUNT: 471 count = DP83869_DOWNSHIFT_8_COUNT_VAL; 472 break; 473 default: 474 phydev_err(phydev, 475 "Downshift count must be 1, 2, 4 or 8\n"); 476 return -EINVAL; 477 } 478 479 val = DP83869_DOWNSHIFT_EN; 480 val |= FIELD_PREP(DP83869_DOWNSHIFT_ATTEMPT_MASK, count); 481 482 return phy_modify(phydev, DP83869_CFG2, 483 DP83869_DOWNSHIFT_EN | DP83869_DOWNSHIFT_ATTEMPT_MASK, 484 val); 485 } 486 487 static int dp83869_get_tunable(struct phy_device *phydev, 488 struct ethtool_tunable *tuna, void *data) 489 { 490 switch (tuna->id) { 491 case ETHTOOL_PHY_DOWNSHIFT: 492 return dp83869_get_downshift(phydev, data); 493 default: 494 return -EOPNOTSUPP; 495 } 496 } 497 498 static int dp83869_set_tunable(struct phy_device *phydev, 499 struct ethtool_tunable *tuna, const void *data) 500 { 501 switch (tuna->id) { 502 case ETHTOOL_PHY_DOWNSHIFT: 503 return dp83869_set_downshift(phydev, *(const u8 *)data); 504 default: 505 return -EOPNOTSUPP; 506 } 507 } 508 509 static int dp83869_config_port_mirroring(struct phy_device *phydev) 510 { 511 struct dp83869_private *dp83869 = phydev->priv; 512 513 if (dp83869->port_mirroring == DP83869_PORT_MIRRORING_EN) 514 return phy_set_bits_mmd(phydev, DP83869_DEVADDR, 515 DP83869_GEN_CFG3, 516 DP83869_CFG3_PORT_MIRROR_EN); 517 else 518 return phy_clear_bits_mmd(phydev, DP83869_DEVADDR, 519 DP83869_GEN_CFG3, 520 DP83869_CFG3_PORT_MIRROR_EN); 521 } 522 523 static int dp83869_set_strapped_mode(struct phy_device *phydev) 524 { 525 struct dp83869_private *dp83869 = phydev->priv; 526 int val; 527 528 val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1); 529 if (val < 0) 530 return val; 531 532 dp83869->mode = FIELD_GET(DP83869_STRAP_OP_MODE_MASK, val); 533 534 return 0; 535 } 536 537 #if IS_ENABLED(CONFIG_OF_MDIO) 538 static const int dp83869_internal_delay[] = {250, 500, 750, 1000, 1250, 1500, 539 1750, 2000, 2250, 2500, 2750, 3000, 540 3250, 3500, 3750, 4000}; 541 542 static int dp83869_of_init(struct phy_device *phydev) 543 { 544 struct device_node *of_node = phydev->mdio.dev.of_node; 545 struct dp83869_private *dp83869 = phydev->priv; 546 int delay_size = ARRAY_SIZE(dp83869_internal_delay); 547 int ret; 548 549 if (!of_node) 550 return -ENODEV; 551 552 dp83869->io_impedance = -EINVAL; 553 554 /* Optional configuration */ 555 ret = of_property_read_u32(of_node, "ti,clk-output-sel", 556 &dp83869->clk_output_sel); 557 if (ret || dp83869->clk_output_sel > DP83869_CLK_O_SEL_REF_CLK) 558 dp83869->clk_output_sel = DP83869_CLK_O_SEL_REF_CLK; 559 560 ret = of_property_read_u32(of_node, "ti,op-mode", &dp83869->mode); 561 if (ret == 0) { 562 if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET || 563 dp83869->mode > DP83869_SGMII_COPPER_ETHERNET) 564 return -EINVAL; 565 } else { 566 ret = dp83869_set_strapped_mode(phydev); 567 if (ret) 568 return ret; 569 } 570 571 if (of_property_read_bool(of_node, "ti,max-output-impedance")) 572 dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX; 573 else if (of_property_read_bool(of_node, "ti,min-output-impedance")) 574 dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN; 575 576 if (of_property_read_bool(of_node, "enet-phy-lane-swap")) { 577 dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN; 578 } else { 579 /* If the lane swap is not in the DT then check the straps */ 580 ret = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1); 581 if (ret < 0) 582 return ret; 583 584 if (ret & DP83869_STRAP_MIRROR_ENABLED) 585 dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN; 586 else 587 dp83869->port_mirroring = DP83869_PORT_MIRRORING_DIS; 588 589 ret = 0; 590 } 591 592 if (of_property_read_u32(of_node, "rx-fifo-depth", 593 &dp83869->rx_fifo_depth)) 594 dp83869->rx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB; 595 596 if (of_property_read_u32(of_node, "tx-fifo-depth", 597 &dp83869->tx_fifo_depth)) 598 dp83869->tx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB; 599 600 dp83869->rx_int_delay = phy_get_internal_delay(phydev, 601 &dp83869_internal_delay[0], 602 delay_size, true); 603 if (dp83869->rx_int_delay < 0) 604 dp83869->rx_int_delay = DP83869_CLK_DELAY_DEF; 605 606 dp83869->tx_int_delay = phy_get_internal_delay(phydev, 607 &dp83869_internal_delay[0], 608 delay_size, false); 609 if (dp83869->tx_int_delay < 0) 610 dp83869->tx_int_delay = DP83869_CLK_DELAY_DEF; 611 612 return ret; 613 } 614 #else 615 static int dp83869_of_init(struct phy_device *phydev) 616 { 617 return dp83869_set_strapped_mode(phydev); 618 } 619 #endif /* CONFIG_OF_MDIO */ 620 621 static int dp83869_configure_rgmii(struct phy_device *phydev, 622 struct dp83869_private *dp83869) 623 { 624 int ret = 0, val; 625 626 if (phy_interface_is_rgmii(phydev)) { 627 val = phy_read(phydev, MII_DP83869_PHYCTRL); 628 if (val < 0) 629 return val; 630 631 val &= ~DP83869_PHYCR_FIFO_DEPTH_MASK; 632 val |= (dp83869->tx_fifo_depth << DP83869_TX_FIFO_SHIFT); 633 val |= (dp83869->rx_fifo_depth << DP83869_RX_FIFO_SHIFT); 634 635 ret = phy_write(phydev, MII_DP83869_PHYCTRL, val); 636 if (ret) 637 return ret; 638 } 639 640 if (dp83869->io_impedance >= 0) 641 ret = phy_modify_mmd(phydev, DP83869_DEVADDR, 642 DP83869_IO_MUX_CFG, 643 DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL, 644 dp83869->io_impedance & 645 DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL); 646 647 return ret; 648 } 649 650 static int dp83869_configure_fiber(struct phy_device *phydev, 651 struct dp83869_private *dp83869) 652 { 653 int bmcr; 654 int ret; 655 656 /* Only allow advertising what this PHY supports */ 657 linkmode_and(phydev->advertising, phydev->advertising, 658 phydev->supported); 659 660 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported); 661 662 if (dp83869->mode == DP83869_RGMII_1000_BASE) { 663 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 664 phydev->supported); 665 } else { 666 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, 667 phydev->supported); 668 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT, 669 phydev->supported); 670 671 /* Auto neg is not supported in 100base FX mode */ 672 bmcr = phy_read(phydev, MII_BMCR); 673 if (bmcr < 0) 674 return bmcr; 675 676 phydev->autoneg = AUTONEG_DISABLE; 677 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); 678 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->advertising); 679 680 if (bmcr & BMCR_ANENABLE) { 681 ret = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0); 682 if (ret < 0) 683 return ret; 684 } 685 } 686 687 /* Update advertising from supported */ 688 linkmode_or(phydev->advertising, phydev->advertising, 689 phydev->supported); 690 691 return 0; 692 } 693 694 static int dp83869_configure_mode(struct phy_device *phydev, 695 struct dp83869_private *dp83869) 696 { 697 int phy_ctrl_val; 698 int ret; 699 700 if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET || 701 dp83869->mode > DP83869_SGMII_COPPER_ETHERNET) 702 return -EINVAL; 703 704 /* Below init sequence for each operational mode is defined in 705 * section 9.4.8 of the datasheet. 706 */ 707 phy_ctrl_val = dp83869->mode; 708 if (phydev->interface == PHY_INTERFACE_MODE_MII) { 709 if (dp83869->mode == DP83869_100M_MEDIA_CONVERT || 710 dp83869->mode == DP83869_RGMII_100_BASE || 711 dp83869->mode == DP83869_RGMII_COPPER_ETHERNET) { 712 phy_ctrl_val |= DP83869_OP_MODE_MII; 713 } else { 714 phydev_err(phydev, "selected op-mode is not valid with MII mode\n"); 715 return -EINVAL; 716 } 717 } 718 719 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE, 720 phy_ctrl_val); 721 if (ret) 722 return ret; 723 724 ret = phy_write(phydev, MII_BMCR, MII_DP83869_BMCR_DEFAULT); 725 if (ret) 726 return ret; 727 728 phy_ctrl_val = (dp83869->rx_fifo_depth << DP83869_RX_FIFO_SHIFT | 729 dp83869->tx_fifo_depth << DP83869_TX_FIFO_SHIFT | 730 DP83869_PHY_CTRL_DEFAULT); 731 732 switch (dp83869->mode) { 733 case DP83869_RGMII_COPPER_ETHERNET: 734 ret = phy_write(phydev, MII_DP83869_PHYCTRL, 735 phy_ctrl_val); 736 if (ret) 737 return ret; 738 739 ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT); 740 if (ret) 741 return ret; 742 743 ret = dp83869_configure_rgmii(phydev, dp83869); 744 if (ret) 745 return ret; 746 break; 747 case DP83869_RGMII_SGMII_BRIDGE: 748 ret = phy_modify_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE, 749 DP83869_SGMII_RGMII_BRIDGE, 750 DP83869_SGMII_RGMII_BRIDGE); 751 if (ret) 752 return ret; 753 754 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 755 DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT); 756 if (ret) 757 return ret; 758 759 break; 760 case DP83869_1000M_MEDIA_CONVERT: 761 ret = phy_write(phydev, MII_DP83869_PHYCTRL, 762 phy_ctrl_val); 763 if (ret) 764 return ret; 765 766 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 767 DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT); 768 if (ret) 769 return ret; 770 break; 771 case DP83869_100M_MEDIA_CONVERT: 772 ret = phy_write(phydev, MII_DP83869_PHYCTRL, 773 phy_ctrl_val); 774 if (ret) 775 return ret; 776 break; 777 case DP83869_SGMII_COPPER_ETHERNET: 778 ret = phy_write(phydev, MII_DP83869_PHYCTRL, 779 phy_ctrl_val); 780 if (ret) 781 return ret; 782 783 ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT); 784 if (ret) 785 return ret; 786 787 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 788 DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT); 789 if (ret) 790 return ret; 791 792 break; 793 case DP83869_RGMII_1000_BASE: 794 case DP83869_RGMII_100_BASE: 795 ret = dp83869_configure_fiber(phydev, dp83869); 796 break; 797 default: 798 return -EINVAL; 799 } 800 801 return ret; 802 } 803 804 static int dp83869_config_init(struct phy_device *phydev) 805 { 806 struct dp83869_private *dp83869 = phydev->priv; 807 int ret, val; 808 809 /* Force speed optimization for the PHY even if it strapped */ 810 ret = phy_modify(phydev, DP83869_CFG2, DP83869_DOWNSHIFT_EN, 811 DP83869_DOWNSHIFT_EN); 812 if (ret) 813 return ret; 814 815 ret = dp83869_configure_mode(phydev, dp83869); 816 if (ret) 817 return ret; 818 819 /* Enable Interrupt output INT_OE in CFG4 register */ 820 if (phy_interrupt_is_valid(phydev)) { 821 val = phy_read(phydev, DP83869_CFG4); 822 val |= DP83869_INT_OE; 823 phy_write(phydev, DP83869_CFG4, val); 824 } 825 826 if (dp83869->port_mirroring != DP83869_PORT_MIRRORING_KEEP) 827 dp83869_config_port_mirroring(phydev); 828 829 /* Clock output selection if muxing property is set */ 830 if (dp83869->clk_output_sel != DP83869_CLK_O_SEL_REF_CLK) { 831 /* 832 * Table 7-121 in datasheet says we have to set register 0xc6 833 * to value 0x10 before CLK_O_SEL can be modified. 834 */ 835 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 836 DP83869_ANA_PLL_PROG_PI, 0x10); 837 if (ret) 838 return ret; 839 840 ret = phy_modify_mmd(phydev, 841 DP83869_DEVADDR, DP83869_IO_MUX_CFG, 842 DP83869_IO_MUX_CFG_CLK_O_SEL_MASK, 843 dp83869->clk_output_sel << 844 DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT); 845 } 846 847 if (phy_interface_is_rgmii(phydev)) { 848 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIIDCTL, 849 dp83869->rx_int_delay | 850 dp83869->tx_int_delay << DP83869_RGMII_CLK_DELAY_SHIFT); 851 if (ret) 852 return ret; 853 854 val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL); 855 val |= (DP83869_RGMII_TX_CLK_DELAY_EN | 856 DP83869_RGMII_RX_CLK_DELAY_EN); 857 858 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 859 val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN | 860 DP83869_RGMII_RX_CLK_DELAY_EN); 861 862 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 863 val &= ~DP83869_RGMII_TX_CLK_DELAY_EN; 864 865 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 866 val &= ~DP83869_RGMII_RX_CLK_DELAY_EN; 867 868 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL, 869 val); 870 } 871 872 return ret; 873 } 874 875 static int dp83869_probe(struct phy_device *phydev) 876 { 877 struct dp83869_private *dp83869; 878 int ret; 879 880 dp83869 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83869), 881 GFP_KERNEL); 882 if (!dp83869) 883 return -ENOMEM; 884 885 phydev->priv = dp83869; 886 887 ret = dp83869_of_init(phydev); 888 if (ret) 889 return ret; 890 891 if (dp83869->mode == DP83869_RGMII_100_BASE || 892 dp83869->mode == DP83869_RGMII_1000_BASE) 893 phydev->port = PORT_FIBRE; 894 895 return dp83869_config_init(phydev); 896 } 897 898 static int dp83869_phy_reset(struct phy_device *phydev) 899 { 900 int ret; 901 902 ret = phy_write(phydev, DP83869_CTRL, DP83869_SW_RESET); 903 if (ret < 0) 904 return ret; 905 906 usleep_range(10, 20); 907 908 /* Global sw reset sets all registers to default. 909 * Need to set the registers in the PHY to the right config. 910 */ 911 return dp83869_config_init(phydev); 912 } 913 914 915 #define DP83869_PHY_DRIVER(_id, _name) \ 916 { \ 917 PHY_ID_MATCH_MODEL(_id), \ 918 .name = (_name), \ 919 .probe = dp83869_probe, \ 920 .config_init = dp83869_config_init, \ 921 .soft_reset = dp83869_phy_reset, \ 922 .config_intr = dp83869_config_intr, \ 923 .handle_interrupt = dp83869_handle_interrupt, \ 924 .config_aneg = dp83869_config_aneg, \ 925 .read_status = dp83869_read_status, \ 926 .get_tunable = dp83869_get_tunable, \ 927 .set_tunable = dp83869_set_tunable, \ 928 .get_wol = dp83869_get_wol, \ 929 .set_wol = dp83869_set_wol, \ 930 .suspend = genphy_suspend, \ 931 .resume = genphy_resume, \ 932 } 933 934 static struct phy_driver dp83869_driver[] = { 935 DP83869_PHY_DRIVER(DP83869_PHY_ID, "TI DP83869"), 936 DP83869_PHY_DRIVER(DP83561_PHY_ID, "TI DP83561-SP"), 937 938 }; 939 module_phy_driver(dp83869_driver); 940 941 static const struct mdio_device_id __maybe_unused dp83869_tbl[] = { 942 { PHY_ID_MATCH_MODEL(DP83869_PHY_ID) }, 943 { PHY_ID_MATCH_MODEL(DP83561_PHY_ID) }, 944 { } 945 }; 946 MODULE_DEVICE_TABLE(mdio, dp83869_tbl); 947 948 MODULE_DESCRIPTION("Texas Instruments DP83869 PHY driver"); 949 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com"); 950 MODULE_LICENSE("GPL v2"); 951