1 // SPDX-License-Identifier: GPL-2.0 2 /* Driver for the Texas Instruments DP83867 PHY 3 * 4 * Copyright (C) 2015 Texas Instruments Inc. 5 */ 6 7 #include <linux/ethtool.h> 8 #include <linux/kernel.h> 9 #include <linux/mii.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/phy.h> 13 #include <linux/delay.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/bitfield.h> 17 #include <linux/nvmem-consumer.h> 18 19 #include <dt-bindings/net/ti-dp83867.h> 20 21 #define DP83867_PHY_ID 0x2000a231 22 #define DP83867_DEVADDR 0x1f 23 24 #define MII_DP83867_PHYCTRL 0x10 25 #define MII_DP83867_PHYSTS 0x11 26 #define MII_DP83867_MICR 0x12 27 #define MII_DP83867_ISR 0x13 28 #define DP83867_CFG2 0x14 29 #define DP83867_LEDCR1 0x18 30 #define DP83867_LEDCR2 0x19 31 #define DP83867_CFG3 0x1e 32 #define DP83867_CTRL 0x1f 33 34 /* Extended Registers */ 35 #define DP83867_FLD_THR_CFG 0x002e 36 #define DP83867_CFG4 0x0031 37 #define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6)) 38 #define DP83867_CFG4_SGMII_ANEG_TIMER_11MS (3 << 5) 39 #define DP83867_CFG4_SGMII_ANEG_TIMER_800US (2 << 5) 40 #define DP83867_CFG4_SGMII_ANEG_TIMER_2US (1 << 5) 41 #define DP83867_CFG4_SGMII_ANEG_TIMER_16MS (0 << 5) 42 43 #define DP83867_RGMIICTL 0x0032 44 #define DP83867_STRAP_STS1 0x006E 45 #define DP83867_STRAP_STS2 0x006f 46 #define DP83867_RGMIIDCTL 0x0086 47 #define DP83867_DSP_FFE_CFG 0x012c 48 #define DP83867_RXFCFG 0x0134 49 #define DP83867_RXFPMD1 0x0136 50 #define DP83867_RXFPMD2 0x0137 51 #define DP83867_RXFPMD3 0x0138 52 #define DP83867_RXFSOP1 0x0139 53 #define DP83867_RXFSOP2 0x013A 54 #define DP83867_RXFSOP3 0x013B 55 #define DP83867_IO_MUX_CFG 0x0170 56 #define DP83867_SGMIICTL 0x00D3 57 #define DP83867_10M_SGMII_CFG 0x016F 58 #define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7) 59 60 #define DP83867_SW_RESET BIT(15) 61 #define DP83867_SW_RESTART BIT(14) 62 63 /* MICR Interrupt bits */ 64 #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15) 65 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14) 66 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13) 67 #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12) 68 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11) 69 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10) 70 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8) 71 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) 72 #define MII_DP83867_MICR_WOL_INT_EN BIT(3) 73 #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2) 74 #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1) 75 #define MII_DP83867_MICR_JABBER_INT_EN BIT(0) 76 77 /* RGMIICTL bits */ 78 #define DP83867_RGMII_EN BIT(7) 79 #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1) 80 #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0) 81 82 /* SGMIICTL bits */ 83 #define DP83867_SGMII_TYPE BIT(14) 84 85 /* RXFCFG bits*/ 86 #define DP83867_WOL_MAGIC_EN BIT(0) 87 #define DP83867_WOL_BCAST_EN BIT(2) 88 #define DP83867_WOL_UCAST_EN BIT(4) 89 #define DP83867_WOL_SEC_EN BIT(5) 90 #define DP83867_WOL_ENH_MAC BIT(7) 91 92 /* STRAP_STS1 bits */ 93 #define DP83867_STRAP_STS1_RESERVED BIT(11) 94 95 /* STRAP_STS2 bits */ 96 #define DP83867_STRAP_STS2_STRAP_FLD BIT(10) 97 98 /* PHY CTRL bits */ 99 #define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT 14 100 #define DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT 12 101 #define DP83867_PHYCR_FIFO_DEPTH_MAX 0x03 102 #define DP83867_PHYCR_TX_FIFO_DEPTH_MASK GENMASK(15, 14) 103 #define DP83867_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12) 104 #define DP83867_PHYCR_SGMII_EN BIT(11) 105 #define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10) 106 107 /* RGMIIDCTL bits */ 108 #define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf 109 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4 110 #define DP83867_RGMII_RX_CLK_DELAY_MAX 0xf 111 #define DP83867_RGMII_RX_CLK_DELAY_SHIFT 0 112 113 /* IO_MUX_CFG bits */ 114 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK 0x1f 115 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0 116 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f 117 #define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6) 118 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8) 119 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8 120 121 /* PHY STS bits */ 122 #define DP83867_PHYSTS_1000 BIT(15) 123 #define DP83867_PHYSTS_100 BIT(14) 124 #define DP83867_PHYSTS_DUPLEX BIT(13) 125 #define DP83867_PHYSTS_LINK BIT(10) 126 127 /* CFG2 bits */ 128 #define DP83867_DOWNSHIFT_EN (BIT(8) | BIT(9)) 129 #define DP83867_DOWNSHIFT_ATTEMPT_MASK (BIT(10) | BIT(11)) 130 #define DP83867_DOWNSHIFT_1_COUNT_VAL 0 131 #define DP83867_DOWNSHIFT_2_COUNT_VAL 1 132 #define DP83867_DOWNSHIFT_4_COUNT_VAL 2 133 #define DP83867_DOWNSHIFT_8_COUNT_VAL 3 134 #define DP83867_DOWNSHIFT_1_COUNT 1 135 #define DP83867_DOWNSHIFT_2_COUNT 2 136 #define DP83867_DOWNSHIFT_4_COUNT 4 137 #define DP83867_DOWNSHIFT_8_COUNT 8 138 #define DP83867_SGMII_AUTONEG_EN BIT(7) 139 140 /* CFG3 bits */ 141 #define DP83867_CFG3_INT_OE BIT(7) 142 #define DP83867_CFG3_ROBUST_AUTO_MDIX BIT(9) 143 144 /* CFG4 bits */ 145 #define DP83867_CFG4_PORT_MIRROR_EN BIT(0) 146 147 /* FLD_THR_CFG */ 148 #define DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK 0x7 149 150 #define DP83867_LED_COUNT 4 151 152 /* LED_DRV bits */ 153 #define DP83867_LED_DRV_EN(x) BIT((x) * 4) 154 #define DP83867_LED_DRV_VAL(x) BIT((x) * 4 + 1) 155 #define DP83867_LED_POLARITY(x) BIT((x) * 4 + 2) 156 157 #define DP83867_LED_FN(idx, val) (((val) & 0xf) << ((idx) * 4)) 158 #define DP83867_LED_FN_MASK(idx) (0xf << ((idx) * 4)) 159 #define DP83867_LED_FN_RX_ERR 0xe /* Receive Error */ 160 #define DP83867_LED_FN_RX_TX_ERR 0xd /* Receive Error or Transmit Error */ 161 #define DP83867_LED_FN_LINK_RX_TX 0xb /* Link established, blink for rx or tx activity */ 162 #define DP83867_LED_FN_FULL_DUPLEX 0xa /* Full duplex */ 163 #define DP83867_LED_FN_LINK_100_1000_BT 0x9 /* 100/1000BT link established */ 164 #define DP83867_LED_FN_LINK_10_100_BT 0x8 /* 10/100BT link established */ 165 #define DP83867_LED_FN_LINK_10_BT 0x7 /* 10BT link established */ 166 #define DP83867_LED_FN_LINK_100_BTX 0x6 /* 100 BTX link established */ 167 #define DP83867_LED_FN_LINK_1000_BT 0x5 /* 1000 BT link established */ 168 #define DP83867_LED_FN_COLLISION 0x4 /* Collision detected */ 169 #define DP83867_LED_FN_RX 0x3 /* Receive activity */ 170 #define DP83867_LED_FN_TX 0x2 /* Transmit activity */ 171 #define DP83867_LED_FN_RX_TX 0x1 /* Receive or Transmit activity */ 172 #define DP83867_LED_FN_LINK 0x0 /* Link established */ 173 174 enum { 175 DP83867_PORT_MIRROING_KEEP, 176 DP83867_PORT_MIRROING_EN, 177 DP83867_PORT_MIRROING_DIS, 178 }; 179 180 struct dp83867_private { 181 u32 rx_id_delay; 182 u32 tx_id_delay; 183 u32 tx_fifo_depth; 184 u32 rx_fifo_depth; 185 int io_impedance; 186 int port_mirroring; 187 bool rxctrl_strap_quirk; 188 bool set_clk_output; 189 u32 clk_output_sel; 190 bool sgmii_ref_clk_en; 191 }; 192 193 static int dp83867_ack_interrupt(struct phy_device *phydev) 194 { 195 int err = phy_read(phydev, MII_DP83867_ISR); 196 197 if (err < 0) 198 return err; 199 200 return 0; 201 } 202 203 static int dp83867_set_wol(struct phy_device *phydev, 204 struct ethtool_wolinfo *wol) 205 { 206 struct net_device *ndev = phydev->attached_dev; 207 u16 val_rxcfg, val_micr; 208 const u8 *mac; 209 210 val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG); 211 val_micr = phy_read(phydev, MII_DP83867_MICR); 212 213 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | 214 WAKE_BCAST)) { 215 val_rxcfg |= DP83867_WOL_ENH_MAC; 216 val_micr |= MII_DP83867_MICR_WOL_INT_EN; 217 218 if (wol->wolopts & WAKE_MAGIC) { 219 mac = (const u8 *)ndev->dev_addr; 220 221 if (!is_valid_ether_addr(mac)) 222 return -EINVAL; 223 224 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1, 225 (mac[1] << 8 | mac[0])); 226 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2, 227 (mac[3] << 8 | mac[2])); 228 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3, 229 (mac[5] << 8 | mac[4])); 230 231 val_rxcfg |= DP83867_WOL_MAGIC_EN; 232 } else { 233 val_rxcfg &= ~DP83867_WOL_MAGIC_EN; 234 } 235 236 if (wol->wolopts & WAKE_MAGICSECURE) { 237 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1, 238 (wol->sopass[1] << 8) | wol->sopass[0]); 239 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP2, 240 (wol->sopass[3] << 8) | wol->sopass[2]); 241 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP3, 242 (wol->sopass[5] << 8) | wol->sopass[4]); 243 244 val_rxcfg |= DP83867_WOL_SEC_EN; 245 } else { 246 val_rxcfg &= ~DP83867_WOL_SEC_EN; 247 } 248 249 if (wol->wolopts & WAKE_UCAST) 250 val_rxcfg |= DP83867_WOL_UCAST_EN; 251 else 252 val_rxcfg &= ~DP83867_WOL_UCAST_EN; 253 254 if (wol->wolopts & WAKE_BCAST) 255 val_rxcfg |= DP83867_WOL_BCAST_EN; 256 else 257 val_rxcfg &= ~DP83867_WOL_BCAST_EN; 258 } else { 259 val_rxcfg &= ~DP83867_WOL_ENH_MAC; 260 val_micr &= ~MII_DP83867_MICR_WOL_INT_EN; 261 } 262 263 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg); 264 phy_write(phydev, MII_DP83867_MICR, val_micr); 265 266 return 0; 267 } 268 269 static void dp83867_get_wol(struct phy_device *phydev, 270 struct ethtool_wolinfo *wol) 271 { 272 u16 value, sopass_val; 273 274 wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC | 275 WAKE_MAGICSECURE); 276 wol->wolopts = 0; 277 278 value = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG); 279 280 if (value & DP83867_WOL_UCAST_EN) 281 wol->wolopts |= WAKE_UCAST; 282 283 if (value & DP83867_WOL_BCAST_EN) 284 wol->wolopts |= WAKE_BCAST; 285 286 if (value & DP83867_WOL_MAGIC_EN) 287 wol->wolopts |= WAKE_MAGIC; 288 289 if (value & DP83867_WOL_SEC_EN) { 290 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR, 291 DP83867_RXFSOP1); 292 wol->sopass[0] = (sopass_val & 0xff); 293 wol->sopass[1] = (sopass_val >> 8); 294 295 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR, 296 DP83867_RXFSOP2); 297 wol->sopass[2] = (sopass_val & 0xff); 298 wol->sopass[3] = (sopass_val >> 8); 299 300 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR, 301 DP83867_RXFSOP3); 302 wol->sopass[4] = (sopass_val & 0xff); 303 wol->sopass[5] = (sopass_val >> 8); 304 305 wol->wolopts |= WAKE_MAGICSECURE; 306 } 307 308 if (!(value & DP83867_WOL_ENH_MAC)) 309 wol->wolopts = 0; 310 } 311 312 static int dp83867_config_intr(struct phy_device *phydev) 313 { 314 int micr_status, err; 315 316 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 317 err = dp83867_ack_interrupt(phydev); 318 if (err) 319 return err; 320 321 micr_status = phy_read(phydev, MII_DP83867_MICR); 322 if (micr_status < 0) 323 return micr_status; 324 325 micr_status |= 326 (MII_DP83867_MICR_AN_ERR_INT_EN | 327 MII_DP83867_MICR_SPEED_CHNG_INT_EN | 328 MII_DP83867_MICR_AUTONEG_COMP_INT_EN | 329 MII_DP83867_MICR_LINK_STS_CHNG_INT_EN | 330 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN | 331 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN); 332 333 err = phy_write(phydev, MII_DP83867_MICR, micr_status); 334 } else { 335 micr_status = 0x0; 336 err = phy_write(phydev, MII_DP83867_MICR, micr_status); 337 if (err) 338 return err; 339 340 err = dp83867_ack_interrupt(phydev); 341 } 342 343 return err; 344 } 345 346 static irqreturn_t dp83867_handle_interrupt(struct phy_device *phydev) 347 { 348 int irq_status, irq_enabled; 349 350 irq_status = phy_read(phydev, MII_DP83867_ISR); 351 if (irq_status < 0) { 352 phy_error(phydev); 353 return IRQ_NONE; 354 } 355 356 irq_enabled = phy_read(phydev, MII_DP83867_MICR); 357 if (irq_enabled < 0) { 358 phy_error(phydev); 359 return IRQ_NONE; 360 } 361 362 if (!(irq_status & irq_enabled)) 363 return IRQ_NONE; 364 365 phy_trigger_machine(phydev); 366 367 return IRQ_HANDLED; 368 } 369 370 static int dp83867_read_status(struct phy_device *phydev) 371 { 372 int status = phy_read(phydev, MII_DP83867_PHYSTS); 373 int ret; 374 375 ret = genphy_read_status(phydev); 376 if (ret) 377 return ret; 378 379 if (status < 0) 380 return status; 381 382 if (status & DP83867_PHYSTS_DUPLEX) 383 phydev->duplex = DUPLEX_FULL; 384 else 385 phydev->duplex = DUPLEX_HALF; 386 387 if (status & DP83867_PHYSTS_1000) 388 phydev->speed = SPEED_1000; 389 else if (status & DP83867_PHYSTS_100) 390 phydev->speed = SPEED_100; 391 else 392 phydev->speed = SPEED_10; 393 394 return 0; 395 } 396 397 static int dp83867_get_downshift(struct phy_device *phydev, u8 *data) 398 { 399 int val, cnt, enable, count; 400 401 val = phy_read(phydev, DP83867_CFG2); 402 if (val < 0) 403 return val; 404 405 enable = FIELD_GET(DP83867_DOWNSHIFT_EN, val); 406 cnt = FIELD_GET(DP83867_DOWNSHIFT_ATTEMPT_MASK, val); 407 408 switch (cnt) { 409 case DP83867_DOWNSHIFT_1_COUNT_VAL: 410 count = DP83867_DOWNSHIFT_1_COUNT; 411 break; 412 case DP83867_DOWNSHIFT_2_COUNT_VAL: 413 count = DP83867_DOWNSHIFT_2_COUNT; 414 break; 415 case DP83867_DOWNSHIFT_4_COUNT_VAL: 416 count = DP83867_DOWNSHIFT_4_COUNT; 417 break; 418 case DP83867_DOWNSHIFT_8_COUNT_VAL: 419 count = DP83867_DOWNSHIFT_8_COUNT; 420 break; 421 default: 422 return -EINVAL; 423 } 424 425 *data = enable ? count : DOWNSHIFT_DEV_DISABLE; 426 427 return 0; 428 } 429 430 static int dp83867_set_downshift(struct phy_device *phydev, u8 cnt) 431 { 432 int val, count; 433 434 if (cnt > DP83867_DOWNSHIFT_8_COUNT) 435 return -E2BIG; 436 437 if (!cnt) 438 return phy_clear_bits(phydev, DP83867_CFG2, 439 DP83867_DOWNSHIFT_EN); 440 441 switch (cnt) { 442 case DP83867_DOWNSHIFT_1_COUNT: 443 count = DP83867_DOWNSHIFT_1_COUNT_VAL; 444 break; 445 case DP83867_DOWNSHIFT_2_COUNT: 446 count = DP83867_DOWNSHIFT_2_COUNT_VAL; 447 break; 448 case DP83867_DOWNSHIFT_4_COUNT: 449 count = DP83867_DOWNSHIFT_4_COUNT_VAL; 450 break; 451 case DP83867_DOWNSHIFT_8_COUNT: 452 count = DP83867_DOWNSHIFT_8_COUNT_VAL; 453 break; 454 default: 455 phydev_err(phydev, 456 "Downshift count must be 1, 2, 4 or 8\n"); 457 return -EINVAL; 458 } 459 460 val = DP83867_DOWNSHIFT_EN; 461 val |= FIELD_PREP(DP83867_DOWNSHIFT_ATTEMPT_MASK, count); 462 463 return phy_modify(phydev, DP83867_CFG2, 464 DP83867_DOWNSHIFT_EN | DP83867_DOWNSHIFT_ATTEMPT_MASK, 465 val); 466 } 467 468 static int dp83867_get_tunable(struct phy_device *phydev, 469 struct ethtool_tunable *tuna, void *data) 470 { 471 switch (tuna->id) { 472 case ETHTOOL_PHY_DOWNSHIFT: 473 return dp83867_get_downshift(phydev, data); 474 default: 475 return -EOPNOTSUPP; 476 } 477 } 478 479 static int dp83867_set_tunable(struct phy_device *phydev, 480 struct ethtool_tunable *tuna, const void *data) 481 { 482 switch (tuna->id) { 483 case ETHTOOL_PHY_DOWNSHIFT: 484 return dp83867_set_downshift(phydev, *(const u8 *)data); 485 default: 486 return -EOPNOTSUPP; 487 } 488 } 489 490 static int dp83867_config_port_mirroring(struct phy_device *phydev) 491 { 492 struct dp83867_private *dp83867 = phydev->priv; 493 494 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN) 495 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 496 DP83867_CFG4_PORT_MIRROR_EN); 497 else 498 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 499 DP83867_CFG4_PORT_MIRROR_EN); 500 return 0; 501 } 502 503 #if IS_ENABLED(CONFIG_OF_MDIO) 504 static int dp83867_of_init_io_impedance(struct phy_device *phydev) 505 { 506 struct dp83867_private *dp83867 = phydev->priv; 507 struct device *dev = &phydev->mdio.dev; 508 struct device_node *of_node = dev->of_node; 509 struct nvmem_cell *cell; 510 u8 *buf, val; 511 int ret; 512 513 cell = of_nvmem_cell_get(of_node, "io_impedance_ctrl"); 514 if (IS_ERR(cell)) { 515 ret = PTR_ERR(cell); 516 if (ret != -ENOENT && ret != -EOPNOTSUPP) 517 return phydev_err_probe(phydev, ret, 518 "failed to get nvmem cell io_impedance_ctrl\n"); 519 520 /* If no nvmem cell, check for the boolean properties. */ 521 if (of_property_read_bool(of_node, "ti,max-output-impedance")) 522 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX; 523 else if (of_property_read_bool(of_node, "ti,min-output-impedance")) 524 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN; 525 else 526 dp83867->io_impedance = -1; /* leave at default */ 527 528 return 0; 529 } 530 531 buf = nvmem_cell_read(cell, NULL); 532 nvmem_cell_put(cell); 533 534 if (IS_ERR(buf)) 535 return PTR_ERR(buf); 536 537 val = *buf; 538 kfree(buf); 539 540 if ((val & DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK) != val) { 541 phydev_err(phydev, "nvmem cell 'io_impedance_ctrl' contents out of range\n"); 542 return -ERANGE; 543 } 544 dp83867->io_impedance = val; 545 546 return 0; 547 } 548 549 static int dp83867_of_init(struct phy_device *phydev) 550 { 551 struct dp83867_private *dp83867 = phydev->priv; 552 struct device *dev = &phydev->mdio.dev; 553 struct device_node *of_node = dev->of_node; 554 int ret; 555 556 if (!of_node) 557 return -ENODEV; 558 559 /* Optional configuration */ 560 ret = of_property_read_u32(of_node, "ti,clk-output-sel", 561 &dp83867->clk_output_sel); 562 /* If not set, keep default */ 563 if (!ret) { 564 dp83867->set_clk_output = true; 565 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or 566 * DP83867_CLK_O_SEL_OFF. 567 */ 568 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK && 569 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) { 570 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n", 571 dp83867->clk_output_sel); 572 return -EINVAL; 573 } 574 } 575 576 ret = dp83867_of_init_io_impedance(phydev); 577 if (ret) 578 return ret; 579 580 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node, 581 "ti,dp83867-rxctrl-strap-quirk"); 582 583 dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node, 584 "ti,sgmii-ref-clock-output-enable"); 585 586 dp83867->rx_id_delay = DP83867_RGMIIDCTL_2_00_NS; 587 ret = of_property_read_u32(of_node, "ti,rx-internal-delay", 588 &dp83867->rx_id_delay); 589 if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) { 590 phydev_err(phydev, 591 "ti,rx-internal-delay value of %u out of range\n", 592 dp83867->rx_id_delay); 593 return -EINVAL; 594 } 595 596 dp83867->tx_id_delay = DP83867_RGMIIDCTL_2_00_NS; 597 ret = of_property_read_u32(of_node, "ti,tx-internal-delay", 598 &dp83867->tx_id_delay); 599 if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) { 600 phydev_err(phydev, 601 "ti,tx-internal-delay value of %u out of range\n", 602 dp83867->tx_id_delay); 603 return -EINVAL; 604 } 605 606 if (of_property_read_bool(of_node, "enet-phy-lane-swap")) 607 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN; 608 609 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap")) 610 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS; 611 612 ret = of_property_read_u32(of_node, "ti,fifo-depth", 613 &dp83867->tx_fifo_depth); 614 if (ret) { 615 ret = of_property_read_u32(of_node, "tx-fifo-depth", 616 &dp83867->tx_fifo_depth); 617 if (ret) 618 dp83867->tx_fifo_depth = 619 DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; 620 } 621 622 if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { 623 phydev_err(phydev, "tx-fifo-depth value %u out of range\n", 624 dp83867->tx_fifo_depth); 625 return -EINVAL; 626 } 627 628 ret = of_property_read_u32(of_node, "rx-fifo-depth", 629 &dp83867->rx_fifo_depth); 630 if (ret) 631 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; 632 633 if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { 634 phydev_err(phydev, "rx-fifo-depth value %u out of range\n", 635 dp83867->rx_fifo_depth); 636 return -EINVAL; 637 } 638 639 return 0; 640 } 641 #else 642 static int dp83867_of_init(struct phy_device *phydev) 643 { 644 struct dp83867_private *dp83867 = phydev->priv; 645 u16 delay; 646 647 /* For non-OF device, the RX and TX ID values are either strapped 648 * or take from default value. So, we init RX & TX ID values here 649 * so that the RGMIIDCTL is configured correctly later in 650 * dp83867_config_init(); 651 */ 652 delay = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL); 653 dp83867->rx_id_delay = delay & DP83867_RGMII_RX_CLK_DELAY_MAX; 654 dp83867->tx_id_delay = (delay >> DP83867_RGMII_TX_CLK_DELAY_SHIFT) & 655 DP83867_RGMII_TX_CLK_DELAY_MAX; 656 657 /* Per datasheet, IO impedance is default to 50-ohm, so we set the 658 * same here or else the default '0' means highest IO impedance 659 * which is wrong. 660 */ 661 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN / 2; 662 663 /* For non-OF device, the RX and TX FIFO depths are taken from 664 * default value. So, we init RX & TX FIFO depths here 665 * so that it is configured correctly later in dp83867_config_init(); 666 */ 667 dp83867->tx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; 668 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; 669 670 return 0; 671 } 672 #endif /* CONFIG_OF_MDIO */ 673 674 static int dp83867_suspend(struct phy_device *phydev) 675 { 676 /* Disable PHY Interrupts */ 677 if (phy_interrupt_is_valid(phydev)) { 678 phydev->interrupts = PHY_INTERRUPT_DISABLED; 679 dp83867_config_intr(phydev); 680 } 681 682 return genphy_suspend(phydev); 683 } 684 685 static int dp83867_resume(struct phy_device *phydev) 686 { 687 /* Enable PHY Interrupts */ 688 if (phy_interrupt_is_valid(phydev)) { 689 phydev->interrupts = PHY_INTERRUPT_ENABLED; 690 dp83867_config_intr(phydev); 691 } 692 693 genphy_resume(phydev); 694 695 return 0; 696 } 697 698 static int dp83867_probe(struct phy_device *phydev) 699 { 700 struct dp83867_private *dp83867; 701 702 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867), 703 GFP_KERNEL); 704 if (!dp83867) 705 return -ENOMEM; 706 707 phydev->priv = dp83867; 708 709 return dp83867_of_init(phydev); 710 } 711 712 static int dp83867_config_init(struct phy_device *phydev) 713 { 714 struct dp83867_private *dp83867 = phydev->priv; 715 int ret, val, bs; 716 717 /* Force speed optimization for the PHY even if it strapped */ 718 ret = phy_modify(phydev, DP83867_CFG2, DP83867_DOWNSHIFT_EN, 719 DP83867_DOWNSHIFT_EN); 720 if (ret) 721 return ret; 722 723 /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */ 724 if (dp83867->rxctrl_strap_quirk) 725 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 726 BIT(7)); 727 728 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2); 729 if (bs & DP83867_STRAP_STS2_STRAP_FLD) { 730 /* When using strap to enable FLD, the ENERGY_LOST_FLD_THR will 731 * be set to 0x2. This may causes the PHY link to be unstable - 732 * the default value 0x1 need to be restored. 733 */ 734 ret = phy_modify_mmd(phydev, DP83867_DEVADDR, 735 DP83867_FLD_THR_CFG, 736 DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK, 737 0x1); 738 if (ret) 739 return ret; 740 } 741 742 /* Although the DP83867 reports EEE capability through the 743 * MDIO_PCS_EEE_ABLE and MDIO_AN_EEE_ADV registers, the feature 744 * is not actually implemented in hardware. 745 */ 746 phy_disable_eee(phydev); 747 748 val = phy_read(phydev, MII_DP83867_PHYCTRL); 749 if (val < 0) 750 return val; 751 752 val &= ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK; 753 val |= (dp83867->tx_fifo_depth << 754 DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT); 755 756 val &= ~DP83867_PHYCR_SGMII_EN; 757 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 758 val &= ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK; 759 val |= (dp83867->rx_fifo_depth << 760 DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT) | 761 DP83867_PHYCR_SGMII_EN; 762 } 763 764 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val); 765 if (ret) 766 return ret; 767 768 if (phy_interface_is_rgmii(phydev)) { 769 /* Set up RGMII delays */ 770 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL); 771 772 val |= DP83867_RGMII_EN; 773 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN); 774 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 775 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN); 776 777 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 778 val |= DP83867_RGMII_TX_CLK_DELAY_EN; 779 780 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 781 val |= DP83867_RGMII_RX_CLK_DELAY_EN; 782 783 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val); 784 785 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL, 786 dp83867->rx_id_delay | 787 (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT)); 788 } else { 789 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL); 790 val &= ~DP83867_RGMII_EN; 791 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val); 792 } 793 794 /* If specified, set io impedance */ 795 if (dp83867->io_impedance >= 0) 796 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, 797 DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK, 798 dp83867->io_impedance); 799 800 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 801 /* For support SPEED_10 in SGMII mode 802 * DP83867_10M_SGMII_RATE_ADAPT bit 803 * has to be cleared by software. That 804 * does not affect SPEED_100 and 805 * SPEED_1000. 806 */ 807 ret = phy_modify_mmd(phydev, DP83867_DEVADDR, 808 DP83867_10M_SGMII_CFG, 809 DP83867_10M_SGMII_RATE_ADAPT_MASK, 810 0); 811 if (ret) 812 return ret; 813 814 /* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5 815 * are 01). That is not enough to finalize autoneg on some 816 * devices. Increase this timer duration to maximum 16ms. 817 */ 818 ret = phy_modify_mmd(phydev, DP83867_DEVADDR, 819 DP83867_CFG4, 820 DP83867_CFG4_SGMII_ANEG_MASK, 821 DP83867_CFG4_SGMII_ANEG_TIMER_16MS); 822 823 if (ret) 824 return ret; 825 826 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL); 827 /* SGMII type is set to 4-wire mode by default. 828 * If we place appropriate property in dts (see above) 829 * switch on 6-wire mode. 830 */ 831 if (dp83867->sgmii_ref_clk_en) 832 val |= DP83867_SGMII_TYPE; 833 else 834 val &= ~DP83867_SGMII_TYPE; 835 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val); 836 837 /* This is a SW workaround for link instability if RX_CTRL is 838 * not strapped to mode 3 or 4 in HW. This is required for SGMII 839 * in addition to clearing bit 7, handled above. 840 */ 841 if (dp83867->rxctrl_strap_quirk) 842 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 843 BIT(8)); 844 } 845 846 val = phy_read(phydev, DP83867_CFG3); 847 /* Enable Interrupt output INT_OE in CFG3 register */ 848 if (phy_interrupt_is_valid(phydev)) 849 val |= DP83867_CFG3_INT_OE; 850 851 val |= DP83867_CFG3_ROBUST_AUTO_MDIX; 852 phy_write(phydev, DP83867_CFG3, val); 853 854 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP) 855 dp83867_config_port_mirroring(phydev); 856 857 /* Clock output selection if muxing property is set */ 858 if (dp83867->set_clk_output) { 859 u16 mask = DP83867_IO_MUX_CFG_CLK_O_DISABLE; 860 861 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) { 862 val = DP83867_IO_MUX_CFG_CLK_O_DISABLE; 863 } else { 864 mask |= DP83867_IO_MUX_CFG_CLK_O_SEL_MASK; 865 val = dp83867->clk_output_sel << 866 DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT; 867 } 868 869 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, 870 mask, val); 871 } 872 873 return 0; 874 } 875 876 static int dp83867_phy_reset(struct phy_device *phydev) 877 { 878 int err; 879 880 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET); 881 if (err < 0) 882 return err; 883 884 usleep_range(10, 20); 885 886 err = phy_modify(phydev, MII_DP83867_PHYCTRL, 887 DP83867_PHYCR_FORCE_LINK_GOOD, 0); 888 if (err < 0) 889 return err; 890 891 /* Configure the DSP Feedforward Equalizer Configuration register to 892 * improve short cable (< 1 meter) performance. This will not affect 893 * long cable performance. 894 */ 895 err = phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_DSP_FFE_CFG, 896 0x0e81); 897 if (err < 0) 898 return err; 899 900 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESTART); 901 if (err < 0) 902 return err; 903 904 usleep_range(10, 20); 905 906 return 0; 907 } 908 909 static void dp83867_link_change_notify(struct phy_device *phydev) 910 { 911 /* There is a limitation in DP83867 PHY device where SGMII AN is 912 * only triggered once after the device is booted up. Even after the 913 * PHY TPI is down and up again, SGMII AN is not triggered and 914 * hence no new in-band message from PHY to MAC side SGMII. 915 * This could cause an issue during power up, when PHY is up prior 916 * to MAC. At this condition, once MAC side SGMII is up, MAC side 917 * SGMII wouldn`t receive new in-band message from TI PHY with 918 * correct link status, speed and duplex info. 919 * Thus, implemented a SW solution here to retrigger SGMII Auto-Neg 920 * whenever there is a link change. 921 */ 922 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 923 int val; 924 925 val = phy_modify_changed(phydev, DP83867_CFG2, 926 DP83867_SGMII_AUTONEG_EN, 0); 927 928 /* Keep the in-band setting made by dp83867_config_inband() */ 929 if (val != 0) 930 phy_set_bits(phydev, DP83867_CFG2, 931 DP83867_SGMII_AUTONEG_EN); 932 } 933 } 934 935 static int dp83867_loopback(struct phy_device *phydev, bool enable, int speed) 936 { 937 if (enable && speed) 938 return -EOPNOTSUPP; 939 940 return phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, 941 enable ? BMCR_LOOPBACK : 0); 942 } 943 944 static int 945 dp83867_led_brightness_set(struct phy_device *phydev, 946 u8 index, enum led_brightness brightness) 947 { 948 u32 val; 949 950 if (index >= DP83867_LED_COUNT) 951 return -EINVAL; 952 953 /* DRV_EN==1: output is DRV_VAL */ 954 val = DP83867_LED_DRV_EN(index); 955 956 if (brightness) 957 val |= DP83867_LED_DRV_VAL(index); 958 959 return phy_modify(phydev, DP83867_LEDCR2, 960 DP83867_LED_DRV_VAL(index) | 961 DP83867_LED_DRV_EN(index), 962 val); 963 } 964 965 static int dp83867_led_mode(u8 index, unsigned long rules) 966 { 967 if (index >= DP83867_LED_COUNT) 968 return -EINVAL; 969 970 switch (rules) { 971 case BIT(TRIGGER_NETDEV_LINK): 972 return DP83867_LED_FN_LINK; 973 case BIT(TRIGGER_NETDEV_LINK_10): 974 return DP83867_LED_FN_LINK_10_BT; 975 case BIT(TRIGGER_NETDEV_LINK_100): 976 return DP83867_LED_FN_LINK_100_BTX; 977 case BIT(TRIGGER_NETDEV_FULL_DUPLEX): 978 return DP83867_LED_FN_FULL_DUPLEX; 979 case BIT(TRIGGER_NETDEV_TX): 980 return DP83867_LED_FN_TX; 981 case BIT(TRIGGER_NETDEV_RX): 982 return DP83867_LED_FN_RX; 983 case BIT(TRIGGER_NETDEV_LINK_1000): 984 return DP83867_LED_FN_LINK_1000_BT; 985 case BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX): 986 return DP83867_LED_FN_RX_TX; 987 case BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK_1000): 988 return DP83867_LED_FN_LINK_100_1000_BT; 989 case BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK_100): 990 return DP83867_LED_FN_LINK_10_100_BT; 991 case BIT(TRIGGER_NETDEV_LINK) | BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX): 992 return DP83867_LED_FN_LINK_RX_TX; 993 default: 994 return -EOPNOTSUPP; 995 } 996 } 997 998 static int dp83867_led_hw_is_supported(struct phy_device *phydev, u8 index, 999 unsigned long rules) 1000 { 1001 int ret; 1002 1003 ret = dp83867_led_mode(index, rules); 1004 if (ret < 0) 1005 return ret; 1006 1007 return 0; 1008 } 1009 1010 static int dp83867_led_hw_control_set(struct phy_device *phydev, u8 index, 1011 unsigned long rules) 1012 { 1013 int mode, ret; 1014 1015 mode = dp83867_led_mode(index, rules); 1016 if (mode < 0) 1017 return mode; 1018 1019 ret = phy_modify(phydev, DP83867_LEDCR1, DP83867_LED_FN_MASK(index), 1020 DP83867_LED_FN(index, mode)); 1021 if (ret) 1022 return ret; 1023 1024 return phy_modify(phydev, DP83867_LEDCR2, DP83867_LED_DRV_EN(index), 0); 1025 } 1026 1027 static int dp83867_led_hw_control_get(struct phy_device *phydev, u8 index, 1028 unsigned long *rules) 1029 { 1030 int val; 1031 1032 val = phy_read(phydev, DP83867_LEDCR1); 1033 if (val < 0) 1034 return val; 1035 1036 val &= DP83867_LED_FN_MASK(index); 1037 val >>= index * 4; 1038 1039 switch (val) { 1040 case DP83867_LED_FN_LINK: 1041 *rules = BIT(TRIGGER_NETDEV_LINK); 1042 break; 1043 case DP83867_LED_FN_LINK_10_BT: 1044 *rules = BIT(TRIGGER_NETDEV_LINK_10); 1045 break; 1046 case DP83867_LED_FN_LINK_100_BTX: 1047 *rules = BIT(TRIGGER_NETDEV_LINK_100); 1048 break; 1049 case DP83867_LED_FN_FULL_DUPLEX: 1050 *rules = BIT(TRIGGER_NETDEV_FULL_DUPLEX); 1051 break; 1052 case DP83867_LED_FN_TX: 1053 *rules = BIT(TRIGGER_NETDEV_TX); 1054 break; 1055 case DP83867_LED_FN_RX: 1056 *rules = BIT(TRIGGER_NETDEV_RX); 1057 break; 1058 case DP83867_LED_FN_LINK_1000_BT: 1059 *rules = BIT(TRIGGER_NETDEV_LINK_1000); 1060 break; 1061 case DP83867_LED_FN_RX_TX: 1062 *rules = BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX); 1063 break; 1064 case DP83867_LED_FN_LINK_100_1000_BT: 1065 *rules = BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK_1000); 1066 break; 1067 case DP83867_LED_FN_LINK_10_100_BT: 1068 *rules = BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK_100); 1069 break; 1070 case DP83867_LED_FN_LINK_RX_TX: 1071 *rules = BIT(TRIGGER_NETDEV_LINK) | BIT(TRIGGER_NETDEV_TX) | 1072 BIT(TRIGGER_NETDEV_RX); 1073 break; 1074 default: 1075 *rules = 0; 1076 break; 1077 } 1078 1079 return 0; 1080 } 1081 1082 static int dp83867_led_polarity_set(struct phy_device *phydev, int index, 1083 unsigned long modes) 1084 { 1085 /* Default active high */ 1086 u16 polarity = DP83867_LED_POLARITY(index); 1087 u32 mode; 1088 1089 for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) { 1090 switch (mode) { 1091 case PHY_LED_ACTIVE_LOW: 1092 polarity = 0; 1093 break; 1094 default: 1095 return -EINVAL; 1096 } 1097 } 1098 return phy_modify(phydev, DP83867_LEDCR2, 1099 DP83867_LED_POLARITY(index), polarity); 1100 } 1101 1102 static unsigned int dp83867_inband_caps(struct phy_device *phydev, 1103 phy_interface_t interface) 1104 { 1105 if (interface == PHY_INTERFACE_MODE_SGMII) 1106 return LINK_INBAND_ENABLE | LINK_INBAND_DISABLE; 1107 1108 return 0; 1109 } 1110 1111 static int dp83867_config_inband(struct phy_device *phydev, unsigned int modes) 1112 { 1113 int val = 0; 1114 1115 if (modes == LINK_INBAND_ENABLE) 1116 val = DP83867_SGMII_AUTONEG_EN; 1117 1118 return phy_modify(phydev, DP83867_CFG2, DP83867_SGMII_AUTONEG_EN, val); 1119 } 1120 1121 static struct phy_driver dp83867_driver[] = { 1122 { 1123 .phy_id = DP83867_PHY_ID, 1124 .phy_id_mask = 0xfffffff0, 1125 .name = "TI DP83867", 1126 /* PHY_GBIT_FEATURES */ 1127 1128 .probe = dp83867_probe, 1129 .config_init = dp83867_config_init, 1130 .soft_reset = dp83867_phy_reset, 1131 1132 .read_status = dp83867_read_status, 1133 .get_tunable = dp83867_get_tunable, 1134 .set_tunable = dp83867_set_tunable, 1135 1136 .get_wol = dp83867_get_wol, 1137 .set_wol = dp83867_set_wol, 1138 1139 /* IRQ related */ 1140 .config_intr = dp83867_config_intr, 1141 .handle_interrupt = dp83867_handle_interrupt, 1142 1143 .suspend = dp83867_suspend, 1144 .resume = dp83867_resume, 1145 1146 .link_change_notify = dp83867_link_change_notify, 1147 .set_loopback = dp83867_loopback, 1148 1149 .led_brightness_set = dp83867_led_brightness_set, 1150 .led_hw_is_supported = dp83867_led_hw_is_supported, 1151 .led_hw_control_set = dp83867_led_hw_control_set, 1152 .led_hw_control_get = dp83867_led_hw_control_get, 1153 .led_polarity_set = dp83867_led_polarity_set, 1154 1155 .inband_caps = dp83867_inband_caps, 1156 .config_inband = dp83867_config_inband, 1157 }, 1158 }; 1159 module_phy_driver(dp83867_driver); 1160 1161 static const struct mdio_device_id __maybe_unused dp83867_tbl[] = { 1162 { DP83867_PHY_ID, 0xfffffff0 }, 1163 { } 1164 }; 1165 1166 MODULE_DEVICE_TABLE(mdio, dp83867_tbl); 1167 1168 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver"); 1169 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com"); 1170 MODULE_LICENSE("GPL v2"); 1171