1 // SPDX-License-Identifier: GPL-2.0
2 /* Driver for the Texas Instruments DP83822, DP83825 and DP83826 PHYs.
3 *
4 * Copyright (C) 2017 Texas Instruments Inc.
5 */
6
7 #include <linux/ethtool.h>
8 #include <linux/etherdevice.h>
9 #include <linux/kernel.h>
10 #include <linux/mii.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/phy.h>
14 #include <linux/netdevice.h>
15 #include <linux/bitfield.h>
16
17 #define DP83822_PHY_ID 0x2000a240
18 #define DP83825S_PHY_ID 0x2000a140
19 #define DP83825I_PHY_ID 0x2000a150
20 #define DP83825CM_PHY_ID 0x2000a160
21 #define DP83825CS_PHY_ID 0x2000a170
22 #define DP83826C_PHY_ID 0x2000a130
23 #define DP83826NC_PHY_ID 0x2000a110
24
25 #define MII_DP83822_CTRL_2 0x0a
26 #define MII_DP83822_PHYSTS 0x10
27 #define MII_DP83822_PHYSCR 0x11
28 #define MII_DP83822_MISR1 0x12
29 #define MII_DP83822_MISR2 0x13
30 #define MII_DP83822_FCSCR 0x14
31 #define MII_DP83822_RCSR 0x17
32 #define MII_DP83822_RESET_CTRL 0x1f
33 #define MII_DP83822_MLEDCR 0x25
34 #define MII_DP83822_LDCTRL 0x403
35 #define MII_DP83822_LEDCFG1 0x460
36 #define MII_DP83822_IOCTRL1 0x462
37 #define MII_DP83822_IOCTRL2 0x463
38 #define MII_DP83822_GENCFG 0x465
39 #define MII_DP83822_SOR1 0x467
40
41 /* DP83826 specific registers */
42 #define MII_DP83826_VOD_CFG1 0x30b
43 #define MII_DP83826_VOD_CFG2 0x30c
44
45 /* GENCFG */
46 #define DP83822_SIG_DET_LOW BIT(0)
47
48 /* Control Register 2 bits */
49 #define DP83822_FX_ENABLE BIT(14)
50
51 #define DP83822_SW_RESET BIT(15)
52 #define DP83822_DIG_RESTART BIT(14)
53
54 /* PHY STS bits */
55 #define DP83822_PHYSTS_DUPLEX BIT(2)
56 #define DP83822_PHYSTS_10 BIT(1)
57 #define DP83822_PHYSTS_LINK BIT(0)
58
59 /* PHYSCR Register Fields */
60 #define DP83822_PHYSCR_INT_OE BIT(0) /* Interrupt Output Enable */
61 #define DP83822_PHYSCR_INTEN BIT(1) /* Interrupt Enable */
62
63 /* MISR1 bits */
64 #define DP83822_RX_ERR_HF_INT_EN BIT(0)
65 #define DP83822_FALSE_CARRIER_HF_INT_EN BIT(1)
66 #define DP83822_ANEG_COMPLETE_INT_EN BIT(2)
67 #define DP83822_DUP_MODE_CHANGE_INT_EN BIT(3)
68 #define DP83822_SPEED_CHANGED_INT_EN BIT(4)
69 #define DP83822_LINK_STAT_INT_EN BIT(5)
70 #define DP83822_ENERGY_DET_INT_EN BIT(6)
71 #define DP83822_LINK_QUAL_INT_EN BIT(7)
72
73 /* MISR2 bits */
74 #define DP83822_JABBER_DET_INT_EN BIT(0)
75 #define DP83822_WOL_PKT_INT_EN BIT(1)
76 #define DP83822_SLEEP_MODE_INT_EN BIT(2)
77 #define DP83822_MDI_XOVER_INT_EN BIT(3)
78 #define DP83822_LB_FIFO_INT_EN BIT(4)
79 #define DP83822_PAGE_RX_INT_EN BIT(5)
80 #define DP83822_ANEG_ERR_INT_EN BIT(6)
81 #define DP83822_EEE_ERROR_CHANGE_INT_EN BIT(7)
82
83 /* INT_STAT1 bits */
84 #define DP83822_WOL_INT_EN BIT(4)
85 #define DP83822_WOL_INT_STAT BIT(12)
86
87 #define MII_DP83822_RXSOP1 0x04a5
88 #define MII_DP83822_RXSOP2 0x04a6
89 #define MII_DP83822_RXSOP3 0x04a7
90
91 /* WoL Registers */
92 #define MII_DP83822_WOL_CFG 0x04a0
93 #define MII_DP83822_WOL_STAT 0x04a1
94 #define MII_DP83822_WOL_DA1 0x04a2
95 #define MII_DP83822_WOL_DA2 0x04a3
96 #define MII_DP83822_WOL_DA3 0x04a4
97
98 /* WoL bits */
99 #define DP83822_WOL_MAGIC_EN BIT(0)
100 #define DP83822_WOL_SECURE_ON BIT(5)
101 #define DP83822_WOL_EN BIT(7)
102 #define DP83822_WOL_INDICATION_SEL BIT(8)
103 #define DP83822_WOL_CLR_INDICATION BIT(11)
104
105 /* RCSR bits */
106 #define DP83822_RMII_MODE_EN BIT(5)
107 #define DP83822_RMII_MODE_SEL BIT(7)
108 #define DP83822_RGMII_MODE_EN BIT(9)
109 #define DP83822_RX_CLK_SHIFT BIT(12)
110 #define DP83822_TX_CLK_SHIFT BIT(11)
111
112 /* MLEDCR bits */
113 #define DP83822_MLEDCR_CFG GENMASK(6, 3)
114 #define DP83822_MLEDCR_ROUTE GENMASK(1, 0)
115 #define DP83822_MLEDCR_ROUTE_LED_0 DP83822_MLEDCR_ROUTE
116
117 /* LEDCFG1 bits */
118 #define DP83822_LEDCFG1_LED1_CTRL GENMASK(11, 8)
119 #define DP83822_LEDCFG1_LED3_CTRL GENMASK(7, 4)
120
121 /* IOCTRL1 bits */
122 #define DP83822_IOCTRL1_GPIO3_CTRL GENMASK(10, 8)
123 #define DP83822_IOCTRL1_GPIO3_CTRL_LED3 BIT(0)
124 #define DP83822_IOCTRL1_GPIO1_CTRL GENMASK(2, 0)
125 #define DP83822_IOCTRL1_GPIO1_CTRL_LED_1 BIT(0)
126
127 /* LDCTRL bits */
128 #define DP83822_100BASE_TX_LINE_DRIVER_SWING GENMASK(7, 4)
129
130 /* IOCTRL2 bits */
131 #define DP83822_IOCTRL2_GPIO2_CLK_SRC GENMASK(6, 4)
132 #define DP83822_IOCTRL2_GPIO2_CTRL GENMASK(2, 0)
133 #define DP83822_IOCTRL2_GPIO2_CTRL_CLK_REF GENMASK(1, 0)
134 #define DP83822_IOCTRL2_GPIO2_CTRL_MLED BIT(0)
135
136 #define DP83822_CLK_SRC_MAC_IF 0x0
137 #define DP83822_CLK_SRC_XI 0x1
138 #define DP83822_CLK_SRC_INT_REF 0x2
139 #define DP83822_CLK_SRC_RMII_MASTER_MODE_REF 0x4
140 #define DP83822_CLK_SRC_FREE_RUNNING 0x6
141 #define DP83822_CLK_SRC_RECOVERED 0x7
142
143 #define DP83822_LED_FN_LINK 0x0 /* Link established */
144 #define DP83822_LED_FN_RX_TX 0x1 /* Receive or Transmit activity */
145 #define DP83822_LED_FN_TX 0x2 /* Transmit activity */
146 #define DP83822_LED_FN_RX 0x3 /* Receive activity */
147 #define DP83822_LED_FN_COLLISION 0x4 /* Collision detected */
148 #define DP83822_LED_FN_LINK_100_BTX 0x5 /* 100 BTX link established */
149 #define DP83822_LED_FN_LINK_10_BT 0x6 /* 10BT link established */
150 #define DP83822_LED_FN_FULL_DUPLEX 0x7 /* Full duplex */
151 #define DP83822_LED_FN_LINK_RX_TX 0x8 /* Link established, blink for rx or tx activity */
152 #define DP83822_LED_FN_ACTIVE_STRETCH 0x9 /* Active Stretch Signal */
153 #define DP83822_LED_FN_MII_LINK 0xa /* MII LINK (100BT+FD) */
154 #define DP83822_LED_FN_LPI_MODE 0xb /* LPI Mode (EEE) */
155 #define DP83822_LED_FN_RX_TX_ERR 0xc /* TX/RX MII Error */
156 #define DP83822_LED_FN_LINK_LOST 0xd /* Link Lost */
157 #define DP83822_LED_FN_PRBS_ERR 0xe /* Blink for PRBS error */
158
159 /* SOR1 mode */
160 #define DP83822_STRAP_MODE1 0
161 #define DP83822_STRAP_MODE2 BIT(0)
162 #define DP83822_STRAP_MODE3 BIT(1)
163 #define DP83822_STRAP_MODE4 GENMASK(1, 0)
164
165 #define DP83822_COL_STRAP_MASK GENMASK(11, 10)
166 #define DP83822_COL_SHIFT 10
167 #define DP83822_RX_ER_STR_MASK GENMASK(9, 8)
168 #define DP83822_RX_ER_SHIFT 8
169
170 /* DP83826: VOD_CFG1 & VOD_CFG2 */
171 #define DP83826_VOD_CFG1_MINUS_MDIX_MASK GENMASK(13, 12)
172 #define DP83826_VOD_CFG1_MINUS_MDI_MASK GENMASK(11, 6)
173 #define DP83826_VOD_CFG2_MINUS_MDIX_MASK GENMASK(15, 12)
174 #define DP83826_VOD_CFG2_PLUS_MDIX_MASK GENMASK(11, 6)
175 #define DP83826_VOD_CFG2_PLUS_MDI_MASK GENMASK(5, 0)
176 #define DP83826_CFG_DAC_MINUS_MDIX_5_TO_4 GENMASK(5, 4)
177 #define DP83826_CFG_DAC_MINUS_MDIX_3_TO_0 GENMASK(3, 0)
178 #define DP83826_CFG_DAC_PERCENT_PER_STEP 625
179 #define DP83826_CFG_DAC_PERCENT_DEFAULT 10000
180 #define DP83826_CFG_DAC_MINUS_DEFAULT 0x30
181 #define DP83826_CFG_DAC_PLUS_DEFAULT 0x10
182
183 #define MII_DP83822_FIBER_ADVERTISE (ADVERTISED_TP | ADVERTISED_MII | \
184 ADVERTISED_FIBRE | \
185 ADVERTISED_Pause | ADVERTISED_Asym_Pause)
186
187 #define DP83822_MAX_LED_PINS 4
188
189 #define DP83822_LED_INDEX_LED_0 0
190 #define DP83822_LED_INDEX_LED_1_GPIO1 1
191 #define DP83822_LED_INDEX_COL_GPIO2 2
192 #define DP83822_LED_INDEX_RX_D3_GPIO3 3
193
194 struct dp83822_private {
195 bool fx_signal_det_low;
196 int fx_enabled;
197 u16 fx_sd_enable;
198 u8 cfg_dac_minus;
199 u8 cfg_dac_plus;
200 struct ethtool_wolinfo wol;
201 bool set_gpio2_clk_out;
202 u32 gpio2_clk_out;
203 bool led_pin_enable[DP83822_MAX_LED_PINS];
204 int tx_amplitude_100base_tx_index;
205 };
206
dp83822_config_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)207 static int dp83822_config_wol(struct phy_device *phydev,
208 struct ethtool_wolinfo *wol)
209 {
210 struct net_device *ndev = phydev->attached_dev;
211 u16 value;
212 const u8 *mac;
213
214 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) {
215 mac = (const u8 *)ndev->dev_addr;
216
217 if (!is_valid_ether_addr(mac))
218 return -EINVAL;
219
220 /* MAC addresses start with byte 5, but stored in mac[0].
221 * 822 PHYs store bytes 4|5, 2|3, 0|1
222 */
223 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA1,
224 (mac[1] << 8) | mac[0]);
225 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA2,
226 (mac[3] << 8) | mac[2]);
227 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA3,
228 (mac[5] << 8) | mac[4]);
229
230 value = phy_read_mmd(phydev, MDIO_MMD_VEND2,
231 MII_DP83822_WOL_CFG);
232 if (wol->wolopts & WAKE_MAGIC)
233 value |= DP83822_WOL_MAGIC_EN;
234 else
235 value &= ~DP83822_WOL_MAGIC_EN;
236
237 if (wol->wolopts & WAKE_MAGICSECURE) {
238 phy_write_mmd(phydev, MDIO_MMD_VEND2,
239 MII_DP83822_RXSOP1,
240 (wol->sopass[1] << 8) | wol->sopass[0]);
241 phy_write_mmd(phydev, MDIO_MMD_VEND2,
242 MII_DP83822_RXSOP2,
243 (wol->sopass[3] << 8) | wol->sopass[2]);
244 phy_write_mmd(phydev, MDIO_MMD_VEND2,
245 MII_DP83822_RXSOP3,
246 (wol->sopass[5] << 8) | wol->sopass[4]);
247 value |= DP83822_WOL_SECURE_ON;
248 } else {
249 value &= ~DP83822_WOL_SECURE_ON;
250 }
251
252 /* Clear any pending WoL interrupt */
253 phy_read(phydev, MII_DP83822_MISR2);
254
255 value |= DP83822_WOL_EN | DP83822_WOL_INDICATION_SEL |
256 DP83822_WOL_CLR_INDICATION;
257
258 return phy_write_mmd(phydev, MDIO_MMD_VEND2,
259 MII_DP83822_WOL_CFG, value);
260 } else {
261 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
262 MII_DP83822_WOL_CFG,
263 DP83822_WOL_EN |
264 DP83822_WOL_MAGIC_EN |
265 DP83822_WOL_SECURE_ON);
266 }
267 }
268
dp83822_set_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)269 static int dp83822_set_wol(struct phy_device *phydev,
270 struct ethtool_wolinfo *wol)
271 {
272 struct dp83822_private *dp83822 = phydev->priv;
273 int ret;
274
275 ret = dp83822_config_wol(phydev, wol);
276 if (!ret)
277 memcpy(&dp83822->wol, wol, sizeof(*wol));
278 return ret;
279 }
280
dp83822_get_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)281 static void dp83822_get_wol(struct phy_device *phydev,
282 struct ethtool_wolinfo *wol)
283 {
284 int value;
285 u16 sopass_val;
286
287 wol->supported = (WAKE_MAGIC | WAKE_MAGICSECURE);
288 wol->wolopts = 0;
289
290 value = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG);
291
292 if (value & DP83822_WOL_MAGIC_EN)
293 wol->wolopts |= WAKE_MAGIC;
294
295 if (value & DP83822_WOL_SECURE_ON) {
296 sopass_val = phy_read_mmd(phydev, MDIO_MMD_VEND2,
297 MII_DP83822_RXSOP1);
298 wol->sopass[0] = (sopass_val & 0xff);
299 wol->sopass[1] = (sopass_val >> 8);
300
301 sopass_val = phy_read_mmd(phydev, MDIO_MMD_VEND2,
302 MII_DP83822_RXSOP2);
303 wol->sopass[2] = (sopass_val & 0xff);
304 wol->sopass[3] = (sopass_val >> 8);
305
306 sopass_val = phy_read_mmd(phydev, MDIO_MMD_VEND2,
307 MII_DP83822_RXSOP3);
308 wol->sopass[4] = (sopass_val & 0xff);
309 wol->sopass[5] = (sopass_val >> 8);
310
311 wol->wolopts |= WAKE_MAGICSECURE;
312 }
313
314 /* WoL is not enabled so set wolopts to 0 */
315 if (!(value & DP83822_WOL_EN))
316 wol->wolopts = 0;
317 }
318
dp83822_config_intr(struct phy_device * phydev)319 static int dp83822_config_intr(struct phy_device *phydev)
320 {
321 struct dp83822_private *dp83822 = phydev->priv;
322 int misr_status;
323 int physcr_status;
324 int err;
325
326 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
327 misr_status = phy_read(phydev, MII_DP83822_MISR1);
328 if (misr_status < 0)
329 return misr_status;
330
331 misr_status |= (DP83822_LINK_STAT_INT_EN |
332 DP83822_ENERGY_DET_INT_EN |
333 DP83822_LINK_QUAL_INT_EN);
334
335 if (!dp83822->fx_enabled)
336 misr_status |= DP83822_ANEG_COMPLETE_INT_EN |
337 DP83822_DUP_MODE_CHANGE_INT_EN |
338 DP83822_SPEED_CHANGED_INT_EN;
339
340
341 err = phy_write(phydev, MII_DP83822_MISR1, misr_status);
342 if (err < 0)
343 return err;
344
345 misr_status = phy_read(phydev, MII_DP83822_MISR2);
346 if (misr_status < 0)
347 return misr_status;
348
349 misr_status |= (DP83822_JABBER_DET_INT_EN |
350 DP83822_SLEEP_MODE_INT_EN |
351 DP83822_LB_FIFO_INT_EN |
352 DP83822_PAGE_RX_INT_EN |
353 DP83822_EEE_ERROR_CHANGE_INT_EN);
354
355 if (!dp83822->fx_enabled)
356 misr_status |= DP83822_ANEG_ERR_INT_EN |
357 DP83822_WOL_PKT_INT_EN;
358
359 err = phy_write(phydev, MII_DP83822_MISR2, misr_status);
360 if (err < 0)
361 return err;
362
363 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR);
364 if (physcr_status < 0)
365 return physcr_status;
366
367 physcr_status |= DP83822_PHYSCR_INT_OE | DP83822_PHYSCR_INTEN;
368
369 } else {
370 err = phy_write(phydev, MII_DP83822_MISR1, 0);
371 if (err < 0)
372 return err;
373
374 err = phy_write(phydev, MII_DP83822_MISR2, 0);
375 if (err < 0)
376 return err;
377
378 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR);
379 if (physcr_status < 0)
380 return physcr_status;
381
382 physcr_status &= ~DP83822_PHYSCR_INTEN;
383 }
384
385 return phy_write(phydev, MII_DP83822_PHYSCR, physcr_status);
386 }
387
dp83822_handle_interrupt(struct phy_device * phydev)388 static irqreturn_t dp83822_handle_interrupt(struct phy_device *phydev)
389 {
390 bool trigger_machine = false;
391 int irq_status;
392
393 /* The MISR1 and MISR2 registers are holding the interrupt status in
394 * the upper half (15:8), while the lower half (7:0) is used for
395 * controlling the interrupt enable state of those individual interrupt
396 * sources. To determine the possible interrupt sources, just read the
397 * MISR* register and use it directly to know which interrupts have
398 * been enabled previously or not.
399 */
400 irq_status = phy_read(phydev, MII_DP83822_MISR1);
401 if (irq_status < 0) {
402 phy_error(phydev);
403 return IRQ_NONE;
404 }
405 if (irq_status & ((irq_status & GENMASK(7, 0)) << 8))
406 trigger_machine = true;
407
408 irq_status = phy_read(phydev, MII_DP83822_MISR2);
409 if (irq_status < 0) {
410 phy_error(phydev);
411 return IRQ_NONE;
412 }
413 if (irq_status & ((irq_status & GENMASK(7, 0)) << 8))
414 trigger_machine = true;
415
416 if (!trigger_machine)
417 return IRQ_NONE;
418
419 phy_trigger_machine(phydev);
420
421 return IRQ_HANDLED;
422 }
423
dp83822_read_status(struct phy_device * phydev)424 static int dp83822_read_status(struct phy_device *phydev)
425 {
426 struct dp83822_private *dp83822 = phydev->priv;
427 int status = phy_read(phydev, MII_DP83822_PHYSTS);
428 int ctrl2;
429 int ret;
430
431 if (dp83822->fx_enabled) {
432 if (status & DP83822_PHYSTS_LINK) {
433 phydev->speed = SPEED_UNKNOWN;
434 phydev->duplex = DUPLEX_UNKNOWN;
435 } else {
436 ctrl2 = phy_read(phydev, MII_DP83822_CTRL_2);
437 if (ctrl2 < 0)
438 return ctrl2;
439
440 if (!(ctrl2 & DP83822_FX_ENABLE)) {
441 ret = phy_write(phydev, MII_DP83822_CTRL_2,
442 DP83822_FX_ENABLE | ctrl2);
443 if (ret < 0)
444 return ret;
445 }
446 }
447 }
448
449 ret = genphy_read_status(phydev);
450 if (ret)
451 return ret;
452
453 if (status < 0)
454 return status;
455
456 if (status & DP83822_PHYSTS_DUPLEX)
457 phydev->duplex = DUPLEX_FULL;
458 else
459 phydev->duplex = DUPLEX_HALF;
460
461 if (status & DP83822_PHYSTS_10)
462 phydev->speed = SPEED_10;
463 else
464 phydev->speed = SPEED_100;
465
466 return 0;
467 }
468
dp83822_config_init_leds(struct phy_device * phydev)469 static int dp83822_config_init_leds(struct phy_device *phydev)
470 {
471 struct dp83822_private *dp83822 = phydev->priv;
472 int ret;
473
474 if (dp83822->led_pin_enable[DP83822_LED_INDEX_LED_0]) {
475 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_MLEDCR,
476 DP83822_MLEDCR_ROUTE,
477 FIELD_PREP(DP83822_MLEDCR_ROUTE,
478 DP83822_MLEDCR_ROUTE_LED_0));
479 if (ret)
480 return ret;
481 } else if (dp83822->led_pin_enable[DP83822_LED_INDEX_COL_GPIO2]) {
482 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL2,
483 DP83822_IOCTRL2_GPIO2_CTRL,
484 FIELD_PREP(DP83822_IOCTRL2_GPIO2_CTRL,
485 DP83822_IOCTRL2_GPIO2_CTRL_MLED));
486 if (ret)
487 return ret;
488 }
489
490 if (dp83822->led_pin_enable[DP83822_LED_INDEX_LED_1_GPIO1]) {
491 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL1,
492 DP83822_IOCTRL1_GPIO1_CTRL,
493 FIELD_PREP(DP83822_IOCTRL1_GPIO1_CTRL,
494 DP83822_IOCTRL1_GPIO1_CTRL_LED_1));
495 if (ret)
496 return ret;
497 }
498
499 if (dp83822->led_pin_enable[DP83822_LED_INDEX_RX_D3_GPIO3]) {
500 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL1,
501 DP83822_IOCTRL1_GPIO3_CTRL,
502 FIELD_PREP(DP83822_IOCTRL1_GPIO3_CTRL,
503 DP83822_IOCTRL1_GPIO3_CTRL_LED3));
504 if (ret)
505 return ret;
506 }
507
508 return 0;
509 }
510
dp83822_config_init(struct phy_device * phydev)511 static int dp83822_config_init(struct phy_device *phydev)
512 {
513 struct dp83822_private *dp83822 = phydev->priv;
514 struct device *dev = &phydev->mdio.dev;
515 int rgmii_delay = 0;
516 s32 rx_int_delay;
517 s32 tx_int_delay;
518 int err = 0;
519 int bmcr;
520
521 if (dp83822->set_gpio2_clk_out)
522 phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL2,
523 DP83822_IOCTRL2_GPIO2_CTRL |
524 DP83822_IOCTRL2_GPIO2_CLK_SRC,
525 FIELD_PREP(DP83822_IOCTRL2_GPIO2_CTRL,
526 DP83822_IOCTRL2_GPIO2_CTRL_CLK_REF) |
527 FIELD_PREP(DP83822_IOCTRL2_GPIO2_CLK_SRC,
528 dp83822->gpio2_clk_out));
529
530 if (dp83822->tx_amplitude_100base_tx_index >= 0)
531 phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_LDCTRL,
532 DP83822_100BASE_TX_LINE_DRIVER_SWING,
533 FIELD_PREP(DP83822_100BASE_TX_LINE_DRIVER_SWING,
534 dp83822->tx_amplitude_100base_tx_index));
535
536 err = dp83822_config_init_leds(phydev);
537 if (err)
538 return err;
539
540 if (phy_interface_is_rgmii(phydev)) {
541 rx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0,
542 true);
543
544 /* Set DP83822_RX_CLK_SHIFT to enable rx clk internal delay */
545 if (rx_int_delay > 0)
546 rgmii_delay |= DP83822_RX_CLK_SHIFT;
547
548 tx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0,
549 false);
550
551 /* Set DP83822_TX_CLK_SHIFT to disable tx clk internal delay */
552 if (tx_int_delay <= 0)
553 rgmii_delay |= DP83822_TX_CLK_SHIFT;
554
555 err = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR,
556 DP83822_RX_CLK_SHIFT | DP83822_TX_CLK_SHIFT, rgmii_delay);
557 if (err)
558 return err;
559
560 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
561 MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);
562
563 if (err)
564 return err;
565 } else {
566 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
567 MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);
568
569 if (err)
570 return err;
571 }
572
573 if (dp83822->fx_enabled) {
574 err = phy_modify(phydev, MII_DP83822_CTRL_2,
575 DP83822_FX_ENABLE, 1);
576 if (err < 0)
577 return err;
578
579 /* Only allow advertising what this PHY supports */
580 linkmode_and(phydev->advertising, phydev->advertising,
581 phydev->supported);
582
583 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
584 phydev->supported);
585 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
586 phydev->advertising);
587 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
588 phydev->supported);
589 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
590 phydev->supported);
591 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
592 phydev->advertising);
593 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
594 phydev->advertising);
595
596 /* Auto neg is not supported in fiber mode */
597 bmcr = phy_read(phydev, MII_BMCR);
598 if (bmcr < 0)
599 return bmcr;
600
601 if (bmcr & BMCR_ANENABLE) {
602 err = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
603 if (err < 0)
604 return err;
605 }
606 phydev->autoneg = AUTONEG_DISABLE;
607 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
608 phydev->supported);
609 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
610 phydev->advertising);
611
612 /* Setup fiber advertisement */
613 err = phy_modify_changed(phydev, MII_ADVERTISE,
614 MII_DP83822_FIBER_ADVERTISE,
615 MII_DP83822_FIBER_ADVERTISE);
616
617 if (err < 0)
618 return err;
619
620 if (dp83822->fx_signal_det_low) {
621 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
622 MII_DP83822_GENCFG,
623 DP83822_SIG_DET_LOW);
624 if (err)
625 return err;
626 }
627 }
628 return dp83822_config_wol(phydev, &dp83822->wol);
629 }
630
dp8382x_config_rmii_mode(struct phy_device * phydev)631 static int dp8382x_config_rmii_mode(struct phy_device *phydev)
632 {
633 struct device *dev = &phydev->mdio.dev;
634 const char *of_val;
635 int ret;
636
637 if (!device_property_read_string(dev, "ti,rmii-mode", &of_val)) {
638 if (strcmp(of_val, "master") == 0) {
639 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR,
640 DP83822_RMII_MODE_SEL);
641 } else if (strcmp(of_val, "slave") == 0) {
642 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR,
643 DP83822_RMII_MODE_SEL);
644 } else {
645 phydev_err(phydev, "Invalid value for ti,rmii-mode property (%s)\n",
646 of_val);
647 ret = -EINVAL;
648 }
649
650 if (ret)
651 return ret;
652 }
653
654 return 0;
655 }
656
dp83826_config_init(struct phy_device * phydev)657 static int dp83826_config_init(struct phy_device *phydev)
658 {
659 struct dp83822_private *dp83822 = phydev->priv;
660 u16 val, mask;
661 int ret;
662
663 if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
664 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR,
665 DP83822_RMII_MODE_EN);
666 if (ret)
667 return ret;
668
669 ret = dp8382x_config_rmii_mode(phydev);
670 if (ret)
671 return ret;
672 } else {
673 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR,
674 DP83822_RMII_MODE_EN);
675 if (ret)
676 return ret;
677 }
678
679 if (dp83822->cfg_dac_minus != DP83826_CFG_DAC_MINUS_DEFAULT) {
680 val = FIELD_PREP(DP83826_VOD_CFG1_MINUS_MDI_MASK, dp83822->cfg_dac_minus) |
681 FIELD_PREP(DP83826_VOD_CFG1_MINUS_MDIX_MASK,
682 FIELD_GET(DP83826_CFG_DAC_MINUS_MDIX_5_TO_4,
683 dp83822->cfg_dac_minus));
684 mask = DP83826_VOD_CFG1_MINUS_MDIX_MASK | DP83826_VOD_CFG1_MINUS_MDI_MASK;
685 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83826_VOD_CFG1, mask, val);
686 if (ret)
687 return ret;
688
689 val = FIELD_PREP(DP83826_VOD_CFG2_MINUS_MDIX_MASK,
690 FIELD_GET(DP83826_CFG_DAC_MINUS_MDIX_3_TO_0,
691 dp83822->cfg_dac_minus));
692 mask = DP83826_VOD_CFG2_MINUS_MDIX_MASK;
693 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83826_VOD_CFG2, mask, val);
694 if (ret)
695 return ret;
696 }
697
698 if (dp83822->cfg_dac_plus != DP83826_CFG_DAC_PLUS_DEFAULT) {
699 val = FIELD_PREP(DP83826_VOD_CFG2_PLUS_MDIX_MASK, dp83822->cfg_dac_plus) |
700 FIELD_PREP(DP83826_VOD_CFG2_PLUS_MDI_MASK, dp83822->cfg_dac_plus);
701 mask = DP83826_VOD_CFG2_PLUS_MDIX_MASK | DP83826_VOD_CFG2_PLUS_MDI_MASK;
702 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83826_VOD_CFG2, mask, val);
703 if (ret)
704 return ret;
705 }
706
707 return dp83822_config_wol(phydev, &dp83822->wol);
708 }
709
dp83825_config_init(struct phy_device * phydev)710 static int dp83825_config_init(struct phy_device *phydev)
711 {
712 struct dp83822_private *dp83822 = phydev->priv;
713 int ret;
714
715 ret = dp8382x_config_rmii_mode(phydev);
716 if (ret)
717 return ret;
718
719 return dp83822_config_wol(phydev, &dp83822->wol);
720 }
721
dp83822_phy_reset(struct phy_device * phydev)722 static int dp83822_phy_reset(struct phy_device *phydev)
723 {
724 int err;
725
726 err = phy_write(phydev, MII_DP83822_RESET_CTRL, DP83822_SW_RESET);
727 if (err < 0)
728 return err;
729
730 return phydev->drv->config_init(phydev);
731 }
732
733 #ifdef CONFIG_OF_MDIO
734 static const u32 tx_amplitude_100base_tx_gain[] = {
735 80, 82, 83, 85, 87, 88, 90, 92,
736 93, 95, 97, 98, 100, 102, 103, 105,
737 };
738
dp83822_of_init_leds(struct phy_device * phydev)739 static int dp83822_of_init_leds(struct phy_device *phydev)
740 {
741 struct device_node *node = phydev->mdio.dev.of_node;
742 struct dp83822_private *dp83822 = phydev->priv;
743 struct device_node *leds;
744 u32 index;
745 int err;
746
747 if (!node)
748 return 0;
749
750 leds = of_get_child_by_name(node, "leds");
751 if (!leds)
752 return 0;
753
754 for_each_available_child_of_node_scoped(leds, led) {
755 err = of_property_read_u32(led, "reg", &index);
756 if (err) {
757 of_node_put(leds);
758 return err;
759 }
760
761 if (index <= DP83822_LED_INDEX_RX_D3_GPIO3) {
762 dp83822->led_pin_enable[index] = true;
763 } else {
764 of_node_put(leds);
765 return -EINVAL;
766 }
767 }
768
769 of_node_put(leds);
770 /* LED_0 and COL(GPIO2) use the MLED function. MLED can be routed to
771 * only one of these two pins at a time.
772 */
773 if (dp83822->led_pin_enable[DP83822_LED_INDEX_LED_0] &&
774 dp83822->led_pin_enable[DP83822_LED_INDEX_COL_GPIO2]) {
775 phydev_err(phydev, "LED_0 and COL(GPIO2) cannot be used as LED output at the same time\n");
776 return -EINVAL;
777 }
778
779 if (dp83822->led_pin_enable[DP83822_LED_INDEX_COL_GPIO2] &&
780 dp83822->set_gpio2_clk_out) {
781 phydev_err(phydev, "COL(GPIO2) cannot be used as LED output, already used as clock output\n");
782 return -EINVAL;
783 }
784
785 if (dp83822->led_pin_enable[DP83822_LED_INDEX_RX_D3_GPIO3] &&
786 phydev->interface != PHY_INTERFACE_MODE_RMII) {
787 phydev_err(phydev, "RX_D3 can only be used as LED output when in RMII mode\n");
788 return -EINVAL;
789 }
790
791 return 0;
792 }
793
dp83822_of_init(struct phy_device * phydev)794 static int dp83822_of_init(struct phy_device *phydev)
795 {
796 struct dp83822_private *dp83822 = phydev->priv;
797 struct device *dev = &phydev->mdio.dev;
798 const char *of_val;
799 int i, ret;
800 u32 val;
801
802 /* Signal detection for the PHY is only enabled if the FX_EN and the
803 * SD_EN pins are strapped. Signal detection can only enabled if FX_EN
804 * is strapped otherwise signal detection is disabled for the PHY.
805 */
806 if (dp83822->fx_enabled && dp83822->fx_sd_enable)
807 dp83822->fx_signal_det_low = device_property_present(dev,
808 "ti,link-loss-low");
809 if (!dp83822->fx_enabled)
810 dp83822->fx_enabled = device_property_present(dev,
811 "ti,fiber-mode");
812
813 if (!device_property_read_string(dev, "ti,gpio2-clk-out", &of_val)) {
814 if (strcmp(of_val, "mac-if") == 0) {
815 dp83822->gpio2_clk_out = DP83822_CLK_SRC_MAC_IF;
816 } else if (strcmp(of_val, "xi") == 0) {
817 dp83822->gpio2_clk_out = DP83822_CLK_SRC_XI;
818 } else if (strcmp(of_val, "int-ref") == 0) {
819 dp83822->gpio2_clk_out = DP83822_CLK_SRC_INT_REF;
820 } else if (strcmp(of_val, "rmii-master-mode-ref") == 0) {
821 dp83822->gpio2_clk_out = DP83822_CLK_SRC_RMII_MASTER_MODE_REF;
822 } else if (strcmp(of_val, "free-running") == 0) {
823 dp83822->gpio2_clk_out = DP83822_CLK_SRC_FREE_RUNNING;
824 } else if (strcmp(of_val, "recovered") == 0) {
825 dp83822->gpio2_clk_out = DP83822_CLK_SRC_RECOVERED;
826 } else {
827 phydev_err(phydev,
828 "Invalid value for ti,gpio2-clk-out property (%s)\n",
829 of_val);
830 return -EINVAL;
831 }
832
833 dp83822->set_gpio2_clk_out = true;
834 }
835
836 ret = phy_get_tx_amplitude_gain(phydev, dev,
837 ETHTOOL_LINK_MODE_100baseT_Full_BIT,
838 &val);
839 if (!ret) {
840 for (i = 0; i < ARRAY_SIZE(tx_amplitude_100base_tx_gain); i++) {
841 if (tx_amplitude_100base_tx_gain[i] == val) {
842 dp83822->tx_amplitude_100base_tx_index = i;
843 break;
844 }
845 }
846
847 if (dp83822->tx_amplitude_100base_tx_index < 0) {
848 phydev_err(phydev,
849 "Invalid value for tx-amplitude-100base-tx-percent property (%u)\n",
850 val);
851 return -EINVAL;
852 }
853 }
854
855 return dp83822_of_init_leds(phydev);
856 }
857
dp83826_to_dac_minus_one_regval(int percent)858 static int dp83826_to_dac_minus_one_regval(int percent)
859 {
860 int tmp = DP83826_CFG_DAC_PERCENT_DEFAULT - percent;
861
862 return tmp / DP83826_CFG_DAC_PERCENT_PER_STEP;
863 }
864
dp83826_to_dac_plus_one_regval(int percent)865 static int dp83826_to_dac_plus_one_regval(int percent)
866 {
867 int tmp = percent - DP83826_CFG_DAC_PERCENT_DEFAULT;
868
869 return tmp / DP83826_CFG_DAC_PERCENT_PER_STEP;
870 }
871
dp83826_of_init(struct phy_device * phydev)872 static void dp83826_of_init(struct phy_device *phydev)
873 {
874 struct dp83822_private *dp83822 = phydev->priv;
875 struct device *dev = &phydev->mdio.dev;
876 u32 val;
877
878 dp83822->cfg_dac_minus = DP83826_CFG_DAC_MINUS_DEFAULT;
879 if (!device_property_read_u32(dev, "ti,cfg-dac-minus-one-bp", &val))
880 dp83822->cfg_dac_minus += dp83826_to_dac_minus_one_regval(val);
881
882 dp83822->cfg_dac_plus = DP83826_CFG_DAC_PLUS_DEFAULT;
883 if (!device_property_read_u32(dev, "ti,cfg-dac-plus-one-bp", &val))
884 dp83822->cfg_dac_plus += dp83826_to_dac_plus_one_regval(val);
885 }
886 #else
dp83822_of_init(struct phy_device * phydev)887 static int dp83822_of_init(struct phy_device *phydev)
888 {
889 return 0;
890 }
891
dp83826_of_init(struct phy_device * phydev)892 static void dp83826_of_init(struct phy_device *phydev)
893 {
894 }
895 #endif /* CONFIG_OF_MDIO */
896
dp83822_read_straps(struct phy_device * phydev)897 static int dp83822_read_straps(struct phy_device *phydev)
898 {
899 struct dp83822_private *dp83822 = phydev->priv;
900 int fx_enabled, fx_sd_enable;
901 int val;
902
903 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_SOR1);
904 if (val < 0)
905 return val;
906
907 phydev_dbg(phydev, "SOR1 strap register: 0x%04x\n", val);
908
909 fx_enabled = (val & DP83822_COL_STRAP_MASK) >> DP83822_COL_SHIFT;
910 if (fx_enabled == DP83822_STRAP_MODE2 ||
911 fx_enabled == DP83822_STRAP_MODE3)
912 dp83822->fx_enabled = 1;
913
914 if (dp83822->fx_enabled) {
915 fx_sd_enable = (val & DP83822_RX_ER_STR_MASK) >> DP83822_RX_ER_SHIFT;
916 if (fx_sd_enable == DP83822_STRAP_MODE3 ||
917 fx_sd_enable == DP83822_STRAP_MODE4)
918 dp83822->fx_sd_enable = 1;
919 }
920
921 return 0;
922 }
923
dp8382x_probe(struct phy_device * phydev)924 static int dp8382x_probe(struct phy_device *phydev)
925 {
926 struct dp83822_private *dp83822;
927
928 dp83822 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83822),
929 GFP_KERNEL);
930 if (!dp83822)
931 return -ENOMEM;
932
933 dp83822->tx_amplitude_100base_tx_index = -1;
934 phydev->priv = dp83822;
935
936 return 0;
937 }
938
dp83822_probe(struct phy_device * phydev)939 static int dp83822_probe(struct phy_device *phydev)
940 {
941 struct dp83822_private *dp83822;
942 int ret;
943
944 ret = dp8382x_probe(phydev);
945 if (ret)
946 return ret;
947
948 dp83822 = phydev->priv;
949
950 ret = dp83822_read_straps(phydev);
951 if (ret)
952 return ret;
953
954 ret = dp83822_of_init(phydev);
955 if (ret)
956 return ret;
957
958 if (dp83822->fx_enabled)
959 phydev->port = PORT_FIBRE;
960
961 return 0;
962 }
963
dp83826_probe(struct phy_device * phydev)964 static int dp83826_probe(struct phy_device *phydev)
965 {
966 int ret;
967
968 ret = dp8382x_probe(phydev);
969 if (ret)
970 return ret;
971
972 dp83826_of_init(phydev);
973
974 return 0;
975 }
976
dp83822_suspend(struct phy_device * phydev)977 static int dp83822_suspend(struct phy_device *phydev)
978 {
979 int value;
980
981 value = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG);
982
983 if (!(value & DP83822_WOL_EN))
984 genphy_suspend(phydev);
985
986 return 0;
987 }
988
dp83822_resume(struct phy_device * phydev)989 static int dp83822_resume(struct phy_device *phydev)
990 {
991 int value;
992
993 genphy_resume(phydev);
994
995 value = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG);
996
997 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG, value |
998 DP83822_WOL_CLR_INDICATION);
999
1000 return 0;
1001 }
1002
dp83822_led_mode(u8 index,unsigned long rules)1003 static int dp83822_led_mode(u8 index, unsigned long rules)
1004 {
1005 switch (rules) {
1006 case BIT(TRIGGER_NETDEV_LINK):
1007 return DP83822_LED_FN_LINK;
1008 case BIT(TRIGGER_NETDEV_LINK_10):
1009 return DP83822_LED_FN_LINK_10_BT;
1010 case BIT(TRIGGER_NETDEV_LINK_100):
1011 return DP83822_LED_FN_LINK_100_BTX;
1012 case BIT(TRIGGER_NETDEV_FULL_DUPLEX):
1013 return DP83822_LED_FN_FULL_DUPLEX;
1014 case BIT(TRIGGER_NETDEV_TX):
1015 return DP83822_LED_FN_TX;
1016 case BIT(TRIGGER_NETDEV_RX):
1017 return DP83822_LED_FN_RX;
1018 case BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX):
1019 return DP83822_LED_FN_RX_TX;
1020 case BIT(TRIGGER_NETDEV_TX_ERR) | BIT(TRIGGER_NETDEV_RX_ERR):
1021 return DP83822_LED_FN_RX_TX_ERR;
1022 case BIT(TRIGGER_NETDEV_LINK) | BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX):
1023 return DP83822_LED_FN_LINK_RX_TX;
1024 default:
1025 return -EOPNOTSUPP;
1026 }
1027 }
1028
dp83822_led_hw_is_supported(struct phy_device * phydev,u8 index,unsigned long rules)1029 static int dp83822_led_hw_is_supported(struct phy_device *phydev, u8 index,
1030 unsigned long rules)
1031 {
1032 int mode;
1033
1034 mode = dp83822_led_mode(index, rules);
1035 if (mode < 0)
1036 return mode;
1037
1038 return 0;
1039 }
1040
dp83822_led_hw_control_set(struct phy_device * phydev,u8 index,unsigned long rules)1041 static int dp83822_led_hw_control_set(struct phy_device *phydev, u8 index,
1042 unsigned long rules)
1043 {
1044 int mode;
1045
1046 mode = dp83822_led_mode(index, rules);
1047 if (mode < 0)
1048 return mode;
1049
1050 if (index == DP83822_LED_INDEX_LED_0 || index == DP83822_LED_INDEX_COL_GPIO2)
1051 return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
1052 MII_DP83822_MLEDCR, DP83822_MLEDCR_CFG,
1053 FIELD_PREP(DP83822_MLEDCR_CFG, mode));
1054 else if (index == DP83822_LED_INDEX_LED_1_GPIO1)
1055 return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
1056 MII_DP83822_LEDCFG1,
1057 DP83822_LEDCFG1_LED1_CTRL,
1058 FIELD_PREP(DP83822_LEDCFG1_LED1_CTRL,
1059 mode));
1060 else
1061 return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
1062 MII_DP83822_LEDCFG1,
1063 DP83822_LEDCFG1_LED3_CTRL,
1064 FIELD_PREP(DP83822_LEDCFG1_LED3_CTRL,
1065 mode));
1066 }
1067
dp83822_led_hw_control_get(struct phy_device * phydev,u8 index,unsigned long * rules)1068 static int dp83822_led_hw_control_get(struct phy_device *phydev, u8 index,
1069 unsigned long *rules)
1070 {
1071 int val;
1072
1073 if (index == DP83822_LED_INDEX_LED_0 || index == DP83822_LED_INDEX_COL_GPIO2) {
1074 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_MLEDCR);
1075 if (val < 0)
1076 return val;
1077
1078 val = FIELD_GET(DP83822_MLEDCR_CFG, val);
1079 } else {
1080 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_LEDCFG1);
1081 if (val < 0)
1082 return val;
1083
1084 if (index == DP83822_LED_INDEX_LED_1_GPIO1)
1085 val = FIELD_GET(DP83822_LEDCFG1_LED1_CTRL, val);
1086 else
1087 val = FIELD_GET(DP83822_LEDCFG1_LED3_CTRL, val);
1088 }
1089
1090 switch (val) {
1091 case DP83822_LED_FN_LINK:
1092 *rules = BIT(TRIGGER_NETDEV_LINK);
1093 break;
1094 case DP83822_LED_FN_LINK_10_BT:
1095 *rules = BIT(TRIGGER_NETDEV_LINK_10);
1096 break;
1097 case DP83822_LED_FN_LINK_100_BTX:
1098 *rules = BIT(TRIGGER_NETDEV_LINK_100);
1099 break;
1100 case DP83822_LED_FN_FULL_DUPLEX:
1101 *rules = BIT(TRIGGER_NETDEV_FULL_DUPLEX);
1102 break;
1103 case DP83822_LED_FN_TX:
1104 *rules = BIT(TRIGGER_NETDEV_TX);
1105 break;
1106 case DP83822_LED_FN_RX:
1107 *rules = BIT(TRIGGER_NETDEV_RX);
1108 break;
1109 case DP83822_LED_FN_RX_TX:
1110 *rules = BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX);
1111 break;
1112 case DP83822_LED_FN_RX_TX_ERR:
1113 *rules = BIT(TRIGGER_NETDEV_TX_ERR) | BIT(TRIGGER_NETDEV_RX_ERR);
1114 break;
1115 case DP83822_LED_FN_LINK_RX_TX:
1116 *rules = BIT(TRIGGER_NETDEV_LINK) | BIT(TRIGGER_NETDEV_TX) |
1117 BIT(TRIGGER_NETDEV_RX);
1118 break;
1119 default:
1120 *rules = 0;
1121 break;
1122 }
1123
1124 return 0;
1125 }
1126
1127 #define DP83822_PHY_DRIVER(_id, _name) \
1128 { \
1129 PHY_ID_MATCH_MODEL(_id), \
1130 .name = (_name), \
1131 /* PHY_BASIC_FEATURES */ \
1132 .probe = dp83822_probe, \
1133 .soft_reset = dp83822_phy_reset, \
1134 .config_init = dp83822_config_init, \
1135 .read_status = dp83822_read_status, \
1136 .get_wol = dp83822_get_wol, \
1137 .set_wol = dp83822_set_wol, \
1138 .config_intr = dp83822_config_intr, \
1139 .handle_interrupt = dp83822_handle_interrupt, \
1140 .suspend = dp83822_suspend, \
1141 .resume = dp83822_resume, \
1142 .led_hw_is_supported = dp83822_led_hw_is_supported, \
1143 .led_hw_control_set = dp83822_led_hw_control_set, \
1144 .led_hw_control_get = dp83822_led_hw_control_get, \
1145 }
1146
1147 #define DP83825_PHY_DRIVER(_id, _name) \
1148 { \
1149 PHY_ID_MATCH_MODEL(_id), \
1150 .name = (_name), \
1151 /* PHY_BASIC_FEATURES */ \
1152 .probe = dp8382x_probe, \
1153 .soft_reset = dp83822_phy_reset, \
1154 .config_init = dp83825_config_init, \
1155 .get_wol = dp83822_get_wol, \
1156 .set_wol = dp83822_set_wol, \
1157 .config_intr = dp83822_config_intr, \
1158 .handle_interrupt = dp83822_handle_interrupt, \
1159 .suspend = dp83822_suspend, \
1160 .resume = dp83822_resume, \
1161 }
1162
1163 #define DP83826_PHY_DRIVER(_id, _name) \
1164 { \
1165 PHY_ID_MATCH_MODEL(_id), \
1166 .name = (_name), \
1167 /* PHY_BASIC_FEATURES */ \
1168 .probe = dp83826_probe, \
1169 .soft_reset = dp83822_phy_reset, \
1170 .config_init = dp83826_config_init, \
1171 .get_wol = dp83822_get_wol, \
1172 .set_wol = dp83822_set_wol, \
1173 .config_intr = dp83822_config_intr, \
1174 .handle_interrupt = dp83822_handle_interrupt, \
1175 .suspend = dp83822_suspend, \
1176 .resume = dp83822_resume, \
1177 }
1178
1179 static struct phy_driver dp83822_driver[] = {
1180 DP83822_PHY_DRIVER(DP83822_PHY_ID, "TI DP83822"),
1181 DP83825_PHY_DRIVER(DP83825I_PHY_ID, "TI DP83825I"),
1182 DP83825_PHY_DRIVER(DP83825S_PHY_ID, "TI DP83825S"),
1183 DP83825_PHY_DRIVER(DP83825CM_PHY_ID, "TI DP83825M"),
1184 DP83825_PHY_DRIVER(DP83825CS_PHY_ID, "TI DP83825CS"),
1185 DP83826_PHY_DRIVER(DP83826C_PHY_ID, "TI DP83826C"),
1186 DP83826_PHY_DRIVER(DP83826NC_PHY_ID, "TI DP83826NC"),
1187 };
1188 module_phy_driver(dp83822_driver);
1189
1190 static const struct mdio_device_id __maybe_unused dp83822_tbl[] = {
1191 { DP83822_PHY_ID, 0xfffffff0 },
1192 { DP83825I_PHY_ID, 0xfffffff0 },
1193 { DP83826C_PHY_ID, 0xfffffff0 },
1194 { DP83826NC_PHY_ID, 0xfffffff0 },
1195 { DP83825S_PHY_ID, 0xfffffff0 },
1196 { DP83825CM_PHY_ID, 0xfffffff0 },
1197 { DP83825CS_PHY_ID, 0xfffffff0 },
1198 { },
1199 };
1200 MODULE_DEVICE_TABLE(mdio, dp83822_tbl);
1201
1202 MODULE_DESCRIPTION("Texas Instruments DP83822 PHY driver");
1203 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
1204 MODULE_LICENSE("GPL v2");
1205