1 // SPDX-License-Identifier: GPL-2.0 2 /* Driver for the Texas Instruments DP83822, DP83825 and DP83826 PHYs. 3 * 4 * Copyright (C) 2017 Texas Instruments Inc. 5 */ 6 7 #include <linux/ethtool.h> 8 #include <linux/etherdevice.h> 9 #include <linux/kernel.h> 10 #include <linux/mii.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/phy.h> 14 #include <linux/phy_port.h> 15 #include <linux/netdevice.h> 16 #include <linux/bitfield.h> 17 18 #define DP83822_PHY_ID 0x2000a240 19 #define DP83825S_PHY_ID 0x2000a140 20 #define DP83825I_PHY_ID 0x2000a150 21 #define DP83825CM_PHY_ID 0x2000a160 22 #define DP83825CS_PHY_ID 0x2000a170 23 #define DP83826C_PHY_ID 0x2000a130 24 #define DP83826NC_PHY_ID 0x2000a110 25 26 #define MII_DP83822_CTRL_2 0x0a 27 #define MII_DP83822_PHYSTS 0x10 28 #define MII_DP83822_PHYSCR 0x11 29 #define MII_DP83822_MISR1 0x12 30 #define MII_DP83822_MISR2 0x13 31 #define MII_DP83822_FCSCR 0x14 32 #define MII_DP83822_RCSR 0x17 33 #define MII_DP83822_RESET_CTRL 0x1f 34 #define MII_DP83822_MLEDCR 0x25 35 #define MII_DP83822_LDCTRL 0x403 36 #define MII_DP83822_LEDCFG1 0x460 37 #define MII_DP83822_IOCTRL 0x461 38 #define MII_DP83822_IOCTRL1 0x462 39 #define MII_DP83822_IOCTRL2 0x463 40 #define MII_DP83822_GENCFG 0x465 41 #define MII_DP83822_SOR1 0x467 42 43 /* DP83826 specific registers */ 44 #define MII_DP83826_VOD_CFG1 0x30b 45 #define MII_DP83826_VOD_CFG2 0x30c 46 47 /* GENCFG */ 48 #define DP83822_SIG_DET_LOW BIT(0) 49 50 /* Control Register 2 bits */ 51 #define DP83822_FX_ENABLE BIT(14) 52 53 #define DP83822_SW_RESET BIT(15) 54 #define DP83822_DIG_RESTART BIT(14) 55 56 /* PHY STS bits */ 57 #define DP83822_PHYSTS_DUPLEX BIT(2) 58 #define DP83822_PHYSTS_10 BIT(1) 59 #define DP83822_PHYSTS_LINK BIT(0) 60 61 /* PHYSCR Register Fields */ 62 #define DP83822_PHYSCR_INT_OE BIT(0) /* Interrupt Output Enable */ 63 #define DP83822_PHYSCR_INTEN BIT(1) /* Interrupt Enable */ 64 65 /* MISR1 bits */ 66 #define DP83822_RX_ERR_HF_INT_EN BIT(0) 67 #define DP83822_FALSE_CARRIER_HF_INT_EN BIT(1) 68 #define DP83822_ANEG_COMPLETE_INT_EN BIT(2) 69 #define DP83822_DUP_MODE_CHANGE_INT_EN BIT(3) 70 #define DP83822_SPEED_CHANGED_INT_EN BIT(4) 71 #define DP83822_LINK_STAT_INT_EN BIT(5) 72 #define DP83822_ENERGY_DET_INT_EN BIT(6) 73 #define DP83822_LINK_QUAL_INT_EN BIT(7) 74 75 /* MISR2 bits */ 76 #define DP83822_JABBER_DET_INT_EN BIT(0) 77 #define DP83822_WOL_PKT_INT_EN BIT(1) 78 #define DP83822_SLEEP_MODE_INT_EN BIT(2) 79 #define DP83822_MDI_XOVER_INT_EN BIT(3) 80 #define DP83822_LB_FIFO_INT_EN BIT(4) 81 #define DP83822_PAGE_RX_INT_EN BIT(5) 82 #define DP83822_ANEG_ERR_INT_EN BIT(6) 83 #define DP83822_EEE_ERROR_CHANGE_INT_EN BIT(7) 84 85 /* INT_STAT1 bits */ 86 #define DP83822_WOL_INT_EN BIT(4) 87 #define DP83822_WOL_INT_STAT BIT(12) 88 89 #define MII_DP83822_RXSOP1 0x04a5 90 #define MII_DP83822_RXSOP2 0x04a6 91 #define MII_DP83822_RXSOP3 0x04a7 92 93 /* WoL Registers */ 94 #define MII_DP83822_WOL_CFG 0x04a0 95 #define MII_DP83822_WOL_STAT 0x04a1 96 #define MII_DP83822_WOL_DA1 0x04a2 97 #define MII_DP83822_WOL_DA2 0x04a3 98 #define MII_DP83822_WOL_DA3 0x04a4 99 100 /* WoL bits */ 101 #define DP83822_WOL_MAGIC_EN BIT(0) 102 #define DP83822_WOL_SECURE_ON BIT(5) 103 #define DP83822_WOL_EN BIT(7) 104 #define DP83822_WOL_INDICATION_SEL BIT(8) 105 #define DP83822_WOL_CLR_INDICATION BIT(11) 106 107 /* RCSR bits */ 108 #define DP83822_RMII_MODE_EN BIT(5) 109 #define DP83822_RMII_MODE_SEL BIT(7) 110 #define DP83822_RGMII_MODE_EN BIT(9) 111 #define DP83822_RX_CLK_SHIFT BIT(12) 112 #define DP83822_TX_CLK_SHIFT BIT(11) 113 114 /* MLEDCR bits */ 115 #define DP83822_MLEDCR_CFG GENMASK(6, 3) 116 #define DP83822_MLEDCR_ROUTE GENMASK(1, 0) 117 #define DP83822_MLEDCR_ROUTE_LED_0 DP83822_MLEDCR_ROUTE 118 119 /* LEDCFG1 bits */ 120 #define DP83822_LEDCFG1_LED1_CTRL GENMASK(11, 8) 121 #define DP83822_LEDCFG1_LED3_CTRL GENMASK(7, 4) 122 123 /* IOCTRL bits */ 124 #define DP83822_IOCTRL_MAC_IMPEDANCE_CTRL GENMASK(4, 1) 125 126 /* IOCTRL1 bits */ 127 #define DP83822_IOCTRL1_GPIO3_CTRL GENMASK(10, 8) 128 #define DP83822_IOCTRL1_GPIO3_CTRL_LED3 BIT(0) 129 #define DP83822_IOCTRL1_GPIO1_CTRL GENMASK(2, 0) 130 #define DP83822_IOCTRL1_GPIO1_CTRL_LED_1 BIT(0) 131 132 /* LDCTRL bits */ 133 #define DP83822_100BASE_TX_LINE_DRIVER_SWING GENMASK(7, 4) 134 135 /* IOCTRL2 bits */ 136 #define DP83822_IOCTRL2_GPIO2_CLK_SRC GENMASK(6, 4) 137 #define DP83822_IOCTRL2_GPIO2_CTRL GENMASK(2, 0) 138 #define DP83822_IOCTRL2_GPIO2_CTRL_CLK_REF GENMASK(1, 0) 139 #define DP83822_IOCTRL2_GPIO2_CTRL_MLED BIT(0) 140 141 #define DP83822_CLK_SRC_MAC_IF 0x0 142 #define DP83822_CLK_SRC_XI 0x1 143 #define DP83822_CLK_SRC_INT_REF 0x2 144 #define DP83822_CLK_SRC_RMII_MASTER_MODE_REF 0x4 145 #define DP83822_CLK_SRC_FREE_RUNNING 0x6 146 #define DP83822_CLK_SRC_RECOVERED 0x7 147 148 #define DP83822_LED_FN_LINK 0x0 /* Link established */ 149 #define DP83822_LED_FN_RX_TX 0x1 /* Receive or Transmit activity */ 150 #define DP83822_LED_FN_TX 0x2 /* Transmit activity */ 151 #define DP83822_LED_FN_RX 0x3 /* Receive activity */ 152 #define DP83822_LED_FN_COLLISION 0x4 /* Collision detected */ 153 #define DP83822_LED_FN_LINK_100_BTX 0x5 /* 100 BTX link established */ 154 #define DP83822_LED_FN_LINK_10_BT 0x6 /* 10BT link established */ 155 #define DP83822_LED_FN_FULL_DUPLEX 0x7 /* Full duplex */ 156 #define DP83822_LED_FN_LINK_RX_TX 0x8 /* Link established, blink for rx or tx activity */ 157 #define DP83822_LED_FN_ACTIVE_STRETCH 0x9 /* Active Stretch Signal */ 158 #define DP83822_LED_FN_MII_LINK 0xa /* MII LINK (100BT+FD) */ 159 #define DP83822_LED_FN_LPI_MODE 0xb /* LPI Mode (EEE) */ 160 #define DP83822_LED_FN_RX_TX_ERR 0xc /* TX/RX MII Error */ 161 #define DP83822_LED_FN_LINK_LOST 0xd /* Link Lost */ 162 #define DP83822_LED_FN_PRBS_ERR 0xe /* Blink for PRBS error */ 163 164 /* SOR1 mode */ 165 #define DP83822_STRAP_MODE1 0 166 #define DP83822_STRAP_MODE2 BIT(0) 167 #define DP83822_STRAP_MODE3 BIT(1) 168 #define DP83822_STRAP_MODE4 GENMASK(1, 0) 169 170 #define DP83822_COL_STRAP_MASK GENMASK(11, 10) 171 #define DP83822_COL_SHIFT 10 172 #define DP83822_RX_ER_STR_MASK GENMASK(9, 8) 173 #define DP83822_RX_ER_SHIFT 8 174 175 /* DP83826: VOD_CFG1 & VOD_CFG2 */ 176 #define DP83826_VOD_CFG1_MINUS_MDIX_MASK GENMASK(13, 12) 177 #define DP83826_VOD_CFG1_MINUS_MDI_MASK GENMASK(11, 6) 178 #define DP83826_VOD_CFG2_MINUS_MDIX_MASK GENMASK(15, 12) 179 #define DP83826_VOD_CFG2_PLUS_MDIX_MASK GENMASK(11, 6) 180 #define DP83826_VOD_CFG2_PLUS_MDI_MASK GENMASK(5, 0) 181 #define DP83826_CFG_DAC_MINUS_MDIX_5_TO_4 GENMASK(5, 4) 182 #define DP83826_CFG_DAC_MINUS_MDIX_3_TO_0 GENMASK(3, 0) 183 #define DP83826_CFG_DAC_PERCENT_PER_STEP 625 184 #define DP83826_CFG_DAC_PERCENT_DEFAULT 10000 185 #define DP83826_CFG_DAC_MINUS_DEFAULT 0x30 186 #define DP83826_CFG_DAC_PLUS_DEFAULT 0x10 187 188 #define MII_DP83822_FIBER_ADVERTISE (ADVERTISED_TP | ADVERTISED_MII | \ 189 ADVERTISED_FIBRE | \ 190 ADVERTISED_Pause | ADVERTISED_Asym_Pause) 191 192 #define DP83822_MAX_LED_PINS 4 193 194 #define DP83822_LED_INDEX_LED_0 0 195 #define DP83822_LED_INDEX_LED_1_GPIO1 1 196 #define DP83822_LED_INDEX_COL_GPIO2 2 197 #define DP83822_LED_INDEX_RX_D3_GPIO3 3 198 199 struct dp83822_private { 200 bool fx_signal_det_low; 201 int fx_enabled; 202 u16 fx_sd_enable; 203 u8 cfg_dac_minus; 204 u8 cfg_dac_plus; 205 struct ethtool_wolinfo wol; 206 bool set_gpio2_clk_out; 207 u32 gpio2_clk_out; 208 bool led_pin_enable[DP83822_MAX_LED_PINS]; 209 int tx_amplitude_100base_tx_index; 210 int mac_termination_index; 211 }; 212 213 static int dp83822_config_wol(struct phy_device *phydev, 214 struct ethtool_wolinfo *wol) 215 { 216 struct net_device *ndev = phydev->attached_dev; 217 u16 value; 218 const u8 *mac; 219 220 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) { 221 mac = (const u8 *)ndev->dev_addr; 222 223 if (!is_valid_ether_addr(mac)) 224 return -EINVAL; 225 226 /* MAC addresses start with byte 5, but stored in mac[0]. 227 * 822 PHYs store bytes 4|5, 2|3, 0|1 228 */ 229 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA1, 230 (mac[1] << 8) | mac[0]); 231 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA2, 232 (mac[3] << 8) | mac[2]); 233 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA3, 234 (mac[5] << 8) | mac[4]); 235 236 value = phy_read_mmd(phydev, MDIO_MMD_VEND2, 237 MII_DP83822_WOL_CFG); 238 if (wol->wolopts & WAKE_MAGIC) 239 value |= DP83822_WOL_MAGIC_EN; 240 else 241 value &= ~DP83822_WOL_MAGIC_EN; 242 243 if (wol->wolopts & WAKE_MAGICSECURE) { 244 phy_write_mmd(phydev, MDIO_MMD_VEND2, 245 MII_DP83822_RXSOP1, 246 (wol->sopass[1] << 8) | wol->sopass[0]); 247 phy_write_mmd(phydev, MDIO_MMD_VEND2, 248 MII_DP83822_RXSOP2, 249 (wol->sopass[3] << 8) | wol->sopass[2]); 250 phy_write_mmd(phydev, MDIO_MMD_VEND2, 251 MII_DP83822_RXSOP3, 252 (wol->sopass[5] << 8) | wol->sopass[4]); 253 value |= DP83822_WOL_SECURE_ON; 254 } else { 255 value &= ~DP83822_WOL_SECURE_ON; 256 } 257 258 /* Clear any pending WoL interrupt */ 259 phy_read(phydev, MII_DP83822_MISR2); 260 261 value |= DP83822_WOL_EN | DP83822_WOL_INDICATION_SEL | 262 DP83822_WOL_CLR_INDICATION; 263 264 return phy_write_mmd(phydev, MDIO_MMD_VEND2, 265 MII_DP83822_WOL_CFG, value); 266 } else { 267 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 268 MII_DP83822_WOL_CFG, 269 DP83822_WOL_EN | 270 DP83822_WOL_MAGIC_EN | 271 DP83822_WOL_SECURE_ON); 272 } 273 } 274 275 static int dp83822_set_wol(struct phy_device *phydev, 276 struct ethtool_wolinfo *wol) 277 { 278 struct dp83822_private *dp83822 = phydev->priv; 279 int ret; 280 281 ret = dp83822_config_wol(phydev, wol); 282 if (!ret) 283 memcpy(&dp83822->wol, wol, sizeof(*wol)); 284 return ret; 285 } 286 287 static void dp83822_get_wol(struct phy_device *phydev, 288 struct ethtool_wolinfo *wol) 289 { 290 int value; 291 u16 sopass_val; 292 293 wol->supported = (WAKE_MAGIC | WAKE_MAGICSECURE); 294 wol->wolopts = 0; 295 296 value = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG); 297 298 if (value & DP83822_WOL_MAGIC_EN) 299 wol->wolopts |= WAKE_MAGIC; 300 301 if (value & DP83822_WOL_SECURE_ON) { 302 sopass_val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 303 MII_DP83822_RXSOP1); 304 wol->sopass[0] = (sopass_val & 0xff); 305 wol->sopass[1] = (sopass_val >> 8); 306 307 sopass_val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 308 MII_DP83822_RXSOP2); 309 wol->sopass[2] = (sopass_val & 0xff); 310 wol->sopass[3] = (sopass_val >> 8); 311 312 sopass_val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 313 MII_DP83822_RXSOP3); 314 wol->sopass[4] = (sopass_val & 0xff); 315 wol->sopass[5] = (sopass_val >> 8); 316 317 wol->wolopts |= WAKE_MAGICSECURE; 318 } 319 320 /* WoL is not enabled so set wolopts to 0 */ 321 if (!(value & DP83822_WOL_EN)) 322 wol->wolopts = 0; 323 } 324 325 static int dp83822_config_intr(struct phy_device *phydev) 326 { 327 struct dp83822_private *dp83822 = phydev->priv; 328 int misr_status; 329 int physcr_status; 330 int err; 331 332 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 333 misr_status = phy_read(phydev, MII_DP83822_MISR1); 334 if (misr_status < 0) 335 return misr_status; 336 337 misr_status |= (DP83822_LINK_STAT_INT_EN | 338 DP83822_ENERGY_DET_INT_EN | 339 DP83822_LINK_QUAL_INT_EN); 340 341 if (!dp83822->fx_enabled) 342 misr_status |= DP83822_ANEG_COMPLETE_INT_EN | 343 DP83822_DUP_MODE_CHANGE_INT_EN | 344 DP83822_SPEED_CHANGED_INT_EN; 345 346 347 err = phy_write(phydev, MII_DP83822_MISR1, misr_status); 348 if (err < 0) 349 return err; 350 351 misr_status = phy_read(phydev, MII_DP83822_MISR2); 352 if (misr_status < 0) 353 return misr_status; 354 355 misr_status |= (DP83822_JABBER_DET_INT_EN | 356 DP83822_SLEEP_MODE_INT_EN | 357 DP83822_LB_FIFO_INT_EN | 358 DP83822_PAGE_RX_INT_EN | 359 DP83822_EEE_ERROR_CHANGE_INT_EN); 360 361 if (!dp83822->fx_enabled) 362 misr_status |= DP83822_ANEG_ERR_INT_EN | 363 DP83822_WOL_PKT_INT_EN; 364 365 err = phy_write(phydev, MII_DP83822_MISR2, misr_status); 366 if (err < 0) 367 return err; 368 369 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR); 370 if (physcr_status < 0) 371 return physcr_status; 372 373 physcr_status |= DP83822_PHYSCR_INT_OE | DP83822_PHYSCR_INTEN; 374 375 } else { 376 err = phy_write(phydev, MII_DP83822_MISR1, 0); 377 if (err < 0) 378 return err; 379 380 err = phy_write(phydev, MII_DP83822_MISR2, 0); 381 if (err < 0) 382 return err; 383 384 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR); 385 if (physcr_status < 0) 386 return physcr_status; 387 388 physcr_status &= ~DP83822_PHYSCR_INTEN; 389 } 390 391 return phy_write(phydev, MII_DP83822_PHYSCR, physcr_status); 392 } 393 394 static irqreturn_t dp83822_handle_interrupt(struct phy_device *phydev) 395 { 396 bool trigger_machine = false; 397 int irq_status; 398 399 /* The MISR1 and MISR2 registers are holding the interrupt status in 400 * the upper half (15:8), while the lower half (7:0) is used for 401 * controlling the interrupt enable state of those individual interrupt 402 * sources. To determine the possible interrupt sources, just read the 403 * MISR* register and use it directly to know which interrupts have 404 * been enabled previously or not. 405 */ 406 irq_status = phy_read(phydev, MII_DP83822_MISR1); 407 if (irq_status < 0) { 408 phy_error(phydev); 409 return IRQ_NONE; 410 } 411 if (irq_status & ((irq_status & GENMASK(7, 0)) << 8)) 412 trigger_machine = true; 413 414 irq_status = phy_read(phydev, MII_DP83822_MISR2); 415 if (irq_status < 0) { 416 phy_error(phydev); 417 return IRQ_NONE; 418 } 419 if (irq_status & ((irq_status & GENMASK(7, 0)) << 8)) 420 trigger_machine = true; 421 422 if (!trigger_machine) 423 return IRQ_NONE; 424 425 phy_trigger_machine(phydev); 426 427 return IRQ_HANDLED; 428 } 429 430 static int dp83822_read_status(struct phy_device *phydev) 431 { 432 struct dp83822_private *dp83822 = phydev->priv; 433 int status = phy_read(phydev, MII_DP83822_PHYSTS); 434 int ctrl2; 435 int ret; 436 437 if (dp83822->fx_enabled) { 438 if (status & DP83822_PHYSTS_LINK) { 439 phydev->speed = SPEED_UNKNOWN; 440 phydev->duplex = DUPLEX_UNKNOWN; 441 } else { 442 ctrl2 = phy_read(phydev, MII_DP83822_CTRL_2); 443 if (ctrl2 < 0) 444 return ctrl2; 445 446 if (!(ctrl2 & DP83822_FX_ENABLE)) { 447 ret = phy_write(phydev, MII_DP83822_CTRL_2, 448 DP83822_FX_ENABLE | ctrl2); 449 if (ret < 0) 450 return ret; 451 } 452 } 453 } 454 455 ret = genphy_read_status(phydev); 456 if (ret) 457 return ret; 458 459 if (status < 0) 460 return status; 461 462 if (status & DP83822_PHYSTS_DUPLEX) 463 phydev->duplex = DUPLEX_FULL; 464 else 465 phydev->duplex = DUPLEX_HALF; 466 467 if (status & DP83822_PHYSTS_10) 468 phydev->speed = SPEED_10; 469 else 470 phydev->speed = SPEED_100; 471 472 return 0; 473 } 474 475 static int dp83822_config_init_leds(struct phy_device *phydev) 476 { 477 struct dp83822_private *dp83822 = phydev->priv; 478 int ret; 479 480 if (dp83822->led_pin_enable[DP83822_LED_INDEX_LED_0]) { 481 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_MLEDCR, 482 DP83822_MLEDCR_ROUTE, 483 FIELD_PREP(DP83822_MLEDCR_ROUTE, 484 DP83822_MLEDCR_ROUTE_LED_0)); 485 if (ret) 486 return ret; 487 } else if (dp83822->led_pin_enable[DP83822_LED_INDEX_COL_GPIO2]) { 488 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL2, 489 DP83822_IOCTRL2_GPIO2_CTRL, 490 FIELD_PREP(DP83822_IOCTRL2_GPIO2_CTRL, 491 DP83822_IOCTRL2_GPIO2_CTRL_MLED)); 492 if (ret) 493 return ret; 494 } 495 496 if (dp83822->led_pin_enable[DP83822_LED_INDEX_LED_1_GPIO1]) { 497 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL1, 498 DP83822_IOCTRL1_GPIO1_CTRL, 499 FIELD_PREP(DP83822_IOCTRL1_GPIO1_CTRL, 500 DP83822_IOCTRL1_GPIO1_CTRL_LED_1)); 501 if (ret) 502 return ret; 503 } 504 505 if (dp83822->led_pin_enable[DP83822_LED_INDEX_RX_D3_GPIO3]) { 506 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL1, 507 DP83822_IOCTRL1_GPIO3_CTRL, 508 FIELD_PREP(DP83822_IOCTRL1_GPIO3_CTRL, 509 DP83822_IOCTRL1_GPIO3_CTRL_LED3)); 510 if (ret) 511 return ret; 512 } 513 514 return 0; 515 } 516 517 static int dp83822_config_init(struct phy_device *phydev) 518 { 519 struct dp83822_private *dp83822 = phydev->priv; 520 int rgmii_delay = 0; 521 s32 rx_int_delay; 522 s32 tx_int_delay; 523 int err = 0; 524 int bmcr; 525 526 if (dp83822->set_gpio2_clk_out) 527 phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL2, 528 DP83822_IOCTRL2_GPIO2_CTRL | 529 DP83822_IOCTRL2_GPIO2_CLK_SRC, 530 FIELD_PREP(DP83822_IOCTRL2_GPIO2_CTRL, 531 DP83822_IOCTRL2_GPIO2_CTRL_CLK_REF) | 532 FIELD_PREP(DP83822_IOCTRL2_GPIO2_CLK_SRC, 533 dp83822->gpio2_clk_out)); 534 535 if (dp83822->tx_amplitude_100base_tx_index >= 0) 536 phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_LDCTRL, 537 DP83822_100BASE_TX_LINE_DRIVER_SWING, 538 FIELD_PREP(DP83822_100BASE_TX_LINE_DRIVER_SWING, 539 dp83822->tx_amplitude_100base_tx_index)); 540 541 if (dp83822->mac_termination_index >= 0) 542 phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL, 543 DP83822_IOCTRL_MAC_IMPEDANCE_CTRL, 544 FIELD_PREP(DP83822_IOCTRL_MAC_IMPEDANCE_CTRL, 545 dp83822->mac_termination_index)); 546 547 err = dp83822_config_init_leds(phydev); 548 if (err) 549 return err; 550 551 if (phy_interface_is_rgmii(phydev)) { 552 rx_int_delay = phy_get_internal_delay(phydev, NULL, 0, true); 553 554 /* Set DP83822_RX_CLK_SHIFT to enable rx clk internal delay */ 555 if (rx_int_delay > 0) 556 rgmii_delay |= DP83822_RX_CLK_SHIFT; 557 558 tx_int_delay = phy_get_internal_delay(phydev, NULL, 0, false); 559 560 /* Set DP83822_TX_CLK_SHIFT to disable tx clk internal delay */ 561 if (tx_int_delay <= 0) 562 rgmii_delay |= DP83822_TX_CLK_SHIFT; 563 564 err = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR, 565 DP83822_RX_CLK_SHIFT | DP83822_TX_CLK_SHIFT, rgmii_delay); 566 if (err) 567 return err; 568 569 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 570 MII_DP83822_RCSR, DP83822_RGMII_MODE_EN); 571 572 if (err) 573 return err; 574 } else { 575 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 576 MII_DP83822_RCSR, DP83822_RGMII_MODE_EN); 577 578 if (err) 579 return err; 580 } 581 582 if (dp83822->fx_enabled) { 583 err = phy_modify(phydev, MII_DP83822_CTRL_2, 584 DP83822_FX_ENABLE, 1); 585 if (err < 0) 586 return err; 587 588 /* Only allow advertising what this PHY supports */ 589 linkmode_and(phydev->advertising, phydev->advertising, 590 phydev->supported); 591 592 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 593 phydev->supported); 594 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 595 phydev->advertising); 596 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, 597 phydev->supported); 598 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT, 599 phydev->supported); 600 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, 601 phydev->advertising); 602 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT, 603 phydev->advertising); 604 605 /* Auto neg is not supported in fiber mode */ 606 bmcr = phy_read(phydev, MII_BMCR); 607 if (bmcr < 0) 608 return bmcr; 609 610 if (bmcr & BMCR_ANENABLE) { 611 err = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0); 612 if (err < 0) 613 return err; 614 } 615 phydev->autoneg = AUTONEG_DISABLE; 616 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 617 phydev->supported); 618 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 619 phydev->advertising); 620 621 /* Setup fiber advertisement */ 622 err = phy_modify_changed(phydev, MII_ADVERTISE, 623 MII_DP83822_FIBER_ADVERTISE, 624 MII_DP83822_FIBER_ADVERTISE); 625 626 if (err < 0) 627 return err; 628 629 if (dp83822->fx_signal_det_low) { 630 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 631 MII_DP83822_GENCFG, 632 DP83822_SIG_DET_LOW); 633 if (err) 634 return err; 635 } 636 } 637 return dp83822_config_wol(phydev, &dp83822->wol); 638 } 639 640 static int dp8382x_config_rmii_mode(struct phy_device *phydev) 641 { 642 struct device *dev = &phydev->mdio.dev; 643 const char *of_val; 644 int ret; 645 646 if (!device_property_read_string(dev, "ti,rmii-mode", &of_val)) { 647 if (strcmp(of_val, "master") == 0) { 648 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR, 649 DP83822_RMII_MODE_SEL); 650 } else if (strcmp(of_val, "slave") == 0) { 651 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR, 652 DP83822_RMII_MODE_SEL); 653 } else { 654 phydev_err(phydev, "Invalid value for ti,rmii-mode property (%s)\n", 655 of_val); 656 ret = -EINVAL; 657 } 658 659 if (ret) 660 return ret; 661 } 662 663 return 0; 664 } 665 666 static int dp83826_config_init(struct phy_device *phydev) 667 { 668 struct dp83822_private *dp83822 = phydev->priv; 669 u16 val, mask; 670 int ret; 671 672 if (phydev->interface == PHY_INTERFACE_MODE_RMII) { 673 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR, 674 DP83822_RMII_MODE_EN); 675 if (ret) 676 return ret; 677 678 ret = dp8382x_config_rmii_mode(phydev); 679 if (ret) 680 return ret; 681 } else { 682 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR, 683 DP83822_RMII_MODE_EN); 684 if (ret) 685 return ret; 686 } 687 688 if (dp83822->cfg_dac_minus != DP83826_CFG_DAC_MINUS_DEFAULT) { 689 val = FIELD_PREP(DP83826_VOD_CFG1_MINUS_MDI_MASK, dp83822->cfg_dac_minus) | 690 FIELD_PREP(DP83826_VOD_CFG1_MINUS_MDIX_MASK, 691 FIELD_GET(DP83826_CFG_DAC_MINUS_MDIX_5_TO_4, 692 dp83822->cfg_dac_minus)); 693 mask = DP83826_VOD_CFG1_MINUS_MDIX_MASK | DP83826_VOD_CFG1_MINUS_MDI_MASK; 694 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83826_VOD_CFG1, mask, val); 695 if (ret) 696 return ret; 697 698 val = FIELD_PREP(DP83826_VOD_CFG2_MINUS_MDIX_MASK, 699 FIELD_GET(DP83826_CFG_DAC_MINUS_MDIX_3_TO_0, 700 dp83822->cfg_dac_minus)); 701 mask = DP83826_VOD_CFG2_MINUS_MDIX_MASK; 702 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83826_VOD_CFG2, mask, val); 703 if (ret) 704 return ret; 705 } 706 707 if (dp83822->cfg_dac_plus != DP83826_CFG_DAC_PLUS_DEFAULT) { 708 val = FIELD_PREP(DP83826_VOD_CFG2_PLUS_MDIX_MASK, dp83822->cfg_dac_plus) | 709 FIELD_PREP(DP83826_VOD_CFG2_PLUS_MDI_MASK, dp83822->cfg_dac_plus); 710 mask = DP83826_VOD_CFG2_PLUS_MDIX_MASK | DP83826_VOD_CFG2_PLUS_MDI_MASK; 711 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83826_VOD_CFG2, mask, val); 712 if (ret) 713 return ret; 714 } 715 716 return dp83822_config_wol(phydev, &dp83822->wol); 717 } 718 719 static int dp83825_config_init(struct phy_device *phydev) 720 { 721 struct dp83822_private *dp83822 = phydev->priv; 722 int ret; 723 724 ret = dp8382x_config_rmii_mode(phydev); 725 if (ret) 726 return ret; 727 728 return dp83822_config_wol(phydev, &dp83822->wol); 729 } 730 731 static int dp83822_phy_reset(struct phy_device *phydev) 732 { 733 int err; 734 735 err = phy_write(phydev, MII_DP83822_RESET_CTRL, DP83822_SW_RESET); 736 if (err < 0) 737 return err; 738 739 return phydev->drv->config_init(phydev); 740 } 741 742 #if IS_ENABLED(CONFIG_OF_MDIO) 743 static const u32 tx_amplitude_100base_tx_gain[] = { 744 80, 82, 83, 85, 87, 88, 90, 92, 745 93, 95, 97, 98, 100, 102, 103, 105, 746 }; 747 748 static const u32 mac_termination[] = { 749 99, 91, 84, 78, 73, 69, 65, 61, 58, 55, 53, 50, 48, 46, 44, 43, 750 }; 751 752 static int dp83822_of_init_leds(struct phy_device *phydev) 753 { 754 struct device_node *node = phydev->mdio.dev.of_node; 755 struct dp83822_private *dp83822 = phydev->priv; 756 struct device_node *leds; 757 u32 index; 758 int err; 759 760 if (!node) 761 return 0; 762 763 leds = of_get_child_by_name(node, "leds"); 764 if (!leds) 765 return 0; 766 767 for_each_available_child_of_node_scoped(leds, led) { 768 err = of_property_read_u32(led, "reg", &index); 769 if (err) { 770 of_node_put(leds); 771 return err; 772 } 773 774 if (index <= DP83822_LED_INDEX_RX_D3_GPIO3) { 775 dp83822->led_pin_enable[index] = true; 776 } else { 777 of_node_put(leds); 778 return -EINVAL; 779 } 780 } 781 782 of_node_put(leds); 783 /* LED_0 and COL(GPIO2) use the MLED function. MLED can be routed to 784 * only one of these two pins at a time. 785 */ 786 if (dp83822->led_pin_enable[DP83822_LED_INDEX_LED_0] && 787 dp83822->led_pin_enable[DP83822_LED_INDEX_COL_GPIO2]) { 788 phydev_err(phydev, "LED_0 and COL(GPIO2) cannot be used as LED output at the same time\n"); 789 return -EINVAL; 790 } 791 792 if (dp83822->led_pin_enable[DP83822_LED_INDEX_COL_GPIO2] && 793 dp83822->set_gpio2_clk_out) { 794 phydev_err(phydev, "COL(GPIO2) cannot be used as LED output, already used as clock output\n"); 795 return -EINVAL; 796 } 797 798 if (dp83822->led_pin_enable[DP83822_LED_INDEX_RX_D3_GPIO3] && 799 phydev->interface != PHY_INTERFACE_MODE_RMII) { 800 phydev_err(phydev, "RX_D3 can only be used as LED output when in RMII mode\n"); 801 return -EINVAL; 802 } 803 804 return 0; 805 } 806 807 static int dp83822_of_init(struct phy_device *phydev) 808 { 809 struct dp83822_private *dp83822 = phydev->priv; 810 struct device *dev = &phydev->mdio.dev; 811 const char *of_val; 812 int i, ret; 813 u32 val; 814 815 if (!device_property_read_string(dev, "ti,gpio2-clk-out", &of_val)) { 816 if (strcmp(of_val, "mac-if") == 0) { 817 dp83822->gpio2_clk_out = DP83822_CLK_SRC_MAC_IF; 818 } else if (strcmp(of_val, "xi") == 0) { 819 dp83822->gpio2_clk_out = DP83822_CLK_SRC_XI; 820 } else if (strcmp(of_val, "int-ref") == 0) { 821 dp83822->gpio2_clk_out = DP83822_CLK_SRC_INT_REF; 822 } else if (strcmp(of_val, "rmii-master-mode-ref") == 0) { 823 dp83822->gpio2_clk_out = DP83822_CLK_SRC_RMII_MASTER_MODE_REF; 824 } else if (strcmp(of_val, "free-running") == 0) { 825 dp83822->gpio2_clk_out = DP83822_CLK_SRC_FREE_RUNNING; 826 } else if (strcmp(of_val, "recovered") == 0) { 827 dp83822->gpio2_clk_out = DP83822_CLK_SRC_RECOVERED; 828 } else { 829 phydev_err(phydev, 830 "Invalid value for ti,gpio2-clk-out property (%s)\n", 831 of_val); 832 return -EINVAL; 833 } 834 835 dp83822->set_gpio2_clk_out = true; 836 } 837 838 ret = phy_get_tx_amplitude_gain(phydev, dev, 839 ETHTOOL_LINK_MODE_100baseT_Full_BIT, 840 &val); 841 if (!ret) { 842 for (i = 0; i < ARRAY_SIZE(tx_amplitude_100base_tx_gain); i++) { 843 if (tx_amplitude_100base_tx_gain[i] == val) { 844 dp83822->tx_amplitude_100base_tx_index = i; 845 break; 846 } 847 } 848 849 if (dp83822->tx_amplitude_100base_tx_index < 0) { 850 phydev_err(phydev, 851 "Invalid value for tx-amplitude-100base-tx-percent property (%u)\n", 852 val); 853 return -EINVAL; 854 } 855 } 856 857 ret = phy_get_mac_termination(phydev, dev, &val); 858 if (!ret) { 859 for (i = 0; i < ARRAY_SIZE(mac_termination); i++) { 860 if (mac_termination[i] == val) { 861 dp83822->mac_termination_index = i; 862 break; 863 } 864 } 865 866 if (dp83822->mac_termination_index < 0) { 867 phydev_err(phydev, 868 "Invalid value for mac-termination-ohms property (%u)\n", 869 val); 870 return -EINVAL; 871 } 872 } 873 874 return dp83822_of_init_leds(phydev); 875 } 876 877 static int dp83826_to_dac_minus_one_regval(int percent) 878 { 879 int tmp = DP83826_CFG_DAC_PERCENT_DEFAULT - percent; 880 881 return tmp / DP83826_CFG_DAC_PERCENT_PER_STEP; 882 } 883 884 static int dp83826_to_dac_plus_one_regval(int percent) 885 { 886 int tmp = percent - DP83826_CFG_DAC_PERCENT_DEFAULT; 887 888 return tmp / DP83826_CFG_DAC_PERCENT_PER_STEP; 889 } 890 891 static void dp83826_of_init(struct phy_device *phydev) 892 { 893 struct dp83822_private *dp83822 = phydev->priv; 894 struct device *dev = &phydev->mdio.dev; 895 u32 val; 896 897 dp83822->cfg_dac_minus = DP83826_CFG_DAC_MINUS_DEFAULT; 898 if (!device_property_read_u32(dev, "ti,cfg-dac-minus-one-bp", &val)) 899 dp83822->cfg_dac_minus += dp83826_to_dac_minus_one_regval(val); 900 901 dp83822->cfg_dac_plus = DP83826_CFG_DAC_PLUS_DEFAULT; 902 if (!device_property_read_u32(dev, "ti,cfg-dac-plus-one-bp", &val)) 903 dp83822->cfg_dac_plus += dp83826_to_dac_plus_one_regval(val); 904 } 905 #else 906 static int dp83822_of_init(struct phy_device *phydev) 907 { 908 return 0; 909 } 910 911 static void dp83826_of_init(struct phy_device *phydev) 912 { 913 } 914 #endif /* CONFIG_OF_MDIO */ 915 916 static int dp83822_read_straps(struct phy_device *phydev) 917 { 918 struct dp83822_private *dp83822 = phydev->priv; 919 int fx_enabled, fx_sd_enable; 920 int val; 921 922 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_SOR1); 923 if (val < 0) 924 return val; 925 926 phydev_dbg(phydev, "SOR1 strap register: 0x%04x\n", val); 927 928 fx_enabled = (val & DP83822_COL_STRAP_MASK) >> DP83822_COL_SHIFT; 929 if (fx_enabled == DP83822_STRAP_MODE2 || 930 fx_enabled == DP83822_STRAP_MODE3) 931 dp83822->fx_enabled = 1; 932 933 if (dp83822->fx_enabled) { 934 fx_sd_enable = (val & DP83822_RX_ER_STR_MASK) >> DP83822_RX_ER_SHIFT; 935 if (fx_sd_enable == DP83822_STRAP_MODE3 || 936 fx_sd_enable == DP83822_STRAP_MODE4) 937 dp83822->fx_sd_enable = 1; 938 } 939 940 return 0; 941 } 942 943 static int dp83822_attach_mdi_port(struct phy_device *phydev, 944 struct phy_port *port) 945 { 946 struct dp83822_private *dp83822 = phydev->priv; 947 int ret; 948 949 if (port->mediums) { 950 if (phy_port_is_fiber(port)) 951 dp83822->fx_enabled = true; 952 } else { 953 ret = dp83822_read_straps(phydev); 954 if (ret) 955 return ret; 956 957 #if IS_ENABLED(CONFIG_OF_MDIO) 958 if (dp83822->fx_enabled && dp83822->fx_sd_enable) 959 dp83822->fx_signal_det_low = 960 device_property_present(&phydev->mdio.dev, 961 "ti,link-loss-low"); 962 963 /* ti,fiber-mode is still used for backwards compatibility, but 964 * has been replaced with the mdi node definition, see 965 * ethernet-port.yaml 966 */ 967 if (!dp83822->fx_enabled) 968 dp83822->fx_enabled = 969 device_property_present(&phydev->mdio.dev, 970 "ti,fiber-mode"); 971 #endif /* CONFIG_OF_MDIO */ 972 973 if (dp83822->fx_enabled) { 974 port->mediums = BIT(ETHTOOL_LINK_MEDIUM_BASEF); 975 } else { 976 /* This PHY can only to 100BaseTX max, so on 2 pairs */ 977 port->pairs = 2; 978 port->mediums = BIT(ETHTOOL_LINK_MEDIUM_BASET); 979 } 980 } 981 982 return 0; 983 } 984 985 static int dp8382x_probe(struct phy_device *phydev) 986 { 987 struct dp83822_private *dp83822; 988 989 dp83822 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83822), 990 GFP_KERNEL); 991 if (!dp83822) 992 return -ENOMEM; 993 994 dp83822->tx_amplitude_100base_tx_index = -1; 995 dp83822->mac_termination_index = -1; 996 phydev->priv = dp83822; 997 998 return 0; 999 } 1000 1001 static int dp83822_probe(struct phy_device *phydev) 1002 { 1003 int ret; 1004 1005 ret = dp8382x_probe(phydev); 1006 if (ret) 1007 return ret; 1008 1009 return dp83822_of_init(phydev); 1010 } 1011 1012 static int dp83826_probe(struct phy_device *phydev) 1013 { 1014 int ret; 1015 1016 ret = dp8382x_probe(phydev); 1017 if (ret) 1018 return ret; 1019 1020 dp83826_of_init(phydev); 1021 1022 return 0; 1023 } 1024 1025 static int dp83822_suspend(struct phy_device *phydev) 1026 { 1027 int value; 1028 1029 value = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG); 1030 1031 if (!(value & DP83822_WOL_EN)) 1032 genphy_suspend(phydev); 1033 1034 return 0; 1035 } 1036 1037 static int dp83822_resume(struct phy_device *phydev) 1038 { 1039 int value; 1040 1041 genphy_resume(phydev); 1042 1043 value = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG); 1044 1045 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG, value | 1046 DP83822_WOL_CLR_INDICATION); 1047 1048 return 0; 1049 } 1050 1051 static int dp83822_led_mode(u8 index, unsigned long rules) 1052 { 1053 switch (rules) { 1054 case BIT(TRIGGER_NETDEV_LINK): 1055 return DP83822_LED_FN_LINK; 1056 case BIT(TRIGGER_NETDEV_LINK_10): 1057 return DP83822_LED_FN_LINK_10_BT; 1058 case BIT(TRIGGER_NETDEV_LINK_100): 1059 return DP83822_LED_FN_LINK_100_BTX; 1060 case BIT(TRIGGER_NETDEV_FULL_DUPLEX): 1061 return DP83822_LED_FN_FULL_DUPLEX; 1062 case BIT(TRIGGER_NETDEV_TX): 1063 return DP83822_LED_FN_TX; 1064 case BIT(TRIGGER_NETDEV_RX): 1065 return DP83822_LED_FN_RX; 1066 case BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX): 1067 return DP83822_LED_FN_RX_TX; 1068 case BIT(TRIGGER_NETDEV_TX_ERR) | BIT(TRIGGER_NETDEV_RX_ERR): 1069 return DP83822_LED_FN_RX_TX_ERR; 1070 case BIT(TRIGGER_NETDEV_LINK) | BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX): 1071 return DP83822_LED_FN_LINK_RX_TX; 1072 default: 1073 return -EOPNOTSUPP; 1074 } 1075 } 1076 1077 static int dp83822_led_hw_is_supported(struct phy_device *phydev, u8 index, 1078 unsigned long rules) 1079 { 1080 int mode; 1081 1082 mode = dp83822_led_mode(index, rules); 1083 if (mode < 0) 1084 return mode; 1085 1086 return 0; 1087 } 1088 1089 static int dp83822_led_hw_control_set(struct phy_device *phydev, u8 index, 1090 unsigned long rules) 1091 { 1092 int mode; 1093 1094 mode = dp83822_led_mode(index, rules); 1095 if (mode < 0) 1096 return mode; 1097 1098 if (index == DP83822_LED_INDEX_LED_0 || index == DP83822_LED_INDEX_COL_GPIO2) 1099 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, 1100 MII_DP83822_MLEDCR, DP83822_MLEDCR_CFG, 1101 FIELD_PREP(DP83822_MLEDCR_CFG, mode)); 1102 else if (index == DP83822_LED_INDEX_LED_1_GPIO1) 1103 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, 1104 MII_DP83822_LEDCFG1, 1105 DP83822_LEDCFG1_LED1_CTRL, 1106 FIELD_PREP(DP83822_LEDCFG1_LED1_CTRL, 1107 mode)); 1108 else 1109 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, 1110 MII_DP83822_LEDCFG1, 1111 DP83822_LEDCFG1_LED3_CTRL, 1112 FIELD_PREP(DP83822_LEDCFG1_LED3_CTRL, 1113 mode)); 1114 } 1115 1116 static int dp83822_led_hw_control_get(struct phy_device *phydev, u8 index, 1117 unsigned long *rules) 1118 { 1119 int val; 1120 1121 if (index == DP83822_LED_INDEX_LED_0 || index == DP83822_LED_INDEX_COL_GPIO2) { 1122 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_MLEDCR); 1123 if (val < 0) 1124 return val; 1125 1126 val = FIELD_GET(DP83822_MLEDCR_CFG, val); 1127 } else { 1128 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_LEDCFG1); 1129 if (val < 0) 1130 return val; 1131 1132 if (index == DP83822_LED_INDEX_LED_1_GPIO1) 1133 val = FIELD_GET(DP83822_LEDCFG1_LED1_CTRL, val); 1134 else 1135 val = FIELD_GET(DP83822_LEDCFG1_LED3_CTRL, val); 1136 } 1137 1138 switch (val) { 1139 case DP83822_LED_FN_LINK: 1140 *rules = BIT(TRIGGER_NETDEV_LINK); 1141 break; 1142 case DP83822_LED_FN_LINK_10_BT: 1143 *rules = BIT(TRIGGER_NETDEV_LINK_10); 1144 break; 1145 case DP83822_LED_FN_LINK_100_BTX: 1146 *rules = BIT(TRIGGER_NETDEV_LINK_100); 1147 break; 1148 case DP83822_LED_FN_FULL_DUPLEX: 1149 *rules = BIT(TRIGGER_NETDEV_FULL_DUPLEX); 1150 break; 1151 case DP83822_LED_FN_TX: 1152 *rules = BIT(TRIGGER_NETDEV_TX); 1153 break; 1154 case DP83822_LED_FN_RX: 1155 *rules = BIT(TRIGGER_NETDEV_RX); 1156 break; 1157 case DP83822_LED_FN_RX_TX: 1158 *rules = BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX); 1159 break; 1160 case DP83822_LED_FN_RX_TX_ERR: 1161 *rules = BIT(TRIGGER_NETDEV_TX_ERR) | BIT(TRIGGER_NETDEV_RX_ERR); 1162 break; 1163 case DP83822_LED_FN_LINK_RX_TX: 1164 *rules = BIT(TRIGGER_NETDEV_LINK) | BIT(TRIGGER_NETDEV_TX) | 1165 BIT(TRIGGER_NETDEV_RX); 1166 break; 1167 default: 1168 *rules = 0; 1169 break; 1170 } 1171 1172 return 0; 1173 } 1174 1175 #define DP83822_PHY_DRIVER(_id, _name) \ 1176 { \ 1177 PHY_ID_MATCH_MODEL(_id), \ 1178 .name = (_name), \ 1179 /* PHY_BASIC_FEATURES */ \ 1180 .probe = dp83822_probe, \ 1181 .soft_reset = dp83822_phy_reset, \ 1182 .config_init = dp83822_config_init, \ 1183 .read_status = dp83822_read_status, \ 1184 .get_wol = dp83822_get_wol, \ 1185 .set_wol = dp83822_set_wol, \ 1186 .config_intr = dp83822_config_intr, \ 1187 .handle_interrupt = dp83822_handle_interrupt, \ 1188 .suspend = dp83822_suspend, \ 1189 .resume = dp83822_resume, \ 1190 .led_hw_is_supported = dp83822_led_hw_is_supported, \ 1191 .led_hw_control_set = dp83822_led_hw_control_set, \ 1192 .led_hw_control_get = dp83822_led_hw_control_get, \ 1193 .attach_mdi_port = dp83822_attach_mdi_port \ 1194 } 1195 1196 #define DP83825_PHY_DRIVER(_id, _name) \ 1197 { \ 1198 PHY_ID_MATCH_MODEL(_id), \ 1199 .name = (_name), \ 1200 /* PHY_BASIC_FEATURES */ \ 1201 .probe = dp8382x_probe, \ 1202 .soft_reset = dp83822_phy_reset, \ 1203 .config_init = dp83825_config_init, \ 1204 .get_wol = dp83822_get_wol, \ 1205 .set_wol = dp83822_set_wol, \ 1206 .config_intr = dp83822_config_intr, \ 1207 .handle_interrupt = dp83822_handle_interrupt, \ 1208 .suspend = dp83822_suspend, \ 1209 .resume = dp83822_resume, \ 1210 } 1211 1212 #define DP83826_PHY_DRIVER(_id, _name) \ 1213 { \ 1214 PHY_ID_MATCH_MODEL(_id), \ 1215 .name = (_name), \ 1216 /* PHY_BASIC_FEATURES */ \ 1217 .probe = dp83826_probe, \ 1218 .soft_reset = dp83822_phy_reset, \ 1219 .config_init = dp83826_config_init, \ 1220 .get_wol = dp83822_get_wol, \ 1221 .set_wol = dp83822_set_wol, \ 1222 .config_intr = dp83822_config_intr, \ 1223 .handle_interrupt = dp83822_handle_interrupt, \ 1224 .suspend = dp83822_suspend, \ 1225 .resume = dp83822_resume, \ 1226 } 1227 1228 static struct phy_driver dp83822_driver[] = { 1229 DP83822_PHY_DRIVER(DP83822_PHY_ID, "TI DP83822"), 1230 DP83825_PHY_DRIVER(DP83825I_PHY_ID, "TI DP83825I"), 1231 DP83825_PHY_DRIVER(DP83825S_PHY_ID, "TI DP83825S"), 1232 DP83825_PHY_DRIVER(DP83825CM_PHY_ID, "TI DP83825M"), 1233 DP83825_PHY_DRIVER(DP83825CS_PHY_ID, "TI DP83825CS"), 1234 DP83826_PHY_DRIVER(DP83826C_PHY_ID, "TI DP83826C"), 1235 DP83826_PHY_DRIVER(DP83826NC_PHY_ID, "TI DP83826NC"), 1236 }; 1237 module_phy_driver(dp83822_driver); 1238 1239 static const struct mdio_device_id __maybe_unused dp83822_tbl[] = { 1240 { DP83822_PHY_ID, 0xfffffff0 }, 1241 { DP83825I_PHY_ID, 0xfffffff0 }, 1242 { DP83826C_PHY_ID, 0xfffffff0 }, 1243 { DP83826NC_PHY_ID, 0xfffffff0 }, 1244 { DP83825S_PHY_ID, 0xfffffff0 }, 1245 { DP83825CM_PHY_ID, 0xfffffff0 }, 1246 { DP83825CS_PHY_ID, 0xfffffff0 }, 1247 { }, 1248 }; 1249 MODULE_DEVICE_TABLE(mdio, dp83822_tbl); 1250 1251 MODULE_DESCRIPTION("Texas Instruments DP83822 PHY driver"); 1252 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com"); 1253 MODULE_LICENSE("GPL v2"); 1254