1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 /* FILE POLICY AND INTENDED USAGE:
27 * This file manages link detection states and receiver states by using various
28 * link protocols. It also provides helper functions to interpret certain
29 * capabilities or status based on the states it manages or retrieve them
30 * directly from connected receivers.
31 */
32
33 #include "link_dpms.h"
34 #include "link_detection.h"
35 #include "link_hwss.h"
36 #include "protocols/link_edp_panel_control.h"
37 #include "protocols/link_ddc.h"
38 #include "protocols/link_hpd.h"
39 #include "protocols/link_dpcd.h"
40 #include "protocols/link_dp_capability.h"
41 #include "protocols/link_dp_dpia.h"
42 #include "protocols/link_dp_phy.h"
43 #include "protocols/link_dp_training.h"
44 #include "protocols/link_hdmi_frl.h"
45 #include "protocols/link_dp_dpia_bw.h"
46 #include "accessories/link_dp_trace.h"
47
48 #include "link_enc_cfg.h"
49 #include "dm_helpers.h"
50 #include "clk_mgr.h"
51
52 // Offset DPCD 050Eh == 0x5A
53 #define MST_HUB_ID_0x5A 0x5A
54
55 #define DC_LOGGER \
56 link->ctx->logger
57 #define DC_LOGGER_INIT(logger)
58
59 #define LINK_INFO(...) \
60 DC_LOG_HW_HOTPLUG( \
61 __VA_ARGS__)
62 /*
63 * Some receivers fail to train on first try and are good
64 * on subsequent tries. 2 retries should be plenty. If we
65 * don't have a successful training then we don't expect to
66 * ever get one.
67 */
68 #define LINK_TRAINING_MAX_VERIFY_RETRY 2
69
70 static const u8 DP_SINK_BRANCH_DEV_NAME_7580[] = "7580\x80u";
71
72 static const u8 dp_hdmi_dongle_signature_str[] = "DP-HDMI ADAPTOR";
73
get_ddc_transaction_type(enum signal_type sink_signal)74 static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_signal)
75 {
76 enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
77
78 switch (sink_signal) {
79 case SIGNAL_TYPE_DVI_SINGLE_LINK:
80 case SIGNAL_TYPE_DVI_DUAL_LINK:
81 case SIGNAL_TYPE_HDMI_TYPE_A:
82 case SIGNAL_TYPE_HDMI_FRL:
83 case SIGNAL_TYPE_LVDS:
84 case SIGNAL_TYPE_RGB:
85 transaction_type = DDC_TRANSACTION_TYPE_I2C;
86 break;
87
88 case SIGNAL_TYPE_DISPLAY_PORT:
89 case SIGNAL_TYPE_EDP:
90 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
91 break;
92
93 case SIGNAL_TYPE_DISPLAY_PORT_MST:
94 /* MST does not use I2COverAux, but there is the
95 * SPECIAL use case for "immediate dwnstrm device
96 * access" (EPR#370830).
97 */
98 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
99 break;
100
101 default:
102 break;
103 }
104
105 return transaction_type;
106 }
107
get_basic_signal_type(struct graphics_object_id encoder,struct graphics_object_id downstream)108 static enum signal_type get_basic_signal_type(struct graphics_object_id encoder,
109 struct graphics_object_id downstream)
110 {
111 if (downstream.type == OBJECT_TYPE_CONNECTOR) {
112 switch (downstream.id) {
113 case CONNECTOR_ID_SINGLE_LINK_DVII:
114 switch (encoder.id) {
115 case ENCODER_ID_INTERNAL_DAC1:
116 case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
117 case ENCODER_ID_INTERNAL_DAC2:
118 case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
119 return SIGNAL_TYPE_RGB;
120 default:
121 return SIGNAL_TYPE_DVI_SINGLE_LINK;
122 }
123 break;
124 case CONNECTOR_ID_DUAL_LINK_DVII:
125 {
126 switch (encoder.id) {
127 case ENCODER_ID_INTERNAL_DAC1:
128 case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
129 case ENCODER_ID_INTERNAL_DAC2:
130 case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
131 return SIGNAL_TYPE_RGB;
132 default:
133 return SIGNAL_TYPE_DVI_DUAL_LINK;
134 }
135 }
136 break;
137 case CONNECTOR_ID_SINGLE_LINK_DVID:
138 return SIGNAL_TYPE_DVI_SINGLE_LINK;
139 case CONNECTOR_ID_DUAL_LINK_DVID:
140 return SIGNAL_TYPE_DVI_DUAL_LINK;
141 case CONNECTOR_ID_VGA:
142 return SIGNAL_TYPE_RGB;
143 case CONNECTOR_ID_HDMI_TYPE_A:
144 return SIGNAL_TYPE_HDMI_TYPE_A;
145 case CONNECTOR_ID_LVDS:
146 return SIGNAL_TYPE_LVDS;
147 case CONNECTOR_ID_DISPLAY_PORT:
148 case CONNECTOR_ID_USBC:
149 return SIGNAL_TYPE_DISPLAY_PORT;
150 case CONNECTOR_ID_EDP:
151 return SIGNAL_TYPE_EDP;
152 default:
153 return SIGNAL_TYPE_NONE;
154 }
155 }
156
157 return SIGNAL_TYPE_NONE;
158 }
159
160 /*
161 * @brief
162 * Detect output sink type
163 */
link_detect_sink_signal_type(struct dc_link * link,enum dc_detect_reason reason)164 static enum signal_type link_detect_sink_signal_type(struct dc_link *link,
165 enum dc_detect_reason reason)
166 {
167 enum signal_type result;
168 struct audio_support *aud_support;
169 struct graphics_object_id enc_id;
170
171 /* External DP bridges should use DP signal regardless of connector type. */
172 if (link->ext_enc_id.id)
173 return SIGNAL_TYPE_DISPLAY_PORT;
174
175 if (link->is_dig_mapping_flexible)
176 enc_id = (struct graphics_object_id){.id = ENCODER_ID_UNKNOWN};
177 else
178 enc_id = link->link_enc->id;
179 result = get_basic_signal_type(enc_id, link->link_id);
180
181 /* Use basic signal type for link without physical connector. */
182 if (link->ep_type != DISPLAY_ENDPOINT_PHY)
183 return result;
184
185 /*
186 * Internal digital encoder will detect only dongles
187 * that require digital signal
188 */
189
190 /*
191 * Detection mechanism is different
192 * for different native connectors.
193 * LVDS connector supports only LVDS signal;
194 * PCIE is a bus slot, the actual connector needs to be detected first;
195 * eDP connector supports only eDP signal;
196 * HDMI should check straps for audio
197 */
198 switch (link->link_id.id) {
199 case CONNECTOR_ID_HDMI_TYPE_A:
200 /*
201 * check audio support:
202 * if native HDMI is not supported, switch to DVI
203 */
204 aud_support = &link->dc->res_pool->audio_support;
205
206 if (!aud_support->hdmi_audio_native)
207 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
208 break;
209 case CONNECTOR_ID_DISPLAY_PORT:
210 case CONNECTOR_ID_USBC:
211 /*
212 * DP HPD short pulse. Passive DP dongle will not
213 * have short pulse
214 */
215 if (reason != DETECT_REASON_HPDRX) {
216 /*
217 * Check whether DP signal detected: if not -
218 * we assume signal is DVI; it could be corrected
219 * to HDMI after dongle detection
220 */
221 if (!dm_helpers_is_dp_sink_present(link))
222 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
223 }
224 break;
225 case CONNECTOR_ID_PCIE:
226 /* ZAZTODO implement PCIE add-on card detection */
227 break;
228 default:
229 break;
230 }
231
232 return result;
233 }
234
decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type,struct audio_support * audio_support)235 static enum signal_type decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type,
236 struct audio_support *audio_support)
237 {
238 enum signal_type signal = SIGNAL_TYPE_NONE;
239
240 switch (dongle_type) {
241 case DISPLAY_DONGLE_DP_HDMI_DONGLE:
242 if (audio_support->hdmi_audio_on_dongle)
243 signal = SIGNAL_TYPE_HDMI_TYPE_A;
244 else
245 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
246 break;
247 case DISPLAY_DONGLE_DP_DVI_DONGLE:
248 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
249 break;
250 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
251 if (audio_support->hdmi_audio_native)
252 signal = SIGNAL_TYPE_HDMI_TYPE_A;
253 else
254 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
255 break;
256 default:
257 signal = SIGNAL_TYPE_NONE;
258 break;
259 }
260
261 return signal;
262 }
263
read_scdc_caps(struct ddc_service * ddc_service,struct dc_sink * sink)264 static void read_scdc_caps(struct ddc_service *ddc_service,
265 struct dc_sink *sink)
266 {
267 uint8_t slave_address = HDMI_SCDC_ADDRESS;
268 uint8_t offset = HDMI_SCDC_MANUFACTURER_OUI;
269
270 if (ddc_service->link->local_sink &&
271 !ddc_service->link->local_sink->edid_caps.scdc_present)
272 return;
273
274 link_query_ddc_data(ddc_service, slave_address, &offset,
275 sizeof(offset), sink->scdc_caps.manufacturer_OUI.byte,
276 sizeof(sink->scdc_caps.manufacturer_OUI.byte));
277
278 offset = HDMI_SCDC_DEVICE_ID;
279
280 link_query_ddc_data(ddc_service, slave_address, &offset,
281 sizeof(offset), &(sink->scdc_caps.device_id.byte),
282 sizeof(sink->scdc_caps.device_id.byte));
283 }
284
i2c_read(struct ddc_service * ddc,uint32_t address,uint8_t * buffer,uint32_t len)285 static bool i2c_read(
286 struct ddc_service *ddc,
287 uint32_t address,
288 uint8_t *buffer,
289 uint32_t len)
290 {
291 uint8_t offs_data = 0;
292 struct i2c_payload payloads[2] = {
293 {
294 .write = true,
295 .address = (uint8_t)address,
296 .length = 1,
297 .data = &offs_data },
298 {
299 .write = false,
300 .address = (uint8_t)address,
301 .length = len,
302 .data = buffer } };
303
304 struct i2c_command command = {
305 .payloads = payloads,
306 .number_of_payloads = 2,
307 .engine = DDC_I2C_COMMAND_ENGINE,
308 .speed = ddc->ctx->dc->caps.i2c_speed_in_khz };
309
310 return dm_helpers_submit_i2c(
311 ddc->ctx,
312 ddc->link,
313 &command);
314 }
315
316 enum {
317 DP_SINK_CAP_SIZE =
318 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV + 1
319 };
320
query_dp_dual_mode_adaptor(struct ddc_service * ddc,struct display_sink_capability * sink_cap)321 static void query_dp_dual_mode_adaptor(
322 struct ddc_service *ddc,
323 struct display_sink_capability *sink_cap)
324 {
325 uint8_t i;
326 bool is_valid_hdmi_signature;
327 enum display_dongle_type *dongle = &sink_cap->dongle_type;
328 uint8_t type2_dongle_buf[DP_ADAPTOR_TYPE2_SIZE];
329 bool is_type2_dongle = false;
330 int retry_count = 2;
331 struct dp_hdmi_dongle_signature_data *dongle_signature;
332 struct dc_link *link = ddc->link;
333
334 /* Assume we have no valid DP passive dongle connected */
335 *dongle = DISPLAY_DONGLE_NONE;
336 sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_DVI_MAX_TMDS_CLK;
337
338 /* Read DP-HDMI dongle I2c (no response interpreted as DP-DVI dongle)*/
339 if (link->force_to_use_aux) {
340
341 if (!dm_helpers_submit_i2c_over_aux(
342 ddc,
343 DP_HDMI_DONGLE_ADDRESS,
344 0,
345 type2_dongle_buf,
346 sizeof(type2_dongle_buf),
347 true)) {
348
349 /* Use same approach as below with native i2c - HDMI dongles can sometimes fail here without retrying*/
350 while (retry_count > 0) {
351 if (dm_helpers_submit_i2c_over_aux(
352 ddc,
353 DP_HDMI_DONGLE_ADDRESS,
354 0,
355 type2_dongle_buf,
356 sizeof(type2_dongle_buf),
357 true))
358 break;
359 retry_count--;
360 }
361 /* In case I2C over Aux no response, it is interpreted as DISPLAY_DONGLE_NONE */
362 if (retry_count == 0) {
363 return;
364 }
365 }
366 } else {
367 if (!i2c_read(
368 ddc,
369 DP_HDMI_DONGLE_ADDRESS,
370 type2_dongle_buf,
371 sizeof(type2_dongle_buf))) {
372 /* Passive HDMI dongles can sometimes fail here without retrying*/
373 while (retry_count > 0) {
374 if (i2c_read(ddc,
375 DP_HDMI_DONGLE_ADDRESS,
376 type2_dongle_buf,
377 sizeof(type2_dongle_buf)))
378 break;
379 retry_count--;
380 }
381 if (retry_count == 0) {
382 *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
383 sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_DVI_MAX_TMDS_CLK;
384
385 CONN_DATA_DETECT(link, type2_dongle_buf, sizeof(type2_dongle_buf),
386 "DP-DVI passive dongle %dMhz: ",
387 DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000);
388 return;
389 }
390 }
391 }
392
393 /* Check if Type 2 dongle.*/
394 if (type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_ID] == DP_ADAPTOR_TYPE2_ID)
395 is_type2_dongle = true;
396
397 dongle_signature =
398 (struct dp_hdmi_dongle_signature_data *)type2_dongle_buf;
399
400 is_valid_hdmi_signature = true;
401
402 /* Check EOT */
403 if (dongle_signature->eot != DP_HDMI_DONGLE_SIGNATURE_EOT) {
404 is_valid_hdmi_signature = false;
405 }
406
407 /* Check signature */
408 for (i = 0; i < sizeof(dongle_signature->id); ++i) {
409 /* If its not the right signature,
410 * skip mismatch in subversion byte.*/
411 if (dongle_signature->id[i] !=
412 dp_hdmi_dongle_signature_str[i] && i != 3) {
413
414 if (is_type2_dongle) {
415 is_valid_hdmi_signature = false;
416 break;
417 }
418
419 }
420 }
421 if (is_valid_hdmi_signature)
422 sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_HDMI_SAFE_MAX_TMDS_CLK;
423
424 if (is_type2_dongle) {
425 uint32_t max_tmds_clk =
426 type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_MAX_TMDS_CLK];
427
428 max_tmds_clk = max_tmds_clk * 2 + max_tmds_clk / 2;
429
430 if (0 == max_tmds_clk ||
431 max_tmds_clk < DP_ADAPTOR_TYPE2_MIN_TMDS_CLK ||
432 max_tmds_clk > DP_ADAPTOR_TYPE2_MAX_TMDS_CLK) {
433 *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
434
435 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
436 sizeof(type2_dongle_buf),
437 "DP-DVI passive dongle %dMhz: ",
438 DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000);
439 } else {
440 if (is_valid_hdmi_signature == true) {
441 *dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE;
442
443 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
444 sizeof(type2_dongle_buf),
445 "Type 2 DP-HDMI passive dongle %dMhz: ",
446 max_tmds_clk);
447 } else {
448 *dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE;
449
450 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
451 sizeof(type2_dongle_buf),
452 "Type 2 DP-HDMI passive dongle (no signature) %dMhz: ",
453 max_tmds_clk);
454
455 }
456
457 /* Multiply by 1000 to convert to kHz. */
458 sink_cap->max_hdmi_pixel_clock =
459 max_tmds_clk * 1000;
460 }
461 sink_cap->is_dongle_type_one = false;
462
463 } else {
464 if (is_valid_hdmi_signature == true) {
465 *dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE;
466
467 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
468 sizeof(type2_dongle_buf),
469 "Type 1 DP-HDMI passive dongle %dMhz: ",
470 sink_cap->max_hdmi_pixel_clock / 1000);
471 } else {
472 *dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE;
473
474 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
475 sizeof(type2_dongle_buf),
476 "Type 1 DP-HDMI passive dongle (no signature) %dMhz: ",
477 sink_cap->max_hdmi_pixel_clock / 1000);
478 }
479 sink_cap->is_dongle_type_one = true;
480 }
481
482 return;
483 }
484
dp_passive_dongle_detection(struct ddc_service * ddc,struct display_sink_capability * sink_cap,struct audio_support * audio_support)485 static enum signal_type dp_passive_dongle_detection(struct ddc_service *ddc,
486 struct display_sink_capability *sink_cap,
487 struct audio_support *audio_support)
488 {
489 query_dp_dual_mode_adaptor(ddc, sink_cap);
490
491 return decide_signal_from_strap_and_dongle_type(sink_cap->dongle_type,
492 audio_support);
493 }
494
link_disconnect_sink(struct dc_link * link)495 static void link_disconnect_sink(struct dc_link *link)
496 {
497 if (link->local_sink) {
498 dc_sink_release(link->local_sink);
499 link->local_sink = NULL;
500 }
501
502 link->dpcd_sink_count = 0;
503 //link->dpcd_caps.dpcd_rev.raw = 0;
504 }
505
link_disconnect_remap(struct dc_sink * prev_sink,struct dc_link * link)506 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
507 {
508 dc_sink_release(link->local_sink);
509 link->local_sink = prev_sink;
510 }
511
query_hdcp_capability(enum signal_type signal,struct dc_link * link)512 static void query_hdcp_capability(enum signal_type signal, struct dc_link *link)
513 {
514 struct hdcp_protection_message msg22;
515 struct hdcp_protection_message msg14;
516
517 memset(&msg22, 0, sizeof(struct hdcp_protection_message));
518 memset(&msg14, 0, sizeof(struct hdcp_protection_message));
519 memset(link->hdcp_caps.rx_caps.raw, 0,
520 sizeof(link->hdcp_caps.rx_caps.raw));
521
522 if ((link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
523 link->ddc->transaction_type ==
524 DDC_TRANSACTION_TYPE_I2C_OVER_AUX) ||
525 link->connector_signal == SIGNAL_TYPE_EDP) {
526 msg22.data = link->hdcp_caps.rx_caps.raw;
527 msg22.length = sizeof(link->hdcp_caps.rx_caps.raw);
528 msg22.msg_id = HDCP_MESSAGE_ID_RX_CAPS;
529 if (link->force_to_use_aux && (signal == SIGNAL_TYPE_HDMI_TYPE_A)) {
530 // case with passive dongle with i2c over aux
531 msg22.data = &link->hdcp_caps.rx_caps.fields.version;
532 msg22.length = sizeof(link->hdcp_caps.rx_caps.fields.version);
533 msg22.msg_id = HDCP_MESSAGE_ID_HDCP2VERSION;
534 }
535 } else {
536 msg22.data = &link->hdcp_caps.rx_caps.fields.version;
537 msg22.length = sizeof(link->hdcp_caps.rx_caps.fields.version);
538 msg22.msg_id = HDCP_MESSAGE_ID_HDCP2VERSION;
539 }
540 msg22.version = HDCP_VERSION_22;
541 msg22.link = HDCP_LINK_PRIMARY;
542 msg22.max_retries = 5;
543 dc_process_hdcp_msg(signal, link, &msg22);
544
545 if (signal == SIGNAL_TYPE_DISPLAY_PORT || signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
546 msg14.data = &link->hdcp_caps.bcaps.raw;
547 msg14.length = sizeof(link->hdcp_caps.bcaps.raw);
548 msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS;
549 msg14.version = HDCP_VERSION_14;
550 msg14.link = HDCP_LINK_PRIMARY;
551 msg14.max_retries = 5;
552
553 dc_process_hdcp_msg(signal, link, &msg14);
554 }
555
556 }
read_current_link_settings_on_detect(struct dc_link * link)557 static void read_current_link_settings_on_detect(struct dc_link *link)
558 {
559 union lane_count_set lane_count_set = {0};
560 uint8_t link_bw_set = 0;
561 uint8_t link_rate_set = 0;
562 uint32_t read_dpcd_retry_cnt = 10;
563 enum dc_status status = DC_ERROR_UNEXPECTED;
564 unsigned int i;
565 union max_down_spread max_down_spread = {0};
566
567 // Read DPCD 00101h to find out the number of lanes currently set
568 for (i = 0; i < read_dpcd_retry_cnt; i++) {
569 status = core_link_read_dpcd(link,
570 DP_LANE_COUNT_SET,
571 &lane_count_set.raw,
572 sizeof(lane_count_set));
573 /* First DPCD read after VDD ON can fail if the particular board
574 * does not have HPD pin wired correctly. So if DPCD read fails,
575 * which it should never happen, retry a few times. Target worst
576 * case scenario of 80 ms.
577 */
578 if (status == DC_OK) {
579 link->cur_link_settings.lane_count =
580 lane_count_set.bits.LANE_COUNT_SET;
581 break;
582 }
583
584 msleep(8);
585 }
586
587 // Read DPCD 00100h to find if standard link rates are set
588 core_link_read_dpcd(link, DP_LINK_BW_SET,
589 &link_bw_set, sizeof(link_bw_set));
590
591 if (link_bw_set == 0) {
592 if (link->connector_signal == SIGNAL_TYPE_EDP) {
593 /* If standard link rates are not being used,
594 * Read DPCD 00115h to find the edp link rate set used
595 */
596 core_link_read_dpcd(link, DP_LINK_RATE_SET,
597 &link_rate_set, sizeof(link_rate_set));
598
599 // edp_supported_link_rates_count = 0 for DP
600 if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
601 link->cur_link_settings.link_rate =
602 link->dpcd_caps.edp_supported_link_rates[link_rate_set];
603 link->cur_link_settings.link_rate_set = link_rate_set;
604 link->cur_link_settings.use_link_rate_set = true;
605 }
606 } else {
607 // Link Rate not found. Seamless boot may not work.
608 ASSERT(false);
609 }
610 } else {
611 link->cur_link_settings.link_rate = link_bw_set;
612 link->cur_link_settings.use_link_rate_set = false;
613 }
614 // Read DPCD 00003h to find the max down spread.
615 core_link_read_dpcd(link, DP_MAX_DOWNSPREAD,
616 &max_down_spread.raw, sizeof(max_down_spread));
617 link->cur_link_settings.link_spread =
618 max_down_spread.bits.MAX_DOWN_SPREAD ?
619 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
620 }
621
detect_dp(struct dc_link * link,struct display_sink_capability * sink_caps,enum dc_detect_reason reason)622 static bool detect_dp(struct dc_link *link,
623 struct display_sink_capability *sink_caps,
624 enum dc_detect_reason reason)
625 {
626 struct audio_support *audio_support = &link->dc->res_pool->audio_support;
627
628 sink_caps->signal = link_detect_sink_signal_type(link, reason);
629 sink_caps->transaction_type =
630 get_ddc_transaction_type(sink_caps->signal);
631
632 if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
633 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
634 if (!detect_dp_sink_caps(link)) {
635 if (link->force_to_use_aux) {
636 sink_caps->signal = dp_passive_dongle_detection(link->ddc, sink_caps, audio_support);
637 link->dpcd_caps.dongle_type = sink_caps->dongle_type;
638 link->dpcd_caps.is_dongle_type_one = sink_caps->is_dongle_type_one;
639 link->dpcd_caps.dpcd_rev.raw = 0;
640 /* Type 1 dongles do not work with I2C over Aux and also some of
641 * Type 2 dongles do not support I2C over Aux well, so for these
642 * cases when native Aux transactons fails and I2C over Aux fails
643 * report that nothing is connected, as we can't tell is it bad
644 * DP sink or bad passive dongle.
645 */
646 if (sink_caps->dongle_type == DISPLAY_DONGLE_NONE)
647 return false;
648 else
649 return true;
650 } else {
651 return false;
652 }
653 }
654
655 if (is_dp_branch_device(link))
656 /* DP SST branch */
657 link->type = dc_connection_sst_branch;
658 } else {
659 if (link->dc->debug.disable_dp_plus_plus_wa &&
660 link->link_enc->features.flags.bits.IS_UHBR20_CAPABLE)
661 return false;
662
663 /* DP passive dongles */
664 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
665 sink_caps,
666 audio_support);
667 link->dpcd_caps.dongle_type = sink_caps->dongle_type;
668 link->dpcd_caps.is_dongle_type_one = sink_caps->is_dongle_type_one;
669 link->dpcd_caps.dpcd_rev.raw = 0;
670 link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.raw = 0;
671 }
672
673 if (link->ext_enc_id.id) {
674 /* Fix number of connected sinks reported by external DP bridge */
675 link->dpcd_caps.sink_count.bits.SINK_COUNT = 1;
676 /* NUTMEG requires that we use HBR, doesn't work with RBR. */
677 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_00001A)
678 link->wa_flags.dp_skip_rbr = true;
679 }
680
681 return true;
682 }
683
is_same_edid(struct dc_edid * old_edid,struct dc_edid * new_edid)684 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
685 {
686 if (old_edid == NULL || new_edid == NULL)
687 return false;
688
689 if (old_edid->length != new_edid->length)
690 return false;
691
692 if (new_edid->length == 0)
693 return false;
694
695 return (memcmp(old_edid->raw_edid,
696 new_edid->raw_edid, new_edid->length) == 0);
697 }
698
wait_for_entering_dp_alt_mode(struct dc_link * link)699 static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
700 {
701
702 /**
703 * something is terribly wrong if time out is > 200ms. (5Hz)
704 * 500 microseconds * 400 tries us 200 ms
705 **/
706 unsigned int sleep_time_in_microseconds = 500;
707 unsigned int tries_allowed = 400;
708 bool is_in_alt_mode;
709 unsigned long long enter_timestamp;
710 unsigned long long finish_timestamp;
711 unsigned long long time_taken_in_ns;
712 unsigned int tries_taken;
713
714 /**
715 * this function will only exist if we are on dcn21 (is_in_alt_mode is a
716 * function pointer, so checking to see if it is equal to 0 is the same
717 * as checking to see if it is null
718 **/
719 if (!link->link_enc->funcs->is_in_alt_mode)
720 return true;
721
722 is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
723 DC_LOG_DC("DP Alt mode state on HPD: %d Link=%d\n", is_in_alt_mode, link->link_index);
724
725 if (is_in_alt_mode)
726 return true;
727
728 enter_timestamp = dm_get_timestamp(link->ctx);
729
730 for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
731 udelay(sleep_time_in_microseconds);
732 /* ask the link if alt mode is enabled, if so return ok */
733 if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
734 finish_timestamp = dm_get_timestamp(link->ctx);
735 time_taken_in_ns =
736 dm_get_elapse_time_in_ns(link->ctx,
737 finish_timestamp,
738 enter_timestamp);
739 DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
740 div_u64(time_taken_in_ns, 1000000));
741 return true;
742 }
743 }
744 finish_timestamp = dm_get_timestamp(link->ctx);
745 time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
746 enter_timestamp);
747 DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
748 div_u64(time_taken_in_ns, 1000000));
749 return false;
750 }
751
apply_dpia_mst_dsc_always_on_wa(struct dc_link * link)752 static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link)
753 {
754 /* Apply work around for tunneled MST on certain USB4 docks. Always use DSC if dock
755 * reports DSC support.
756 */
757 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
758 link->type == dc_connection_mst_branch &&
759 link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
760 link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_20 &&
761 link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&
762 !link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around)
763 link->wa_flags.dpia_mst_dsc_always_on = true;
764
765 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
766 link->type == dc_connection_mst_branch &&
767 link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
768 link->dpcd_caps.branch_vendor_specific_data[2] == MST_HUB_ID_0x5A &&
769 link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&
770 !link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around) {
771 link->wa_flags.dpia_mst_dsc_always_on = true;
772 }
773 }
774
revert_dpia_mst_dsc_always_on_wa(struct dc_link * link)775 static void revert_dpia_mst_dsc_always_on_wa(struct dc_link *link)
776 {
777 /* Disable work around which keeps DSC on for tunneled MST on certain USB4 docks. */
778 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
779 link->wa_flags.dpia_mst_dsc_always_on = false;
780 }
781
discover_dp_mst_topology(struct dc_link * link,enum dc_detect_reason reason)782 static bool discover_dp_mst_topology(struct dc_link *link, enum dc_detect_reason reason)
783 {
784 LINK_INFO("link=%d, mst branch is now Connected\n",
785 link->link_index);
786
787 link->type = dc_connection_mst_branch;
788 apply_dpia_mst_dsc_always_on_wa(link);
789
790 dm_helpers_dp_update_branch_info(link->ctx, link);
791 if (dm_helpers_dp_mst_start_top_mgr(link->ctx,
792 link, (reason == DETECT_REASON_BOOT || reason == DETECT_REASON_RESUMEFROMS3S4))) {
793 link_disconnect_sink(link);
794 } else {
795 link->type = dc_connection_sst_branch;
796 }
797
798 return link->type == dc_connection_mst_branch;
799 }
800
link_reset_cur_dp_mst_topology(struct dc_link * link)801 bool link_reset_cur_dp_mst_topology(struct dc_link *link)
802 {
803 LINK_INFO("link=%d, mst branch is now Disconnected\n",
804 link->link_index);
805
806 revert_dpia_mst_dsc_always_on_wa(link);
807 return dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
808 }
809
should_prepare_phy_clocks_for_link_verification(const struct dc * dc,enum dc_detect_reason reason)810 static bool should_prepare_phy_clocks_for_link_verification(const struct dc *dc,
811 enum dc_detect_reason reason)
812 {
813 int i;
814 bool can_apply_seamless_boot = false;
815
816 for (i = 0; i < dc->current_state->stream_count; i++) {
817 if (dc->current_state->streams[i]->apply_seamless_boot_optimization) {
818 can_apply_seamless_boot = true;
819 break;
820 }
821 }
822
823 return !can_apply_seamless_boot && reason != DETECT_REASON_BOOT;
824 }
825
is_hdmi_frl_in_use(struct dc_link * link)826 static bool is_hdmi_frl_in_use(struct dc_link *link)
827 {
828 int i;
829 unsigned int hdmi_conn_count = 0;
830 unsigned int hdmi_stream_count = 0;
831 bool hdmi_frl_in_use = false;
832 bool incoming_link_identical = false;
833
834 /*Enumerate HDMI connector from all present links */
835 for (i = 0; i < link->dc->link_count; i++) {
836 if (link->dc->links[i] != NULL &&
837 dc_is_hdmi_signal(link->dc->links[i]->connector_signal))
838 hdmi_conn_count++;
839 }
840 /* If less than 2 HDMI Connector, assume HPO is always available*/
841 if (hdmi_conn_count < 2)
842 return false;
843
844 /*Enumerate existing HDMI stream count*/
845 for (i = 0; i < link->dc->current_state->stream_count; i++) {
846 if (dc_is_hdmi_signal(link->dc->current_state->streams[i]->signal))
847 hdmi_stream_count++;
848 if (link == link->dc->current_state->streams[i]->link &&
849 (dc_is_hdmi_frl_signal(link->dc->current_state->streams[i]->signal)))
850 incoming_link_identical = true;
851 }
852
853 if (hdmi_stream_count > 1 || (hdmi_stream_count == 1 && !incoming_link_identical)) {
854 for (i = 0; i < link->dc->current_state->stream_count; i++) {
855 if (dc_is_hdmi_frl_signal(
856 link->dc->current_state->streams[i]->signal)) {
857 hdmi_frl_in_use = true;
858 break;
859 }
860 }
861 }
862
863 /* Check if previous link already has been assigned with FRL*/
864 if (!hdmi_frl_in_use && !incoming_link_identical) {
865 for (i = 0; i < link->dc->link_count; i++) {
866 if (link->dc->links[i] != NULL &&
867 link->dc->links[i]->local_sink != NULL &&
868 link != link->dc->links[i] &&
869 dc_is_hdmi_frl_signal(
870 link->dc->links[i]->local_sink->sink_signal)) {
871 hdmi_frl_in_use = true;
872 break;
873 }
874 }
875 }
876
877 return hdmi_frl_in_use;
878 }
879
prepare_phy_clocks_for_destructive_link_verification(const struct dc * dc)880 static void prepare_phy_clocks_for_destructive_link_verification(const struct dc *dc)
881 {
882 dc_z10_restore(dc);
883 clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
884 }
885
restore_phy_clocks_for_destructive_link_verification(const struct dc * dc)886 static void restore_phy_clocks_for_destructive_link_verification(const struct dc *dc)
887 {
888 clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
889 }
890
verify_link_capability_destructive(struct dc_link * link,enum dc_detect_reason reason)891 static void verify_link_capability_destructive(struct dc_link *link,
892 enum dc_detect_reason reason)
893 {
894 bool should_prepare_phy_clocks =
895 should_prepare_phy_clocks_for_link_verification(link->dc, reason);
896
897 if (should_prepare_phy_clocks)
898 prepare_phy_clocks_for_destructive_link_verification(link->dc);
899
900 if (dc_is_dp_signal(link->local_sink->sink_signal)) {
901 struct dc_link_settings known_limit_link_setting =
902 dp_get_max_link_cap(link);
903 link_set_all_streams_dpms_off_for_link(link);
904 dp_verify_link_cap_with_retries(
905 link, &known_limit_link_setting,
906 LINK_TRAINING_MAX_VERIFY_RETRY);
907 } else if (dc_is_hdmi_signal(link->local_sink->sink_signal)) {
908 if (!is_hdmi_frl_in_use(link)) {
909 link_set_all_streams_dpms_off_for_link(link);
910 hdmi_frl_verify_link_cap(link, &link->frl_reported_link_cap);
911 link->local_sink->sink_signal = (link->frl_verified_link_cap.frl_link_rate != HDMI_FRL_LINK_RATE_DISABLE)
912 ? SIGNAL_TYPE_HDMI_FRL : SIGNAL_TYPE_HDMI_TYPE_A;
913 } else {
914 link->local_sink->sink_signal = SIGNAL_TYPE_HDMI_TYPE_A;
915 link->frl_verified_link_cap.frl_link_rate = HDMI_FRL_LINK_RATE_DISABLE;
916 }
917 } else {
918 ASSERT(0);
919 }
920
921 if (should_prepare_phy_clocks)
922 restore_phy_clocks_for_destructive_link_verification(link->dc);
923 }
924
verify_link_capability_non_destructive(struct dc_link * link)925 static void verify_link_capability_non_destructive(struct dc_link *link)
926 {
927 if (dc_is_dp_signal(link->local_sink->sink_signal)) {
928 if (dc_is_embedded_signal(link->local_sink->sink_signal) ||
929 link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
930 /* TODO - should we check link encoder's max link caps here?
931 * How do we know which link encoder to check from?
932 */
933 link->verified_link_cap = link->reported_link_cap;
934 else
935 link->verified_link_cap = dp_get_max_link_cap(link);
936 } else if (dc_is_hdmi_signal(link->local_sink->sink_signal)) {
937 link->verified_link_cap = link->reported_link_cap;
938
939 if (is_hdmi_frl_in_use(link)) {
940 link->local_sink->sink_signal = SIGNAL_TYPE_HDMI_TYPE_A;
941 link->frl_verified_link_cap.frl_link_rate = HDMI_FRL_LINK_RATE_DISABLE;
942 }
943 }
944 }
945
should_verify_link_capability_destructively(struct dc_link * link,enum dc_detect_reason reason)946 static bool should_verify_link_capability_destructively(struct dc_link *link,
947 enum dc_detect_reason reason)
948 {
949 (void)reason;
950 bool destrictive = false;
951 struct dc_link_settings max_link_cap;
952 bool is_link_enc_unavailable = false;
953
954 if (!link->dc->config.unify_link_enc_assignment)
955 is_link_enc_unavailable = link->link_enc &&
956 link->dc->res_pool->funcs->link_encs_assign &&
957 !link_enc_cfg_is_link_enc_avail(
958 link->ctx->dc,
959 link->link_enc->preferred_engine,
960 link);
961
962 if (dc_is_dp_signal(link->local_sink->sink_signal)) {
963 max_link_cap = dp_get_max_link_cap(link);
964 destrictive = true;
965
966 if (link->dc->debug.skip_detection_link_training ||
967 dc_is_embedded_signal(link->local_sink->sink_signal) ||
968 (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
969 !link->dc->config.enable_dpia_pre_training)) {
970 destrictive = false;
971 } else if (link_dp_get_encoding_format(&max_link_cap) ==
972 DP_8b_10b_ENCODING) {
973 if (link->dpcd_caps.is_mst_capable ||
974 is_link_enc_unavailable) {
975 destrictive = false;
976 }
977 }
978 } else if (dc_is_hdmi_signal(link->local_sink->sink_signal) && link->link_enc &&
979 link->link_enc->features.flags.bits.IS_HDMI_FRL_CAPABLE &&
980 link->local_sink->edid_caps.max_frl_rate != 0) {
981 int i = 0;
982 struct pipe_ctx *pipes =
983 link->dc->current_state->res_ctx.pipe_ctx;
984
985 destrictive = true;
986 if (is_hdmi_frl_in_use(link)) {
987 destrictive = false;
988 } else if (link->local_sink->edid_caps.panel_patch.skip_frl_pre_training) {
989 for (i = 0; i < MAX_PIPES; i++) {
990 if (pipes[i].stream != NULL &&
991 pipes[i].stream->link == link) {
992 /*If link is already active, skip PHY programming*/
993 if (link->link_status.link_active) {
994 destrictive = false;
995 }
996 }
997 }
998 }
999 }
1000
1001 return destrictive;
1002 }
1003
verify_link_capability(struct dc_link * link,enum dc_detect_reason reason)1004 static void verify_link_capability(struct dc_link *link,
1005 enum dc_detect_reason reason)
1006 {
1007 if (should_verify_link_capability_destructively(link, reason))
1008 verify_link_capability_destructive(link, reason);
1009 else
1010 verify_link_capability_non_destructive(link);
1011 }
1012
1013 /**
1014 * link_detect_evaluate_edid_header() - Evaluate if an EDID header is acceptable.
1015 *
1016 * Evaluates an 8-byte EDID header to check if it's good enough
1017 * for the purpose of determining whether a display is connected
1018 * without reading the full EDID.
1019 *
1020 * @edid_header: The first 8 bytes of the EDID read from DDC.
1021 *
1022 * Return: true if the header looks valid (>= 6 of 8 bytes match the
1023 * expected 00/FF pattern), false otherwise.
1024 */
link_detect_evaluate_edid_header(uint8_t edid_header[8])1025 static bool link_detect_evaluate_edid_header(uint8_t edid_header[8])
1026 {
1027 int edid_header_score = 0;
1028 int i;
1029
1030 for (i = 0; i < 8; ++i)
1031 edid_header_score += edid_header[i] == ((i == 0 || i == 7) ? 0x00 : 0xff);
1032
1033 return edid_header_score >= 6;
1034 }
1035
1036 /**
1037 * link_detect_ddc_probe() - Probe the DDC to see if a display is connected.
1038 *
1039 * Detect whether a display is connected to DDC without reading full EDID.
1040 * Reads only the EDID header (the first 8 bytes of EDID) from DDC and
1041 * evaluates whether that matches.
1042 *
1043 * @link: DC link whose DDC/I2C is probed for the EDID header.
1044 *
1045 * Return: true if the EDID header was read and passes validation,
1046 * false otherwise.
1047 */
link_detect_ddc_probe(struct dc_link * link)1048 static bool link_detect_ddc_probe(struct dc_link *link)
1049 {
1050 enum signal_type signal = link_detect_sink_signal_type(link, DETECT_REASON_HPD);
1051 enum ddc_transaction_type transaction_type = get_ddc_transaction_type(signal);
1052 uint8_t edid_header[8] = {0};
1053 uint8_t zero = 0;
1054 bool ddc_probed;
1055
1056 if (!link->ddc)
1057 return false;
1058
1059 if (link->dc->hwss.prepare_ddc)
1060 link->dc->hwss.prepare_ddc(link);
1061
1062 set_ddc_transaction_type(link->ddc, transaction_type);
1063
1064 ddc_probed = link_query_ddc_data(link->ddc, 0x50, &zero, 1, edid_header, sizeof(edid_header));
1065
1066 if (!ddc_probed)
1067 return false;
1068
1069 if (!link_detect_evaluate_edid_header(edid_header))
1070 return false;
1071
1072 return true;
1073 }
1074
1075 /**
1076 * link_detect_dac_load_detect() - Performs DAC load detection.
1077 *
1078 * Load detection can be used to detect the presence of an
1079 * analog display when we can't read DDC. This causes a visible
1080 * visual glitch so it should be used sparingly.
1081 *
1082 * @link: DC link to test using the DAC load-detect path.
1083 *
1084 * Return: true if the VBIOS load-detect call reports OK, false
1085 * otherwise.
1086 */
link_detect_dac_load_detect(struct dc_link * link)1087 static bool link_detect_dac_load_detect(struct dc_link *link)
1088 {
1089 if (!link->dc->hwss.dac_load_detect)
1090 return false;
1091
1092 return link->dc->hwss.dac_load_detect(link);
1093 }
1094
1095 /*
1096 * detect_link_and_local_sink() - Detect if a sink is attached to a given link
1097 *
1098 * link->local_sink is created or destroyed as needed.
1099 *
1100 * This does not create remote sinks.
1101 */
detect_link_and_local_sink(struct dc_link * link,enum dc_detect_reason reason)1102 static bool detect_link_and_local_sink(struct dc_link *link,
1103 enum dc_detect_reason reason)
1104 {
1105 struct dc_sink_init_data sink_init_data = { 0 };
1106 struct display_sink_capability sink_caps = { 0 };
1107 uint32_t i;
1108 bool converter_disable_audio = false;
1109 struct audio_support *aud_support = &link->dc->res_pool->audio_support;
1110 bool same_edid = false;
1111 enum dc_edid_status edid_status;
1112 struct dc_context *dc_ctx = link->ctx;
1113 struct dc *dc = dc_ctx->dc;
1114 struct dc_sink *sink = NULL;
1115 struct dc_sink *prev_sink = NULL;
1116 struct dpcd_caps prev_dpcd_caps;
1117 enum dc_connection_type new_connection_type = dc_connection_none;
1118 const uint32_t post_oui_delay = 30; // 30ms
1119
1120 if (dc_is_virtual_signal(link->connector_signal))
1121 return false;
1122
1123 if (((link->connector_signal == SIGNAL_TYPE_LVDS ||
1124 link->connector_signal == SIGNAL_TYPE_EDP) &&
1125 (!link->dc->config.allow_edp_hotplug_detection)) &&
1126 link->local_sink) {
1127 // need to re-write OUI and brightness in resume case
1128 if (link->connector_signal == SIGNAL_TYPE_EDP &&
1129 (link->dpcd_sink_ext_caps.bits.oled == 1)) {
1130 dpcd_set_source_specific_data(link);
1131 msleep(post_oui_delay);
1132 set_default_brightness_aux(link);
1133 }
1134
1135 return true;
1136 }
1137
1138 if (!link_detect_connection_type(link, &new_connection_type)) {
1139 BREAK_TO_DEBUGGER();
1140 return false;
1141 }
1142
1143 prev_sink = link->local_sink;
1144 if (prev_sink) {
1145 dc_sink_retain(prev_sink);
1146 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
1147 }
1148
1149 link_disconnect_sink(link);
1150 if (new_connection_type != dc_connection_none) {
1151 link->type = new_connection_type;
1152 link->link_state_valid = false;
1153
1154 /* From Disconnected-to-Connected. */
1155 switch (link->connector_signal) {
1156 case SIGNAL_TYPE_HDMI_FRL:
1157 case SIGNAL_TYPE_HDMI_TYPE_A: {
1158 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1159 if (aud_support->hdmi_audio_native)
1160 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
1161 else
1162 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1163 break;
1164 }
1165
1166 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
1167 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1168 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1169 break;
1170 }
1171
1172 case SIGNAL_TYPE_DVI_DUAL_LINK: {
1173 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1174 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1175 break;
1176 }
1177
1178 case SIGNAL_TYPE_RGB: {
1179 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1180 sink_caps.signal = SIGNAL_TYPE_RGB;
1181 break;
1182 }
1183
1184 case SIGNAL_TYPE_LVDS: {
1185 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1186 sink_caps.signal = SIGNAL_TYPE_LVDS;
1187 break;
1188 }
1189
1190 case SIGNAL_TYPE_EDP: {
1191 detect_edp_sink_caps(link);
1192 read_current_link_settings_on_detect(link);
1193
1194 /* Disable power sequence on MIPI panel + converter
1195 */
1196 if (dc->config.enable_mipi_converter_optimization &&
1197 dc_ctx->dce_version == DCN_VERSION_3_01 &&
1198 link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_0022B9 &&
1199 memcmp(&link->dpcd_caps.branch_dev_name, DP_SINK_BRANCH_DEV_NAME_7580,
1200 sizeof(link->dpcd_caps.branch_dev_name)) == 0) {
1201 dc->config.edp_no_power_sequencing = true;
1202
1203 if (!link->dpcd_caps.set_power_state_capable_edp)
1204 link->wa_flags.dp_keep_receiver_powered = true;
1205 }
1206
1207 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
1208 sink_caps.signal = SIGNAL_TYPE_EDP;
1209 break;
1210 }
1211
1212 case SIGNAL_TYPE_DISPLAY_PORT: {
1213
1214 /* wa HPD high coming too early*/
1215 if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
1216 link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
1217
1218 /* if alt mode times out, return false */
1219 if (!wait_for_entering_dp_alt_mode(link)) {
1220 if (prev_sink)
1221 dc_sink_release(prev_sink);
1222 return false;
1223 }
1224 }
1225
1226 if (!detect_dp(link, &sink_caps, reason)) {
1227
1228 if (prev_sink)
1229 dc_sink_release(prev_sink);
1230 return false;
1231 }
1232
1233 /* Active SST downstream branch device unplug*/
1234 if (link->type == dc_connection_sst_branch &&
1235 link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
1236 if (prev_sink)
1237 /* Downstream unplug */
1238 dc_sink_release(prev_sink);
1239 return true;
1240 }
1241
1242 /* disable audio for non DP to HDMI active sst converter */
1243 if (link->type == dc_connection_sst_branch &&
1244 is_dp_active_dongle(link) &&
1245 (link->dpcd_caps.dongle_type !=
1246 DISPLAY_DONGLE_DP_HDMI_CONVERTER))
1247 converter_disable_audio = true;
1248
1249 /* limited link rate to HBR3 for DPIA until we implement USB4 V2 */
1250 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
1251 link->reported_link_cap.link_rate > LINK_RATE_HIGH3)
1252 link->reported_link_cap.link_rate = LINK_RATE_HIGH3;
1253
1254 if (link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling
1255 && link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc
1256 && link->dpcd_caps.usb4_dp_tun_info.driver_bw_cap.bits.driver_bw_alloc_support) {
1257 if (link_dpia_enable_usb4_dp_bw_alloc_mode(link) == false)
1258 link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc = false;
1259 }
1260 break;
1261 }
1262
1263 default:
1264 DC_ERROR("Invalid connector type! signal:%d\n",
1265 link->connector_signal);
1266 if (prev_sink)
1267 dc_sink_release(prev_sink);
1268 return false;
1269 } /* switch() */
1270
1271 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
1272 link->dpcd_sink_count =
1273 link->dpcd_caps.sink_count.bits.SINK_COUNT;
1274 else
1275 link->dpcd_sink_count = 1;
1276
1277 set_ddc_transaction_type(link->ddc,
1278 sink_caps.transaction_type);
1279
1280 link->aux_mode =
1281 link_is_in_aux_transaction_mode(link->ddc);
1282
1283 sink_init_data.link = link;
1284 sink_init_data.sink_signal = sink_caps.signal;
1285
1286 sink = dc_sink_create(&sink_init_data);
1287 if (!sink) {
1288 DC_ERROR("Failed to create sink!\n");
1289 if (prev_sink)
1290 dc_sink_release(prev_sink);
1291 return false;
1292 }
1293
1294 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
1295 sink->converter_disable_audio = converter_disable_audio;
1296
1297 /* dc_sink_create returns a new reference */
1298 link->local_sink = sink;
1299
1300 edid_status = dm_helpers_read_local_edid(link->ctx,
1301 link, sink);
1302
1303 switch (edid_status) {
1304 case EDID_BAD_CHECKSUM:
1305 DC_LOG_ERROR("EDID checksum invalid.\n");
1306 break;
1307 case EDID_PARTIAL_VALID:
1308 DC_LOG_ERROR("Partial EDID valid, abandon invalid blocks.\n");
1309 break;
1310 case EDID_NO_RESPONSE:
1311 /* Analog connectors without EDID:
1312 * - old monitor that actually doesn't have EDID
1313 * - cheap DVI-A cable or adapter that doesn't connect DDC
1314 */
1315 if (dc_connector_supports_analog(link->link_id.id)) {
1316 /* If we didn't already detect a display using
1317 * DAC load detection, we know it isn't connected.
1318 */
1319 if (link->type != dc_connection_analog_load) {
1320 if (prev_sink)
1321 dc_sink_release(prev_sink);
1322 link_disconnect_sink(link);
1323 return false;
1324 }
1325
1326 LINK_INFO("link=%d, analog display detected without EDID\n",
1327 link->link_index);
1328
1329 link->type = dc_connection_analog_load;
1330 sink->edid_caps.analog = true;
1331 break;
1332 }
1333
1334 DC_LOG_ERROR("No EDID read.\n");
1335
1336 /*
1337 * Abort detection for non-DP connectors if we have
1338 * no EDID
1339 *
1340 * DP needs to report as connected if HDP is high
1341 * even if we have no EDID in order to go to
1342 * fail-safe mode
1343 */
1344 if (dc_is_hdmi_signal(link->connector_signal) ||
1345 dc_is_dvi_signal(link->connector_signal)) {
1346 if (prev_sink)
1347 dc_sink_release(prev_sink);
1348
1349 return false;
1350 }
1351
1352 if (link->type == dc_connection_sst_branch &&
1353 link->dpcd_caps.dongle_type ==
1354 DISPLAY_DONGLE_DP_VGA_CONVERTER &&
1355 reason == DETECT_REASON_HPDRX) {
1356 /* Abort detection for DP-VGA adapters when EDID
1357 * can't be read and detection reason is VGA-side
1358 * hotplug
1359 */
1360 if (prev_sink)
1361 dc_sink_release(prev_sink);
1362 link_disconnect_sink(link);
1363
1364 return true;
1365 }
1366
1367 break;
1368 default:
1369 break;
1370 }
1371
1372 // Check if edid is the same
1373 if ((prev_sink) &&
1374 (edid_status == EDID_THE_SAME || edid_status == EDID_OK))
1375 same_edid = is_same_edid(&prev_sink->dc_edid,
1376 &sink->dc_edid);
1377
1378 if (sink->edid_caps.panel_patch.skip_scdc_overwrite)
1379 link->ctx->dc->debug.hdmi20_disable = true;
1380
1381 if (sink->edid_caps.panel_patch.remove_sink_ext_caps)
1382 link->dpcd_sink_ext_caps.raw = 0;
1383
1384 if (dc_is_hdmi_signal(link->connector_signal))
1385 read_scdc_caps(link->ddc, link->local_sink);
1386
1387 if (dc_is_hdmi_signal(link->connector_signal) && dc->debug.enable_hdmi_idcc) {
1388 memset(&link->hdmi_cable_id, 0, sizeof(union hdmi_idcc_cable_id));
1389 read_idcc_data(link->ddc, HDMI_IDCC_SCOPE_RW_CA,
1390 link->hdmi_cable_id.raw, 0, 4);
1391 }
1392 if (sink->edid_caps.rr_capable)
1393 hdmi_frl_write_read_request_enable(link->ddc);
1394 /* When FreeSync is toggled through OSD,
1395 * we see same EDID no matter what. Check MCCS caps
1396 * to see if we should update FreeSync caps now.
1397 */
1398 dm_helpers_read_mccs_caps(
1399 link->ctx,
1400 link,
1401 sink);
1402
1403 if (prev_sink != NULL) {
1404 if (memcmp(&sink->mccs_caps, &prev_sink->mccs_caps, sizeof(struct mccs_caps)))
1405 same_edid = false;
1406 }
1407
1408 if (reason != DETECT_REASON_FALLBACK && dc_is_hdmi_signal(link->connector_signal) &&
1409 link->link_enc->features.flags.bits.IS_HDMI_FRL_CAPABLE && sink->edid_caps.max_frl_rate != 0) {
1410 hdmi_frl_retrieve_link_cap(link, link->local_sink);
1411 }
1412 if (reason == DETECT_REASON_FALLBACK && sink->sink_signal == SIGNAL_TYPE_HDMI_FRL)
1413 same_edid = false;
1414 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
1415 sink_caps.transaction_type ==
1416 DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
1417 /*
1418 * TODO debug why certain monitors don't like
1419 * two link trainings
1420 */
1421 query_hdcp_capability(sink->sink_signal, link);
1422 } else {
1423 // If edid is the same, then discard new sink and revert back to original sink
1424 if (same_edid) {
1425 link_disconnect_remap(prev_sink, link);
1426 sink = prev_sink;
1427 prev_sink = NULL;
1428 if (reason == DETECT_REASON_FALLBACK && sink->sink_signal == SIGNAL_TYPE_HDMI_FRL)
1429 sink->sink_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1430 }
1431
1432 if (!sink->edid_caps.analog)
1433 query_hdcp_capability(sink->sink_signal, link);
1434 }
1435
1436 /* DVI-I connector connected to analog display. */
1437 if ((link->link_id.id == CONNECTOR_ID_DUAL_LINK_DVII ||
1438 link->link_id.id == CONNECTOR_ID_SINGLE_LINK_DVII) &&
1439 sink->edid_caps.analog)
1440 sink->sink_signal = SIGNAL_TYPE_RGB;
1441
1442 /* HDMI-DVI Dongle */
1443 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
1444 !sink->edid_caps.edid_hdmi)
1445 sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1446 else if (dc_is_dvi_signal(sink->sink_signal) &&
1447 dc_is_dvi_signal(link->connector_signal) &&
1448 aud_support->hdmi_audio_native &&
1449 sink->edid_caps.edid_hdmi)
1450 sink->sink_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1451
1452 if (link->local_sink && dc_is_dp_signal(sink_caps.signal))
1453 dp_trace_init(link);
1454
1455 /* Connectivity log: detection */
1456 for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) {
1457 CONN_DATA_DETECT(link,
1458 &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE],
1459 DC_EDID_BLOCK_SIZE,
1460 "%s: [Block %d] ", sink->edid_caps.display_name, i);
1461 }
1462
1463 DC_LOG_DETECTION_EDID_PARSER("%s: "
1464 "manufacturer_id = %X, "
1465 "product_id = %X, "
1466 "serial_number = %X, "
1467 "manufacture_week = %d, "
1468 "manufacture_year = %d, "
1469 "display_name = %s, "
1470 "speaker_flag = %d, "
1471 "audio_mode_count = %d\n",
1472 __func__,
1473 sink->edid_caps.manufacturer_id,
1474 sink->edid_caps.product_id,
1475 sink->edid_caps.serial_number,
1476 sink->edid_caps.manufacture_week,
1477 sink->edid_caps.manufacture_year,
1478 sink->edid_caps.display_name,
1479 sink->edid_caps.speaker_flags,
1480 sink->edid_caps.audio_mode_count);
1481
1482 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
1483 DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
1484 "format_code = %d, "
1485 "channel_count = %d, "
1486 "sample_rate = %d, "
1487 "sample_size = %d\n",
1488 __func__,
1489 i,
1490 sink->edid_caps.audio_modes[i].format_code,
1491 sink->edid_caps.audio_modes[i].channel_count,
1492 sink->edid_caps.audio_modes[i].sample_rate,
1493 sink->edid_caps.audio_modes[i].sample_size);
1494 }
1495
1496 if (link->connector_signal == SIGNAL_TYPE_EDP) {
1497 // Init dc_panel_config by HW config
1498 if (dc_ctx->dc->res_pool->funcs->get_panel_config_defaults)
1499 dc_ctx->dc->res_pool->funcs->get_panel_config_defaults(&link->panel_config);
1500 // Pickup base DM settings
1501 dm_helpers_init_panel_settings(dc_ctx, &link->panel_config, sink);
1502 // Override dc_panel_config if system has specific settings
1503 dm_helpers_override_panel_settings(dc_ctx, link);
1504
1505 //sink only can use supported link rate table, we are foreced to enable it
1506 if (link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)
1507 link->panel_config.ilr.optimize_edp_link_rate = true;
1508 link->reported_link_cap.link_rate = get_max_edp_link_rate(link);
1509 }
1510
1511 } else {
1512 /* From Connected-to-Disconnected. */
1513 link->type = dc_connection_none;
1514 sink_caps.signal = SIGNAL_TYPE_NONE;
1515 memset(&link->hdcp_caps, 0, sizeof(struct hdcp_caps));
1516 /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk
1517 * is not cleared. If we emulate a DP signal on this connection, it thinks
1518 * the dongle is still there and limits the number of modes we can emulate.
1519 * Clear dongle_max_pix_clk on disconnect to fix this
1520 */
1521 link->dongle_max_pix_clk = 0;
1522
1523 dc_link_clear_dprx_states(link);
1524 dp_trace_reset(link);
1525 }
1526
1527 LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p edid same=%d\n",
1528 link->link_index, sink,
1529 (sink_caps.signal ==
1530 SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"),
1531 prev_sink, same_edid);
1532
1533 if (prev_sink)
1534 dc_sink_release(prev_sink);
1535
1536 return true;
1537 }
1538
1539 /**
1540 * link_detect_connection_type_analog() - Determines if an analog sink is connected.
1541 *
1542 * @link: DC link to evaluate (must support analog signalling).
1543 * @type: Updated with the detected connection type:
1544 * dc_connection_single (analog via DDC),
1545 * dc_connection_analog_load (via load-detect),
1546 * or dc_connection_none.
1547 *
1548 * Return: true if detection completed.
1549 */
link_detect_connection_type_analog(struct dc_link * link,enum dc_connection_type * type)1550 static bool link_detect_connection_type_analog(struct dc_link *link, enum dc_connection_type *type)
1551 {
1552 /* Don't care about connectors that don't support an analog signal. */
1553 ASSERT(dc_connector_supports_analog(link->link_id.id));
1554
1555 if (link_detect_ddc_probe(link)) {
1556 *type = dc_connection_single;
1557 return true;
1558 }
1559
1560 if (link_detect_dac_load_detect(link)) {
1561 *type = dc_connection_analog_load;
1562 return true;
1563 }
1564
1565 *type = dc_connection_none;
1566 return true;
1567 }
1568
1569 /*
1570 * link_detect_connection_type() - Determine if there is a sink connected
1571 *
1572 * @type: Returned connection type
1573 * Does not detect downstream devices, such as MST sinks
1574 * or display connected through active dongles
1575 */
link_detect_connection_type(struct dc_link * link,enum dc_connection_type * type)1576 bool link_detect_connection_type(struct dc_link *link, enum dc_connection_type *type)
1577 {
1578 if (link->connector_signal == SIGNAL_TYPE_LVDS) {
1579 *type = dc_connection_single;
1580 return true;
1581 }
1582
1583 /* Ignore the HPD pin (if any) for analog connectors.
1584 * Instead rely on DDC and DAC.
1585 *
1586 * - VGA connectors don't have any HPD at all.
1587 * - Some DVI-A cables don't connect the HPD pin.
1588 * - Some DVI-A cables pull up the HPD pin.
1589 * (So it's high even when no display is connected.)
1590 */
1591 if (dc_connector_supports_analog(link->link_id.id))
1592 return link_detect_connection_type_analog(link, type);
1593
1594 if (link->connector_signal == SIGNAL_TYPE_EDP) {
1595 /*in case it is not on*/
1596 if (!link->dc->config.edp_no_power_sequencing)
1597 link->dc->hwss.edp_power_control(link, true);
1598 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1599 }
1600
1601 /* Link may not have physical HPD pin. */
1602 if (link->ep_type != DISPLAY_ENDPOINT_PHY) {
1603 if (link->is_hpd_pending || !dpia_query_hpd_status(link))
1604 *type = dc_connection_none;
1605 else
1606 *type = dc_connection_single;
1607
1608 return true;
1609 }
1610
1611
1612 if (link_get_hpd_state(link)) {
1613 *type = dc_connection_single;
1614 /* TODO: need to do the actual detection */
1615 } else {
1616 *type = dc_connection_none;
1617 if (link->connector_signal == SIGNAL_TYPE_EDP) {
1618 /* eDP is not connected, power down it */
1619 if (!link->dc->config.edp_no_power_sequencing)
1620 link->dc->hwss.edp_power_control(link, false);
1621 }
1622 }
1623
1624 return true;
1625 }
1626
link_detect(struct dc_link * link,enum dc_detect_reason reason)1627 bool link_detect(struct dc_link *link, enum dc_detect_reason reason)
1628 {
1629 bool is_local_sink_detect_success;
1630 bool is_delegated_to_mst_top_mgr = false;
1631 enum dc_connection_type pre_link_type = link->type;
1632
1633 is_local_sink_detect_success = detect_link_and_local_sink(link, reason);
1634
1635 if (is_local_sink_detect_success && link->local_sink) {
1636 verify_link_capability(link, reason);
1637 }
1638
1639 DC_LOG_DC("%s: link_index=%d is_local_sink_detect_success=%d pre_link_type=%d link_type=%d\n", __func__,
1640 link->link_index, is_local_sink_detect_success, pre_link_type, link->type);
1641
1642 if (is_local_sink_detect_success && link->local_sink &&
1643 dc_is_dp_signal(link->local_sink->sink_signal) &&
1644 link->dpcd_caps.is_mst_capable)
1645 is_delegated_to_mst_top_mgr = discover_dp_mst_topology(link, reason);
1646
1647 if (pre_link_type == dc_connection_mst_branch &&
1648 link->type != dc_connection_mst_branch)
1649 is_delegated_to_mst_top_mgr = link_reset_cur_dp_mst_topology(link);
1650
1651 return is_local_sink_detect_success && !is_delegated_to_mst_top_mgr;
1652 }
1653
link_clear_dprx_states(struct dc_link * link)1654 void link_clear_dprx_states(struct dc_link *link)
1655 {
1656 memset(&link->dprx_states, 0, sizeof(link->dprx_states));
1657 }
1658
link_is_hdcp14(struct dc_link * link,enum signal_type signal)1659 bool link_is_hdcp14(struct dc_link *link, enum signal_type signal)
1660 {
1661 bool ret = false;
1662
1663 switch (signal) {
1664 case SIGNAL_TYPE_DISPLAY_PORT:
1665 case SIGNAL_TYPE_DISPLAY_PORT_MST:
1666 ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE;
1667 break;
1668 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1669 case SIGNAL_TYPE_DVI_DUAL_LINK:
1670 case SIGNAL_TYPE_HDMI_TYPE_A:
1671 /* HDMI doesn't tell us its HDCP(1.4) capability, so assume to always be capable,
1672 * we can poll for bksv but some displays have an issue with this. Since its so rare
1673 * for a display to not be 1.4 capable, this assumtion is ok
1674 */
1675 ret = true;
1676 break;
1677 default:
1678 break;
1679 }
1680 return ret;
1681 }
1682
link_is_hdcp22(struct dc_link * link,enum signal_type signal)1683 bool link_is_hdcp22(struct dc_link *link, enum signal_type signal)
1684 {
1685 bool ret = false;
1686
1687 switch (signal) {
1688 case SIGNAL_TYPE_DISPLAY_PORT:
1689 case SIGNAL_TYPE_DISPLAY_PORT_MST:
1690 ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE &&
1691 link->hdcp_caps.rx_caps.fields.byte0.hdcp_capable &&
1692 (link->hdcp_caps.rx_caps.fields.version == 0x2)) ? 1 : 0;
1693 break;
1694 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1695 case SIGNAL_TYPE_DVI_DUAL_LINK:
1696 case SIGNAL_TYPE_HDMI_TYPE_A:
1697 case SIGNAL_TYPE_HDMI_FRL:
1698 ret = (link->hdcp_caps.rx_caps.fields.version == 0x4) ? 1:0;
1699 break;
1700 default:
1701 break;
1702 }
1703
1704 return ret;
1705 }
1706
link_get_status(const struct dc_link * link)1707 const struct dc_link_status *link_get_status(const struct dc_link *link)
1708 {
1709 return &link->link_status;
1710 }
1711
1712
link_add_remote_sink_helper(struct dc_link * dc_link,struct dc_sink * sink)1713 static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink)
1714 {
1715 if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
1716 BREAK_TO_DEBUGGER();
1717 return false;
1718 }
1719
1720 dc_sink_retain(sink);
1721
1722 dc_link->remote_sinks[dc_link->sink_count] = sink;
1723 dc_link->sink_count++;
1724
1725 return true;
1726 }
1727
link_add_remote_sink(struct dc_link * link,const uint8_t * edid,unsigned int len,struct dc_sink_init_data * init_data)1728 struct dc_sink *link_add_remote_sink(
1729 struct dc_link *link,
1730 const uint8_t *edid,
1731 unsigned int len,
1732 struct dc_sink_init_data *init_data)
1733 {
1734 struct dc_sink *dc_sink;
1735 enum dc_edid_status edid_status;
1736
1737 if (len > DC_MAX_EDID_BUFFER_SIZE) {
1738 dm_error("Max EDID buffer size breached!\n");
1739 return NULL;
1740 }
1741
1742 if (!init_data) {
1743 BREAK_TO_DEBUGGER();
1744 return NULL;
1745 }
1746
1747 if (!init_data->link) {
1748 BREAK_TO_DEBUGGER();
1749 return NULL;
1750 }
1751
1752 dc_sink = dc_sink_create(init_data);
1753
1754 if (!dc_sink)
1755 return NULL;
1756
1757 memmove(dc_sink->dc_edid.raw_edid, edid, len);
1758 dc_sink->dc_edid.length = len;
1759
1760 if (!link_add_remote_sink_helper(
1761 link,
1762 dc_sink))
1763 goto fail_add_sink;
1764
1765 edid_status = dm_helpers_parse_edid_caps(
1766 link,
1767 &dc_sink->dc_edid,
1768 &dc_sink->edid_caps);
1769
1770 /*
1771 * Treat device as no EDID device if EDID
1772 * parsing fails
1773 */
1774 if (edid_status != EDID_OK && edid_status != EDID_PARTIAL_VALID) {
1775 dc_sink->dc_edid.length = 0;
1776 dm_error("Bad EDID, status%d!\n", edid_status);
1777 }
1778
1779 return dc_sink;
1780
1781 fail_add_sink:
1782 dc_sink_release(dc_sink);
1783 return NULL;
1784 }
1785
link_remove_remote_sink(struct dc_link * link,struct dc_sink * sink)1786 void link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink)
1787 {
1788 unsigned int i;
1789
1790 if (!link->sink_count) {
1791 BREAK_TO_DEBUGGER();
1792 return;
1793 }
1794
1795 for (i = 0; i < link->sink_count; i++) {
1796 if (link->remote_sinks[i] == sink) {
1797 dc_sink_release(sink);
1798 link->remote_sinks[i] = NULL;
1799
1800 /* shrink array to remove empty place */
1801 while (i < link->sink_count - 1) {
1802 link->remote_sinks[i] = link->remote_sinks[i+1];
1803 i++;
1804 }
1805 link->remote_sinks[i] = NULL;
1806 link->sink_count--;
1807 return;
1808 }
1809 }
1810 }
1811