1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */
3
4 #ifndef _WX_TYPE_H_
5 #define _WX_TYPE_H_
6
7 #include <linux/ptp_clock_kernel.h>
8 #include <linux/timecounter.h>
9 #include <linux/bitfield.h>
10 #include <linux/netdevice.h>
11 #include <linux/if_vlan.h>
12 #include <linux/phylink.h>
13 #include <linux/dim.h>
14 #include <net/ip.h>
15
16 #define WX_NCSI_SUP 0x8000
17 #define WX_NCSI_MASK 0x8000
18 #define WX_WOL_SUP 0x4000
19 #define WX_WOL_MASK 0x4000
20
21 /* MSI-X capability fields masks */
22 #define WX_PCIE_MSIX_TBL_SZ_MASK 0x7FF
23 #define WX_PCI_LINK_STATUS 0xB2
24 #define WX_MAX_PF_MACVLANS 15
25 #define WX_MAX_VF_MC_ENTRIES 30
26
27 /**************** Global Registers ****************************/
28 #define WX_VF_REG_OFFSET(_v) FIELD_GET(GENMASK(15, 5), (_v))
29 #define WX_VF_IND_SHIFT(_v) FIELD_GET(GENMASK(4, 0), (_v))
30
31 /* chip control Registers */
32 #define WX_MIS_PWR 0x10000
33 #define WX_MIS_RST 0x1000C
34 #define WX_MIS_RST_LAN_RST(_i) BIT((_i) + 1)
35 #define WX_MIS_RST_SW_RST BIT(0)
36 #define WX_MIS_ST 0x10028
37 #define WX_MIS_ST_MNG_INIT_DN BIT(0)
38 #define WX_MIS_SWSM 0x1002C
39 #define WX_MIS_SWSM_SMBI BIT(0)
40 #define WX_MIS_RST_ST 0x10030
41 #define WX_MIS_RST_ST_RST_INI_SHIFT 8
42 #define WX_MIS_RST_ST_RST_INIT (0xFF << WX_MIS_RST_ST_RST_INI_SHIFT)
43
44 /* FMGR Registers */
45 #define WX_SPI_CMD 0x10104
46 #define WX_SPI_CMD_READ_DWORD 0x1
47 #define WX_SPI_CLK_DIV 0x3
48 #define WX_SPI_CMD_CMD(_v) FIELD_PREP(GENMASK(30, 28), _v)
49 #define WX_SPI_CMD_CLK(_v) FIELD_PREP(GENMASK(27, 25), _v)
50 #define WX_SPI_CMD_ADDR(_v) FIELD_PREP(GENMASK(23, 0), _v)
51 #define WX_SPI_DATA 0x10108
52 #define WX_SPI_DATA_BYPASS BIT(31)
53 #define WX_SPI_DATA_OP_DONE BIT(0)
54 #define WX_SPI_STATUS 0x1010C
55 #define WX_SPI_STATUS_OPDONE BIT(0)
56 #define WX_SPI_STATUS_FLASH_BYPASS BIT(31)
57 #define WX_SPI_ILDR_STATUS 0x10120
58
59 /* Sensors for PVT(Process Voltage Temperature) */
60 #define WX_TS_EN 0x10304
61 #define WX_TS_EN_ENA BIT(0)
62 #define WX_TS_ALARM_THRE 0x1030C
63 #define WX_TS_DALARM_THRE 0x10310
64 #define WX_TS_INT_EN 0x10314
65 #define WX_TS_INT_EN_DALARM_INT_EN BIT(1)
66 #define WX_TS_INT_EN_ALARM_INT_EN BIT(0)
67 #define WX_TS_ALARM_ST 0x10318
68 #define WX_TS_ALARM_ST_DALARM BIT(1)
69 #define WX_TS_ALARM_ST_ALARM BIT(0)
70
71 /* statistic */
72 #define WX_TX_FRAME_CNT_GOOD_BAD_L 0x1181C
73 #define WX_TX_BC_FRAMES_GOOD_L 0x11824
74 #define WX_TX_MC_FRAMES_GOOD_L 0x1182C
75 #define WX_RX_FRAME_CNT_GOOD_BAD_L 0x11900
76 #define WX_RX_BC_FRAMES_GOOD_L 0x11918
77 #define WX_RX_MC_FRAMES_GOOD_L 0x11920
78 #define WX_RX_CRC_ERROR_FRAMES_L 0x11928
79 #define WX_RX_LEN_ERROR_FRAMES_L 0x11978
80 #define WX_RX_UNDERSIZE_FRAMES_GOOD 0x11938
81 #define WX_RX_OVERSIZE_FRAMES_GOOD 0x1193C
82 #define WX_MAC_LXOFFRXC 0x11988
83 #define WX_MAC_LXONRXC 0x11E0C
84 #define WX_MAC_LXOFFRXC_AML 0x11F80
85 #define WX_MAC_LXONRXC_AML 0x11F84
86
87 /*********************** Receive DMA registers **************************/
88 #define WX_RDM_VF_RE(_i) (0x12004 + ((_i) * 4))
89 #define WX_RDM_RSC_CTL 0x1200C
90 #define WX_RDM_RSC_CTL_FREE_CNT_DIS BIT(8)
91 #define WX_RDM_RSC_CTL_FREE_CTL BIT(7)
92 #define WX_RDM_PF_QDE(_i) (0x12080 + ((_i) * 4))
93 #define WX_RDM_VFRE_CLR(_i) (0x120A0 + ((_i) * 4))
94 #define WX_RDM_DCACHE_CTL 0x120A8
95 #define WX_RDM_DCACHE_CTL_EN BIT(0)
96 #define WX_RDM_DRP_PKT 0x12500
97 #define WX_RDM_PKT_CNT 0x12504
98 #define WX_RDM_BYTE_CNT_LSB 0x12508
99 #define WX_RDM_BMC2OS_CNT 0x12510
100
101 /************************* Port Registers ************************************/
102 /* port cfg Registers */
103 #define WX_CFG_PORT_CTL 0x14400
104 #define WX_CFG_PORT_CTL_PFRSTD BIT(14)
105 #define WX_CFG_PORT_CTL_DRV_LOAD BIT(3)
106 #define WX_CFG_PORT_CTL_QINQ BIT(2)
107 #define WX_CFG_PORT_CTL_D_VLAN BIT(0) /* double vlan*/
108 #define WX_CFG_PORT_ST 0x14404
109 #define WX_CFG_PORT_ST_LANID GENMASK(9, 8)
110 #define WX_CFG_TAG_TPID(_i) (0x14430 + ((_i) * 4))
111 #define WX_CFG_PORT_CTL_NUM_VT_MASK GENMASK(13, 12) /* number of TVs */
112
113 #define WX_CFG_PORT_CTL_NUM_VT_NONE 0
114 #define WX_CFG_PORT_CTL_NUM_VT_8 FIELD_PREP(GENMASK(13, 12), 1)
115 #define WX_CFG_PORT_CTL_NUM_VT_32 FIELD_PREP(GENMASK(13, 12), 2)
116 #define WX_CFG_PORT_CTL_NUM_VT_64 FIELD_PREP(GENMASK(13, 12), 3)
117
118 /* GPIO Registers */
119 #define WX_GPIO_DR 0x14800
120 #define WX_GPIO_DR_0 BIT(0) /* SDP0 Data Value */
121 #define WX_GPIO_DR_1 BIT(1) /* SDP1 Data Value */
122 #define WX_GPIO_DDR 0x14804
123 #define WX_GPIO_DDR_0 BIT(0) /* SDP0 IO direction */
124 #define WX_GPIO_DDR_1 BIT(1) /* SDP1 IO direction */
125 #define WX_GPIO_CTL 0x14808
126 #define WX_GPIO_INTEN 0x14830
127 #define WX_GPIO_INTEN_0 BIT(0)
128 #define WX_GPIO_INTEN_1 BIT(1)
129 #define WX_GPIO_INTMASK 0x14834
130 #define WX_GPIO_INTTYPE_LEVEL 0x14838
131 #define WX_GPIO_POLARITY 0x1483C
132 #define WX_GPIO_INTSTATUS 0x14844
133 #define WX_GPIO_EOI 0x1484C
134 #define WX_GPIO_EXT 0x14850
135
136 /*********************** Transmit DMA registers **************************/
137 /* transmit global control */
138 #define WX_TDM_CTL 0x18000
139 #define WX_TDM_VF_TE(_i) (0x18004 + ((_i) * 4))
140 #define WX_TDM_MAC_AS(_i) (0x18060 + ((_i) * 4))
141 #define WX_TDM_VLAN_AS(_i) (0x18070 + ((_i) * 4))
142 #define WX_TDM_VFTE_CLR(_i) (0x180A0 + ((_i) * 4))
143
144 /* TDM CTL BIT */
145 #define WX_TDM_CTL_TE BIT(0) /* Transmit Enable */
146 #define WX_TDM_PB_THRE(_i) (0x18020 + ((_i) * 4))
147 #define WX_TDM_RP_IDX 0x1820C
148 #define WX_TDM_PKT_CNT 0x18308
149 #define WX_TDM_BYTE_CNT_LSB 0x1830C
150 #define WX_TDM_OS2BMC_CNT 0x18314
151 #define WX_TDM_RP_RATE 0x18404
152
153 /***************************** RDB registers *********************************/
154 /* receive packet buffer */
155 #define WX_RDB_PB_CTL 0x19000
156 #define WX_RDB_PB_CTL_RXEN BIT(31) /* Enable Receiver */
157 #define WX_RDB_PB_CTL_DISABLED BIT(0)
158 #define WX_RDB_PB_SZ(_i) (0x19020 + ((_i) * 4))
159 #define WX_RDB_PB_SZ_SHIFT 10
160 /* statistic */
161 #define WX_RDB_PFCMACDAL 0x19210
162 #define WX_RDB_PFCMACDAH 0x19214
163 #define WX_RDB_LXOFFTXC 0x19218
164 #define WX_RDB_LXONTXC 0x1921C
165 /* Flow Control Registers */
166 #define WX_RDB_RFCV 0x19200
167 #define WX_RDB_RFCL 0x19220
168 #define WX_RDB_RFCL_XONE BIT(31)
169 #define WX_RDB_RFCH 0x19260
170 #define WX_RDB_RFCH_XOFFE BIT(31)
171 #define WX_RDB_RFCRT 0x192A0
172 #define WX_RDB_RFCC 0x192A4
173 #define WX_RDB_RFCC_RFCE_802_3X BIT(3)
174 /* ring assignment */
175 #define WX_RDB_PL_CFG(_i) (0x19300 + ((_i) * 4))
176 #define WX_RDB_PL_CFG_L4HDR BIT(1)
177 #define WX_RDB_PL_CFG_L3HDR BIT(2)
178 #define WX_RDB_PL_CFG_L2HDR BIT(3)
179 #define WX_RDB_PL_CFG_TUN_TUNHDR BIT(4)
180 #define WX_RDB_PL_CFG_TUN_OUTL2HDR BIT(5)
181 #define WX_RDB_PL_CFG_RSS_EN BIT(24)
182 #define WX_RDB_PL_CFG_RSS_MASK GENMASK(23, 16)
183 #define WX_RDB_RSSTBL(_i) (0x19400 + ((_i) * 4))
184 #define WX_RDB_RSSRK(_i) (0x19480 + ((_i) * 4))
185 #define WX_RDB_RA_CTL 0x194F4
186 #define WX_RDB_RA_CTL_MULTI_RSS BIT(0)
187 #define WX_RDB_RA_CTL_RSS_EN BIT(2) /* RSS Enable */
188 #define WX_RDB_RA_CTL_RSS_IPV4_TCP BIT(16)
189 #define WX_RDB_RA_CTL_RSS_IPV4 BIT(17)
190 #define WX_RDB_RA_CTL_RSS_IPV6 BIT(20)
191 #define WX_RDB_RA_CTL_RSS_IPV6_TCP BIT(21)
192 #define WX_RDB_RA_CTL_RSS_IPV4_UDP BIT(22)
193 #define WX_RDB_RA_CTL_RSS_IPV6_UDP BIT(23)
194 #define WX_RDB_RA_CTL_RSS_MASK GENMASK(23, 16)
195 #define WX_RDB_FDIR_MATCH 0x19558
196 #define WX_RDB_FDIR_MISS 0x1955C
197 /* VM RSS */
198 #define WX_RDB_VMRSSRK(_i, _p) (0x1A000 + ((_i) * 4) + ((_p) * 0x40))
199 #define WX_RDB_VMRSSTBL(_i, _p) (0x1B000 + ((_i) * 4) + ((_p) * 0x40))
200
201 /******************************* PSR Registers *******************************/
202 /* psr control */
203 #define WX_PSR_CTL 0x15000
204 #define WX_PSR_VM_CTL 0x151B0
205 /* Header split receive */
206 #define WX_PSR_CTL_SW_EN BIT(18)
207 #define WX_PSR_CTL_RSC_ACK BIT(17)
208 #define WX_PSR_CTL_RSC_DIS BIT(16)
209 #define WX_PSR_CTL_PCSD BIT(13)
210 #define WX_PSR_CTL_IPPCSE BIT(12)
211 #define WX_PSR_CTL_BAM BIT(10)
212 #define WX_PSR_CTL_UPE BIT(9)
213 #define WX_PSR_CTL_MPE BIT(8)
214 #define WX_PSR_CTL_MFE BIT(7)
215 #define WX_PSR_CTL_MO_SHIFT 5
216 #define WX_PSR_CTL_MO (0x3 << WX_PSR_CTL_MO_SHIFT)
217 #define WX_PSR_CTL_TPE BIT(4)
218 #define WX_PSR_MAX_SZ 0x15020
219 #define WX_PSR_VLAN_CTL 0x15088
220 #define WX_PSR_VLAN_CTL_CFIEN BIT(29) /* bit 29 */
221 #define WX_PSR_VLAN_CTL_VFE BIT(30) /* bit 30 */
222 /* EType Queue Filter */
223 #define WX_PSR_ETYPE_SWC(_i) (0x15128 + ((_i) * 4))
224 #define WX_PSR_ETYPE_SWC_FILTER_1588 3
225 #define WX_PSR_ETYPE_SWC_FILTER_EN BIT(31)
226 #define WX_PSR_ETYPE_SWC_1588 BIT(30)
227 /* 1588 */
228 #define WX_PSR_1588_MSG 0x15120
229 #define WX_PSR_1588_MSG_V1_SYNC FIELD_PREP(GENMASK(7, 0), 0)
230 #define WX_PSR_1588_MSG_V1_DELAY_REQ FIELD_PREP(GENMASK(7, 0), 1)
231 #define WX_PSR_1588_STMPL 0x151E8
232 #define WX_PSR_1588_STMPH 0x151A4
233 #define WX_PSR_1588_CTL 0x15188
234 #define WX_PSR_1588_CTL_ENABLED BIT(4)
235 #define WX_PSR_1588_CTL_TYPE_MASK GENMASK(3, 1)
236 #define WX_PSR_1588_CTL_TYPE_L4_V1 FIELD_PREP(GENMASK(3, 1), 1)
237 #define WX_PSR_1588_CTL_TYPE_EVENT_V2 FIELD_PREP(GENMASK(3, 1), 5)
238 #define WX_PSR_1588_CTL_VALID BIT(0)
239 /* mcasst/ucast overflow tbl */
240 #define WX_PSR_MC_TBL(_i) (0x15200 + ((_i) * 4))
241 #define WX_PSR_MC_TBL_REG(_i) FIELD_GET(GENMASK(11, 5), (_i))
242 #define WX_PSR_MC_TBL_BIT(_i) FIELD_GET(GENMASK(4, 0), (_i))
243 #define WX_PSR_UC_TBL(_i) (0x15400 + ((_i) * 4))
244 #define WX_PSR_VM_CTL_REPLEN BIT(30) /* replication enabled */
245 #define WX_PSR_VM_CTL_POOL_MASK GENMASK(12, 7)
246
247 /* VM L2 contorl */
248 #define WX_PSR_VM_L2CTL(_i) (0x15600 + ((_i) * 4))
249 #define WX_PSR_VM_L2CTL_UPE BIT(4) /* unicast promiscuous */
250 #define WX_PSR_VM_L2CTL_VACC BIT(6) /* accept nomatched vlan */
251 #define WX_PSR_VM_L2CTL_VPE BIT(7) /* vlan promiscuous mode */
252 #define WX_PSR_VM_L2CTL_AUPE BIT(8) /* accept untagged packets */
253 #define WX_PSR_VM_L2CTL_ROMPE BIT(9) /* accept packets in MTA tbl */
254 #define WX_PSR_VM_L2CTL_ROPE BIT(10) /* accept packets in UC tbl */
255 #define WX_PSR_VM_L2CTL_BAM BIT(11) /* accept broadcast packets */
256 #define WX_PSR_VM_L2CTL_MPE BIT(12) /* multicast promiscuous */
257
258 /* Management */
259 #define WX_PSR_MNG_FLEX_SEL 0x1582C
260 #define WX_PSR_MNG_FLEX_DW_L(_i) (0x15A00 + ((_i) * 16))
261 #define WX_PSR_MNG_FLEX_DW_H(_i) (0x15A04 + ((_i) * 16))
262 #define WX_PSR_MNG_FLEX_MSK(_i) (0x15A08 + ((_i) * 16))
263 #define WX_PSR_LAN_FLEX_SEL 0x15B8C
264 #define WX_PSR_LAN_FLEX_DW_L(_i) (0x15C00 + ((_i) * 16))
265 #define WX_PSR_LAN_FLEX_DW_H(_i) (0x15C04 + ((_i) * 16))
266 #define WX_PSR_LAN_FLEX_MSK(_i) (0x15C08 + ((_i) * 16))
267
268 #define WX_PSR_WKUP_CTL 0x15B80
269 /* Wake Up Filter Control Bit */
270 #define WX_PSR_WKUP_CTL_MAG BIT(1) /* Magic Packet Wakeup Enable */
271
272 /* vlan tbl */
273 #define WX_PSR_VLAN_TBL(_i) (0x16000 + ((_i) * 4))
274
275 /* mac switcher */
276 #define WX_PSR_MAC_SWC_AD_L 0x16200
277 #define WX_PSR_MAC_SWC_AD_H 0x16204
278 #define WX_PSR_MAC_SWC_AD_H_AD(v) FIELD_PREP(U16_MAX, v)
279 #define WX_PSR_MAC_SWC_AD_H_ADTYPE(v) FIELD_PREP(BIT(30), v)
280 #define WX_PSR_MAC_SWC_AD_H_AV BIT(31)
281 #define WX_PSR_MAC_SWC_VM_L 0x16208
282 #define WX_PSR_MAC_SWC_VM_H 0x1620C
283 #define WX_PSR_MAC_SWC_IDX 0x16210
284 #define WX_CLEAR_VMDQ_ALL 0xFFFFFFFFU
285
286 /* vlan switch */
287 #define WX_PSR_VLAN_SWC 0x16220
288 #define WX_PSR_VLAN_SWC_VM_L 0x16224
289 #define WX_PSR_VLAN_SWC_VM_H 0x16228
290 #define WX_PSR_VLAN_SWC_VM(_i) (0x16224 + ((_i) * 4))
291 #define WX_PSR_VLAN_SWC_IDX 0x16230 /* 64 vlan entries */
292 /* VLAN pool filtering masks */
293 #define WX_PSR_VLAN_SWC_VIEN BIT(31) /* filter is valid */
294 #define WX_PSR_VLAN_SWC_ENTRIES 64
295 #define WX_PSR_VLAN_SWC_VLANID_MASK GENMASK(11, 0)
296
297 /********************************* RSEC **************************************/
298 /* general rsec */
299 #define WX_RSC_CTL 0x17000
300 #define WX_RSC_CTL_SAVE_MAC_ERR BIT(6)
301 #define WX_RSC_CTL_CRC_STRIP BIT(2)
302 #define WX_RSC_CTL_RX_DIS BIT(1)
303 #define WX_RSC_ST 0x17004
304 #define WX_RSC_ST_RSEC_RDY BIT(0)
305
306 /*********************** Transmit DMA registers **************************/
307 /* transmit global control */
308 #define WX_TDM_ETYPE_AS(_i) (0x18058 + ((_i) * 4))
309 #define WX_TDM_VLAN_INS(_i) (0x18100 + ((_i) * 4))
310 /* Per VF Port VLAN insertion rules */
311 #define WX_TDM_VLAN_INS_VLANA_DEFAULT BIT(30) /* Always use default VLAN*/
312
313 /****************************** TDB ******************************************/
314 #define WX_TDB_PB_SZ(_i) (0x1CC00 + ((_i) * 4))
315 #define WX_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */
316
317 /****************************** TSEC *****************************************/
318 /* Security Control Registers */
319 #define WX_TSC_CTL 0x1D000
320 #define WX_TSC_CTL_TX_DIS BIT(1)
321 #define WX_TSC_CTL_TSEC_DIS BIT(0)
322 #define WX_TSC_ST 0x1D004
323 #define WX_TSC_ST_SECTX_RDY BIT(0)
324 #define WX_TSC_BUF_AE 0x1D00C
325 #define WX_TSC_BUF_AE_THR GENMASK(9, 0)
326 /* 1588 */
327 #define WX_TSC_1588_CTL 0x11F00
328 #define WX_TSC_1588_CTL_ENABLED BIT(4)
329 #define WX_TSC_1588_CTL_VALID BIT(0)
330 #define WX_TSC_1588_STMPL 0x11F04
331 #define WX_TSC_1588_STMPH 0x11F08
332 #define WX_TSC_1588_SYSTIML 0x11F0C
333 #define WX_TSC_1588_SYSTIMH 0x11F10
334 #define WX_TSC_1588_INC 0x11F14
335 #define WX_TSC_1588_INT_ST 0x11F20
336 #define WX_TSC_1588_INT_ST_TT1 BIT(5)
337 #define WX_TSC_1588_INT_EN 0x11F24
338 #define WX_TSC_1588_INT_EN_TT1 BIT(5)
339 #define WX_TSC_1588_AUX_CTL 0x11F28
340 #define WX_TSC_1588_AUX_CTL_EN_TS0 BIT(8)
341 #define WX_TSC_1588_AUX_CTL_EN_TT1 BIT(2)
342 #define WX_TSC_1588_AUX_CTL_PLSG BIT(1)
343 #define WX_TSC_1588_AUX_CTL_EN_TT0 BIT(0)
344 #define WX_TSC_1588_TRGT_L(i) (0x11F2C + ((i) * 8)) /* [0,1] */
345 #define WX_TSC_1588_TRGT_H(i) (0x11F30 + ((i) * 8)) /* [0,1] */
346 #define WX_TSC_1588_SDP(i) (0x11F5C + ((i) * 4)) /* [0,3] */
347 #define WX_TSC_1588_SDP_OUT_LEVEL_H FIELD_PREP(BIT(4), 0)
348 #define WX_TSC_1588_SDP_OUT_LEVEL_L FIELD_PREP(BIT(4), 1)
349 #define WX_TSC_1588_SDP_FUN_SEL_MASK GENMASK(2, 0)
350 #define WX_TSC_1588_SDP_FUN_SEL_TT0 FIELD_PREP(WX_TSC_1588_SDP_FUN_SEL_MASK, 1)
351 #define WX_TSC_1588_SDP_FUN_SEL_TS0 FIELD_PREP(WX_TSC_1588_SDP_FUN_SEL_MASK, 5)
352
353 /************************************** MNG ********************************/
354 #define WX_MNG_SWFW_SYNC 0x1E008
355 #define WX_MNG_SWFW_SYNC_SW_MB BIT(2)
356 #define WX_MNG_SWFW_SYNC_SW_FLASH BIT(3)
357 #define WX_MNG_MBOX 0x1E100
358 #define WX_MNG_MBOX_CTL 0x1E044
359 #define WX_MNG_MBOX_CTL_SWRDY BIT(0)
360 #define WX_MNG_MBOX_CTL_FWRDY BIT(2)
361 #define WX_MNG_BMC2OS_CNT 0x1E090
362 #define WX_MNG_OS2BMC_CNT 0x1E094
363 #define WX_SW2FW_MBOX_CMD 0x1E0A0
364 #define WX_SW2FW_MBOX_CMD_VLD BIT(31)
365 #define WX_SW2FW_MBOX 0x1E200
366 #define WX_FW2SW_MBOX 0x1E300
367
368 /************************************* ETH MAC *****************************/
369 #define WX_MAC_TX_CFG 0x11000
370 #define WX_MAC_TX_CFG_TE BIT(0)
371 #define WX_MAC_TX_CFG_SPEED_MASK GENMASK(30, 29)
372 #define WX_MAC_TX_CFG_SPEED_10G FIELD_PREP(WX_MAC_TX_CFG_SPEED_MASK, 0)
373 #define WX_MAC_TX_CFG_SPEED_1G FIELD_PREP(WX_MAC_TX_CFG_SPEED_MASK, 3)
374 #define WX_MAC_RX_CFG 0x11004
375 #define WX_MAC_RX_CFG_RE BIT(0)
376 #define WX_MAC_RX_CFG_JE BIT(8)
377 #define WX_MAC_PKT_FLT 0x11008
378 #define WX_MAC_PKT_FLT_PR BIT(0) /* promiscuous mode */
379 #define WX_MAC_WDG_TIMEOUT 0x1100C
380 #define WX_MAC_RX_FLOW_CTRL 0x11090
381 #define WX_MAC_RX_FLOW_CTRL_RFE BIT(0) /* receive fc enable */
382
383 #define WX_MAC_WDG_TIMEOUT_WTO_MASK GENMASK(3, 0)
384 #define WX_MAC_WDG_TIMEOUT_WTO_DELTA 2
385 /* MDIO Registers */
386 #define WX_MSCA 0x11200
387 #define WX_MSCA_RA(v) FIELD_PREP(U16_MAX, v)
388 #define WX_MSCA_PA(v) FIELD_PREP(GENMASK(20, 16), v)
389 #define WX_MSCA_DA(v) FIELD_PREP(GENMASK(25, 21), v)
390 #define WX_MSCC 0x11204
391 #define WX_MSCC_CMD(v) FIELD_PREP(GENMASK(17, 16), v)
392
393 enum WX_MSCA_CMD_value {
394 WX_MSCA_CMD_RSV = 0,
395 WX_MSCA_CMD_WRITE,
396 WX_MSCA_CMD_POST_READ,
397 WX_MSCA_CMD_READ,
398 };
399
400 #define WX_MSCC_SADDR BIT(18)
401 #define WX_MSCC_BUSY BIT(22)
402 #define WX_MDIO_CLK(v) FIELD_PREP(GENMASK(21, 19), v)
403 #define WX_MDIO_CLAUSE_SELECT 0x11220
404 #define WX_MMC_CONTROL 0x11800
405 #define WX_MMC_CONTROL_RSTONRD BIT(2) /* reset on read */
406
407 /********************************* BAR registers ***************************/
408 /* Interrupt Registers */
409 #define WX_BME_CTL 0x12020
410 #define WX_PX_MISC_IC 0x100
411 #define WX_PX_MISC_ICS 0x104
412 #define WX_PX_MISC_IEN 0x108
413 #define WX_PX_INTA 0x110
414 #define WX_PX_GPIE 0x118
415 #define WX_PX_GPIE_MODEL BIT(0)
416 #define WX_PX_IC(_i) (0x120 + (_i) * 4)
417 #define WX_PX_IMS(_i) (0x140 + (_i) * 4)
418 #define WX_PX_IMC(_i) (0x150 + (_i) * 4)
419 #define WX_PX_ISB_ADDR_L 0x160
420 #define WX_PX_ISB_ADDR_H 0x164
421 #define WX_PX_TRANSACTION_PENDING 0x168
422 #define WX_PX_ITRSEL 0x180
423 #define WX_PX_ITR(_i) (0x200 + (_i) * 4)
424 #define WX_PX_ITR_CNT_WDIS BIT(31)
425 #define WX_PX_MISC_IVAR 0x4FC
426 #define WX_PX_IVAR(_i) (0x500 + (_i) * 4)
427
428 #define WX_PX_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */
429 #define WX_7K_ITR 595
430 #define WX_12K_ITR 336
431 #define WX_20K_ITR 200
432 #define WX_MIN_RSC_ITR 24
433 #define WX_SP_MAX_EITR 0x00000FF8U
434 #define WX_AML_MAX_EITR 0x00000FFFU
435 #define WX_EM_MAX_EITR 0x00007FFCU
436
437 /* transmit DMA Registers */
438 #define WX_PX_TR_BAL(_i) (0x03000 + ((_i) * 0x40))
439 #define WX_PX_TR_BAH(_i) (0x03004 + ((_i) * 0x40))
440 #define WX_PX_TR_WP(_i) (0x03008 + ((_i) * 0x40))
441 #define WX_PX_TR_RP(_i) (0x0300C + ((_i) * 0x40))
442 #define WX_PX_TR_CFG(_i) (0x03010 + ((_i) * 0x40))
443 #define WX_PX_TR_HEAD_ADDRL(_i) (0x03028 + ((_i) * 0x40))
444 #define WX_PX_TR_HEAD_ADDRH(_i) (0x0302C + ((_i) * 0x40))
445 /* Transmit Config masks */
446 #define WX_PX_TR_CFG_ENABLE BIT(0) /* Ena specific Tx Queue */
447 #define WX_PX_TR_CFG_TR_SIZE_SHIFT 1 /* tx desc number per ring */
448 #define WX_PX_TR_CFG_SWFLSH BIT(26) /* Tx Desc. wr-bk flushing */
449 #define WX_PX_TR_CFG_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */
450 #define WX_PX_TR_CFG_THRE_SHIFT 8
451 #define WX_PX_TR_CFG_HEAD_WB BIT(27)
452
453 #define WX_PX_TR_RP_PV(q_per_pool, vf_number, vf_q_index) \
454 (WX_PX_TR_RP((q_per_pool) * (vf_number) + (vf_q_index)))
455 #define WX_PX_TR_WP_PV(q_per_pool, vf_number, vf_q_index) \
456 (WX_PX_TR_WP((q_per_pool) * (vf_number) + (vf_q_index)))
457
458 /* Receive DMA Registers */
459 #define WX_PX_RR_BAL(_i) (0x01000 + ((_i) * 0x40))
460 #define WX_PX_RR_BAH(_i) (0x01004 + ((_i) * 0x40))
461 #define WX_PX_RR_WP(_i) (0x01008 + ((_i) * 0x40))
462 #define WX_PX_RR_RP(_i) (0x0100C + ((_i) * 0x40))
463 #define WX_PX_RR_CFG(_i) (0x01010 + ((_i) * 0x40))
464 #define WX_PX_MPRC(_i) (0x01020 + ((_i) * 0x40))
465 /* PX_RR_CFG bit definitions */
466 #define WX_PX_RR_CFG_VLAN BIT(31)
467 #define WX_PX_RR_CFG_DROP_EN BIT(30)
468 #define WX_PX_RR_CFG_RSC BIT(29)
469 #define WX_PX_RR_CFG_SPLIT_MODE BIT(26)
470 #define WX_PX_RR_CFG_MAX_RSCBUF_16 FIELD_PREP(GENMASK(24, 23), 3)
471 #define WX_PX_RR_CFG_DESC_MERGE BIT(19)
472 #define WX_PX_RR_CFG_RR_THER_SHIFT 16
473 #define WX_PX_RR_CFG_RR_HDR_SZ GENMASK(15, 12)
474 #define WX_PX_RR_CFG_RR_BUF_SZ GENMASK(11, 8)
475 #define WX_PX_RR_CFG_BHDRSIZE_SHIFT 6 /* 64byte resolution (>> 6)
476 * + at bit 8 offset (<< 12)
477 * = (<< 6)
478 */
479 #define WX_PX_RR_CFG_BSIZEPKT_SHIFT 2 /* so many KBs */
480 #define WX_PX_RR_CFG_RR_SIZE_SHIFT 1
481 #define WX_PX_RR_CFG_RR_EN BIT(0)
482
483 /* Number of 80 microseconds we wait for PCI Express master disable */
484 #define WX_PCI_MASTER_DISABLE_TIMEOUT 80000
485
486 #define WX_RSS_64Q_MASK 0x3F
487 #define WX_RSS_8Q_MASK 0x7
488 #define WX_RSS_4Q_MASK 0x3
489 #define WX_RSS_2Q_MASK 0x1
490 #define WX_RSS_DISABLED_MASK 0x0
491
492 #define WX_VMDQ_4Q_MASK 0x7C
493 #define WX_VMDQ_2Q_MASK 0x7E
494 #define WX_VMDQ_1Q_MASK 0x7F
495
496 /****************** Manageablility Host Interface defines ********************/
497 #define WX_HI_MAX_BLOCK_BYTE_LENGTH 256 /* Num of bytes in range */
498 #define WX_HI_COMMAND_TIMEOUT 1000 /* Process HI command limit */
499 #define WX_HIC_HDR_INDEX_MAX 255
500
501 #define FW_READ_SHADOW_RAM_CMD 0x31
502 #define FW_READ_SHADOW_RAM_LEN 0x6
503 #define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */
504 #define FW_NVM_DATA_OFFSET 3
505 #define FW_MAX_READ_BUFFER_SIZE 244
506 #define FW_RESET_CMD 0xDF
507 #define FW_RESET_LEN 0x2
508 #define FW_CEM_HDR_LEN 0x4
509 #define FW_CEM_CMD_RESERVED 0X0
510 #define FW_CEM_MAX_RETRIES 3
511 #define FW_CEM_RESP_STATUS_SUCCESS 0x1
512 #define FW_PPS_SET_CMD 0xF6
513 #define FW_PPS_SET_LEN 0x14
514
515 #define WX_SW_REGION_PTR 0x1C
516
517 #define WX_MAC_STATE_DEFAULT 0x1
518 #define WX_MAC_STATE_MODIFIED 0x2
519 #define WX_MAC_STATE_IN_USE 0x4
520
521 /* BitTimes (BT) conversion */
522 #define WX_BT2KB(BT) (((BT) + (8 * 1024 - 1)) / (8 * 1024))
523 #define WX_B2BT(BT) ((BT) * 8)
524
525 /* Calculate Delay to respond to PFC */
526 #define WX_PFC_D 672
527 /* Calculate Cable Delay */
528 #define WX_CABLE_DC 5556 /* Delay Copper */
529 /* Calculate Delay incurred from higher layer */
530 #define WX_HD 6144
531
532 /* Calculate Interface Delay */
533 #define WX_PHY_D 12800
534 #define WX_MAC_D 4096
535 #define WX_XAUI_D (2 * 1024)
536 #define WX_ID (WX_MAC_D + WX_XAUI_D + WX_PHY_D)
537 /* Calculate PCI Bus delay for low thresholds */
538 #define WX_PCI_DELAY 10000
539
540 /* Calculate delay value in bit times */
541 #define WX_DV(_max_frame_link, _max_frame_tc) \
542 ((36 * (WX_B2BT(_max_frame_link) + WX_PFC_D + \
543 (2 * WX_CABLE_DC) + (2 * WX_ID) + WX_HD) / 25 + 1) + \
544 2 * WX_B2BT(_max_frame_tc))
545
546 /* Calculate low threshold delay values */
547 #define WX_LOW_DV(_max_frame_tc) \
548 (2 * (2 * WX_B2BT(_max_frame_tc) + (36 * WX_PCI_DELAY / 25) + 1))
549
550 /* flow control */
551 #define WX_DEFAULT_FCPAUSE 0xFFFF
552
553 #define WX_MAX_RXD 8192
554 #define WX_MAX_TXD 8192
555 #define WX_MIN_RXD 128
556 #define WX_MIN_TXD 128
557
558 /* Number of Transmit and Receive Descriptors must be a multiple of 128 */
559 #define WX_REQ_RX_DESCRIPTOR_MULTIPLE 128
560 #define WX_REQ_TX_DESCRIPTOR_MULTIPLE 128
561
562 #define WX_MAX_JUMBO_FRAME_SIZE 9432 /* max payload 9414 */
563 #define VMDQ_P(p) ((p) + wx->ring_feature[RING_F_VMDQ].offset)
564
565 /* Supported Rx Buffer Sizes */
566 #define WX_RXBUFFER_256 256 /* Used for skb receive header */
567 #define WX_RXBUFFER_2K 2048
568 #define WX_RXBUFFER_3K 3072
569 #define WX_MAX_RXBUFFER 16384 /* largest size for single descriptor */
570
571 #define WX_RX_BUFFER_WRITE 16 /* Must be power of 2 */
572
573 #define WX_MAX_DATA_PER_TXD BIT(14)
574 /* Tx Descriptors needed, worst case */
575 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), WX_MAX_DATA_PER_TXD)
576 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
577
578 /******************* Receive Descriptor bit definitions **********************/
579 #define WX_RXD_STAT_DD BIT(0) /* Done */
580 #define WX_RXD_STAT_EOP BIT(1) /* End of Packet */
581 #define WX_RXD_STAT_VP BIT(5) /* IEEE VLAN Pkt */
582 #define WX_RXD_STAT_L4CS BIT(7) /* L4 xsum calculated */
583 #define WX_RXD_STAT_IPCS BIT(8) /* IP xsum calculated */
584 #define WX_RXD_STAT_OUTERIPCS BIT(10) /* Cloud IP xsum calculated*/
585 #define WX_RXD_STAT_IPV6EX BIT(12) /* IPv6 Dest Header */
586 #define WX_RXD_STAT_TS BIT(14) /* IEEE1588 Time Stamp */
587
588 #define WX_RXD_ERR_OUTERIPER BIT(26) /* CRC IP Header error */
589 #define WX_RXD_ERR_RXE BIT(29) /* Any MAC Error */
590 #define WX_RXD_ERR_TCPE BIT(30) /* TCP/UDP Checksum Error */
591 #define WX_RXD_ERR_IPE BIT(31) /* IP Checksum Error */
592
593 /* RSS Hash results */
594 #define WX_RXD_RSSTYPE_MASK GENMASK(3, 0)
595 #define WX_RXD_RSSTYPE_IPV4_TCP 0x00000001U
596 #define WX_RXD_RSSTYPE_IPV6_TCP 0x00000003U
597 #define WX_RXD_RSSTYPE_IPV4_SCTP 0x00000004U
598 #define WX_RXD_RSSTYPE_IPV6_SCTP 0x00000006U
599 #define WX_RXD_RSSTYPE_IPV4_UDP 0x00000007U
600 #define WX_RXD_RSSTYPE_IPV6_UDP 0x00000008U
601
602 #define WX_RSS_L4_TYPES_MASK \
603 ((1ul << WX_RXD_RSSTYPE_IPV4_TCP) | \
604 (1ul << WX_RXD_RSSTYPE_IPV4_UDP) | \
605 (1ul << WX_RXD_RSSTYPE_IPV4_SCTP) | \
606 (1ul << WX_RXD_RSSTYPE_IPV6_TCP) | \
607 (1ul << WX_RXD_RSSTYPE_IPV6_UDP) | \
608 (1ul << WX_RXD_RSSTYPE_IPV6_SCTP))
609 /* TUN */
610 #define WX_PTYPE_TUN_IPV4 0x80
611 #define WX_PTYPE_TUN_IPV6 0xC0
612
613 /* PKT for TUN */
614 #define WX_PTYPE_PKT_IPIP 0x00 /* IP+IP */
615 #define WX_PTYPE_PKT_IG 0x10 /* IP+GRE */
616 #define WX_PTYPE_PKT_IGM 0x20 /* IP+GRE+MAC */
617 #define WX_PTYPE_PKT_IGMV 0x30 /* IP+GRE+MAC+VLAN */
618 /* PKT for !TUN */
619 #define WX_PTYPE_PKT_MAC 0x10
620 #define WX_PTYPE_PKT_IP 0x20
621
622 /* TYP for PKT=mac */
623 #define WX_PTYPE_TYP_MAC 0x01
624 /* TYP for PKT=ip */
625 #define WX_PTYPE_PKT_IPV6 0x08
626 #define WX_PTYPE_TYP_IPFRAG 0x01
627 #define WX_PTYPE_TYP_IP 0x02
628 #define WX_PTYPE_TYP_UDP 0x03
629 #define WX_PTYPE_TYP_TCP 0x04
630 #define WX_PTYPE_TYP_SCTP 0x05
631
632 /* Packet type non-ip values */
633 enum wx_l2_ptypes {
634 WX_PTYPE_L2_ABORTED = (WX_PTYPE_PKT_MAC),
635 WX_PTYPE_L2_MAC = (WX_PTYPE_PKT_MAC | WX_PTYPE_TYP_MAC),
636
637 WX_PTYPE_L2_IPV4_FRAG = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_IPFRAG),
638 WX_PTYPE_L2_IPV4 = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_IP),
639 WX_PTYPE_L2_IPV4_UDP = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_UDP),
640 WX_PTYPE_L2_IPV4_TCP = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_TCP),
641 WX_PTYPE_L2_IPV4_SCTP = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_SCTP),
642 WX_PTYPE_L2_IPV6_FRAG = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
643 WX_PTYPE_TYP_IPFRAG),
644 WX_PTYPE_L2_IPV6 = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
645 WX_PTYPE_TYP_IP),
646 WX_PTYPE_L2_IPV6_UDP = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
647 WX_PTYPE_TYP_UDP),
648 WX_PTYPE_L2_IPV6_TCP = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
649 WX_PTYPE_TYP_TCP),
650 WX_PTYPE_L2_IPV6_SCTP = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
651 WX_PTYPE_TYP_SCTP),
652
653 WX_PTYPE_L2_TUN4_MAC = (WX_PTYPE_TUN_IPV4 | WX_PTYPE_PKT_IGM),
654 WX_PTYPE_L2_TUN6_MAC = (WX_PTYPE_TUN_IPV6 | WX_PTYPE_PKT_IGM),
655 };
656
657 #define WX_PTYPE_PKT(_pt) ((_pt) & 0x30)
658 #define WX_PTYPE_TYPL4(_pt) ((_pt) & 0x07)
659
660 #define WX_RXD_PKTTYPE(_rxd) \
661 ((le32_to_cpu((_rxd)->wb.lower.lo_dword.data) >> 9) & 0xFF)
662
663 #define WX_RXD_RSCCNT_MASK GENMASK(20, 17)
664 #define WX_RXD_RSCCNT_SHIFT 17
665 #define WX_RXD_NEXTP_MASK GENMASK(19, 4)
666 #define WX_RXD_NEXTP_SHIFT 4
667
668 /*********************** Transmit Descriptor Config Masks ****************/
669 #define WX_TXD_STAT_DD BIT(0) /* Descriptor Done */
670 #define WX_TXD_DTYP_DATA 0 /* Adv Data Descriptor */
671 #define WX_TXD_PAYLEN_SHIFT 13 /* Desc PAYLEN shift */
672 #define WX_TXD_EOP BIT(24) /* End of Packet */
673 #define WX_TXD_IFCS BIT(25) /* Insert FCS */
674 #define WX_TXD_RS BIT(27) /* Report Status */
675
676 /*********************** Adv Transmit Descriptor Config Masks ****************/
677 #define WX_TXD_MAC_TSTAMP BIT(19) /* IEEE1588 time stamp */
678 #define WX_TXD_DTYP_CTXT BIT(20) /* Adv Context Desc */
679 #define WX_TXD_LINKSEC BIT(26) /* enable linksec */
680 #define WX_TXD_VLE BIT(30) /* VLAN pkt enable */
681 #define WX_TXD_TSE BIT(31) /* TCP Seg enable */
682 #define WX_TXD_CC BIT(7) /* Check Context */
683 #define WX_TXD_IPSEC BIT(8) /* enable ipsec esp */
684 #define WX_TXD_L4CS BIT(9)
685 #define WX_TXD_IIPCS BIT(10)
686 #define WX_TXD_EIPCS BIT(11)
687 #define WX_TXD_PAYLEN_SHIFT 13 /* Adv desc PAYLEN shift */
688 #define WX_TXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
689 #define WX_TXD_TAG_TPID_SEL_SHIFT 11
690
691 #define WX_TXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
692 #define WX_TXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
693
694 #define WX_TXD_OUTER_IPLEN_SHIFT 12 /* Adv ctxt OUTERIPLEN shift */
695 #define WX_TXD_TUNNEL_LEN_SHIFT 21 /* Adv ctxt TUNNELLEN shift */
696 #define WX_TXD_TUNNEL_TYPE_SHIFT 11 /* Adv Tx Desc Tunnel Type shift */
697 #define WX_TXD_TUNNEL_UDP FIELD_PREP(BIT(WX_TXD_TUNNEL_TYPE_SHIFT), 0)
698 #define WX_TXD_TUNNEL_GRE FIELD_PREP(BIT(WX_TXD_TUNNEL_TYPE_SHIFT), 1)
699
700 enum wx_tx_flags {
701 /* cmd_type flags */
702 WX_TX_FLAGS_HW_VLAN = 0x01,
703 WX_TX_FLAGS_TSO = 0x02,
704 WX_TX_FLAGS_TSTAMP = 0x04,
705
706 /* olinfo flags */
707 WX_TX_FLAGS_CC = 0x08,
708 WX_TX_FLAGS_IPV4 = 0x10,
709 WX_TX_FLAGS_CSUM = 0x20,
710 WX_TX_FLAGS_OUTER_IPV4 = 0x100,
711 WX_TX_FLAGS_LINKSEC = 0x200,
712 WX_TX_FLAGS_IPSEC = 0x400,
713
714 /* software defined flags */
715 WX_TX_FLAGS_SW_VLAN = 0x40,
716 };
717
718 /* VLAN info */
719 #define WX_TX_FLAGS_VLAN_MASK GENMASK(31, 16)
720 #define WX_TX_FLAGS_VLAN_SHIFT 16
721
722 /* wx_dec_ptype.mac: outer mac */
723 enum wx_dec_ptype_mac {
724 WX_DEC_PTYPE_MAC_IP = 0,
725 WX_DEC_PTYPE_MAC_L2 = 2,
726 WX_DEC_PTYPE_MAC_FCOE = 3,
727 };
728
729 /* wx_dec_ptype.[e]ip: outer&encaped ip */
730 #define WX_DEC_PTYPE_IP_FRAG 0x4
731 enum wx_dec_ptype_ip {
732 WX_DEC_PTYPE_IP_NONE = 0,
733 WX_DEC_PTYPE_IP_IPV4 = 1,
734 WX_DEC_PTYPE_IP_IPV6 = 2,
735 WX_DEC_PTYPE_IP_FGV4 = WX_DEC_PTYPE_IP_FRAG | WX_DEC_PTYPE_IP_IPV4,
736 WX_DEC_PTYPE_IP_FGV6 = WX_DEC_PTYPE_IP_FRAG | WX_DEC_PTYPE_IP_IPV6,
737 };
738
739 /* wx_dec_ptype.etype: encaped type */
740 enum wx_dec_ptype_etype {
741 WX_DEC_PTYPE_ETYPE_NONE = 0,
742 WX_DEC_PTYPE_ETYPE_IPIP = 1, /* IP+IP */
743 WX_DEC_PTYPE_ETYPE_IG = 2, /* IP+GRE */
744 WX_DEC_PTYPE_ETYPE_IGM = 3, /* IP+GRE+MAC */
745 WX_DEC_PTYPE_ETYPE_IGMV = 4, /* IP+GRE+MAC+VLAN */
746 };
747
748 /* wx_dec_ptype.proto: payload proto */
749 enum wx_dec_ptype_prot {
750 WX_DEC_PTYPE_PROT_NONE = 0,
751 WX_DEC_PTYPE_PROT_UDP = 1,
752 WX_DEC_PTYPE_PROT_TCP = 2,
753 WX_DEC_PTYPE_PROT_SCTP = 3,
754 WX_DEC_PTYPE_PROT_ICMP = 4,
755 WX_DEC_PTYPE_PROT_TS = 5, /* time sync */
756 };
757
758 /* wx_dec_ptype.layer: payload layer */
759 enum wx_dec_ptype_layer {
760 WX_DEC_PTYPE_LAYER_NONE = 0,
761 WX_DEC_PTYPE_LAYER_PAY2 = 1,
762 WX_DEC_PTYPE_LAYER_PAY3 = 2,
763 WX_DEC_PTYPE_LAYER_PAY4 = 3,
764 };
765
766 struct wx_dec_ptype {
767 u32 known:1;
768 u32 mac:2; /* outer mac */
769 u32 ip:3; /* outer ip*/
770 u32 etype:3; /* encaped type */
771 u32 eip:3; /* encaped ip */
772 u32 prot:4; /* payload proto */
773 u32 layer:3; /* payload layer */
774 };
775
776 /* macro to make the table lines short */
777 #define WX_PTT(mac, ip, etype, eip, proto, layer)\
778 {1, \
779 WX_DEC_PTYPE_MAC_##mac, /* mac */\
780 WX_DEC_PTYPE_IP_##ip, /* ip */ \
781 WX_DEC_PTYPE_ETYPE_##etype, /* etype */\
782 WX_DEC_PTYPE_IP_##eip, /* eip */\
783 WX_DEC_PTYPE_PROT_##proto, /* proto */\
784 WX_DEC_PTYPE_LAYER_##layer /* layer */}
785
786 /* Host Interface Command Structures */
787 struct wx_hic_hdr {
788 u8 cmd;
789 u8 buf_len;
790 union {
791 u8 cmd_resv;
792 u8 ret_status;
793 } cmd_or_resp;
794 union {
795 u8 checksum;
796 u8 index;
797 };
798 };
799
800 struct wx_hic_hdr2_req {
801 u8 cmd;
802 u8 buf_lenh;
803 u8 buf_lenl;
804 union {
805 u8 checksum;
806 u8 index;
807 };
808 };
809
810 struct wx_hic_hdr2_rsp {
811 u8 cmd;
812 u8 buf_lenl;
813 u8 buf_lenh_status; /* 7-5: high bits of buf_len, 4-0: status */
814 union {
815 u8 checksum;
816 u8 index;
817 };
818 };
819
820 union wx_hic_hdr2 {
821 struct wx_hic_hdr2_req req;
822 struct wx_hic_hdr2_rsp rsp;
823 };
824
825 /* These need to be dword aligned */
826 struct wx_hic_read_shadow_ram {
827 union wx_hic_hdr2 hdr;
828 u32 address;
829 u16 length;
830 u16 pad2;
831 u16 data;
832 u16 pad3;
833 };
834
835 struct wx_hic_reset {
836 struct wx_hic_hdr hdr;
837 u16 lan_id;
838 u16 reset_type;
839 };
840
841 struct wx_hic_set_pps {
842 struct wx_hic_hdr hdr;
843 u8 lan_id;
844 u8 enable;
845 u16 pad2;
846 u64 nsec;
847 u64 cycles;
848 };
849
850 /* Bus parameters */
851 struct wx_bus_info {
852 u8 func;
853 u16 device;
854 };
855
856 struct wx_mbx_info {
857 u16 size;
858 u32 mailbox;
859 u32 udelay;
860 u32 timeout;
861 /* lock mbx access */
862 spinlock_t mbx_lock;
863 };
864
865 struct wx_thermal_sensor_data {
866 s16 temp;
867 s16 alarm_thresh;
868 s16 dalarm_thresh;
869 };
870
871 enum wx_mac_type {
872 wx_mac_unknown = 0,
873 wx_mac_sp,
874 wx_mac_em,
875 wx_mac_aml,
876 wx_mac_aml40,
877 };
878
879 enum wx_media_type {
880 wx_media_unknown = 0,
881 wx_media_fiber,
882 wx_media_copper,
883 wx_media_backplane
884 };
885
886 enum em_mac_type {
887 em_mac_type_unknown = 0,
888 em_mac_type_mdi,
889 em_mac_type_rgmii
890 };
891
892 struct wx_mac_info {
893 enum wx_mac_type type;
894 bool set_lben;
895 u8 addr[ETH_ALEN];
896 u8 perm_addr[ETH_ALEN];
897 u32 mta_shadow[128];
898 s32 mc_filter_type;
899 u32 mcft_size;
900 u32 vft_shadow[128];
901 u32 vft_size;
902 u32 num_rar_entries;
903 u32 rx_pb_size;
904 u32 tx_pb_size;
905 u32 max_tx_queues;
906 u32 max_rx_queues;
907
908 u16 max_msix_vectors;
909 struct wx_thermal_sensor_data sensor;
910 };
911
912 enum wx_eeprom_type {
913 wx_eeprom_uninitialized = 0,
914 wx_eeprom_spi,
915 wx_flash,
916 wx_eeprom_none /* No NVM support */
917 };
918
919 struct wx_eeprom_info {
920 enum wx_eeprom_type type;
921 u32 semaphore_delay;
922 u16 word_size;
923 u16 sw_region_offset;
924 };
925
926 struct wx_addr_filter_info {
927 u32 num_mc_addrs;
928 u32 mta_in_use;
929 bool user_set_promisc;
930 };
931
932 struct wx_mac_addr {
933 u8 addr[ETH_ALEN];
934 u16 state; /* bitmask */
935 u64 pools;
936 };
937
938 enum wx_reset_type {
939 WX_LAN_RESET = 0,
940 WX_SW_RESET,
941 WX_GLOBAL_RESET
942 };
943
944 struct wx_cb {
945 dma_addr_t dma;
946 u16 append_cnt; /* number of skb's appended */
947 bool dma_released;
948 };
949
950 #define WX_CB(skb) ((struct wx_cb *)(skb)->cb)
951
952 /* Transmit Descriptor */
953 union wx_tx_desc {
954 struct {
955 __le64 buffer_addr; /* Address of descriptor's data buf */
956 __le32 cmd_type_len;
957 __le32 olinfo_status;
958 } read;
959 struct {
960 __le64 rsvd; /* Reserved */
961 __le32 nxtseq_seed;
962 __le32 status;
963 } wb;
964 };
965
966 /* Receive Descriptor */
967 union wx_rx_desc {
968 struct {
969 __le64 pkt_addr; /* Packet buffer address */
970 __le64 hdr_addr; /* Header buffer address */
971 } read;
972 struct {
973 struct {
974 union {
975 __le32 data;
976 struct {
977 __le16 pkt_info; /* RSS, Pkt type */
978 __le16 hdr_info; /* Splithdr, hdrlen */
979 } hs_rss;
980 } lo_dword;
981 union {
982 __le32 rss; /* RSS Hash */
983 struct {
984 __le16 ip_id; /* IP id */
985 __le16 csum; /* Packet Checksum */
986 } csum_ip;
987 } hi_dword;
988 } lower;
989 struct {
990 __le32 status_error; /* ext status/error */
991 __le16 length; /* Packet length */
992 __le16 vlan; /* VLAN tag */
993 } upper;
994 } wb; /* writeback */
995 };
996
997 struct wx_tx_context_desc {
998 __le32 vlan_macip_lens;
999 __le32 seqnum_seed;
1000 __le32 type_tucmd_mlhl;
1001 __le32 mss_l4len_idx;
1002 };
1003
1004 /* if _flag is in _input, return _result */
1005 #define WX_SET_FLAG(_input, _flag, _result) \
1006 (((_flag) <= (_result)) ? \
1007 ((u32)((_input) & (_flag)) * ((_result) / (_flag))) : \
1008 ((u32)((_input) & (_flag)) / ((_flag) / (_result))))
1009
1010 #define WX_RX_DESC(R, i) \
1011 (&(((union wx_rx_desc *)((R)->desc))[i]))
1012 #define WX_TX_DESC(R, i) \
1013 (&(((union wx_tx_desc *)((R)->desc))[i]))
1014 #define WX_TX_CTXTDESC(R, i) \
1015 (&(((struct wx_tx_context_desc *)((R)->desc))[i]))
1016
1017 /* wrapper around a pointer to a socket buffer,
1018 * so a DMA handle can be stored along with the buffer
1019 */
1020 struct wx_tx_buffer {
1021 union wx_tx_desc *next_to_watch;
1022 unsigned long time_stamp;
1023 struct sk_buff *skb;
1024 unsigned int bytecount;
1025 unsigned short gso_segs;
1026 DEFINE_DMA_UNMAP_ADDR(dma);
1027 DEFINE_DMA_UNMAP_LEN(len);
1028 __be16 protocol;
1029 u32 tx_flags;
1030 u32 next_eop;
1031 };
1032
1033 struct wx_rx_buffer {
1034 struct sk_buff *skb;
1035 dma_addr_t dma;
1036 struct page *page;
1037 unsigned int page_offset;
1038 };
1039
1040 struct wx_queue_stats {
1041 u64 packets;
1042 u64 bytes;
1043 };
1044
1045 struct wx_tx_queue_stats {
1046 u64 restart_queue;
1047 u64 tx_busy;
1048 u32 tx_done_old;
1049 };
1050
1051 struct wx_rx_queue_stats {
1052 u64 non_eop_descs;
1053 u64 csum_good_cnt;
1054 u64 csum_err;
1055 u64 alloc_rx_buff_failed;
1056 u64 rsc_count;
1057 u64 rsc_flush;
1058 };
1059
1060 /* iterator for handling rings in ring container */
1061 #define wx_for_each_ring(posm, headm) \
1062 for (posm = (headm).ring; posm; posm = posm->next)
1063
1064 enum wx_ring_state {
1065 WX_TX_DETECT_HANG,
1066 WX_HANG_CHECK_ARMED,
1067 WX_RING_STATE_NBITS
1068 };
1069
1070 struct wx_ring_container {
1071 struct wx_ring *ring; /* pointer to linked list of rings */
1072 unsigned int total_bytes; /* total bytes processed this int */
1073 unsigned int total_packets; /* total packets processed this int */
1074 u8 count; /* total number of rings in vector */
1075 u8 itr; /* current ITR setting for ring */
1076 struct dim dim; /* data for net_dim algorithm */
1077 };
1078 struct wx_ring {
1079 struct wx_ring *next; /* pointer to next ring in q_vector */
1080 struct wx_q_vector *q_vector; /* backpointer to host q_vector */
1081 struct net_device *netdev; /* netdev ring belongs to */
1082 struct device *dev; /* device for DMA mapping */
1083 struct page_pool *page_pool;
1084 void *desc; /* descriptor ring memory */
1085 union {
1086 struct wx_tx_buffer *tx_buffer_info;
1087 struct wx_rx_buffer *rx_buffer_info;
1088 };
1089 DECLARE_BITMAP(state, WX_RING_STATE_NBITS);
1090 u8 __iomem *tail;
1091 dma_addr_t dma; /* phys. address of descriptor ring */
1092 dma_addr_t headwb_dma;
1093 u32 *headwb_mem;
1094 unsigned int size; /* length in bytes */
1095
1096 u16 count; /* amount of descriptors */
1097 unsigned long last_rx_timestamp;
1098
1099 u8 queue_index; /* needed for multiqueue queue management */
1100 u8 reg_idx; /* holds the special value that gets
1101 * the hardware register offset
1102 * associated with this ring, which is
1103 * different for DCB and RSS modes
1104 */
1105 u16 next_to_use;
1106 u16 next_to_clean;
1107 u16 rx_buf_len;
1108 union {
1109 u16 next_to_alloc;
1110 struct {
1111 u8 atr_sample_rate;
1112 u8 atr_count;
1113 };
1114 };
1115
1116 struct wx_queue_stats stats;
1117 struct u64_stats_sync syncp;
1118 union {
1119 struct wx_tx_queue_stats tx_stats;
1120 struct wx_rx_queue_stats rx_stats;
1121 };
1122 } ____cacheline_internodealigned_in_smp;
1123
1124 struct wx_q_vector {
1125 struct wx *wx;
1126 int cpu; /* CPU for DCA */
1127 int numa_node;
1128 u16 v_idx; /* index of q_vector within array, also used for
1129 * finding the bit in EICR and friends that
1130 * represents the vector for this ring
1131 */
1132 u16 itr; /* Interrupt throttle rate written to EITR */
1133 struct wx_ring_container rx, tx;
1134 struct napi_struct napi;
1135 struct rcu_head rcu; /* to avoid race with update stats on free */
1136
1137 u16 total_events; /* number of interrupts processed */
1138
1139 char name[IFNAMSIZ + 17];
1140
1141 /* for dynamic allocation of rings associated with this q_vector */
1142 struct wx_ring ring[] ____cacheline_internodealigned_in_smp;
1143 };
1144
1145 struct wx_ring_feature {
1146 u16 limit; /* upper limit on feature indices */
1147 u16 indices; /* current value of indices */
1148 u16 mask; /* Mask used for feature to ring mapping */
1149 u16 offset; /* offset to start of feature */
1150 };
1151
1152 enum wx_ring_f_enum {
1153 RING_F_NONE = 0,
1154 RING_F_VMDQ,
1155 RING_F_RSS,
1156 RING_F_FDIR,
1157 RING_F_ARRAY_SIZE /* must be last in enum set */
1158 };
1159
1160 enum wx_isb_idx {
1161 WX_ISB_HEADER,
1162 WX_ISB_MISC,
1163 WX_ISB_VEC0,
1164 WX_ISB_VEC1,
1165 WX_ISB_MAX
1166 };
1167
1168 /* Flow Control Settings */
1169 enum wx_fc_mode {
1170 wx_fc_none = 0,
1171 wx_fc_rx_pause,
1172 wx_fc_tx_pause,
1173 wx_fc_full
1174 };
1175
1176 struct wx_fc_info {
1177 u32 high_water; /* Flow Ctrl High-water */
1178 u32 low_water; /* Flow Ctrl Low-water */
1179 enum wx_fc_mode mode; /* Flow Control Mode */
1180 };
1181
1182 /* Statistics counters collected by the MAC */
1183 struct wx_hw_stats {
1184 u64 gprc;
1185 u64 gptc;
1186 u64 gorc;
1187 u64 gotc;
1188 u64 tpr;
1189 u64 tpt;
1190 u64 bprc;
1191 u64 bptc;
1192 u64 mprc;
1193 u64 mptc;
1194 u64 roc;
1195 u64 ruc;
1196 u64 lxonrxc;
1197 u64 lxoffrxc;
1198 u64 lxontxc;
1199 u64 lxofftxc;
1200 u64 o2bgptc;
1201 u64 b2ospc;
1202 u64 o2bspc;
1203 u64 b2ogprc;
1204 u64 rdmdrop;
1205 u64 crcerrs;
1206 u64 rlec;
1207 u64 qmprc;
1208 u64 fdirmatch;
1209 u64 fdirmiss;
1210 };
1211
1212 struct wx_last_stats {
1213 u32 qmprc[128];
1214 u32 lxoffrxc;
1215 u32 lxonrxc;
1216 };
1217
1218 enum wx_state {
1219 WX_STATE_DOWN,
1220 WX_STATE_RESETTING,
1221 WX_STATE_SWFW_BUSY,
1222 WX_STATE_PTP_RUNNING,
1223 WX_STATE_PTP_TX_IN_PROGRESS,
1224 WX_STATE_SERVICE_SCHED,
1225 WX_STATE_DISABLED,
1226 WX_STATE_RES_FREED,
1227 WX_STATE_NBITS /* must be last */
1228 };
1229
1230 struct vf_data_storage {
1231 struct pci_dev *vfdev;
1232 unsigned char vf_mac_addr[ETH_ALEN];
1233 bool spoofchk_enabled;
1234 bool link_enable;
1235 bool trusted;
1236 int xcast_mode;
1237 unsigned int vf_api;
1238 bool clear_to_send;
1239 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
1240 u16 pf_qos;
1241 bool pf_set_mac;
1242
1243 u16 vf_mc_hashes[WX_MAX_VF_MC_ENTRIES];
1244 u16 num_vf_mc_hashes;
1245 u16 vlan_count;
1246 int link_state;
1247 };
1248
1249 struct vf_macvlans {
1250 struct list_head mvlist;
1251 int vf;
1252 bool free;
1253 bool is_macvlan;
1254 u8 vf_macvlan[ETH_ALEN];
1255 };
1256
1257 #define WX_RSS_FIELD_IPV4_TCP BIT(0)
1258 #define WX_RSS_FIELD_IPV4 BIT(1)
1259 #define WX_RSS_FIELD_IPV4_SCTP BIT(2)
1260 #define WX_RSS_FIELD_IPV6_SCTP BIT(3)
1261 #define WX_RSS_FIELD_IPV6_TCP BIT(4)
1262 #define WX_RSS_FIELD_IPV6 BIT(5)
1263 #define WX_RSS_FIELD_IPV4_UDP BIT(6)
1264 #define WX_RSS_FIELD_IPV6_UDP BIT(7)
1265
1266 struct wx_rss_flow_map {
1267 u8 flow_type;
1268 u32 data;
1269 u8 flag;
1270 };
1271
1272 enum wx_pf_flags {
1273 WX_FLAG_MULTI_64_FUNC,
1274 WX_FLAG_SWFW_RING,
1275 WX_FLAG_VMDQ_ENABLED,
1276 WX_FLAG_VLAN_PROMISC,
1277 WX_FLAG_SRIOV_ENABLED,
1278 WX_FLAG_IRQ_VECTOR_SHARED,
1279 WX_FLAG_FDIR_CAPABLE,
1280 WX_FLAG_FDIR_HASH,
1281 WX_FLAG_FDIR_PERFECT,
1282 WX_FLAG_RSC_CAPABLE,
1283 WX_FLAG_RSC_ENABLED,
1284 WX_FLAG_RX_HWTSTAMP_ENABLED,
1285 WX_FLAG_RX_HWTSTAMP_IN_REGISTER,
1286 WX_FLAG_PTP_PPS_ENABLED,
1287 WX_FLAG_NEED_LINK_CONFIG,
1288 WX_FLAG_NEED_MODULE_RESET,
1289 WX_FLAG_NEED_UPDATE_LINK,
1290 WX_FLAG_NEED_DO_RESET,
1291 WX_FLAG_RX_MERGE_ENABLED,
1292 WX_FLAG_TXHEAD_WB_ENABLED,
1293 WX_FLAG_NEED_PCIE_RECOVERY,
1294 WX_PF_FLAGS_NBITS /* must be last */
1295 };
1296
1297 struct wx {
1298 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
1299 DECLARE_BITMAP(state, WX_STATE_NBITS);
1300 DECLARE_BITMAP(flags, WX_PF_FLAGS_NBITS);
1301
1302 void *priv;
1303 u8 __iomem *hw_addr;
1304 u8 __iomem *b4_addr; /* vf only */
1305 struct pci_dev *pdev;
1306 struct net_device *netdev;
1307 struct wx_bus_info bus;
1308 struct wx_mbx_info mbx;
1309 struct wx_mac_info mac;
1310 enum em_mac_type mac_type;
1311 enum wx_media_type media_type;
1312 struct wx_eeprom_info eeprom;
1313 struct wx_addr_filter_info addr_ctrl;
1314 struct wx_fc_info fc;
1315 struct wx_mac_addr *mac_table;
1316 u16 device_id;
1317 u16 vendor_id;
1318 u16 subsystem_device_id;
1319 u16 subsystem_vendor_id;
1320 u8 revision_id;
1321 u16 oem_ssid;
1322 u16 oem_svid;
1323 u16 msg_enable;
1324 bool adapter_stopped;
1325 u16 tpid[8];
1326 char eeprom_id[32];
1327 char *driver_name;
1328 enum wx_reset_type reset_type;
1329 u8 swfw_index;
1330
1331 /* PHY stuff */
1332 bool notify_down;
1333 unsigned int link;
1334 int speed;
1335 int duplex;
1336 struct phy_device *phydev;
1337 struct phylink *phylink;
1338 struct phylink_config phylink_config;
1339
1340 bool wol_hw_supported;
1341 bool ncsi_enabled;
1342 bool gpio_ctrl;
1343 raw_spinlock_t gpio_lock;
1344
1345 /* Tx fast path data */
1346 int num_tx_queues;
1347 u16 tx_itr_setting;
1348 u16 tx_work_limit;
1349
1350 /* Rx fast path data */
1351 int num_rx_queues;
1352 u16 rx_itr_setting;
1353 u16 rx_work_limit;
1354 bool adaptive_itr;
1355
1356 int num_q_vectors; /* current number of q_vectors for device */
1357 int max_q_vectors; /* upper limit of q_vectors for device */
1358
1359 u32 tx_ring_count;
1360 u32 rx_ring_count;
1361
1362 struct wx_ring *tx_ring[64] ____cacheline_aligned_in_smp;
1363 struct wx_ring *rx_ring[64];
1364 struct wx_q_vector *q_vector[64];
1365 int num_rx_pools;
1366 int num_rx_queues_per_pool;
1367
1368 unsigned int queues_per_pool;
1369 struct msix_entry *msix_q_entries;
1370 struct msix_entry *msix_entry;
1371 struct wx_ring_feature ring_feature[RING_F_ARRAY_SIZE];
1372
1373 /* misc interrupt status block */
1374 dma_addr_t isb_dma;
1375 u32 *isb_mem;
1376 u32 isb_tag[WX_ISB_MAX];
1377 bool misc_irq_domain;
1378 u32 eims_other;
1379 u32 eims_enable_mask;
1380
1381 #define WX_MAX_RETA_ENTRIES 128
1382 #define WX_RSS_INDIR_TBL_MAX 64
1383 u8 rss_indir_tbl[WX_MAX_RETA_ENTRIES];
1384 u8 rss_flags;
1385 bool rss_enabled;
1386 #define WX_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */
1387 u32 *rss_key;
1388 u32 wol;
1389
1390 u16 bd_number;
1391 bool default_up;
1392
1393 struct wx_hw_stats stats;
1394 struct wx_last_stats last_stats;
1395 spinlock_t hw_stats_lock; /* spinlock for accessing to hw stats */
1396 u64 tx_busy;
1397 u64 non_eop_descs;
1398 u64 restart_queue;
1399 u64 hw_csum_rx_good;
1400 u64 hw_csum_rx_error;
1401 u64 alloc_rx_buff_failed;
1402 u64 rsc_count;
1403 u64 rsc_flush;
1404 unsigned int num_vfs;
1405 struct vf_data_storage *vfinfo;
1406 struct vf_macvlans vf_mvs;
1407 struct vf_macvlans *mv_list;
1408 unsigned long fwd_bitmask;
1409
1410 u32 atr_sample_rate;
1411 void (*atr)(struct wx_ring *ring, struct wx_tx_buffer *first, u8 ptype);
1412 void (*configure_fdir)(struct wx *wx);
1413 int (*setup_tc)(struct net_device *netdev, u8 tc);
1414 void (*do_reset)(struct net_device *netdev, bool reinit);
1415 void (*down_suspend)(struct wx *wx);
1416 int (*ptp_setup_sdp)(struct wx *wx);
1417 void (*set_num_queues)(struct wx *wx);
1418
1419 bool pps_enabled;
1420 u64 pps_width;
1421 u64 pps_edge_start;
1422 u64 pps_edge_end;
1423 u64 sec_to_cc;
1424 u32 base_incval;
1425 u32 tx_hwtstamp_pkts;
1426 u32 tx_hwtstamp_timeouts;
1427 u32 tx_hwtstamp_skipped;
1428 u32 tx_hwtstamp_errors;
1429 u32 rx_hwtstamp_cleared;
1430 unsigned long last_overflow_check;
1431 unsigned long last_rx_ptp_check;
1432 unsigned long ptp_tx_start;
1433 seqlock_t hw_tc_lock; /* seqlock for ptp */
1434 struct cyclecounter hw_cc;
1435 struct timecounter hw_tc;
1436 struct ptp_clock *ptp_clock;
1437 struct ptp_clock_info ptp_caps;
1438 struct kernel_hwtstamp_config tstamp_config;
1439 struct sk_buff *ptp_tx_skb;
1440
1441 struct timer_list service_timer;
1442 struct work_struct service_task;
1443 struct work_struct reset_task;
1444 struct workqueue_struct *reset_wq;
1445 struct mutex reset_lock; /* mutex for reset */
1446 };
1447
1448 #define WX_INTR_ALL (~0ULL)
1449 #define WX_INTR_Q(i) BIT((i))
1450
1451 /* register operations */
1452 #define wr32(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
1453 #define rd32(a, reg) readl((a)->hw_addr + (reg))
1454 #define rd32a(a, reg, offset) ( \
1455 rd32((a), (reg) + ((offset) << 2)))
1456 #define wr32a(a, reg, off, val) \
1457 wr32((a), (reg) + ((off) << 2), (val))
1458
1459 static inline u32
rd32m(struct wx * wx,u32 reg,u32 mask)1460 rd32m(struct wx *wx, u32 reg, u32 mask)
1461 {
1462 u32 val;
1463
1464 val = rd32(wx, reg);
1465 return val & mask;
1466 }
1467
1468 static inline void
wr32m(struct wx * wx,u32 reg,u32 mask,u32 field)1469 wr32m(struct wx *wx, u32 reg, u32 mask, u32 field)
1470 {
1471 u32 val;
1472
1473 val = rd32(wx, reg);
1474 val = ((val & ~mask) | (field & mask));
1475
1476 wr32(wx, reg, val);
1477 }
1478
1479 static inline u64
rd64(struct wx * wx,u32 reg)1480 rd64(struct wx *wx, u32 reg)
1481 {
1482 u64 lsb, msb;
1483
1484 lsb = rd32(wx, reg);
1485 msb = rd32(wx, reg + 4);
1486
1487 return (lsb | msb << 32);
1488 }
1489
1490 static inline u32
rd32ptp(struct wx * wx,u32 reg)1491 rd32ptp(struct wx *wx, u32 reg)
1492 {
1493 if (wx->mac.type == wx_mac_em)
1494 return rd32(wx, reg);
1495
1496 return rd32(wx, reg + 0xB500);
1497 }
1498
1499 static inline void
wr32ptp(struct wx * wx,u32 reg,u32 value)1500 wr32ptp(struct wx *wx, u32 reg, u32 value)
1501 {
1502 if (wx->mac.type == wx_mac_em)
1503 return wr32(wx, reg, value);
1504
1505 return wr32(wx, reg + 0xB500, value);
1506 }
1507
1508 static inline u32
rd32_wrap(struct wx * wx,u32 reg,u32 * last)1509 rd32_wrap(struct wx *wx, u32 reg, u32 *last)
1510 {
1511 u32 val, delta;
1512
1513 val = rd32(wx, reg);
1514 delta = val - *last;
1515 *last = val;
1516
1517 return delta;
1518 }
1519
1520 /* On some domestic CPU platforms, sometimes IO is not synchronized with
1521 * flushing memory, here use readl() to flush PCI read and write.
1522 */
1523 #define WX_WRITE_FLUSH(H) rd32(H, WX_MIS_PWR)
1524
1525 #define wx_err(wx, fmt, arg...) \
1526 dev_err(&(wx)->pdev->dev, fmt, ##arg)
1527 #define wx_warn(wx, fmt, arg...) \
1528 dev_warn(&(wx)->pdev->dev, fmt, ##arg)
1529 #define wx_dbg(wx, fmt, arg...) \
1530 dev_dbg(&(wx)->pdev->dev, fmt, ##arg)
1531
phylink_to_wx(struct phylink_config * config)1532 static inline struct wx *phylink_to_wx(struct phylink_config *config)
1533 {
1534 return container_of(config, struct wx, phylink_config);
1535 }
1536
wx_rx_pg_order(struct wx_ring * ring)1537 static inline unsigned int wx_rx_pg_order(struct wx_ring *ring)
1538 {
1539 #if (PAGE_SIZE < 8192)
1540 if (ring->rx_buf_len == WX_RXBUFFER_3K)
1541 return 1;
1542 #endif
1543 return 0;
1544 }
1545
1546 #define wx_rx_pg_size(_ring) (PAGE_SIZE << wx_rx_pg_order(_ring))
1547
1548 #endif /* _WX_TYPE_H_ */
1549