1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/types.h> 7 #include <linux/pci.h> 8 #include <linux/netdevice.h> 9 #include <linux/etherdevice.h> 10 #include <linux/ethtool.h> 11 #include <linux/slab.h> 12 #include <linux/device.h> 13 #include <linux/skbuff.h> 14 #include <linux/if_vlan.h> 15 #include <linux/if_bridge.h> 16 #include <linux/workqueue.h> 17 #include <linux/jiffies.h> 18 #include <linux/bitops.h> 19 #include <linux/list.h> 20 #include <linux/notifier.h> 21 #include <linux/dcbnl.h> 22 #include <linux/inetdevice.h> 23 #include <linux/netlink.h> 24 #include <linux/jhash.h> 25 #include <linux/log2.h> 26 #include <linux/refcount.h> 27 #include <linux/rhashtable.h> 28 #include <net/switchdev.h> 29 #include <net/pkt_cls.h> 30 #include <net/netevent.h> 31 #include <net/addrconf.h> 32 #include <linux/ptp_classify.h> 33 34 #include "spectrum.h" 35 #include "pci.h" 36 #include "core.h" 37 #include "core_env.h" 38 #include "reg.h" 39 #include "port.h" 40 #include "trap.h" 41 #include "txheader.h" 42 #include "spectrum_cnt.h" 43 #include "spectrum_dpipe.h" 44 #include "spectrum_acl_flex_actions.h" 45 #include "spectrum_span.h" 46 #include "spectrum_ptp.h" 47 #include "spectrum_trap.h" 48 49 #define MLXSW_SP_FWREV_MINOR 2010 50 #define MLXSW_SP_FWREV_SUBMINOR 1006 51 52 #define MLXSW_SP1_FWREV_MAJOR 13 53 #define MLXSW_SP1_FWREV_CAN_RESET_MINOR 1702 54 55 static const struct mlxsw_fw_rev mlxsw_sp1_fw_rev = { 56 .major = MLXSW_SP1_FWREV_MAJOR, 57 .minor = MLXSW_SP_FWREV_MINOR, 58 .subminor = MLXSW_SP_FWREV_SUBMINOR, 59 .can_reset_minor = MLXSW_SP1_FWREV_CAN_RESET_MINOR, 60 }; 61 62 #define MLXSW_SP1_FW_FILENAME \ 63 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_SP1_FWREV_MAJOR) \ 64 "." __stringify(MLXSW_SP_FWREV_MINOR) \ 65 "." __stringify(MLXSW_SP_FWREV_SUBMINOR) ".mfa2" 66 67 #define MLXSW_SP2_FWREV_MAJOR 29 68 69 static const struct mlxsw_fw_rev mlxsw_sp2_fw_rev = { 70 .major = MLXSW_SP2_FWREV_MAJOR, 71 .minor = MLXSW_SP_FWREV_MINOR, 72 .subminor = MLXSW_SP_FWREV_SUBMINOR, 73 }; 74 75 #define MLXSW_SP2_FW_FILENAME \ 76 "mellanox/mlxsw_spectrum2-" __stringify(MLXSW_SP2_FWREV_MAJOR) \ 77 "." __stringify(MLXSW_SP_FWREV_MINOR) \ 78 "." __stringify(MLXSW_SP_FWREV_SUBMINOR) ".mfa2" 79 80 #define MLXSW_SP3_FWREV_MAJOR 30 81 82 static const struct mlxsw_fw_rev mlxsw_sp3_fw_rev = { 83 .major = MLXSW_SP3_FWREV_MAJOR, 84 .minor = MLXSW_SP_FWREV_MINOR, 85 .subminor = MLXSW_SP_FWREV_SUBMINOR, 86 }; 87 88 #define MLXSW_SP3_FW_FILENAME \ 89 "mellanox/mlxsw_spectrum3-" __stringify(MLXSW_SP3_FWREV_MAJOR) \ 90 "." __stringify(MLXSW_SP_FWREV_MINOR) \ 91 "." __stringify(MLXSW_SP_FWREV_SUBMINOR) ".mfa2" 92 93 #define MLXSW_SP_LINECARDS_INI_BUNDLE_FILENAME \ 94 "mellanox/lc_ini_bundle_" \ 95 __stringify(MLXSW_SP_FWREV_MINOR) "_" \ 96 __stringify(MLXSW_SP_FWREV_SUBMINOR) ".bin" 97 98 static const char mlxsw_sp1_driver_name[] = "mlxsw_spectrum"; 99 static const char mlxsw_sp2_driver_name[] = "mlxsw_spectrum2"; 100 static const char mlxsw_sp3_driver_name[] = "mlxsw_spectrum3"; 101 static const char mlxsw_sp4_driver_name[] = "mlxsw_spectrum4"; 102 103 static const unsigned char mlxsw_sp1_mac_mask[ETH_ALEN] = { 104 0xff, 0xff, 0xff, 0xff, 0xfc, 0x00 105 }; 106 static const unsigned char mlxsw_sp2_mac_mask[ETH_ALEN] = { 107 0xff, 0xff, 0xff, 0xff, 0xf0, 0x00 108 }; 109 110 int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp, 111 unsigned int counter_index, bool clear, 112 u64 *packets, u64 *bytes) 113 { 114 enum mlxsw_reg_mgpc_opcode op = clear ? MLXSW_REG_MGPC_OPCODE_CLEAR : 115 MLXSW_REG_MGPC_OPCODE_NOP; 116 char mgpc_pl[MLXSW_REG_MGPC_LEN]; 117 int err; 118 119 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, op, 120 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 121 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl); 122 if (err) 123 return err; 124 if (packets) 125 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl); 126 if (bytes) 127 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl); 128 return 0; 129 } 130 131 static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp, 132 unsigned int counter_index) 133 { 134 char mgpc_pl[MLXSW_REG_MGPC_LEN]; 135 136 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR, 137 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 138 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl); 139 } 140 141 int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp, 142 unsigned int *p_counter_index) 143 { 144 int err; 145 146 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 147 p_counter_index); 148 if (err) 149 return err; 150 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index); 151 if (err) 152 goto err_counter_clear; 153 return 0; 154 155 err_counter_clear: 156 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 157 *p_counter_index); 158 return err; 159 } 160 161 void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp, 162 unsigned int counter_index) 163 { 164 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 165 counter_index); 166 } 167 168 static bool mlxsw_sp_skb_requires_ts(struct sk_buff *skb) 169 { 170 unsigned int type; 171 172 if (!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) 173 return false; 174 175 type = ptp_classify_raw(skb); 176 return !!ptp_parse_header(skb, type); 177 } 178 179 static void mlxsw_sp_txhdr_info_data_init(struct mlxsw_core *mlxsw_core, 180 struct sk_buff *skb, 181 struct mlxsw_txhdr_info *txhdr_info) 182 { 183 /* Resource validation was done as part of PTP init. */ 184 u16 max_fid = MLXSW_CORE_RES_GET(mlxsw_core, FID); 185 186 txhdr_info->data = true; 187 txhdr_info->max_fid = max_fid; 188 } 189 190 static struct sk_buff * 191 mlxsw_sp_vlan_tag_push(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb) 192 { 193 /* In some Spectrum ASICs, in order for PTP event packets to have their 194 * correction field correctly set on the egress port they must be 195 * transmitted as data packets. Such packets ingress the ASIC via the 196 * CPU port and must have a VLAN tag, as the CPU port is not configured 197 * with a PVID. Push the default VLAN (4095), which is configured as 198 * egress untagged on all the ports. 199 */ 200 if (skb_vlan_tagged(skb)) 201 return skb; 202 203 return vlan_insert_tag_set_proto(skb, htons(ETH_P_8021Q), 204 MLXSW_SP_DEFAULT_VID); 205 } 206 207 static struct sk_buff * 208 mlxsw_sp_txhdr_preparations(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb, 209 struct mlxsw_txhdr_info *txhdr_info) 210 { 211 if (likely(!mlxsw_sp_skb_requires_ts(skb))) 212 return skb; 213 214 if (!mlxsw_sp->ptp_ops->tx_as_data) 215 return skb; 216 217 /* Special handling for PTP events that require a time stamp and cannot 218 * be transmitted as regular control packets. 219 */ 220 mlxsw_sp_txhdr_info_data_init(mlxsw_sp->core, skb, txhdr_info); 221 return mlxsw_sp_vlan_tag_push(mlxsw_sp, skb); 222 } 223 224 enum mlxsw_reg_spms_state mlxsw_sp_stp_spms_state(u8 state) 225 { 226 switch (state) { 227 case BR_STATE_FORWARDING: 228 return MLXSW_REG_SPMS_STATE_FORWARDING; 229 case BR_STATE_LEARNING: 230 return MLXSW_REG_SPMS_STATE_LEARNING; 231 case BR_STATE_LISTENING: 232 case BR_STATE_DISABLED: 233 case BR_STATE_BLOCKING: 234 return MLXSW_REG_SPMS_STATE_DISCARDING; 235 default: 236 BUG(); 237 } 238 } 239 240 int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid, 241 u8 state) 242 { 243 enum mlxsw_reg_spms_state spms_state = mlxsw_sp_stp_spms_state(state); 244 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 245 char *spms_pl; 246 int err; 247 248 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL); 249 if (!spms_pl) 250 return -ENOMEM; 251 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port); 252 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state); 253 254 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl); 255 kfree(spms_pl); 256 return err; 257 } 258 259 static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp) 260 { 261 char spad_pl[MLXSW_REG_SPAD_LEN] = {0}; 262 int err; 263 264 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl); 265 if (err) 266 return err; 267 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac); 268 return 0; 269 } 270 271 int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port, 272 bool is_up) 273 { 274 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 275 char paos_pl[MLXSW_REG_PAOS_LEN]; 276 277 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port, 278 is_up ? MLXSW_PORT_ADMIN_STATUS_UP : 279 MLXSW_PORT_ADMIN_STATUS_DOWN); 280 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl); 281 } 282 283 static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port, 284 const unsigned char *addr) 285 { 286 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 287 char ppad_pl[MLXSW_REG_PPAD_LEN]; 288 289 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port); 290 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr); 291 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl); 292 } 293 294 static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port) 295 { 296 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 297 298 eth_hw_addr_gen(mlxsw_sp_port->dev, mlxsw_sp->base_mac, 299 mlxsw_sp_port->local_port); 300 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, 301 mlxsw_sp_port->dev->dev_addr); 302 } 303 304 static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu) 305 { 306 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 307 char pmtu_pl[MLXSW_REG_PMTU_LEN]; 308 309 mtu += MLXSW_PORT_ETH_FRAME_HDR; 310 311 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu); 312 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl); 313 } 314 315 static int mlxsw_sp_port_swid_set(struct mlxsw_sp *mlxsw_sp, 316 u16 local_port, u8 swid) 317 { 318 char pspa_pl[MLXSW_REG_PSPA_LEN]; 319 320 mlxsw_reg_pspa_pack(pspa_pl, swid, local_port); 321 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl); 322 } 323 324 int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable) 325 { 326 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 327 char svpe_pl[MLXSW_REG_SVPE_LEN]; 328 329 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable); 330 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl); 331 } 332 333 int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid, 334 bool learn_enable) 335 { 336 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 337 char *spvmlr_pl; 338 int err; 339 340 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL); 341 if (!spvmlr_pl) 342 return -ENOMEM; 343 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid, 344 learn_enable); 345 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl); 346 kfree(spvmlr_pl); 347 return err; 348 } 349 350 int mlxsw_sp_port_security_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable) 351 { 352 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 353 char spfsr_pl[MLXSW_REG_SPFSR_LEN]; 354 int err; 355 356 if (mlxsw_sp_port->security == enable) 357 return 0; 358 359 mlxsw_reg_spfsr_pack(spfsr_pl, mlxsw_sp_port->local_port, enable); 360 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spfsr), spfsr_pl); 361 if (err) 362 return err; 363 364 mlxsw_sp_port->security = enable; 365 return 0; 366 } 367 368 int mlxsw_sp_ethtype_to_sver_type(u16 ethtype, u8 *p_sver_type) 369 { 370 switch (ethtype) { 371 case ETH_P_8021Q: 372 *p_sver_type = 0; 373 break; 374 case ETH_P_8021AD: 375 *p_sver_type = 1; 376 break; 377 default: 378 return -EINVAL; 379 } 380 381 return 0; 382 } 383 384 int mlxsw_sp_port_egress_ethtype_set(struct mlxsw_sp_port *mlxsw_sp_port, 385 u16 ethtype) 386 { 387 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 388 char spevet_pl[MLXSW_REG_SPEVET_LEN]; 389 u8 sver_type; 390 int err; 391 392 err = mlxsw_sp_ethtype_to_sver_type(ethtype, &sver_type); 393 if (err) 394 return err; 395 396 mlxsw_reg_spevet_pack(spevet_pl, mlxsw_sp_port->local_port, sver_type); 397 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spevet), spevet_pl); 398 } 399 400 static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, 401 u16 vid, u16 ethtype) 402 { 403 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 404 char spvid_pl[MLXSW_REG_SPVID_LEN]; 405 u8 sver_type; 406 int err; 407 408 err = mlxsw_sp_ethtype_to_sver_type(ethtype, &sver_type); 409 if (err) 410 return err; 411 412 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid, 413 sver_type); 414 415 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl); 416 } 417 418 static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port, 419 bool allow) 420 { 421 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 422 char spaft_pl[MLXSW_REG_SPAFT_LEN]; 423 424 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow); 425 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl); 426 } 427 428 int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid, 429 u16 ethtype) 430 { 431 int err; 432 433 if (!vid) { 434 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false); 435 if (err) 436 return err; 437 } else { 438 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid, ethtype); 439 if (err) 440 return err; 441 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true); 442 if (err) 443 goto err_port_allow_untagged_set; 444 } 445 446 mlxsw_sp_port->pvid = vid; 447 return 0; 448 449 err_port_allow_untagged_set: 450 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid, ethtype); 451 return err; 452 } 453 454 static int 455 mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port) 456 { 457 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 458 char sspr_pl[MLXSW_REG_SSPR_LEN]; 459 460 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port); 461 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl); 462 } 463 464 static int 465 mlxsw_sp_port_module_info_parse(struct mlxsw_sp *mlxsw_sp, 466 u16 local_port, char *pmlp_pl, 467 struct mlxsw_sp_port_mapping *port_mapping) 468 { 469 bool separate_rxtx; 470 u8 first_lane; 471 u8 slot_index; 472 u8 module; 473 u8 width; 474 int i; 475 476 module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0); 477 slot_index = mlxsw_reg_pmlp_slot_index_get(pmlp_pl, 0); 478 width = mlxsw_reg_pmlp_width_get(pmlp_pl); 479 separate_rxtx = mlxsw_reg_pmlp_rxtx_get(pmlp_pl); 480 first_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0); 481 482 if (width && !is_power_of_2(width)) { 483 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: width value is not power of 2\n", 484 local_port); 485 return -EINVAL; 486 } 487 488 for (i = 0; i < width; i++) { 489 if (mlxsw_reg_pmlp_module_get(pmlp_pl, i) != module) { 490 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: contains multiple modules\n", 491 local_port); 492 return -EINVAL; 493 } 494 if (mlxsw_reg_pmlp_slot_index_get(pmlp_pl, i) != slot_index) { 495 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: contains multiple slot indexes\n", 496 local_port); 497 return -EINVAL; 498 } 499 if (separate_rxtx && 500 mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, i) != 501 mlxsw_reg_pmlp_rx_lane_get(pmlp_pl, i)) { 502 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: TX and RX lane numbers are different\n", 503 local_port); 504 return -EINVAL; 505 } 506 if (mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, i) != i + first_lane) { 507 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: TX and RX lane numbers are not sequential\n", 508 local_port); 509 return -EINVAL; 510 } 511 } 512 513 port_mapping->module = module; 514 port_mapping->slot_index = slot_index; 515 port_mapping->width = width; 516 port_mapping->module_width = width; 517 port_mapping->lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0); 518 return 0; 519 } 520 521 static int 522 mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp, u16 local_port, 523 struct mlxsw_sp_port_mapping *port_mapping) 524 { 525 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 526 int err; 527 528 mlxsw_reg_pmlp_pack(pmlp_pl, local_port); 529 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 530 if (err) 531 return err; 532 return mlxsw_sp_port_module_info_parse(mlxsw_sp, local_port, 533 pmlp_pl, port_mapping); 534 } 535 536 static int 537 mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u16 local_port, 538 const struct mlxsw_sp_port_mapping *port_mapping) 539 { 540 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 541 int i, err; 542 543 mlxsw_env_module_port_map(mlxsw_sp->core, port_mapping->slot_index, 544 port_mapping->module); 545 546 mlxsw_reg_pmlp_pack(pmlp_pl, local_port); 547 mlxsw_reg_pmlp_width_set(pmlp_pl, port_mapping->width); 548 for (i = 0; i < port_mapping->width; i++) { 549 mlxsw_reg_pmlp_slot_index_set(pmlp_pl, i, 550 port_mapping->slot_index); 551 mlxsw_reg_pmlp_module_set(pmlp_pl, i, port_mapping->module); 552 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, port_mapping->lane + i); /* Rx & Tx */ 553 } 554 555 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 556 if (err) 557 goto err_pmlp_write; 558 return 0; 559 560 err_pmlp_write: 561 mlxsw_env_module_port_unmap(mlxsw_sp->core, port_mapping->slot_index, 562 port_mapping->module); 563 return err; 564 } 565 566 static void mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u16 local_port, 567 u8 slot_index, u8 module) 568 { 569 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 570 571 mlxsw_reg_pmlp_pack(pmlp_pl, local_port); 572 mlxsw_reg_pmlp_width_set(pmlp_pl, 0); 573 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 574 mlxsw_env_module_port_unmap(mlxsw_sp->core, slot_index, module); 575 } 576 577 static int mlxsw_sp_port_open(struct net_device *dev) 578 { 579 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 580 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 581 int err; 582 583 err = mlxsw_env_module_port_up(mlxsw_sp->core, 584 mlxsw_sp_port->mapping.slot_index, 585 mlxsw_sp_port->mapping.module); 586 if (err) 587 return err; 588 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true); 589 if (err) 590 goto err_port_admin_status_set; 591 netif_start_queue(dev); 592 return 0; 593 594 err_port_admin_status_set: 595 mlxsw_env_module_port_down(mlxsw_sp->core, 596 mlxsw_sp_port->mapping.slot_index, 597 mlxsw_sp_port->mapping.module); 598 return err; 599 } 600 601 static int mlxsw_sp_port_stop(struct net_device *dev) 602 { 603 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 604 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 605 606 netif_stop_queue(dev); 607 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 608 mlxsw_env_module_port_down(mlxsw_sp->core, 609 mlxsw_sp_port->mapping.slot_index, 610 mlxsw_sp_port->mapping.module); 611 return 0; 612 } 613 614 static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb, 615 struct net_device *dev) 616 { 617 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 618 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 619 struct mlxsw_sp_port_pcpu_stats *pcpu_stats; 620 struct mlxsw_txhdr_info txhdr_info = { 621 .tx_info.local_port = mlxsw_sp_port->local_port, 622 .tx_info.is_emad = false, 623 }; 624 u64 len; 625 int err; 626 627 memset(skb->cb, 0, sizeof(struct mlxsw_skb_cb)); 628 629 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &txhdr_info.tx_info)) 630 return NETDEV_TX_BUSY; 631 632 if (eth_skb_pad(skb)) { 633 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 634 return NETDEV_TX_OK; 635 } 636 637 skb = mlxsw_sp_txhdr_preparations(mlxsw_sp, skb, &txhdr_info); 638 if (!skb) { 639 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 640 return NETDEV_TX_OK; 641 } 642 643 /* TX header is consumed by HW on the way so we shouldn't count its 644 * bytes as being sent. 645 */ 646 len = skb->len - MLXSW_TXHDR_LEN; 647 648 /* Due to a race we might fail here because of a full queue. In that 649 * unlikely case we simply drop the packet. 650 */ 651 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &txhdr_info); 652 653 if (!err) { 654 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats); 655 u64_stats_update_begin(&pcpu_stats->syncp); 656 pcpu_stats->tx_packets++; 657 pcpu_stats->tx_bytes += len; 658 u64_stats_update_end(&pcpu_stats->syncp); 659 } else { 660 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 661 dev_kfree_skb_any(skb); 662 } 663 return NETDEV_TX_OK; 664 } 665 666 static void mlxsw_sp_set_rx_mode(struct net_device *dev) 667 { 668 } 669 670 static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p) 671 { 672 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 673 struct sockaddr *addr = p; 674 int err; 675 676 if (!is_valid_ether_addr(addr->sa_data)) 677 return -EADDRNOTAVAIL; 678 679 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data); 680 if (err) 681 return err; 682 eth_hw_addr_set(dev, addr->sa_data); 683 return 0; 684 } 685 686 static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu) 687 { 688 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 689 struct mlxsw_sp_hdroom orig_hdroom; 690 struct mlxsw_sp_hdroom hdroom; 691 int err; 692 693 orig_hdroom = *mlxsw_sp_port->hdroom; 694 695 hdroom = orig_hdroom; 696 hdroom.mtu = mtu; 697 mlxsw_sp_hdroom_bufs_reset_sizes(mlxsw_sp_port, &hdroom); 698 699 err = mlxsw_sp_hdroom_configure(mlxsw_sp_port, &hdroom); 700 if (err) { 701 netdev_err(dev, "Failed to configure port's headroom\n"); 702 return err; 703 } 704 705 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu); 706 if (err) 707 goto err_port_mtu_set; 708 WRITE_ONCE(dev->mtu, mtu); 709 return 0; 710 711 err_port_mtu_set: 712 mlxsw_sp_hdroom_configure(mlxsw_sp_port, &orig_hdroom); 713 return err; 714 } 715 716 static int 717 mlxsw_sp_port_get_sw_stats64(const struct net_device *dev, 718 struct rtnl_link_stats64 *stats) 719 { 720 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 721 struct mlxsw_sp_port_pcpu_stats *p; 722 u64 rx_packets, rx_bytes, tx_packets, tx_bytes; 723 u32 tx_dropped = 0; 724 unsigned int start; 725 int i; 726 727 for_each_possible_cpu(i) { 728 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i); 729 do { 730 start = u64_stats_fetch_begin(&p->syncp); 731 rx_packets = p->rx_packets; 732 rx_bytes = p->rx_bytes; 733 tx_packets = p->tx_packets; 734 tx_bytes = p->tx_bytes; 735 } while (u64_stats_fetch_retry(&p->syncp, start)); 736 737 stats->rx_packets += rx_packets; 738 stats->rx_bytes += rx_bytes; 739 stats->tx_packets += tx_packets; 740 stats->tx_bytes += tx_bytes; 741 /* tx_dropped is u32, updated without syncp protection. */ 742 tx_dropped += p->tx_dropped; 743 } 744 stats->tx_dropped = tx_dropped; 745 return 0; 746 } 747 748 static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id) 749 { 750 switch (attr_id) { 751 case IFLA_OFFLOAD_XSTATS_CPU_HIT: 752 return true; 753 } 754 755 return false; 756 } 757 758 static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev, 759 void *sp) 760 { 761 switch (attr_id) { 762 case IFLA_OFFLOAD_XSTATS_CPU_HIT: 763 return mlxsw_sp_port_get_sw_stats64(dev, sp); 764 } 765 766 return -EINVAL; 767 } 768 769 int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp, 770 int prio, char *ppcnt_pl) 771 { 772 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 773 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 774 775 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio); 776 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl); 777 } 778 779 static int mlxsw_sp_port_get_hw_stats(struct net_device *dev, 780 struct rtnl_link_stats64 *stats) 781 { 782 char ppcnt_pl[MLXSW_REG_PPCNT_LEN]; 783 int err; 784 785 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 786 0, ppcnt_pl); 787 if (err) 788 goto out; 789 790 stats->tx_packets = 791 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl); 792 stats->rx_packets = 793 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl); 794 stats->tx_bytes = 795 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl); 796 stats->rx_bytes = 797 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl); 798 stats->multicast = 799 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl); 800 801 stats->rx_crc_errors = 802 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl); 803 stats->rx_frame_errors = 804 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl); 805 806 stats->rx_length_errors = ( 807 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) + 808 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) + 809 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl)); 810 811 stats->rx_errors = (stats->rx_crc_errors + 812 stats->rx_frame_errors + stats->rx_length_errors); 813 814 out: 815 return err; 816 } 817 818 static void 819 mlxsw_sp_port_get_hw_xstats(struct net_device *dev, 820 struct mlxsw_sp_port_xstats *xstats) 821 { 822 char ppcnt_pl[MLXSW_REG_PPCNT_LEN]; 823 int err, i; 824 825 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0, 826 ppcnt_pl); 827 if (!err) 828 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl); 829 830 for (i = 0; i < TC_MAX_QUEUE; i++) { 831 err = mlxsw_sp_port_get_stats_raw(dev, 832 MLXSW_REG_PPCNT_TC_CONG_CNT, 833 i, ppcnt_pl); 834 if (err) 835 goto tc_cnt; 836 837 xstats->wred_drop[i] = 838 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl); 839 xstats->tc_ecn[i] = mlxsw_reg_ppcnt_ecn_marked_tc_get(ppcnt_pl); 840 841 tc_cnt: 842 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT, 843 i, ppcnt_pl); 844 if (err) 845 continue; 846 847 xstats->backlog[i] = 848 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl); 849 xstats->tail_drop[i] = 850 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl); 851 } 852 853 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 854 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT, 855 i, ppcnt_pl); 856 if (err) 857 continue; 858 859 xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl); 860 xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl); 861 } 862 } 863 864 static void update_stats_cache(struct work_struct *work) 865 { 866 struct mlxsw_sp_port *mlxsw_sp_port = 867 container_of(work, struct mlxsw_sp_port, 868 periodic_hw_stats.update_dw.work); 869 870 if (!netif_carrier_ok(mlxsw_sp_port->dev)) 871 /* Note: mlxsw_sp_port_down_wipe_counters() clears the cache as 872 * necessary when port goes down. 873 */ 874 goto out; 875 876 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev, 877 &mlxsw_sp_port->periodic_hw_stats.stats); 878 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev, 879 &mlxsw_sp_port->periodic_hw_stats.xstats); 880 881 out: 882 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 883 MLXSW_HW_STATS_UPDATE_TIME); 884 } 885 886 /* Return the stats from a cache that is updated periodically, 887 * as this function might get called in an atomic context. 888 */ 889 static void 890 mlxsw_sp_port_get_stats64(struct net_device *dev, 891 struct rtnl_link_stats64 *stats) 892 { 893 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 894 895 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats)); 896 } 897 898 static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, 899 u16 vid_begin, u16 vid_end, 900 bool is_member, bool untagged) 901 { 902 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 903 char *spvm_pl; 904 int err; 905 906 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL); 907 if (!spvm_pl) 908 return -ENOMEM; 909 910 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin, 911 vid_end, is_member, untagged); 912 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl); 913 kfree(spvm_pl); 914 return err; 915 } 916 917 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin, 918 u16 vid_end, bool is_member, bool untagged) 919 { 920 u16 vid, vid_e; 921 int err; 922 923 for (vid = vid_begin; vid <= vid_end; 924 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) { 925 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1), 926 vid_end); 927 928 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e, 929 is_member, untagged); 930 if (err) 931 return err; 932 } 933 934 return 0; 935 } 936 937 static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port, 938 bool flush_default) 939 { 940 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp; 941 942 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp, 943 &mlxsw_sp_port->vlans_list, list) { 944 if (!flush_default && 945 mlxsw_sp_port_vlan->vid == MLXSW_SP_DEFAULT_VID) 946 continue; 947 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan); 948 } 949 } 950 951 static void 952 mlxsw_sp_port_vlan_cleanup(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan) 953 { 954 if (mlxsw_sp_port_vlan->bridge_port) 955 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan); 956 else if (mlxsw_sp_port_vlan->fid) 957 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan); 958 } 959 960 struct mlxsw_sp_port_vlan * 961 mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid) 962 { 963 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 964 bool untagged = vid == MLXSW_SP_DEFAULT_VID; 965 int err; 966 967 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid); 968 if (mlxsw_sp_port_vlan) 969 return ERR_PTR(-EEXIST); 970 971 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged); 972 if (err) 973 return ERR_PTR(err); 974 975 mlxsw_sp_port_vlan = kzalloc_obj(*mlxsw_sp_port_vlan); 976 if (!mlxsw_sp_port_vlan) { 977 err = -ENOMEM; 978 goto err_port_vlan_alloc; 979 } 980 981 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port; 982 mlxsw_sp_port_vlan->vid = vid; 983 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list); 984 985 return mlxsw_sp_port_vlan; 986 987 err_port_vlan_alloc: 988 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false); 989 return ERR_PTR(err); 990 } 991 992 void mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan) 993 { 994 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port; 995 u16 vid = mlxsw_sp_port_vlan->vid; 996 997 mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port_vlan); 998 list_del(&mlxsw_sp_port_vlan->list); 999 kfree(mlxsw_sp_port_vlan); 1000 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false); 1001 } 1002 1003 static int mlxsw_sp_port_add_vid(struct net_device *dev, 1004 __be16 __always_unused proto, u16 vid) 1005 { 1006 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1007 1008 /* VLAN 0 is added to HW filter when device goes up, but it is 1009 * reserved in our case, so simply return. 1010 */ 1011 if (!vid) 1012 return 0; 1013 1014 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid)); 1015 } 1016 1017 int mlxsw_sp_port_kill_vid(struct net_device *dev, 1018 __be16 __always_unused proto, u16 vid) 1019 { 1020 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1021 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 1022 1023 /* VLAN 0 is removed from HW filter when device goes down, but 1024 * it is reserved in our case, so simply return. 1025 */ 1026 if (!vid) 1027 return 0; 1028 1029 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid); 1030 if (!mlxsw_sp_port_vlan) 1031 return 0; 1032 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan); 1033 1034 return 0; 1035 } 1036 1037 static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port, 1038 struct flow_block_offload *f) 1039 { 1040 switch (f->binder_type) { 1041 case FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS: 1042 return mlxsw_sp_setup_tc_block_clsact(mlxsw_sp_port, f, true); 1043 case FLOW_BLOCK_BINDER_TYPE_CLSACT_EGRESS: 1044 return mlxsw_sp_setup_tc_block_clsact(mlxsw_sp_port, f, false); 1045 case FLOW_BLOCK_BINDER_TYPE_RED_EARLY_DROP: 1046 return mlxsw_sp_setup_tc_block_qevent_early_drop(mlxsw_sp_port, f); 1047 case FLOW_BLOCK_BINDER_TYPE_RED_MARK: 1048 return mlxsw_sp_setup_tc_block_qevent_mark(mlxsw_sp_port, f); 1049 default: 1050 return -EOPNOTSUPP; 1051 } 1052 } 1053 1054 static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type, 1055 void *type_data) 1056 { 1057 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1058 1059 switch (type) { 1060 case TC_SETUP_BLOCK: 1061 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data); 1062 case TC_SETUP_QDISC_RED: 1063 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data); 1064 case TC_SETUP_QDISC_PRIO: 1065 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data); 1066 case TC_SETUP_QDISC_ETS: 1067 return mlxsw_sp_setup_tc_ets(mlxsw_sp_port, type_data); 1068 case TC_SETUP_QDISC_TBF: 1069 return mlxsw_sp_setup_tc_tbf(mlxsw_sp_port, type_data); 1070 case TC_SETUP_QDISC_FIFO: 1071 return mlxsw_sp_setup_tc_fifo(mlxsw_sp_port, type_data); 1072 default: 1073 return -EOPNOTSUPP; 1074 } 1075 } 1076 1077 static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable) 1078 { 1079 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1080 1081 if (!enable) { 1082 if (mlxsw_sp_flow_block_rule_count(mlxsw_sp_port->ing_flow_block) || 1083 mlxsw_sp_flow_block_rule_count(mlxsw_sp_port->eg_flow_block)) { 1084 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n"); 1085 return -EINVAL; 1086 } 1087 mlxsw_sp_flow_block_disable_inc(mlxsw_sp_port->ing_flow_block); 1088 mlxsw_sp_flow_block_disable_inc(mlxsw_sp_port->eg_flow_block); 1089 } else { 1090 mlxsw_sp_flow_block_disable_dec(mlxsw_sp_port->ing_flow_block); 1091 mlxsw_sp_flow_block_disable_dec(mlxsw_sp_port->eg_flow_block); 1092 } 1093 return 0; 1094 } 1095 1096 static int mlxsw_sp_feature_loopback(struct net_device *dev, bool enable) 1097 { 1098 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1099 char pplr_pl[MLXSW_REG_PPLR_LEN]; 1100 int err; 1101 1102 if (netif_running(dev)) 1103 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 1104 1105 mlxsw_reg_pplr_pack(pplr_pl, mlxsw_sp_port->local_port, enable); 1106 err = mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pplr), 1107 pplr_pl); 1108 1109 if (netif_running(dev)) 1110 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true); 1111 1112 return err; 1113 } 1114 1115 typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable); 1116 1117 static int mlxsw_sp_handle_feature(struct net_device *dev, 1118 netdev_features_t wanted_features, 1119 netdev_features_t feature, 1120 mlxsw_sp_feature_handler feature_handler) 1121 { 1122 netdev_features_t changes = wanted_features ^ dev->features; 1123 bool enable = !!(wanted_features & feature); 1124 int err; 1125 1126 if (!(changes & feature)) 1127 return 0; 1128 1129 err = feature_handler(dev, enable); 1130 if (err) { 1131 netdev_err(dev, "%s feature %pNF failed, err %d\n", 1132 enable ? "Enable" : "Disable", &feature, err); 1133 return err; 1134 } 1135 1136 if (enable) 1137 dev->features |= feature; 1138 else 1139 dev->features &= ~feature; 1140 1141 return 0; 1142 } 1143 static int mlxsw_sp_set_features(struct net_device *dev, 1144 netdev_features_t features) 1145 { 1146 netdev_features_t oper_features = dev->features; 1147 int err = 0; 1148 1149 err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC, 1150 mlxsw_sp_feature_hw_tc); 1151 err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_LOOPBACK, 1152 mlxsw_sp_feature_loopback); 1153 1154 if (err) { 1155 dev->features = oper_features; 1156 return -EINVAL; 1157 } 1158 1159 return 0; 1160 } 1161 1162 static int mlxsw_sp_port_hwtstamp_set(struct net_device *dev, 1163 struct kernel_hwtstamp_config *config, 1164 struct netlink_ext_ack *extack) 1165 { 1166 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1167 1168 return mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port, 1169 config, extack); 1170 } 1171 1172 static int mlxsw_sp_port_hwtstamp_get(struct net_device *dev, 1173 struct kernel_hwtstamp_config *config) 1174 { 1175 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1176 1177 return mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_get(mlxsw_sp_port, 1178 config); 1179 } 1180 1181 static inline void mlxsw_sp_port_ptp_clear(struct mlxsw_sp_port *mlxsw_sp_port) 1182 { 1183 struct kernel_hwtstamp_config config = {}; 1184 1185 mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port, &config, 1186 NULL); 1187 } 1188 1189 static const struct net_device_ops mlxsw_sp_port_netdev_ops = { 1190 .ndo_open = mlxsw_sp_port_open, 1191 .ndo_stop = mlxsw_sp_port_stop, 1192 .ndo_start_xmit = mlxsw_sp_port_xmit, 1193 .ndo_setup_tc = mlxsw_sp_setup_tc, 1194 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode, 1195 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address, 1196 .ndo_change_mtu = mlxsw_sp_port_change_mtu, 1197 .ndo_get_stats64 = mlxsw_sp_port_get_stats64, 1198 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats, 1199 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats, 1200 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid, 1201 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid, 1202 .ndo_set_features = mlxsw_sp_set_features, 1203 .ndo_hwtstamp_get = mlxsw_sp_port_hwtstamp_get, 1204 .ndo_hwtstamp_set = mlxsw_sp_port_hwtstamp_set, 1205 }; 1206 1207 static int 1208 mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port) 1209 { 1210 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1211 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper; 1212 const struct mlxsw_sp_port_type_speed_ops *ops; 1213 char ptys_pl[MLXSW_REG_PTYS_LEN]; 1214 u32 eth_proto_cap_masked; 1215 int err; 1216 1217 ops = mlxsw_sp->port_type_speed_ops; 1218 1219 /* Set advertised speeds to speeds supported by both the driver 1220 * and the device. 1221 */ 1222 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port, 1223 0, false); 1224 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 1225 if (err) 1226 return err; 1227 1228 ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, ð_proto_cap, 1229 ð_proto_admin, ð_proto_oper); 1230 eth_proto_cap_masked = ops->ptys_proto_cap_masked_get(eth_proto_cap); 1231 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port, 1232 eth_proto_cap_masked, 1233 mlxsw_sp_port->link.autoneg); 1234 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 1235 } 1236 1237 int mlxsw_sp_port_speed_get(struct mlxsw_sp_port *mlxsw_sp_port, u32 *speed) 1238 { 1239 const struct mlxsw_sp_port_type_speed_ops *port_type_speed_ops; 1240 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1241 char ptys_pl[MLXSW_REG_PTYS_LEN]; 1242 u32 eth_proto_oper; 1243 int err; 1244 1245 port_type_speed_ops = mlxsw_sp->port_type_speed_ops; 1246 port_type_speed_ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, 1247 mlxsw_sp_port->local_port, 0, 1248 false); 1249 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 1250 if (err) 1251 return err; 1252 port_type_speed_ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, NULL, NULL, 1253 ð_proto_oper); 1254 *speed = port_type_speed_ops->from_ptys_speed(mlxsw_sp, eth_proto_oper); 1255 return 0; 1256 } 1257 1258 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port, 1259 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index, 1260 bool dwrr, u8 dwrr_weight) 1261 { 1262 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1263 char qeec_pl[MLXSW_REG_QEEC_LEN]; 1264 1265 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index, 1266 next_index); 1267 mlxsw_reg_qeec_de_set(qeec_pl, true); 1268 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr); 1269 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight); 1270 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl); 1271 } 1272 1273 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port, 1274 enum mlxsw_reg_qeec_hr hr, u8 index, 1275 u8 next_index, u32 maxrate, u8 burst_size) 1276 { 1277 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1278 char qeec_pl[MLXSW_REG_QEEC_LEN]; 1279 1280 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index, 1281 next_index); 1282 mlxsw_reg_qeec_mase_set(qeec_pl, true); 1283 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate); 1284 mlxsw_reg_qeec_max_shaper_bs_set(qeec_pl, burst_size); 1285 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl); 1286 } 1287 1288 static int mlxsw_sp_port_min_bw_set(struct mlxsw_sp_port *mlxsw_sp_port, 1289 enum mlxsw_reg_qeec_hr hr, u8 index, 1290 u8 next_index, u32 minrate) 1291 { 1292 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1293 char qeec_pl[MLXSW_REG_QEEC_LEN]; 1294 1295 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index, 1296 next_index); 1297 mlxsw_reg_qeec_mise_set(qeec_pl, true); 1298 mlxsw_reg_qeec_min_shaper_rate_set(qeec_pl, minrate); 1299 1300 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl); 1301 } 1302 1303 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port, 1304 u8 switch_prio, u8 tclass) 1305 { 1306 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1307 char qtct_pl[MLXSW_REG_QTCT_LEN]; 1308 1309 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio, 1310 tclass); 1311 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl); 1312 } 1313 1314 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port) 1315 { 1316 int err, i; 1317 1318 /* Setup the elements hierarcy, so that each TC is linked to 1319 * one subgroup, which are all member in the same group. 1320 */ 1321 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 1322 MLXSW_REG_QEEC_HR_GROUP, 0, 0, false, 0); 1323 if (err) 1324 return err; 1325 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1326 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 1327 MLXSW_REG_QEEC_HR_SUBGROUP, i, 1328 0, false, 0); 1329 if (err) 1330 return err; 1331 } 1332 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1333 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 1334 MLXSW_REG_QEEC_HR_TC, i, i, 1335 false, 0); 1336 if (err) 1337 return err; 1338 1339 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 1340 MLXSW_REG_QEEC_HR_TC, 1341 i + 8, i, 1342 true, 100); 1343 if (err) 1344 return err; 1345 } 1346 1347 /* Make sure the max shaper is disabled in all hierarchies that support 1348 * it. Note that this disables ptps (PTP shaper), but that is intended 1349 * for the initial configuration. 1350 */ 1351 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 1352 MLXSW_REG_QEEC_HR_PORT, 0, 0, 1353 MLXSW_REG_QEEC_MAS_DIS, 0); 1354 if (err) 1355 return err; 1356 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1357 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 1358 MLXSW_REG_QEEC_HR_SUBGROUP, 1359 i, 0, 1360 MLXSW_REG_QEEC_MAS_DIS, 0); 1361 if (err) 1362 return err; 1363 } 1364 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1365 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 1366 MLXSW_REG_QEEC_HR_TC, 1367 i, i, 1368 MLXSW_REG_QEEC_MAS_DIS, 0); 1369 if (err) 1370 return err; 1371 1372 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 1373 MLXSW_REG_QEEC_HR_TC, 1374 i + 8, i, 1375 MLXSW_REG_QEEC_MAS_DIS, 0); 1376 if (err) 1377 return err; 1378 } 1379 1380 /* Configure the min shaper for multicast TCs. */ 1381 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1382 err = mlxsw_sp_port_min_bw_set(mlxsw_sp_port, 1383 MLXSW_REG_QEEC_HR_TC, 1384 i + 8, i, 1385 MLXSW_REG_QEEC_MIS_MIN); 1386 if (err) 1387 return err; 1388 } 1389 1390 /* Map all priorities to traffic class 0. */ 1391 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1392 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0); 1393 if (err) 1394 return err; 1395 } 1396 1397 return 0; 1398 } 1399 1400 static int mlxsw_sp_port_tc_mc_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, 1401 bool enable) 1402 { 1403 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1404 char qtctm_pl[MLXSW_REG_QTCTM_LEN]; 1405 1406 mlxsw_reg_qtctm_pack(qtctm_pl, mlxsw_sp_port->local_port, enable); 1407 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtctm), qtctm_pl); 1408 } 1409 1410 static int mlxsw_sp_port_overheat_init_val_set(struct mlxsw_sp_port *mlxsw_sp_port) 1411 { 1412 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1413 u8 slot_index = mlxsw_sp_port->mapping.slot_index; 1414 u8 module = mlxsw_sp_port->mapping.module; 1415 u64 overheat_counter; 1416 int err; 1417 1418 err = mlxsw_env_module_overheat_counter_get(mlxsw_sp->core, slot_index, 1419 module, &overheat_counter); 1420 if (err) 1421 return err; 1422 1423 mlxsw_sp_port->module_overheat_initial_val = overheat_counter; 1424 return 0; 1425 } 1426 1427 int 1428 mlxsw_sp_port_vlan_classification_set(struct mlxsw_sp_port *mlxsw_sp_port, 1429 bool is_8021ad_tagged, 1430 bool is_8021q_tagged) 1431 { 1432 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1433 char spvc_pl[MLXSW_REG_SPVC_LEN]; 1434 1435 mlxsw_reg_spvc_pack(spvc_pl, mlxsw_sp_port->local_port, 1436 is_8021ad_tagged, is_8021q_tagged); 1437 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvc), spvc_pl); 1438 } 1439 1440 static int mlxsw_sp_port_label_info_get(struct mlxsw_sp *mlxsw_sp, 1441 u16 local_port, u8 *port_number, 1442 u8 *split_port_subnumber, 1443 u8 *slot_index) 1444 { 1445 char pllp_pl[MLXSW_REG_PLLP_LEN]; 1446 int err; 1447 1448 mlxsw_reg_pllp_pack(pllp_pl, local_port); 1449 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pllp), pllp_pl); 1450 if (err) 1451 return err; 1452 mlxsw_reg_pllp_unpack(pllp_pl, port_number, 1453 split_port_subnumber, slot_index); 1454 return 0; 1455 } 1456 1457 static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u16 local_port, 1458 bool split, 1459 struct mlxsw_sp_port_mapping *port_mapping) 1460 { 1461 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 1462 struct mlxsw_sp_port *mlxsw_sp_port; 1463 u32 lanes = port_mapping->width; 1464 u8 split_port_subnumber; 1465 struct net_device *dev; 1466 u8 port_number; 1467 u8 slot_index; 1468 bool splittable; 1469 int err; 1470 1471 err = mlxsw_sp_port_module_map(mlxsw_sp, local_port, port_mapping); 1472 if (err) { 1473 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n", 1474 local_port); 1475 return err; 1476 } 1477 1478 err = mlxsw_sp_port_swid_set(mlxsw_sp, local_port, 0); 1479 if (err) { 1480 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n", 1481 local_port); 1482 goto err_port_swid_set; 1483 } 1484 1485 err = mlxsw_sp_port_label_info_get(mlxsw_sp, local_port, &port_number, 1486 &split_port_subnumber, &slot_index); 1487 if (err) { 1488 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to get port label information\n", 1489 local_port); 1490 goto err_port_label_info_get; 1491 } 1492 1493 splittable = lanes > 1 && !split; 1494 err = mlxsw_core_port_init(mlxsw_sp->core, local_port, slot_index, 1495 port_number, split, split_port_subnumber, 1496 splittable, lanes, mlxsw_sp->base_mac, 1497 sizeof(mlxsw_sp->base_mac)); 1498 if (err) { 1499 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n", 1500 local_port); 1501 goto err_core_port_init; 1502 } 1503 1504 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port)); 1505 if (!dev) { 1506 err = -ENOMEM; 1507 goto err_alloc_etherdev; 1508 } 1509 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev); 1510 dev_net_set(dev, mlxsw_sp_net(mlxsw_sp)); 1511 mlxsw_sp_port = netdev_priv(dev); 1512 mlxsw_core_port_netdev_link(mlxsw_sp->core, local_port, 1513 mlxsw_sp_port, dev); 1514 mlxsw_sp_port->dev = dev; 1515 mlxsw_sp_port->mlxsw_sp = mlxsw_sp; 1516 mlxsw_sp_port->local_port = local_port; 1517 mlxsw_sp_port->pvid = MLXSW_SP_DEFAULT_VID; 1518 mlxsw_sp_port->split = split; 1519 mlxsw_sp_port->mapping = *port_mapping; 1520 mlxsw_sp_port->link.autoneg = 1; 1521 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list); 1522 1523 mlxsw_sp_port->pcpu_stats = 1524 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats); 1525 if (!mlxsw_sp_port->pcpu_stats) { 1526 err = -ENOMEM; 1527 goto err_alloc_stats; 1528 } 1529 1530 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw, 1531 &update_stats_cache); 1532 1533 dev->netdev_ops = &mlxsw_sp_port_netdev_ops; 1534 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops; 1535 1536 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port); 1537 if (err) { 1538 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n", 1539 mlxsw_sp_port->local_port); 1540 goto err_dev_addr_init; 1541 } 1542 1543 netif_carrier_off(dev); 1544 1545 dev->features |= NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_FILTER | 1546 NETIF_F_HW_TC | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1547 dev->hw_features |= NETIF_F_HW_TC | NETIF_F_LOOPBACK | 1548 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1549 dev->vlan_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1550 dev->lltx = true; 1551 dev->netns_immutable = true; 1552 1553 dev->min_mtu = ETH_MIN_MTU; 1554 dev->max_mtu = MLXSW_PORT_MAX_MTU - MLXSW_PORT_ETH_FRAME_HDR; 1555 1556 /* Each packet needs to have a Tx header (metadata) on top all other 1557 * headers. 1558 */ 1559 dev->needed_headroom = MLXSW_TXHDR_LEN; 1560 1561 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port); 1562 if (err) { 1563 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n", 1564 mlxsw_sp_port->local_port); 1565 goto err_port_system_port_mapping_set; 1566 } 1567 1568 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port); 1569 if (err) { 1570 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n", 1571 mlxsw_sp_port->local_port); 1572 goto err_port_speed_by_width_set; 1573 } 1574 1575 err = mlxsw_sp->port_type_speed_ops->ptys_max_speed(mlxsw_sp_port, 1576 &mlxsw_sp_port->max_speed); 1577 if (err) { 1578 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to get maximum speed\n", 1579 mlxsw_sp_port->local_port); 1580 goto err_max_speed_get; 1581 } 1582 1583 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN); 1584 if (err) { 1585 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n", 1586 mlxsw_sp_port->local_port); 1587 goto err_port_mtu_set; 1588 } 1589 1590 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 1591 if (err) 1592 goto err_port_admin_status_set; 1593 1594 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port); 1595 if (err) { 1596 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n", 1597 mlxsw_sp_port->local_port); 1598 goto err_port_buffers_init; 1599 } 1600 1601 err = mlxsw_sp_port_ets_init(mlxsw_sp_port); 1602 if (err) { 1603 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n", 1604 mlxsw_sp_port->local_port); 1605 goto err_port_ets_init; 1606 } 1607 1608 err = mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, true); 1609 if (err) { 1610 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC MC mode\n", 1611 mlxsw_sp_port->local_port); 1612 goto err_port_tc_mc_mode; 1613 } 1614 1615 /* ETS and buffers must be initialized before DCB. */ 1616 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port); 1617 if (err) { 1618 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n", 1619 mlxsw_sp_port->local_port); 1620 goto err_port_dcb_init; 1621 } 1622 1623 err = mlxsw_sp_port_fids_init(mlxsw_sp_port); 1624 if (err) { 1625 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n", 1626 mlxsw_sp_port->local_port); 1627 goto err_port_fids_init; 1628 } 1629 1630 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port); 1631 if (err) { 1632 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n", 1633 mlxsw_sp_port->local_port); 1634 goto err_port_qdiscs_init; 1635 } 1636 1637 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 0, VLAN_N_VID - 1, false, 1638 false); 1639 if (err) { 1640 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to clear VLAN filter\n", 1641 mlxsw_sp_port->local_port); 1642 goto err_port_vlan_clear; 1643 } 1644 1645 err = mlxsw_sp_port_nve_init(mlxsw_sp_port); 1646 if (err) { 1647 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize NVE\n", 1648 mlxsw_sp_port->local_port); 1649 goto err_port_nve_init; 1650 } 1651 1652 err = mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID, 1653 ETH_P_8021Q); 1654 if (err) { 1655 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set PVID\n", 1656 mlxsw_sp_port->local_port); 1657 goto err_port_pvid_set; 1658 } 1659 1660 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_create(mlxsw_sp_port, 1661 MLXSW_SP_DEFAULT_VID); 1662 if (IS_ERR(mlxsw_sp_port_vlan)) { 1663 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n", 1664 mlxsw_sp_port->local_port); 1665 err = PTR_ERR(mlxsw_sp_port_vlan); 1666 goto err_port_vlan_create; 1667 } 1668 mlxsw_sp_port->default_vlan = mlxsw_sp_port_vlan; 1669 1670 /* Set SPVC.et0=true and SPVC.et1=false to make the local port to treat 1671 * only packets with 802.1q header as tagged packets. 1672 */ 1673 err = mlxsw_sp_port_vlan_classification_set(mlxsw_sp_port, false, true); 1674 if (err) { 1675 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set default VLAN classification\n", 1676 local_port); 1677 goto err_port_vlan_classification_set; 1678 } 1679 1680 INIT_DELAYED_WORK(&mlxsw_sp_port->ptp.shaper_dw, 1681 mlxsw_sp->ptp_ops->shaper_work); 1682 1683 mlxsw_sp->ports[local_port] = mlxsw_sp_port; 1684 1685 err = mlxsw_sp_port_overheat_init_val_set(mlxsw_sp_port); 1686 if (err) { 1687 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set overheat initial value\n", 1688 mlxsw_sp_port->local_port); 1689 goto err_port_overheat_init_val_set; 1690 } 1691 1692 err = register_netdev(dev); 1693 if (err) { 1694 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n", 1695 mlxsw_sp_port->local_port); 1696 goto err_register_netdev; 1697 } 1698 1699 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0); 1700 return 0; 1701 1702 err_register_netdev: 1703 err_port_overheat_init_val_set: 1704 mlxsw_sp_port_vlan_classification_set(mlxsw_sp_port, true, true); 1705 err_port_vlan_classification_set: 1706 mlxsw_sp->ports[local_port] = NULL; 1707 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan); 1708 err_port_vlan_create: 1709 err_port_pvid_set: 1710 mlxsw_sp_port_nve_fini(mlxsw_sp_port); 1711 err_port_nve_init: 1712 err_port_vlan_clear: 1713 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port); 1714 err_port_qdiscs_init: 1715 mlxsw_sp_port_fids_fini(mlxsw_sp_port); 1716 err_port_fids_init: 1717 mlxsw_sp_port_dcb_fini(mlxsw_sp_port); 1718 err_port_dcb_init: 1719 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false); 1720 err_port_tc_mc_mode: 1721 err_port_ets_init: 1722 mlxsw_sp_port_buffers_fini(mlxsw_sp_port); 1723 err_port_buffers_init: 1724 err_port_admin_status_set: 1725 err_port_mtu_set: 1726 err_max_speed_get: 1727 err_port_speed_by_width_set: 1728 err_port_system_port_mapping_set: 1729 err_dev_addr_init: 1730 free_percpu(mlxsw_sp_port->pcpu_stats); 1731 err_alloc_stats: 1732 free_netdev(dev); 1733 err_alloc_etherdev: 1734 mlxsw_core_port_fini(mlxsw_sp->core, local_port); 1735 err_core_port_init: 1736 err_port_label_info_get: 1737 mlxsw_sp_port_swid_set(mlxsw_sp, local_port, 1738 MLXSW_PORT_SWID_DISABLED_PORT); 1739 err_port_swid_set: 1740 mlxsw_sp_port_module_unmap(mlxsw_sp, local_port, 1741 port_mapping->slot_index, 1742 port_mapping->module); 1743 return err; 1744 } 1745 1746 static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u16 local_port) 1747 { 1748 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port]; 1749 u8 slot_index = mlxsw_sp_port->mapping.slot_index; 1750 u8 module = mlxsw_sp_port->mapping.module; 1751 1752 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw); 1753 cancel_delayed_work_sync(&mlxsw_sp_port->ptp.shaper_dw); 1754 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */ 1755 mlxsw_sp_port_ptp_clear(mlxsw_sp_port); 1756 mlxsw_sp_port_vlan_classification_set(mlxsw_sp_port, true, true); 1757 mlxsw_sp->ports[local_port] = NULL; 1758 mlxsw_sp_port_vlan_flush(mlxsw_sp_port, true); 1759 mlxsw_sp_port_nve_fini(mlxsw_sp_port); 1760 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port); 1761 mlxsw_sp_port_fids_fini(mlxsw_sp_port); 1762 mlxsw_sp_port_dcb_fini(mlxsw_sp_port); 1763 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false); 1764 mlxsw_sp_port_buffers_fini(mlxsw_sp_port); 1765 free_percpu(mlxsw_sp_port->pcpu_stats); 1766 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list)); 1767 free_netdev(mlxsw_sp_port->dev); 1768 mlxsw_core_port_fini(mlxsw_sp->core, local_port); 1769 mlxsw_sp_port_swid_set(mlxsw_sp, local_port, 1770 MLXSW_PORT_SWID_DISABLED_PORT); 1771 mlxsw_sp_port_module_unmap(mlxsw_sp, local_port, slot_index, module); 1772 } 1773 1774 static int mlxsw_sp_cpu_port_create(struct mlxsw_sp *mlxsw_sp) 1775 { 1776 struct mlxsw_sp_port *mlxsw_sp_port; 1777 int err; 1778 1779 mlxsw_sp_port = kzalloc_obj(*mlxsw_sp_port); 1780 if (!mlxsw_sp_port) 1781 return -ENOMEM; 1782 1783 mlxsw_sp_port->mlxsw_sp = mlxsw_sp; 1784 mlxsw_sp_port->local_port = MLXSW_PORT_CPU_PORT; 1785 1786 err = mlxsw_core_cpu_port_init(mlxsw_sp->core, 1787 mlxsw_sp_port, 1788 mlxsw_sp->base_mac, 1789 sizeof(mlxsw_sp->base_mac)); 1790 if (err) { 1791 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize core CPU port\n"); 1792 goto err_core_cpu_port_init; 1793 } 1794 1795 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = mlxsw_sp_port; 1796 return 0; 1797 1798 err_core_cpu_port_init: 1799 kfree(mlxsw_sp_port); 1800 return err; 1801 } 1802 1803 static void mlxsw_sp_cpu_port_remove(struct mlxsw_sp *mlxsw_sp) 1804 { 1805 struct mlxsw_sp_port *mlxsw_sp_port = 1806 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT]; 1807 1808 mlxsw_core_cpu_port_fini(mlxsw_sp->core); 1809 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = NULL; 1810 kfree(mlxsw_sp_port); 1811 } 1812 1813 static bool mlxsw_sp_local_port_valid(u16 local_port) 1814 { 1815 return local_port != MLXSW_PORT_CPU_PORT; 1816 } 1817 1818 static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u16 local_port) 1819 { 1820 if (!mlxsw_sp_local_port_valid(local_port)) 1821 return false; 1822 return mlxsw_sp->ports[local_port] != NULL; 1823 } 1824 1825 static int mlxsw_sp_port_mapping_event_set(struct mlxsw_sp *mlxsw_sp, 1826 u16 local_port, bool enable) 1827 { 1828 char pmecr_pl[MLXSW_REG_PMECR_LEN]; 1829 1830 mlxsw_reg_pmecr_pack(pmecr_pl, local_port, 1831 enable ? MLXSW_REG_PMECR_E_GENERATE_EVENT : 1832 MLXSW_REG_PMECR_E_DO_NOT_GENERATE_EVENT); 1833 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmecr), pmecr_pl); 1834 } 1835 1836 struct mlxsw_sp_port_mapping_event { 1837 struct list_head list; 1838 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 1839 }; 1840 1841 static void mlxsw_sp_port_mapping_events_work(struct work_struct *work) 1842 { 1843 struct mlxsw_sp_port_mapping_event *event, *next_event; 1844 struct mlxsw_sp_port_mapping_events *events; 1845 struct mlxsw_sp_port_mapping port_mapping; 1846 struct mlxsw_sp *mlxsw_sp; 1847 struct devlink *devlink; 1848 LIST_HEAD(event_queue); 1849 u16 local_port; 1850 int err; 1851 1852 events = container_of(work, struct mlxsw_sp_port_mapping_events, work); 1853 mlxsw_sp = container_of(events, struct mlxsw_sp, port_mapping_events); 1854 devlink = priv_to_devlink(mlxsw_sp->core); 1855 1856 spin_lock_bh(&events->queue_lock); 1857 list_splice_init(&events->queue, &event_queue); 1858 spin_unlock_bh(&events->queue_lock); 1859 1860 list_for_each_entry_safe(event, next_event, &event_queue, list) { 1861 local_port = mlxsw_reg_pmlp_local_port_get(event->pmlp_pl); 1862 err = mlxsw_sp_port_module_info_parse(mlxsw_sp, local_port, 1863 event->pmlp_pl, &port_mapping); 1864 if (err) 1865 goto out; 1866 1867 if (WARN_ON_ONCE(!port_mapping.width)) 1868 goto out; 1869 1870 devl_lock(devlink); 1871 1872 if (!mlxsw_sp_port_created(mlxsw_sp, local_port)) 1873 mlxsw_sp_port_create(mlxsw_sp, local_port, 1874 false, &port_mapping); 1875 else 1876 WARN_ON_ONCE(1); 1877 1878 devl_unlock(devlink); 1879 1880 mlxsw_sp->port_mapping[local_port] = port_mapping; 1881 1882 out: 1883 kfree(event); 1884 } 1885 } 1886 1887 static void 1888 mlxsw_sp_port_mapping_listener_func(const struct mlxsw_reg_info *reg, 1889 char *pmlp_pl, void *priv) 1890 { 1891 struct mlxsw_sp_port_mapping_events *events; 1892 struct mlxsw_sp_port_mapping_event *event; 1893 struct mlxsw_sp *mlxsw_sp = priv; 1894 u16 local_port; 1895 1896 local_port = mlxsw_reg_pmlp_local_port_get(pmlp_pl); 1897 if (WARN_ON_ONCE(!mlxsw_sp_local_port_is_valid(mlxsw_sp, local_port))) 1898 return; 1899 1900 events = &mlxsw_sp->port_mapping_events; 1901 event = kmalloc_obj(*event, GFP_ATOMIC); 1902 if (!event) 1903 return; 1904 memcpy(event->pmlp_pl, pmlp_pl, sizeof(event->pmlp_pl)); 1905 spin_lock(&events->queue_lock); 1906 list_add_tail(&event->list, &events->queue); 1907 spin_unlock(&events->queue_lock); 1908 mlxsw_core_schedule_work(&events->work); 1909 } 1910 1911 static void 1912 __mlxsw_sp_port_mapping_events_cancel(struct mlxsw_sp *mlxsw_sp) 1913 { 1914 struct mlxsw_sp_port_mapping_event *event, *next_event; 1915 struct mlxsw_sp_port_mapping_events *events; 1916 1917 events = &mlxsw_sp->port_mapping_events; 1918 1919 /* Caller needs to make sure that no new event is going to appear. */ 1920 cancel_work_sync(&events->work); 1921 list_for_each_entry_safe(event, next_event, &events->queue, list) { 1922 list_del(&event->list); 1923 kfree(event); 1924 } 1925 } 1926 1927 static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp) 1928 { 1929 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core); 1930 int i; 1931 1932 for (i = 1; i < max_ports; i++) 1933 mlxsw_sp_port_mapping_event_set(mlxsw_sp, i, false); 1934 /* Make sure all scheduled events are processed */ 1935 __mlxsw_sp_port_mapping_events_cancel(mlxsw_sp); 1936 1937 for (i = 1; i < max_ports; i++) 1938 if (mlxsw_sp_port_created(mlxsw_sp, i)) 1939 mlxsw_sp_port_remove(mlxsw_sp, i); 1940 mlxsw_sp_cpu_port_remove(mlxsw_sp); 1941 kfree(mlxsw_sp->ports); 1942 mlxsw_sp->ports = NULL; 1943 } 1944 1945 static void 1946 mlxsw_sp_ports_remove_selected(struct mlxsw_core *mlxsw_core, 1947 bool (*selector)(void *priv, u16 local_port), 1948 void *priv) 1949 { 1950 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 1951 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_core); 1952 int i; 1953 1954 for (i = 1; i < max_ports; i++) 1955 if (mlxsw_sp_port_created(mlxsw_sp, i) && selector(priv, i)) 1956 mlxsw_sp_port_remove(mlxsw_sp, i); 1957 } 1958 1959 static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp) 1960 { 1961 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core); 1962 struct mlxsw_sp_port_mapping_events *events; 1963 struct mlxsw_sp_port_mapping *port_mapping; 1964 size_t alloc_size; 1965 int i; 1966 int err; 1967 1968 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports; 1969 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL); 1970 if (!mlxsw_sp->ports) 1971 return -ENOMEM; 1972 1973 events = &mlxsw_sp->port_mapping_events; 1974 INIT_LIST_HEAD(&events->queue); 1975 spin_lock_init(&events->queue_lock); 1976 INIT_WORK(&events->work, mlxsw_sp_port_mapping_events_work); 1977 1978 for (i = 1; i < max_ports; i++) { 1979 err = mlxsw_sp_port_mapping_event_set(mlxsw_sp, i, true); 1980 if (err) 1981 goto err_event_enable; 1982 } 1983 1984 err = mlxsw_sp_cpu_port_create(mlxsw_sp); 1985 if (err) 1986 goto err_cpu_port_create; 1987 1988 for (i = 1; i < max_ports; i++) { 1989 port_mapping = &mlxsw_sp->port_mapping[i]; 1990 if (!port_mapping->width) 1991 continue; 1992 err = mlxsw_sp_port_create(mlxsw_sp, i, false, port_mapping); 1993 if (err) 1994 goto err_port_create; 1995 } 1996 return 0; 1997 1998 err_port_create: 1999 for (i--; i >= 1; i--) 2000 if (mlxsw_sp_port_created(mlxsw_sp, i)) 2001 mlxsw_sp_port_remove(mlxsw_sp, i); 2002 i = max_ports; 2003 mlxsw_sp_cpu_port_remove(mlxsw_sp); 2004 err_cpu_port_create: 2005 err_event_enable: 2006 for (i--; i >= 1; i--) 2007 mlxsw_sp_port_mapping_event_set(mlxsw_sp, i, false); 2008 /* Make sure all scheduled events are processed */ 2009 __mlxsw_sp_port_mapping_events_cancel(mlxsw_sp); 2010 kfree(mlxsw_sp->ports); 2011 mlxsw_sp->ports = NULL; 2012 return err; 2013 } 2014 2015 static int mlxsw_sp_port_module_info_init(struct mlxsw_sp *mlxsw_sp) 2016 { 2017 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core); 2018 struct mlxsw_sp_port_mapping *port_mapping; 2019 int i; 2020 int err; 2021 2022 mlxsw_sp->port_mapping = kzalloc_objs(struct mlxsw_sp_port_mapping, 2023 max_ports); 2024 if (!mlxsw_sp->port_mapping) 2025 return -ENOMEM; 2026 2027 for (i = 1; i < max_ports; i++) { 2028 port_mapping = &mlxsw_sp->port_mapping[i]; 2029 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, port_mapping); 2030 if (err) 2031 goto err_port_module_info_get; 2032 } 2033 return 0; 2034 2035 err_port_module_info_get: 2036 kfree(mlxsw_sp->port_mapping); 2037 return err; 2038 } 2039 2040 static void mlxsw_sp_port_module_info_fini(struct mlxsw_sp *mlxsw_sp) 2041 { 2042 kfree(mlxsw_sp->port_mapping); 2043 } 2044 2045 static int 2046 mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, 2047 struct mlxsw_sp_port_mapping *port_mapping, 2048 unsigned int count, const char *pmtdb_pl) 2049 { 2050 struct mlxsw_sp_port_mapping split_port_mapping; 2051 int err, i; 2052 2053 split_port_mapping = *port_mapping; 2054 split_port_mapping.width /= count; 2055 for (i = 0; i < count; i++) { 2056 u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i); 2057 2058 if (!mlxsw_sp_local_port_valid(s_local_port)) 2059 continue; 2060 2061 err = mlxsw_sp_port_create(mlxsw_sp, s_local_port, 2062 true, &split_port_mapping); 2063 if (err) 2064 goto err_port_create; 2065 split_port_mapping.lane += split_port_mapping.width; 2066 } 2067 2068 return 0; 2069 2070 err_port_create: 2071 for (i--; i >= 0; i--) { 2072 u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i); 2073 2074 if (mlxsw_sp_port_created(mlxsw_sp, s_local_port)) 2075 mlxsw_sp_port_remove(mlxsw_sp, s_local_port); 2076 } 2077 return err; 2078 } 2079 2080 static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp, 2081 unsigned int count, 2082 const char *pmtdb_pl) 2083 { 2084 struct mlxsw_sp_port_mapping *port_mapping; 2085 int i; 2086 2087 /* Go over original unsplit ports in the gap and recreate them. */ 2088 for (i = 0; i < count; i++) { 2089 u16 local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i); 2090 2091 port_mapping = &mlxsw_sp->port_mapping[local_port]; 2092 if (!port_mapping->width || !mlxsw_sp_local_port_valid(local_port)) 2093 continue; 2094 mlxsw_sp_port_create(mlxsw_sp, local_port, 2095 false, port_mapping); 2096 } 2097 } 2098 2099 static struct mlxsw_sp_port * 2100 mlxsw_sp_port_get_by_local_port(struct mlxsw_sp *mlxsw_sp, u16 local_port) 2101 { 2102 if (mlxsw_sp->ports && mlxsw_sp->ports[local_port]) 2103 return mlxsw_sp->ports[local_port]; 2104 return NULL; 2105 } 2106 2107 static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u16 local_port, 2108 unsigned int count, 2109 struct netlink_ext_ack *extack) 2110 { 2111 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 2112 struct mlxsw_sp_port_mapping port_mapping; 2113 struct mlxsw_sp_port *mlxsw_sp_port; 2114 enum mlxsw_reg_pmtdb_status status; 2115 char pmtdb_pl[MLXSW_REG_PMTDB_LEN]; 2116 int i; 2117 int err; 2118 2119 mlxsw_sp_port = mlxsw_sp_port_get_by_local_port(mlxsw_sp, local_port); 2120 if (!mlxsw_sp_port) { 2121 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n", 2122 local_port); 2123 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist"); 2124 return -EINVAL; 2125 } 2126 2127 if (mlxsw_sp_port->split) { 2128 NL_SET_ERR_MSG_MOD(extack, "Port is already split"); 2129 return -EINVAL; 2130 } 2131 2132 mlxsw_reg_pmtdb_pack(pmtdb_pl, mlxsw_sp_port->mapping.slot_index, 2133 mlxsw_sp_port->mapping.module, 2134 mlxsw_sp_port->mapping.module_width / count, 2135 count); 2136 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(pmtdb), pmtdb_pl); 2137 if (err) { 2138 NL_SET_ERR_MSG_MOD(extack, "Failed to query split info"); 2139 return err; 2140 } 2141 2142 status = mlxsw_reg_pmtdb_status_get(pmtdb_pl); 2143 if (status != MLXSW_REG_PMTDB_STATUS_SUCCESS) { 2144 NL_SET_ERR_MSG_MOD(extack, "Unsupported split configuration"); 2145 return -EINVAL; 2146 } 2147 2148 port_mapping = mlxsw_sp_port->mapping; 2149 2150 for (i = 0; i < count; i++) { 2151 u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i); 2152 2153 if (mlxsw_sp_port_created(mlxsw_sp, s_local_port)) 2154 mlxsw_sp_port_remove(mlxsw_sp, s_local_port); 2155 } 2156 2157 err = mlxsw_sp_port_split_create(mlxsw_sp, &port_mapping, 2158 count, pmtdb_pl); 2159 if (err) { 2160 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n"); 2161 goto err_port_split_create; 2162 } 2163 2164 return 0; 2165 2166 err_port_split_create: 2167 mlxsw_sp_port_unsplit_create(mlxsw_sp, count, pmtdb_pl); 2168 2169 return err; 2170 } 2171 2172 static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u16 local_port, 2173 struct netlink_ext_ack *extack) 2174 { 2175 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 2176 struct mlxsw_sp_port *mlxsw_sp_port; 2177 char pmtdb_pl[MLXSW_REG_PMTDB_LEN]; 2178 unsigned int count; 2179 int i; 2180 int err; 2181 2182 mlxsw_sp_port = mlxsw_sp_port_get_by_local_port(mlxsw_sp, local_port); 2183 if (!mlxsw_sp_port) { 2184 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n", 2185 local_port); 2186 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist"); 2187 return -EINVAL; 2188 } 2189 2190 if (!mlxsw_sp_port->split) { 2191 NL_SET_ERR_MSG_MOD(extack, "Port was not split"); 2192 return -EINVAL; 2193 } 2194 2195 count = mlxsw_sp_port->mapping.module_width / 2196 mlxsw_sp_port->mapping.width; 2197 2198 mlxsw_reg_pmtdb_pack(pmtdb_pl, mlxsw_sp_port->mapping.slot_index, 2199 mlxsw_sp_port->mapping.module, 2200 mlxsw_sp_port->mapping.module_width / count, 2201 count); 2202 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(pmtdb), pmtdb_pl); 2203 if (err) { 2204 NL_SET_ERR_MSG_MOD(extack, "Failed to query split info"); 2205 return err; 2206 } 2207 2208 for (i = 0; i < count; i++) { 2209 u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i); 2210 2211 if (mlxsw_sp_port_created(mlxsw_sp, s_local_port)) 2212 mlxsw_sp_port_remove(mlxsw_sp, s_local_port); 2213 } 2214 2215 mlxsw_sp_port_unsplit_create(mlxsw_sp, count, pmtdb_pl); 2216 2217 return 0; 2218 } 2219 2220 static void 2221 mlxsw_sp_port_down_wipe_counters(struct mlxsw_sp_port *mlxsw_sp_port) 2222 { 2223 int i; 2224 2225 for (i = 0; i < TC_MAX_QUEUE; i++) 2226 mlxsw_sp_port->periodic_hw_stats.xstats.backlog[i] = 0; 2227 } 2228 2229 static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg, 2230 char *pude_pl, void *priv) 2231 { 2232 struct mlxsw_sp *mlxsw_sp = priv; 2233 struct mlxsw_sp_port *mlxsw_sp_port; 2234 enum mlxsw_reg_pude_oper_status status; 2235 u16 local_port; 2236 2237 local_port = mlxsw_reg_pude_local_port_get(pude_pl); 2238 2239 if (WARN_ON_ONCE(!mlxsw_sp_local_port_is_valid(mlxsw_sp, local_port))) 2240 return; 2241 mlxsw_sp_port = mlxsw_sp->ports[local_port]; 2242 if (!mlxsw_sp_port) 2243 return; 2244 2245 status = mlxsw_reg_pude_oper_status_get(pude_pl); 2246 if (status == MLXSW_PORT_OPER_STATUS_UP) { 2247 netdev_info(mlxsw_sp_port->dev, "link up\n"); 2248 netif_carrier_on(mlxsw_sp_port->dev); 2249 mlxsw_core_schedule_dw(&mlxsw_sp_port->ptp.shaper_dw, 0); 2250 } else { 2251 netdev_info(mlxsw_sp_port->dev, "link down\n"); 2252 netif_carrier_off(mlxsw_sp_port->dev); 2253 mlxsw_sp_port_down_wipe_counters(mlxsw_sp_port); 2254 } 2255 } 2256 2257 static void mlxsw_sp1_ptp_fifo_event_func(struct mlxsw_sp *mlxsw_sp, 2258 char *mtpptr_pl, bool ingress) 2259 { 2260 u16 local_port; 2261 u8 num_rec; 2262 int i; 2263 2264 local_port = mlxsw_reg_mtpptr_local_port_get(mtpptr_pl); 2265 num_rec = mlxsw_reg_mtpptr_num_rec_get(mtpptr_pl); 2266 for (i = 0; i < num_rec; i++) { 2267 u8 domain_number; 2268 u8 message_type; 2269 u16 sequence_id; 2270 u64 timestamp; 2271 2272 mlxsw_reg_mtpptr_unpack(mtpptr_pl, i, &message_type, 2273 &domain_number, &sequence_id, 2274 ×tamp); 2275 mlxsw_sp1_ptp_got_timestamp(mlxsw_sp, ingress, local_port, 2276 message_type, domain_number, 2277 sequence_id, timestamp); 2278 } 2279 } 2280 2281 static void mlxsw_sp1_ptp_ing_fifo_event_func(const struct mlxsw_reg_info *reg, 2282 char *mtpptr_pl, void *priv) 2283 { 2284 struct mlxsw_sp *mlxsw_sp = priv; 2285 2286 mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, true); 2287 } 2288 2289 static void mlxsw_sp1_ptp_egr_fifo_event_func(const struct mlxsw_reg_info *reg, 2290 char *mtpptr_pl, void *priv) 2291 { 2292 struct mlxsw_sp *mlxsw_sp = priv; 2293 2294 mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, false); 2295 } 2296 2297 void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb, 2298 u16 local_port, void *priv) 2299 { 2300 struct mlxsw_sp *mlxsw_sp = priv; 2301 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port]; 2302 struct mlxsw_sp_port_pcpu_stats *pcpu_stats; 2303 2304 if (unlikely(!mlxsw_sp_port)) { 2305 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n", 2306 local_port); 2307 return; 2308 } 2309 2310 skb->dev = mlxsw_sp_port->dev; 2311 2312 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats); 2313 u64_stats_update_begin(&pcpu_stats->syncp); 2314 pcpu_stats->rx_packets++; 2315 pcpu_stats->rx_bytes += skb->len; 2316 u64_stats_update_end(&pcpu_stats->syncp); 2317 2318 skb->protocol = eth_type_trans(skb, skb->dev); 2319 napi_gro_receive(mlxsw_skb_cb(skb)->rx_md_info.napi, skb); 2320 } 2321 2322 static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u16 local_port, 2323 void *priv) 2324 { 2325 skb->offload_fwd_mark = 1; 2326 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv); 2327 } 2328 2329 static void mlxsw_sp_rx_listener_l3_mark_func(struct sk_buff *skb, 2330 u16 local_port, void *priv) 2331 { 2332 skb->offload_l3_fwd_mark = 1; 2333 skb->offload_fwd_mark = 1; 2334 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv); 2335 } 2336 2337 void mlxsw_sp_ptp_receive(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb, 2338 u16 local_port) 2339 { 2340 mlxsw_sp->ptp_ops->receive(mlxsw_sp, skb, local_port); 2341 } 2342 2343 #define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 2344 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \ 2345 _is_ctrl, SP_##_trap_group, DISCARD) 2346 2347 #define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 2348 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \ 2349 _is_ctrl, SP_##_trap_group, DISCARD) 2350 2351 #define MLXSW_SP_RXL_L3_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 2352 MLXSW_RXL(mlxsw_sp_rx_listener_l3_mark_func, _trap_id, _action, \ 2353 _is_ctrl, SP_##_trap_group, DISCARD) 2354 2355 #define MLXSW_SP_EVENTL(_func, _trap_id) \ 2356 MLXSW_EVENTL(_func, _trap_id, SP_EVENT) 2357 2358 static const struct mlxsw_listener mlxsw_sp_listener[] = { 2359 /* Events */ 2360 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE), 2361 /* L2 traps */ 2362 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, FID_MISS, false), 2363 /* L3 traps */ 2364 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP, 2365 false), 2366 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false), 2367 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, 2368 false), 2369 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_SIP_CLASS_E, FORWARD, 2370 ROUTER_EXP, false), 2371 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_MC_DMAC, FORWARD, 2372 ROUTER_EXP, false), 2373 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_SIP_DIP, FORWARD, 2374 ROUTER_EXP, false), 2375 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_DIP_LINK_LOCAL, FORWARD, 2376 ROUTER_EXP, false), 2377 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_SIP_LINK_LOCAL, FORWARD, 2378 ROUTER_EXP, false), 2379 /* Multicast Router Traps */ 2380 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false), 2381 MLXSW_SP_RXL_L3_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false), 2382 }; 2383 2384 static const struct mlxsw_listener mlxsw_sp1_listener[] = { 2385 /* Events */ 2386 MLXSW_EVENTL(mlxsw_sp1_ptp_egr_fifo_event_func, PTP_EGR_FIFO, SP_PTP0), 2387 MLXSW_EVENTL(mlxsw_sp1_ptp_ing_fifo_event_func, PTP_ING_FIFO, SP_PTP0), 2388 }; 2389 2390 static const struct mlxsw_listener mlxsw_sp2_listener[] = { 2391 /* Events */ 2392 MLXSW_SP_EVENTL(mlxsw_sp_port_mapping_listener_func, PMLPE), 2393 }; 2394 2395 static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core) 2396 { 2397 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 2398 char qpcr_pl[MLXSW_REG_QPCR_LEN]; 2399 enum mlxsw_reg_qpcr_ir_units ir_units; 2400 int max_cpu_policers; 2401 bool is_bytes; 2402 u8 burst_size; 2403 u32 rate; 2404 int i, err; 2405 2406 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS)) 2407 return -EIO; 2408 2409 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS); 2410 2411 ir_units = MLXSW_REG_QPCR_IR_UNITS_M; 2412 for (i = 0; i < max_cpu_policers; i++) { 2413 is_bytes = false; 2414 switch (i) { 2415 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP: 2416 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST: 2417 case MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS: 2418 rate = 1024; 2419 burst_size = 7; 2420 break; 2421 default: 2422 continue; 2423 } 2424 2425 __set_bit(i, mlxsw_sp->trap->policers_usage); 2426 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate, 2427 burst_size); 2428 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl); 2429 if (err) 2430 return err; 2431 } 2432 2433 return 0; 2434 } 2435 2436 static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core) 2437 { 2438 char htgt_pl[MLXSW_REG_HTGT_LEN]; 2439 enum mlxsw_reg_htgt_trap_group i; 2440 int max_cpu_policers; 2441 int max_trap_groups; 2442 u8 priority, tc; 2443 u16 policer_id; 2444 int err; 2445 2446 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS)) 2447 return -EIO; 2448 2449 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS); 2450 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS); 2451 2452 for (i = 0; i < max_trap_groups; i++) { 2453 policer_id = i; 2454 switch (i) { 2455 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP: 2456 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST: 2457 case MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS: 2458 priority = 1; 2459 tc = 1; 2460 break; 2461 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT: 2462 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY; 2463 tc = MLXSW_REG_HTGT_DEFAULT_TC; 2464 policer_id = MLXSW_REG_HTGT_INVALID_POLICER; 2465 break; 2466 default: 2467 continue; 2468 } 2469 2470 if (max_cpu_policers <= policer_id && 2471 policer_id != MLXSW_REG_HTGT_INVALID_POLICER) 2472 return -EIO; 2473 2474 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc); 2475 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl); 2476 if (err) 2477 return err; 2478 } 2479 2480 return 0; 2481 } 2482 2483 static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp) 2484 { 2485 struct mlxsw_sp_trap *trap; 2486 u64 max_policers; 2487 int err; 2488 2489 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_CPU_POLICERS)) 2490 return -EIO; 2491 max_policers = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_CPU_POLICERS); 2492 trap = kzalloc_flex(*trap, policers_usage, BITS_TO_LONGS(max_policers)); 2493 if (!trap) 2494 return -ENOMEM; 2495 trap->max_policers = max_policers; 2496 mlxsw_sp->trap = trap; 2497 2498 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core); 2499 if (err) 2500 goto err_cpu_policers_set; 2501 2502 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core); 2503 if (err) 2504 goto err_trap_groups_set; 2505 2506 err = mlxsw_core_traps_register(mlxsw_sp->core, mlxsw_sp_listener, 2507 ARRAY_SIZE(mlxsw_sp_listener), 2508 mlxsw_sp); 2509 if (err) 2510 goto err_traps_register; 2511 2512 err = mlxsw_core_traps_register(mlxsw_sp->core, mlxsw_sp->listeners, 2513 mlxsw_sp->listeners_count, mlxsw_sp); 2514 if (err) 2515 goto err_extra_traps_init; 2516 2517 return 0; 2518 2519 err_extra_traps_init: 2520 mlxsw_core_traps_unregister(mlxsw_sp->core, mlxsw_sp_listener, 2521 ARRAY_SIZE(mlxsw_sp_listener), 2522 mlxsw_sp); 2523 err_traps_register: 2524 err_trap_groups_set: 2525 err_cpu_policers_set: 2526 kfree(trap); 2527 return err; 2528 } 2529 2530 static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp) 2531 { 2532 mlxsw_core_traps_unregister(mlxsw_sp->core, mlxsw_sp->listeners, 2533 mlxsw_sp->listeners_count, 2534 mlxsw_sp); 2535 mlxsw_core_traps_unregister(mlxsw_sp->core, mlxsw_sp_listener, 2536 ARRAY_SIZE(mlxsw_sp_listener), mlxsw_sp); 2537 kfree(mlxsw_sp->trap); 2538 } 2539 2540 static int mlxsw_sp_lag_pgt_init(struct mlxsw_sp *mlxsw_sp) 2541 { 2542 char sgcr_pl[MLXSW_REG_SGCR_LEN]; 2543 int err; 2544 2545 if (mlxsw_core_lag_mode(mlxsw_sp->core) != 2546 MLXSW_CMD_MBOX_CONFIG_PROFILE_LAG_MODE_SW) 2547 return 0; 2548 2549 /* In DDD mode, which we by default use, each LAG entry is 8 PGT 2550 * entries. The LAG table address needs to be 8-aligned, but that ought 2551 * to be the case, since the LAG table is allocated first. 2552 */ 2553 err = mlxsw_sp_pgt_mid_alloc_range(mlxsw_sp, &mlxsw_sp->lag_pgt_base, 2554 mlxsw_sp->max_lag * 8); 2555 if (err) 2556 return err; 2557 if (WARN_ON_ONCE(mlxsw_sp->lag_pgt_base % 8)) { 2558 err = -EINVAL; 2559 goto err_mid_alloc_range; 2560 } 2561 2562 mlxsw_reg_sgcr_pack(sgcr_pl, mlxsw_sp->lag_pgt_base); 2563 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sgcr), sgcr_pl); 2564 if (err) 2565 goto err_mid_alloc_range; 2566 2567 return 0; 2568 2569 err_mid_alloc_range: 2570 mlxsw_sp_pgt_mid_free_range(mlxsw_sp, mlxsw_sp->lag_pgt_base, 2571 mlxsw_sp->max_lag * 8); 2572 return err; 2573 } 2574 2575 static void mlxsw_sp_lag_pgt_fini(struct mlxsw_sp *mlxsw_sp) 2576 { 2577 if (mlxsw_core_lag_mode(mlxsw_sp->core) != 2578 MLXSW_CMD_MBOX_CONFIG_PROFILE_LAG_MODE_SW) 2579 return; 2580 2581 mlxsw_sp_pgt_mid_free_range(mlxsw_sp, mlxsw_sp->lag_pgt_base, 2582 mlxsw_sp->max_lag * 8); 2583 } 2584 2585 #define MLXSW_SP_LAG_SEED_INIT 0xcafecafe 2586 2587 struct mlxsw_sp_lag { 2588 struct net_device *dev; 2589 refcount_t ref_count; 2590 u16 lag_id; 2591 }; 2592 2593 static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp) 2594 { 2595 char slcr_pl[MLXSW_REG_SLCR_LEN]; 2596 u32 seed; 2597 int err; 2598 2599 seed = jhash(mlxsw_sp->base_mac, sizeof(mlxsw_sp->base_mac), 2600 MLXSW_SP_LAG_SEED_INIT); 2601 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC | 2602 MLXSW_REG_SLCR_LAG_HASH_DMAC | 2603 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE | 2604 MLXSW_REG_SLCR_LAG_HASH_VLANID | 2605 MLXSW_REG_SLCR_LAG_HASH_SIP | 2606 MLXSW_REG_SLCR_LAG_HASH_DIP | 2607 MLXSW_REG_SLCR_LAG_HASH_SPORT | 2608 MLXSW_REG_SLCR_LAG_HASH_DPORT | 2609 MLXSW_REG_SLCR_LAG_HASH_IPPROTO, seed); 2610 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl); 2611 if (err) 2612 return err; 2613 2614 err = mlxsw_core_max_lag(mlxsw_sp->core, &mlxsw_sp->max_lag); 2615 if (err) 2616 return err; 2617 2618 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS)) 2619 return -EIO; 2620 2621 err = mlxsw_sp_lag_pgt_init(mlxsw_sp); 2622 if (err) 2623 return err; 2624 2625 mlxsw_sp->lags = kzalloc_objs(struct mlxsw_sp_lag, mlxsw_sp->max_lag); 2626 if (!mlxsw_sp->lags) { 2627 err = -ENOMEM; 2628 goto err_kcalloc; 2629 } 2630 2631 return 0; 2632 2633 err_kcalloc: 2634 mlxsw_sp_lag_pgt_fini(mlxsw_sp); 2635 return err; 2636 } 2637 2638 static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp) 2639 { 2640 mlxsw_sp_lag_pgt_fini(mlxsw_sp); 2641 kfree(mlxsw_sp->lags); 2642 } 2643 2644 static const struct mlxsw_sp_ptp_ops mlxsw_sp1_ptp_ops = { 2645 .clock_init = mlxsw_sp1_ptp_clock_init, 2646 .clock_fini = mlxsw_sp1_ptp_clock_fini, 2647 .init = mlxsw_sp1_ptp_init, 2648 .fini = mlxsw_sp1_ptp_fini, 2649 .receive = mlxsw_sp1_ptp_receive, 2650 .transmitted = mlxsw_sp1_ptp_transmitted, 2651 .hwtstamp_get = mlxsw_sp1_ptp_hwtstamp_get, 2652 .hwtstamp_set = mlxsw_sp1_ptp_hwtstamp_set, 2653 .shaper_work = mlxsw_sp1_ptp_shaper_work, 2654 #if IS_REACHABLE(CONFIG_PTP_1588_CLOCK) 2655 .get_ts_info = mlxsw_sp1_ptp_get_ts_info, 2656 #endif 2657 .get_stats_count = mlxsw_sp1_get_stats_count, 2658 .get_stats_strings = mlxsw_sp1_get_stats_strings, 2659 .get_stats = mlxsw_sp1_get_stats, 2660 }; 2661 2662 static const struct mlxsw_sp_ptp_ops mlxsw_sp2_ptp_ops = { 2663 .clock_init = mlxsw_sp2_ptp_clock_init, 2664 .clock_fini = mlxsw_sp2_ptp_clock_fini, 2665 .init = mlxsw_sp2_ptp_init, 2666 .fini = mlxsw_sp2_ptp_fini, 2667 .receive = mlxsw_sp2_ptp_receive, 2668 .transmitted = mlxsw_sp2_ptp_transmitted, 2669 .hwtstamp_get = mlxsw_sp2_ptp_hwtstamp_get, 2670 .hwtstamp_set = mlxsw_sp2_ptp_hwtstamp_set, 2671 .shaper_work = mlxsw_sp2_ptp_shaper_work, 2672 #if IS_REACHABLE(CONFIG_PTP_1588_CLOCK) 2673 .get_ts_info = mlxsw_sp2_ptp_get_ts_info, 2674 #endif 2675 .get_stats_count = mlxsw_sp2_get_stats_count, 2676 .get_stats_strings = mlxsw_sp2_get_stats_strings, 2677 .get_stats = mlxsw_sp2_get_stats, 2678 .tx_as_data = true, 2679 }; 2680 2681 static const struct mlxsw_sp_ptp_ops mlxsw_sp4_ptp_ops = { 2682 .clock_init = mlxsw_sp2_ptp_clock_init, 2683 .clock_fini = mlxsw_sp2_ptp_clock_fini, 2684 .init = mlxsw_sp2_ptp_init, 2685 .fini = mlxsw_sp2_ptp_fini, 2686 .receive = mlxsw_sp2_ptp_receive, 2687 .transmitted = mlxsw_sp2_ptp_transmitted, 2688 .hwtstamp_get = mlxsw_sp2_ptp_hwtstamp_get, 2689 .hwtstamp_set = mlxsw_sp2_ptp_hwtstamp_set, 2690 .shaper_work = mlxsw_sp2_ptp_shaper_work, 2691 #if IS_REACHABLE(CONFIG_PTP_1588_CLOCK) 2692 .get_ts_info = mlxsw_sp2_ptp_get_ts_info, 2693 #endif 2694 .get_stats_count = mlxsw_sp2_get_stats_count, 2695 .get_stats_strings = mlxsw_sp2_get_stats_strings, 2696 .get_stats = mlxsw_sp2_get_stats, 2697 }; 2698 2699 struct mlxsw_sp_sample_trigger_node { 2700 struct mlxsw_sp_sample_trigger trigger; 2701 struct mlxsw_sp_sample_params params; 2702 struct rhash_head ht_node; 2703 struct rcu_head rcu; 2704 refcount_t refcount; 2705 }; 2706 2707 static const struct rhashtable_params mlxsw_sp_sample_trigger_ht_params = { 2708 .key_offset = offsetof(struct mlxsw_sp_sample_trigger_node, trigger), 2709 .head_offset = offsetof(struct mlxsw_sp_sample_trigger_node, ht_node), 2710 .key_len = sizeof(struct mlxsw_sp_sample_trigger), 2711 .automatic_shrinking = true, 2712 }; 2713 2714 static void 2715 mlxsw_sp_sample_trigger_key_init(struct mlxsw_sp_sample_trigger *key, 2716 const struct mlxsw_sp_sample_trigger *trigger) 2717 { 2718 memset(key, 0, sizeof(*key)); 2719 key->type = trigger->type; 2720 key->local_port = trigger->local_port; 2721 } 2722 2723 /* RCU read lock must be held */ 2724 struct mlxsw_sp_sample_params * 2725 mlxsw_sp_sample_trigger_params_lookup(struct mlxsw_sp *mlxsw_sp, 2726 const struct mlxsw_sp_sample_trigger *trigger) 2727 { 2728 struct mlxsw_sp_sample_trigger_node *trigger_node; 2729 struct mlxsw_sp_sample_trigger key; 2730 2731 mlxsw_sp_sample_trigger_key_init(&key, trigger); 2732 trigger_node = rhashtable_lookup(&mlxsw_sp->sample_trigger_ht, &key, 2733 mlxsw_sp_sample_trigger_ht_params); 2734 if (!trigger_node) 2735 return NULL; 2736 2737 return &trigger_node->params; 2738 } 2739 2740 static int 2741 mlxsw_sp_sample_trigger_node_init(struct mlxsw_sp *mlxsw_sp, 2742 const struct mlxsw_sp_sample_trigger *trigger, 2743 const struct mlxsw_sp_sample_params *params) 2744 { 2745 struct mlxsw_sp_sample_trigger_node *trigger_node; 2746 int err; 2747 2748 trigger_node = kzalloc_obj(*trigger_node); 2749 if (!trigger_node) 2750 return -ENOMEM; 2751 2752 trigger_node->trigger = *trigger; 2753 trigger_node->params = *params; 2754 refcount_set(&trigger_node->refcount, 1); 2755 2756 err = rhashtable_insert_fast(&mlxsw_sp->sample_trigger_ht, 2757 &trigger_node->ht_node, 2758 mlxsw_sp_sample_trigger_ht_params); 2759 if (err) 2760 goto err_rhashtable_insert; 2761 2762 return 0; 2763 2764 err_rhashtable_insert: 2765 kfree(trigger_node); 2766 return err; 2767 } 2768 2769 static void 2770 mlxsw_sp_sample_trigger_node_fini(struct mlxsw_sp *mlxsw_sp, 2771 struct mlxsw_sp_sample_trigger_node *trigger_node) 2772 { 2773 rhashtable_remove_fast(&mlxsw_sp->sample_trigger_ht, 2774 &trigger_node->ht_node, 2775 mlxsw_sp_sample_trigger_ht_params); 2776 kfree_rcu(trigger_node, rcu); 2777 } 2778 2779 int 2780 mlxsw_sp_sample_trigger_params_set(struct mlxsw_sp *mlxsw_sp, 2781 const struct mlxsw_sp_sample_trigger *trigger, 2782 const struct mlxsw_sp_sample_params *params, 2783 struct netlink_ext_ack *extack) 2784 { 2785 struct mlxsw_sp_sample_trigger_node *trigger_node; 2786 struct mlxsw_sp_sample_trigger key; 2787 2788 ASSERT_RTNL(); 2789 2790 mlxsw_sp_sample_trigger_key_init(&key, trigger); 2791 2792 trigger_node = rhashtable_lookup_fast(&mlxsw_sp->sample_trigger_ht, 2793 &key, 2794 mlxsw_sp_sample_trigger_ht_params); 2795 if (!trigger_node) 2796 return mlxsw_sp_sample_trigger_node_init(mlxsw_sp, &key, 2797 params); 2798 2799 if (trigger_node->trigger.local_port) { 2800 NL_SET_ERR_MSG_MOD(extack, "Sampling already enabled on port"); 2801 return -EINVAL; 2802 } 2803 2804 if (trigger_node->params.psample_group != params->psample_group || 2805 trigger_node->params.truncate != params->truncate || 2806 trigger_node->params.rate != params->rate || 2807 trigger_node->params.trunc_size != params->trunc_size) { 2808 NL_SET_ERR_MSG_MOD(extack, "Sampling parameters do not match for an existing sampling trigger"); 2809 return -EINVAL; 2810 } 2811 2812 refcount_inc(&trigger_node->refcount); 2813 2814 return 0; 2815 } 2816 2817 void 2818 mlxsw_sp_sample_trigger_params_unset(struct mlxsw_sp *mlxsw_sp, 2819 const struct mlxsw_sp_sample_trigger *trigger) 2820 { 2821 struct mlxsw_sp_sample_trigger_node *trigger_node; 2822 struct mlxsw_sp_sample_trigger key; 2823 2824 ASSERT_RTNL(); 2825 2826 mlxsw_sp_sample_trigger_key_init(&key, trigger); 2827 2828 trigger_node = rhashtable_lookup_fast(&mlxsw_sp->sample_trigger_ht, 2829 &key, 2830 mlxsw_sp_sample_trigger_ht_params); 2831 if (!trigger_node) 2832 return; 2833 2834 if (!refcount_dec_and_test(&trigger_node->refcount)) 2835 return; 2836 2837 mlxsw_sp_sample_trigger_node_fini(mlxsw_sp, trigger_node); 2838 } 2839 2840 static int mlxsw_sp_netdevice_event(struct notifier_block *unused, 2841 unsigned long event, void *ptr); 2842 2843 #define MLXSW_SP_DEFAULT_PARSING_DEPTH 96 2844 #define MLXSW_SP_INCREASED_PARSING_DEPTH 128 2845 #define MLXSW_SP_DEFAULT_VXLAN_UDP_DPORT 4789 2846 2847 static void mlxsw_sp_parsing_init(struct mlxsw_sp *mlxsw_sp) 2848 { 2849 refcount_set(&mlxsw_sp->parsing.parsing_depth_ref, 0); 2850 mlxsw_sp->parsing.parsing_depth = MLXSW_SP_DEFAULT_PARSING_DEPTH; 2851 mlxsw_sp->parsing.vxlan_udp_dport = MLXSW_SP_DEFAULT_VXLAN_UDP_DPORT; 2852 mutex_init(&mlxsw_sp->parsing.lock); 2853 } 2854 2855 static void mlxsw_sp_parsing_fini(struct mlxsw_sp *mlxsw_sp) 2856 { 2857 mutex_destroy(&mlxsw_sp->parsing.lock); 2858 WARN_ON_ONCE(refcount_read(&mlxsw_sp->parsing.parsing_depth_ref)); 2859 } 2860 2861 struct mlxsw_sp_ipv6_addr_node { 2862 struct in6_addr key; 2863 struct rhash_head ht_node; 2864 u32 kvdl_index; 2865 refcount_t refcount; 2866 }; 2867 2868 static const struct rhashtable_params mlxsw_sp_ipv6_addr_ht_params = { 2869 .key_offset = offsetof(struct mlxsw_sp_ipv6_addr_node, key), 2870 .head_offset = offsetof(struct mlxsw_sp_ipv6_addr_node, ht_node), 2871 .key_len = sizeof(struct in6_addr), 2872 .automatic_shrinking = true, 2873 }; 2874 2875 static int 2876 mlxsw_sp_ipv6_addr_init(struct mlxsw_sp *mlxsw_sp, const struct in6_addr *addr6, 2877 u32 *p_kvdl_index) 2878 { 2879 struct mlxsw_sp_ipv6_addr_node *node; 2880 char rips_pl[MLXSW_REG_RIPS_LEN]; 2881 int err; 2882 2883 err = mlxsw_sp_kvdl_alloc(mlxsw_sp, 2884 MLXSW_SP_KVDL_ENTRY_TYPE_IPV6_ADDRESS, 1, 2885 p_kvdl_index); 2886 if (err) 2887 return err; 2888 2889 mlxsw_reg_rips_pack(rips_pl, *p_kvdl_index, addr6); 2890 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(rips), rips_pl); 2891 if (err) 2892 goto err_rips_write; 2893 2894 node = kzalloc_obj(*node); 2895 if (!node) { 2896 err = -ENOMEM; 2897 goto err_node_alloc; 2898 } 2899 2900 node->key = *addr6; 2901 node->kvdl_index = *p_kvdl_index; 2902 refcount_set(&node->refcount, 1); 2903 2904 err = rhashtable_insert_fast(&mlxsw_sp->ipv6_addr_ht, 2905 &node->ht_node, 2906 mlxsw_sp_ipv6_addr_ht_params); 2907 if (err) 2908 goto err_rhashtable_insert; 2909 2910 return 0; 2911 2912 err_rhashtable_insert: 2913 kfree(node); 2914 err_node_alloc: 2915 err_rips_write: 2916 mlxsw_sp_kvdl_free(mlxsw_sp, MLXSW_SP_KVDL_ENTRY_TYPE_IPV6_ADDRESS, 1, 2917 *p_kvdl_index); 2918 return err; 2919 } 2920 2921 static void mlxsw_sp_ipv6_addr_fini(struct mlxsw_sp *mlxsw_sp, 2922 struct mlxsw_sp_ipv6_addr_node *node) 2923 { 2924 u32 kvdl_index = node->kvdl_index; 2925 2926 rhashtable_remove_fast(&mlxsw_sp->ipv6_addr_ht, &node->ht_node, 2927 mlxsw_sp_ipv6_addr_ht_params); 2928 kfree(node); 2929 mlxsw_sp_kvdl_free(mlxsw_sp, MLXSW_SP_KVDL_ENTRY_TYPE_IPV6_ADDRESS, 1, 2930 kvdl_index); 2931 } 2932 2933 int mlxsw_sp_ipv6_addr_kvdl_index_get(struct mlxsw_sp *mlxsw_sp, 2934 const struct in6_addr *addr6, 2935 u32 *p_kvdl_index) 2936 { 2937 struct mlxsw_sp_ipv6_addr_node *node; 2938 int err = 0; 2939 2940 mutex_lock(&mlxsw_sp->ipv6_addr_ht_lock); 2941 node = rhashtable_lookup_fast(&mlxsw_sp->ipv6_addr_ht, addr6, 2942 mlxsw_sp_ipv6_addr_ht_params); 2943 if (node) { 2944 refcount_inc(&node->refcount); 2945 *p_kvdl_index = node->kvdl_index; 2946 goto out_unlock; 2947 } 2948 2949 err = mlxsw_sp_ipv6_addr_init(mlxsw_sp, addr6, p_kvdl_index); 2950 2951 out_unlock: 2952 mutex_unlock(&mlxsw_sp->ipv6_addr_ht_lock); 2953 return err; 2954 } 2955 2956 void 2957 mlxsw_sp_ipv6_addr_put(struct mlxsw_sp *mlxsw_sp, const struct in6_addr *addr6) 2958 { 2959 struct mlxsw_sp_ipv6_addr_node *node; 2960 2961 mutex_lock(&mlxsw_sp->ipv6_addr_ht_lock); 2962 node = rhashtable_lookup_fast(&mlxsw_sp->ipv6_addr_ht, addr6, 2963 mlxsw_sp_ipv6_addr_ht_params); 2964 if (WARN_ON(!node)) 2965 goto out_unlock; 2966 2967 if (!refcount_dec_and_test(&node->refcount)) 2968 goto out_unlock; 2969 2970 mlxsw_sp_ipv6_addr_fini(mlxsw_sp, node); 2971 2972 out_unlock: 2973 mutex_unlock(&mlxsw_sp->ipv6_addr_ht_lock); 2974 } 2975 2976 static int mlxsw_sp_ipv6_addr_ht_init(struct mlxsw_sp *mlxsw_sp) 2977 { 2978 int err; 2979 2980 err = rhashtable_init(&mlxsw_sp->ipv6_addr_ht, 2981 &mlxsw_sp_ipv6_addr_ht_params); 2982 if (err) 2983 return err; 2984 2985 mutex_init(&mlxsw_sp->ipv6_addr_ht_lock); 2986 return 0; 2987 } 2988 2989 static void mlxsw_sp_ipv6_addr_ht_fini(struct mlxsw_sp *mlxsw_sp) 2990 { 2991 mutex_destroy(&mlxsw_sp->ipv6_addr_ht_lock); 2992 rhashtable_destroy(&mlxsw_sp->ipv6_addr_ht); 2993 } 2994 2995 static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core, 2996 const struct mlxsw_bus_info *mlxsw_bus_info, 2997 struct netlink_ext_ack *extack) 2998 { 2999 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3000 int err; 3001 3002 mlxsw_sp->core = mlxsw_core; 3003 mlxsw_sp->bus_info = mlxsw_bus_info; 3004 3005 mlxsw_sp_parsing_init(mlxsw_sp); 3006 3007 err = mlxsw_sp_base_mac_get(mlxsw_sp); 3008 if (err) { 3009 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n"); 3010 return err; 3011 } 3012 3013 err = mlxsw_sp_kvdl_init(mlxsw_sp); 3014 if (err) { 3015 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n"); 3016 return err; 3017 } 3018 3019 err = mlxsw_sp_pgt_init(mlxsw_sp); 3020 if (err) { 3021 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize PGT\n"); 3022 goto err_pgt_init; 3023 } 3024 3025 /* Initialize before FIDs so that the LAG table is at the start of PGT 3026 * and 8-aligned without overallocation. 3027 */ 3028 err = mlxsw_sp_lag_init(mlxsw_sp); 3029 if (err) { 3030 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n"); 3031 goto err_lag_init; 3032 } 3033 3034 err = mlxsw_sp->fid_core_ops->init(mlxsw_sp); 3035 if (err) { 3036 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n"); 3037 goto err_fid_core_init; 3038 } 3039 3040 err = mlxsw_sp_policers_init(mlxsw_sp); 3041 if (err) { 3042 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize policers\n"); 3043 goto err_policers_init; 3044 } 3045 3046 err = mlxsw_sp_traps_init(mlxsw_sp); 3047 if (err) { 3048 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n"); 3049 goto err_traps_init; 3050 } 3051 3052 err = mlxsw_sp_devlink_traps_init(mlxsw_sp); 3053 if (err) { 3054 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize devlink traps\n"); 3055 goto err_devlink_traps_init; 3056 } 3057 3058 err = mlxsw_sp_buffers_init(mlxsw_sp); 3059 if (err) { 3060 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n"); 3061 goto err_buffers_init; 3062 } 3063 3064 /* Initialize SPAN before router and switchdev, so that those components 3065 * can call mlxsw_sp_span_respin(). 3066 */ 3067 err = mlxsw_sp_span_init(mlxsw_sp); 3068 if (err) { 3069 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n"); 3070 goto err_span_init; 3071 } 3072 3073 err = mlxsw_sp_switchdev_init(mlxsw_sp); 3074 if (err) { 3075 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n"); 3076 goto err_switchdev_init; 3077 } 3078 3079 err = mlxsw_sp_counter_pool_init(mlxsw_sp); 3080 if (err) { 3081 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n"); 3082 goto err_counter_pool_init; 3083 } 3084 3085 err = mlxsw_sp_afa_init(mlxsw_sp); 3086 if (err) { 3087 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n"); 3088 goto err_afa_init; 3089 } 3090 3091 err = mlxsw_sp_ipv6_addr_ht_init(mlxsw_sp); 3092 if (err) { 3093 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize hash table for IPv6 addresses\n"); 3094 goto err_ipv6_addr_ht_init; 3095 } 3096 3097 err = mlxsw_sp_nve_init(mlxsw_sp); 3098 if (err) { 3099 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize NVE\n"); 3100 goto err_nve_init; 3101 } 3102 3103 err = mlxsw_sp_port_range_init(mlxsw_sp); 3104 if (err) { 3105 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize port ranges\n"); 3106 goto err_port_range_init; 3107 } 3108 3109 err = mlxsw_sp_acl_init(mlxsw_sp); 3110 if (err) { 3111 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n"); 3112 goto err_acl_init; 3113 } 3114 3115 err = mlxsw_sp_router_init(mlxsw_sp, extack); 3116 if (err) { 3117 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n"); 3118 goto err_router_init; 3119 } 3120 3121 if (mlxsw_sp->bus_info->read_clock_capable) { 3122 /* NULL is a valid return value from clock_init */ 3123 mlxsw_sp->clock = 3124 mlxsw_sp->ptp_ops->clock_init(mlxsw_sp, 3125 mlxsw_sp->bus_info->dev); 3126 if (IS_ERR(mlxsw_sp->clock)) { 3127 err = PTR_ERR(mlxsw_sp->clock); 3128 dev_err(mlxsw_sp->bus_info->dev, "Failed to init ptp clock\n"); 3129 goto err_ptp_clock_init; 3130 } 3131 } 3132 3133 if (mlxsw_sp->clock) { 3134 /* NULL is a valid return value from ptp_ops->init */ 3135 mlxsw_sp->ptp_state = mlxsw_sp->ptp_ops->init(mlxsw_sp); 3136 if (IS_ERR(mlxsw_sp->ptp_state)) { 3137 err = PTR_ERR(mlxsw_sp->ptp_state); 3138 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize PTP\n"); 3139 goto err_ptp_init; 3140 } 3141 } 3142 3143 /* Initialize netdevice notifier after SPAN is initialized, so that the 3144 * event handler can call SPAN respin. 3145 */ 3146 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event; 3147 err = register_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp), 3148 &mlxsw_sp->netdevice_nb); 3149 if (err) { 3150 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n"); 3151 goto err_netdev_notifier; 3152 } 3153 3154 err = mlxsw_sp_dpipe_init(mlxsw_sp); 3155 if (err) { 3156 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n"); 3157 goto err_dpipe_init; 3158 } 3159 3160 err = mlxsw_sp_port_module_info_init(mlxsw_sp); 3161 if (err) { 3162 dev_err(mlxsw_sp->bus_info->dev, "Failed to init port module info\n"); 3163 goto err_port_module_info_init; 3164 } 3165 3166 err = rhashtable_init(&mlxsw_sp->sample_trigger_ht, 3167 &mlxsw_sp_sample_trigger_ht_params); 3168 if (err) { 3169 dev_err(mlxsw_sp->bus_info->dev, "Failed to init sampling trigger hashtable\n"); 3170 goto err_sample_trigger_init; 3171 } 3172 3173 err = mlxsw_sp_ports_create(mlxsw_sp); 3174 if (err) { 3175 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n"); 3176 goto err_ports_create; 3177 } 3178 3179 return 0; 3180 3181 err_ports_create: 3182 rhashtable_destroy(&mlxsw_sp->sample_trigger_ht); 3183 err_sample_trigger_init: 3184 mlxsw_sp_port_module_info_fini(mlxsw_sp); 3185 err_port_module_info_init: 3186 mlxsw_sp_dpipe_fini(mlxsw_sp); 3187 err_dpipe_init: 3188 unregister_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp), 3189 &mlxsw_sp->netdevice_nb); 3190 err_netdev_notifier: 3191 if (mlxsw_sp->clock) 3192 mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state); 3193 err_ptp_init: 3194 if (mlxsw_sp->clock) 3195 mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock); 3196 err_ptp_clock_init: 3197 mlxsw_sp_router_fini(mlxsw_sp); 3198 err_router_init: 3199 mlxsw_sp_acl_fini(mlxsw_sp); 3200 err_acl_init: 3201 mlxsw_sp_port_range_fini(mlxsw_sp); 3202 err_port_range_init: 3203 mlxsw_sp_nve_fini(mlxsw_sp); 3204 err_nve_init: 3205 mlxsw_sp_ipv6_addr_ht_fini(mlxsw_sp); 3206 err_ipv6_addr_ht_init: 3207 mlxsw_sp_afa_fini(mlxsw_sp); 3208 err_afa_init: 3209 mlxsw_sp_counter_pool_fini(mlxsw_sp); 3210 err_counter_pool_init: 3211 mlxsw_sp_switchdev_fini(mlxsw_sp); 3212 err_switchdev_init: 3213 mlxsw_sp_span_fini(mlxsw_sp); 3214 err_span_init: 3215 mlxsw_sp_buffers_fini(mlxsw_sp); 3216 err_buffers_init: 3217 mlxsw_sp_devlink_traps_fini(mlxsw_sp); 3218 err_devlink_traps_init: 3219 mlxsw_sp_traps_fini(mlxsw_sp); 3220 err_traps_init: 3221 mlxsw_sp_policers_fini(mlxsw_sp); 3222 err_policers_init: 3223 mlxsw_sp->fid_core_ops->fini(mlxsw_sp); 3224 err_fid_core_init: 3225 mlxsw_sp_lag_fini(mlxsw_sp); 3226 err_lag_init: 3227 mlxsw_sp_pgt_fini(mlxsw_sp); 3228 err_pgt_init: 3229 mlxsw_sp_kvdl_fini(mlxsw_sp); 3230 mlxsw_sp_parsing_fini(mlxsw_sp); 3231 return err; 3232 } 3233 3234 static int mlxsw_sp1_init(struct mlxsw_core *mlxsw_core, 3235 const struct mlxsw_bus_info *mlxsw_bus_info, 3236 struct netlink_ext_ack *extack) 3237 { 3238 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3239 3240 mlxsw_sp->switchdev_ops = &mlxsw_sp1_switchdev_ops; 3241 mlxsw_sp->kvdl_ops = &mlxsw_sp1_kvdl_ops; 3242 mlxsw_sp->afa_ops = &mlxsw_sp1_act_afa_ops; 3243 mlxsw_sp->afk_ops = &mlxsw_sp1_afk_ops; 3244 mlxsw_sp->mr_tcam_ops = &mlxsw_sp1_mr_tcam_ops; 3245 mlxsw_sp->acl_rulei_ops = &mlxsw_sp1_acl_rulei_ops; 3246 mlxsw_sp->acl_tcam_ops = &mlxsw_sp1_acl_tcam_ops; 3247 mlxsw_sp->nve_ops_arr = mlxsw_sp1_nve_ops_arr; 3248 mlxsw_sp->mac_mask = mlxsw_sp1_mac_mask; 3249 mlxsw_sp->sb_vals = &mlxsw_sp1_sb_vals; 3250 mlxsw_sp->sb_ops = &mlxsw_sp1_sb_ops; 3251 mlxsw_sp->port_type_speed_ops = &mlxsw_sp1_port_type_speed_ops; 3252 mlxsw_sp->ptp_ops = &mlxsw_sp1_ptp_ops; 3253 mlxsw_sp->span_ops = &mlxsw_sp1_span_ops; 3254 mlxsw_sp->policer_core_ops = &mlxsw_sp1_policer_core_ops; 3255 mlxsw_sp->trap_ops = &mlxsw_sp1_trap_ops; 3256 mlxsw_sp->mall_ops = &mlxsw_sp1_mall_ops; 3257 mlxsw_sp->router_ops = &mlxsw_sp1_router_ops; 3258 mlxsw_sp->listeners = mlxsw_sp1_listener; 3259 mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp1_listener); 3260 mlxsw_sp->fid_core_ops = &mlxsw_sp1_fid_core_ops; 3261 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1; 3262 mlxsw_sp->pgt_smpe_index_valid = true; 3263 3264 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack); 3265 } 3266 3267 static int mlxsw_sp2_init(struct mlxsw_core *mlxsw_core, 3268 const struct mlxsw_bus_info *mlxsw_bus_info, 3269 struct netlink_ext_ack *extack) 3270 { 3271 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3272 3273 mlxsw_sp->switchdev_ops = &mlxsw_sp2_switchdev_ops; 3274 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops; 3275 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops; 3276 mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops; 3277 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops; 3278 mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops; 3279 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops; 3280 mlxsw_sp->acl_bf_ops = &mlxsw_sp2_acl_bf_ops; 3281 mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr; 3282 mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask; 3283 mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals; 3284 mlxsw_sp->sb_ops = &mlxsw_sp2_sb_ops; 3285 mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops; 3286 mlxsw_sp->ptp_ops = &mlxsw_sp2_ptp_ops; 3287 mlxsw_sp->span_ops = &mlxsw_sp2_span_ops; 3288 mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops; 3289 mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops; 3290 mlxsw_sp->mall_ops = &mlxsw_sp2_mall_ops; 3291 mlxsw_sp->router_ops = &mlxsw_sp2_router_ops; 3292 mlxsw_sp->listeners = mlxsw_sp2_listener; 3293 mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp2_listener); 3294 mlxsw_sp->fid_core_ops = &mlxsw_sp2_fid_core_ops; 3295 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2; 3296 mlxsw_sp->pgt_smpe_index_valid = false; 3297 3298 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack); 3299 } 3300 3301 static int mlxsw_sp3_init(struct mlxsw_core *mlxsw_core, 3302 const struct mlxsw_bus_info *mlxsw_bus_info, 3303 struct netlink_ext_ack *extack) 3304 { 3305 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3306 3307 mlxsw_sp->switchdev_ops = &mlxsw_sp2_switchdev_ops; 3308 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops; 3309 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops; 3310 mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops; 3311 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops; 3312 mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops; 3313 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops; 3314 mlxsw_sp->acl_bf_ops = &mlxsw_sp2_acl_bf_ops; 3315 mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr; 3316 mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask; 3317 mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals; 3318 mlxsw_sp->sb_ops = &mlxsw_sp3_sb_ops; 3319 mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops; 3320 mlxsw_sp->ptp_ops = &mlxsw_sp2_ptp_ops; 3321 mlxsw_sp->span_ops = &mlxsw_sp3_span_ops; 3322 mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops; 3323 mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops; 3324 mlxsw_sp->mall_ops = &mlxsw_sp2_mall_ops; 3325 mlxsw_sp->router_ops = &mlxsw_sp2_router_ops; 3326 mlxsw_sp->listeners = mlxsw_sp2_listener; 3327 mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp2_listener); 3328 mlxsw_sp->fid_core_ops = &mlxsw_sp2_fid_core_ops; 3329 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3; 3330 mlxsw_sp->pgt_smpe_index_valid = false; 3331 3332 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack); 3333 } 3334 3335 static int mlxsw_sp4_init(struct mlxsw_core *mlxsw_core, 3336 const struct mlxsw_bus_info *mlxsw_bus_info, 3337 struct netlink_ext_ack *extack) 3338 { 3339 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3340 3341 mlxsw_sp->switchdev_ops = &mlxsw_sp2_switchdev_ops; 3342 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops; 3343 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops; 3344 mlxsw_sp->afk_ops = &mlxsw_sp4_afk_ops; 3345 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops; 3346 mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops; 3347 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops; 3348 mlxsw_sp->acl_bf_ops = &mlxsw_sp4_acl_bf_ops; 3349 mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr; 3350 mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask; 3351 mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals; 3352 mlxsw_sp->sb_ops = &mlxsw_sp3_sb_ops; 3353 mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops; 3354 mlxsw_sp->ptp_ops = &mlxsw_sp4_ptp_ops; 3355 mlxsw_sp->span_ops = &mlxsw_sp3_span_ops; 3356 mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops; 3357 mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops; 3358 mlxsw_sp->mall_ops = &mlxsw_sp2_mall_ops; 3359 mlxsw_sp->router_ops = &mlxsw_sp2_router_ops; 3360 mlxsw_sp->listeners = mlxsw_sp2_listener; 3361 mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp2_listener); 3362 mlxsw_sp->fid_core_ops = &mlxsw_sp2_fid_core_ops; 3363 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP4; 3364 mlxsw_sp->pgt_smpe_index_valid = false; 3365 3366 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack); 3367 } 3368 3369 static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core) 3370 { 3371 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3372 3373 mlxsw_sp_ports_remove(mlxsw_sp); 3374 rhashtable_destroy(&mlxsw_sp->sample_trigger_ht); 3375 mlxsw_sp_port_module_info_fini(mlxsw_sp); 3376 mlxsw_sp_dpipe_fini(mlxsw_sp); 3377 unregister_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp), 3378 &mlxsw_sp->netdevice_nb); 3379 if (mlxsw_sp->clock) { 3380 mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state); 3381 mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock); 3382 } 3383 mlxsw_sp_router_fini(mlxsw_sp); 3384 mlxsw_sp_acl_fini(mlxsw_sp); 3385 mlxsw_sp_port_range_fini(mlxsw_sp); 3386 mlxsw_sp_nve_fini(mlxsw_sp); 3387 mlxsw_sp_ipv6_addr_ht_fini(mlxsw_sp); 3388 mlxsw_sp_afa_fini(mlxsw_sp); 3389 mlxsw_sp_counter_pool_fini(mlxsw_sp); 3390 mlxsw_sp_switchdev_fini(mlxsw_sp); 3391 mlxsw_sp_span_fini(mlxsw_sp); 3392 mlxsw_sp_buffers_fini(mlxsw_sp); 3393 mlxsw_sp_devlink_traps_fini(mlxsw_sp); 3394 mlxsw_sp_traps_fini(mlxsw_sp); 3395 mlxsw_sp_policers_fini(mlxsw_sp); 3396 mlxsw_sp->fid_core_ops->fini(mlxsw_sp); 3397 mlxsw_sp_lag_fini(mlxsw_sp); 3398 mlxsw_sp_pgt_fini(mlxsw_sp); 3399 mlxsw_sp_kvdl_fini(mlxsw_sp); 3400 mlxsw_sp_parsing_fini(mlxsw_sp); 3401 } 3402 3403 static const struct mlxsw_config_profile mlxsw_sp1_config_profile = { 3404 .used_flood_mode = 1, 3405 .flood_mode = MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_CONTROLLED, 3406 .used_max_ib_mc = 1, 3407 .max_ib_mc = 0, 3408 .used_max_pkey = 1, 3409 .max_pkey = 0, 3410 .used_ubridge = 1, 3411 .ubridge = 1, 3412 .used_kvd_sizes = 1, 3413 .kvd_hash_single_parts = 59, 3414 .kvd_hash_double_parts = 41, 3415 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE, 3416 .swid_config = { 3417 { 3418 .used_type = 1, 3419 .type = MLXSW_PORT_SWID_TYPE_ETH, 3420 } 3421 }, 3422 }; 3423 3424 static const struct mlxsw_config_profile mlxsw_sp2_config_profile = { 3425 .used_flood_mode = 1, 3426 .flood_mode = MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_CONTROLLED, 3427 .used_max_ib_mc = 1, 3428 .max_ib_mc = 0, 3429 .used_max_pkey = 1, 3430 .max_pkey = 0, 3431 .used_ubridge = 1, 3432 .ubridge = 1, 3433 .swid_config = { 3434 { 3435 .used_type = 1, 3436 .type = MLXSW_PORT_SWID_TYPE_ETH, 3437 } 3438 }, 3439 .used_cqe_time_stamp_type = 1, 3440 .cqe_time_stamp_type = MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_UTC, 3441 .lag_mode_prefer_sw = true, 3442 .flood_mode_prefer_cff = true, 3443 }; 3444 3445 /* Reduce number of LAGs from full capacity (256) to the maximum supported LAGs 3446 * in Spectrum-2/3, to avoid regression in number of free entries in the PGT 3447 * table. 3448 */ 3449 #define MLXSW_SP4_CONFIG_PROFILE_MAX_LAG 128 3450 3451 static const struct mlxsw_config_profile mlxsw_sp4_config_profile = { 3452 .used_max_lag = 1, 3453 .max_lag = MLXSW_SP4_CONFIG_PROFILE_MAX_LAG, 3454 .used_flood_mode = 1, 3455 .flood_mode = MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_CONTROLLED, 3456 .used_max_ib_mc = 1, 3457 .max_ib_mc = 0, 3458 .used_max_pkey = 1, 3459 .max_pkey = 0, 3460 .used_ubridge = 1, 3461 .ubridge = 1, 3462 .swid_config = { 3463 { 3464 .used_type = 1, 3465 .type = MLXSW_PORT_SWID_TYPE_ETH, 3466 } 3467 }, 3468 .used_cqe_time_stamp_type = 1, 3469 .cqe_time_stamp_type = MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_UTC, 3470 .lag_mode_prefer_sw = true, 3471 .flood_mode_prefer_cff = true, 3472 }; 3473 3474 static void 3475 mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core, 3476 struct devlink_resource_size_params *kvd_size_params, 3477 struct devlink_resource_size_params *linear_size_params, 3478 struct devlink_resource_size_params *hash_double_size_params, 3479 struct devlink_resource_size_params *hash_single_size_params) 3480 { 3481 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core, 3482 KVD_SINGLE_MIN_SIZE); 3483 u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core, 3484 KVD_DOUBLE_MIN_SIZE); 3485 u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE); 3486 u32 linear_size_min = 0; 3487 3488 devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size, 3489 MLXSW_SP_KVD_GRANULARITY, 3490 DEVLINK_RESOURCE_UNIT_ENTRY); 3491 devlink_resource_size_params_init(linear_size_params, linear_size_min, 3492 kvd_size - single_size_min - 3493 double_size_min, 3494 MLXSW_SP_KVD_GRANULARITY, 3495 DEVLINK_RESOURCE_UNIT_ENTRY); 3496 devlink_resource_size_params_init(hash_double_size_params, 3497 double_size_min, 3498 kvd_size - single_size_min - 3499 linear_size_min, 3500 MLXSW_SP_KVD_GRANULARITY, 3501 DEVLINK_RESOURCE_UNIT_ENTRY); 3502 devlink_resource_size_params_init(hash_single_size_params, 3503 single_size_min, 3504 kvd_size - double_size_min - 3505 linear_size_min, 3506 MLXSW_SP_KVD_GRANULARITY, 3507 DEVLINK_RESOURCE_UNIT_ENTRY); 3508 } 3509 3510 static int mlxsw_sp1_resources_kvd_register(struct mlxsw_core *mlxsw_core) 3511 { 3512 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3513 struct devlink_resource_size_params hash_single_size_params; 3514 struct devlink_resource_size_params hash_double_size_params; 3515 struct devlink_resource_size_params linear_size_params; 3516 struct devlink_resource_size_params kvd_size_params; 3517 u32 kvd_size, single_size, double_size, linear_size; 3518 const struct mlxsw_config_profile *profile; 3519 int err; 3520 3521 profile = &mlxsw_sp1_config_profile; 3522 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE)) 3523 return -EIO; 3524 3525 mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params, 3526 &linear_size_params, 3527 &hash_double_size_params, 3528 &hash_single_size_params); 3529 3530 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE); 3531 err = devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD, 3532 kvd_size, MLXSW_SP_RESOURCE_KVD, 3533 DEVLINK_RESOURCE_ID_PARENT_TOP, 3534 &kvd_size_params); 3535 if (err) 3536 return err; 3537 3538 linear_size = profile->kvd_linear_size; 3539 err = devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR, 3540 linear_size, 3541 MLXSW_SP_RESOURCE_KVD_LINEAR, 3542 MLXSW_SP_RESOURCE_KVD, 3543 &linear_size_params); 3544 if (err) 3545 return err; 3546 3547 err = mlxsw_sp1_kvdl_resources_register(mlxsw_core); 3548 if (err) 3549 return err; 3550 3551 double_size = kvd_size - linear_size; 3552 double_size *= profile->kvd_hash_double_parts; 3553 double_size /= profile->kvd_hash_double_parts + 3554 profile->kvd_hash_single_parts; 3555 double_size = rounddown(double_size, MLXSW_SP_KVD_GRANULARITY); 3556 err = devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE, 3557 double_size, 3558 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE, 3559 MLXSW_SP_RESOURCE_KVD, 3560 &hash_double_size_params); 3561 if (err) 3562 return err; 3563 3564 single_size = kvd_size - double_size - linear_size; 3565 err = devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE, 3566 single_size, 3567 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE, 3568 MLXSW_SP_RESOURCE_KVD, 3569 &hash_single_size_params); 3570 if (err) 3571 return err; 3572 3573 return 0; 3574 } 3575 3576 static int mlxsw_sp2_resources_kvd_register(struct mlxsw_core *mlxsw_core) 3577 { 3578 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3579 struct devlink_resource_size_params kvd_size_params; 3580 u32 kvd_size; 3581 3582 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE)) 3583 return -EIO; 3584 3585 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE); 3586 devlink_resource_size_params_init(&kvd_size_params, kvd_size, kvd_size, 3587 MLXSW_SP_KVD_GRANULARITY, 3588 DEVLINK_RESOURCE_UNIT_ENTRY); 3589 3590 return devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD, 3591 kvd_size, MLXSW_SP_RESOURCE_KVD, 3592 DEVLINK_RESOURCE_ID_PARENT_TOP, 3593 &kvd_size_params); 3594 } 3595 3596 static int mlxsw_sp_resources_span_register(struct mlxsw_core *mlxsw_core) 3597 { 3598 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3599 struct devlink_resource_size_params span_size_params; 3600 u32 max_span; 3601 3602 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_SPAN)) 3603 return -EIO; 3604 3605 max_span = MLXSW_CORE_RES_GET(mlxsw_core, MAX_SPAN); 3606 devlink_resource_size_params_init(&span_size_params, max_span, max_span, 3607 1, DEVLINK_RESOURCE_UNIT_ENTRY); 3608 3609 return devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_SPAN, 3610 max_span, MLXSW_SP_RESOURCE_SPAN, 3611 DEVLINK_RESOURCE_ID_PARENT_TOP, 3612 &span_size_params); 3613 } 3614 3615 static int 3616 mlxsw_sp_resources_rif_mac_profile_register(struct mlxsw_core *mlxsw_core) 3617 { 3618 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3619 struct devlink_resource_size_params size_params; 3620 u8 max_rif_mac_profiles; 3621 3622 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_RIF_MAC_PROFILES)) 3623 max_rif_mac_profiles = 1; 3624 else 3625 max_rif_mac_profiles = MLXSW_CORE_RES_GET(mlxsw_core, 3626 MAX_RIF_MAC_PROFILES); 3627 devlink_resource_size_params_init(&size_params, max_rif_mac_profiles, 3628 max_rif_mac_profiles, 1, 3629 DEVLINK_RESOURCE_UNIT_ENTRY); 3630 3631 return devl_resource_register(devlink, 3632 "rif_mac_profiles", 3633 max_rif_mac_profiles, 3634 MLXSW_SP_RESOURCE_RIF_MAC_PROFILES, 3635 DEVLINK_RESOURCE_ID_PARENT_TOP, 3636 &size_params); 3637 } 3638 3639 static int mlxsw_sp_resources_rifs_register(struct mlxsw_core *mlxsw_core) 3640 { 3641 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3642 struct devlink_resource_size_params size_params; 3643 u64 max_rifs; 3644 3645 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_RIFS)) 3646 return -EIO; 3647 3648 max_rifs = MLXSW_CORE_RES_GET(mlxsw_core, MAX_RIFS); 3649 devlink_resource_size_params_init(&size_params, max_rifs, max_rifs, 3650 1, DEVLINK_RESOURCE_UNIT_ENTRY); 3651 3652 return devl_resource_register(devlink, "rifs", max_rifs, 3653 MLXSW_SP_RESOURCE_RIFS, 3654 DEVLINK_RESOURCE_ID_PARENT_TOP, 3655 &size_params); 3656 } 3657 3658 static int 3659 mlxsw_sp_resources_port_range_register(struct mlxsw_core *mlxsw_core) 3660 { 3661 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3662 struct devlink_resource_size_params size_params; 3663 u64 max; 3664 3665 if (!MLXSW_CORE_RES_VALID(mlxsw_core, ACL_MAX_L4_PORT_RANGE)) 3666 return -EIO; 3667 3668 max = MLXSW_CORE_RES_GET(mlxsw_core, ACL_MAX_L4_PORT_RANGE); 3669 devlink_resource_size_params_init(&size_params, max, max, 1, 3670 DEVLINK_RESOURCE_UNIT_ENTRY); 3671 3672 return devl_resource_register(devlink, "port_range_registers", max, 3673 MLXSW_SP_RESOURCE_PORT_RANGE_REGISTERS, 3674 DEVLINK_RESOURCE_ID_PARENT_TOP, 3675 &size_params); 3676 } 3677 3678 static int mlxsw_sp1_resources_register(struct mlxsw_core *mlxsw_core) 3679 { 3680 int err; 3681 3682 err = mlxsw_sp1_resources_kvd_register(mlxsw_core); 3683 if (err) 3684 return err; 3685 3686 err = mlxsw_sp_resources_span_register(mlxsw_core); 3687 if (err) 3688 goto err_resources_span_register; 3689 3690 err = mlxsw_sp_counter_resources_register(mlxsw_core); 3691 if (err) 3692 goto err_resources_counter_register; 3693 3694 err = mlxsw_sp_policer_resources_register(mlxsw_core); 3695 if (err) 3696 goto err_policer_resources_register; 3697 3698 err = mlxsw_sp_resources_rif_mac_profile_register(mlxsw_core); 3699 if (err) 3700 goto err_resources_rif_mac_profile_register; 3701 3702 err = mlxsw_sp_resources_rifs_register(mlxsw_core); 3703 if (err) 3704 goto err_resources_rifs_register; 3705 3706 err = mlxsw_sp_resources_port_range_register(mlxsw_core); 3707 if (err) 3708 goto err_resources_port_range_register; 3709 3710 return 0; 3711 3712 err_resources_port_range_register: 3713 err_resources_rifs_register: 3714 err_resources_rif_mac_profile_register: 3715 err_policer_resources_register: 3716 err_resources_counter_register: 3717 err_resources_span_register: 3718 devl_resources_unregister(priv_to_devlink(mlxsw_core)); 3719 return err; 3720 } 3721 3722 static int mlxsw_sp2_resources_register(struct mlxsw_core *mlxsw_core) 3723 { 3724 int err; 3725 3726 err = mlxsw_sp2_resources_kvd_register(mlxsw_core); 3727 if (err) 3728 return err; 3729 3730 err = mlxsw_sp_resources_span_register(mlxsw_core); 3731 if (err) 3732 goto err_resources_span_register; 3733 3734 err = mlxsw_sp_counter_resources_register(mlxsw_core); 3735 if (err) 3736 goto err_resources_counter_register; 3737 3738 err = mlxsw_sp_policer_resources_register(mlxsw_core); 3739 if (err) 3740 goto err_policer_resources_register; 3741 3742 err = mlxsw_sp_resources_rif_mac_profile_register(mlxsw_core); 3743 if (err) 3744 goto err_resources_rif_mac_profile_register; 3745 3746 err = mlxsw_sp_resources_rifs_register(mlxsw_core); 3747 if (err) 3748 goto err_resources_rifs_register; 3749 3750 err = mlxsw_sp_resources_port_range_register(mlxsw_core); 3751 if (err) 3752 goto err_resources_port_range_register; 3753 3754 return 0; 3755 3756 err_resources_port_range_register: 3757 err_resources_rifs_register: 3758 err_resources_rif_mac_profile_register: 3759 err_policer_resources_register: 3760 err_resources_counter_register: 3761 err_resources_span_register: 3762 devl_resources_unregister(priv_to_devlink(mlxsw_core)); 3763 return err; 3764 } 3765 3766 static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core, 3767 const struct mlxsw_config_profile *profile, 3768 u64 *p_single_size, u64 *p_double_size, 3769 u64 *p_linear_size) 3770 { 3771 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3772 u32 double_size; 3773 int err; 3774 3775 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) || 3776 !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE)) 3777 return -EIO; 3778 3779 /* The hash part is what left of the kvd without the 3780 * linear part. It is split to the single size and 3781 * double size by the parts ratio from the profile. 3782 * Both sizes must be a multiplications of the 3783 * granularity from the profile. In case the user 3784 * provided the sizes they are obtained via devlink. 3785 */ 3786 err = devl_resource_size_get(devlink, 3787 MLXSW_SP_RESOURCE_KVD_LINEAR, 3788 p_linear_size); 3789 if (err) 3790 *p_linear_size = profile->kvd_linear_size; 3791 3792 err = devl_resource_size_get(devlink, 3793 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE, 3794 p_double_size); 3795 if (err) { 3796 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) - 3797 *p_linear_size; 3798 double_size *= profile->kvd_hash_double_parts; 3799 double_size /= profile->kvd_hash_double_parts + 3800 profile->kvd_hash_single_parts; 3801 *p_double_size = rounddown(double_size, 3802 MLXSW_SP_KVD_GRANULARITY); 3803 } 3804 3805 err = devl_resource_size_get(devlink, 3806 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE, 3807 p_single_size); 3808 if (err) 3809 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) - 3810 *p_double_size - *p_linear_size; 3811 3812 /* Check results are legal. */ 3813 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) || 3814 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) || 3815 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size) 3816 return -EIO; 3817 3818 return 0; 3819 } 3820 3821 static void mlxsw_sp_ptp_transmitted(struct mlxsw_core *mlxsw_core, 3822 struct sk_buff *skb, u16 local_port) 3823 { 3824 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3825 3826 skb_pull(skb, MLXSW_TXHDR_LEN); 3827 mlxsw_sp->ptp_ops->transmitted(mlxsw_sp, skb, local_port); 3828 } 3829 3830 static struct mlxsw_driver mlxsw_sp1_driver = { 3831 .kind = mlxsw_sp1_driver_name, 3832 .priv_size = sizeof(struct mlxsw_sp), 3833 .fw_req_rev = &mlxsw_sp1_fw_rev, 3834 .fw_filename = MLXSW_SP1_FW_FILENAME, 3835 .init = mlxsw_sp1_init, 3836 .fini = mlxsw_sp_fini, 3837 .port_split = mlxsw_sp_port_split, 3838 .port_unsplit = mlxsw_sp_port_unsplit, 3839 .sb_pool_get = mlxsw_sp_sb_pool_get, 3840 .sb_pool_set = mlxsw_sp_sb_pool_set, 3841 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get, 3842 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set, 3843 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get, 3844 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set, 3845 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot, 3846 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear, 3847 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get, 3848 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get, 3849 .trap_init = mlxsw_sp_trap_init, 3850 .trap_fini = mlxsw_sp_trap_fini, 3851 .trap_action_set = mlxsw_sp_trap_action_set, 3852 .trap_group_init = mlxsw_sp_trap_group_init, 3853 .trap_group_set = mlxsw_sp_trap_group_set, 3854 .trap_policer_init = mlxsw_sp_trap_policer_init, 3855 .trap_policer_fini = mlxsw_sp_trap_policer_fini, 3856 .trap_policer_set = mlxsw_sp_trap_policer_set, 3857 .trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get, 3858 .resources_register = mlxsw_sp1_resources_register, 3859 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get, 3860 .ptp_transmitted = mlxsw_sp_ptp_transmitted, 3861 .profile = &mlxsw_sp1_config_profile, 3862 .sdq_supports_cqe_v2 = false, 3863 }; 3864 3865 static struct mlxsw_driver mlxsw_sp2_driver = { 3866 .kind = mlxsw_sp2_driver_name, 3867 .priv_size = sizeof(struct mlxsw_sp), 3868 .fw_req_rev = &mlxsw_sp2_fw_rev, 3869 .fw_filename = MLXSW_SP2_FW_FILENAME, 3870 .init = mlxsw_sp2_init, 3871 .fini = mlxsw_sp_fini, 3872 .port_split = mlxsw_sp_port_split, 3873 .port_unsplit = mlxsw_sp_port_unsplit, 3874 .ports_remove_selected = mlxsw_sp_ports_remove_selected, 3875 .sb_pool_get = mlxsw_sp_sb_pool_get, 3876 .sb_pool_set = mlxsw_sp_sb_pool_set, 3877 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get, 3878 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set, 3879 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get, 3880 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set, 3881 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot, 3882 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear, 3883 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get, 3884 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get, 3885 .trap_init = mlxsw_sp_trap_init, 3886 .trap_fini = mlxsw_sp_trap_fini, 3887 .trap_action_set = mlxsw_sp_trap_action_set, 3888 .trap_group_init = mlxsw_sp_trap_group_init, 3889 .trap_group_set = mlxsw_sp_trap_group_set, 3890 .trap_policer_init = mlxsw_sp_trap_policer_init, 3891 .trap_policer_fini = mlxsw_sp_trap_policer_fini, 3892 .trap_policer_set = mlxsw_sp_trap_policer_set, 3893 .trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get, 3894 .resources_register = mlxsw_sp2_resources_register, 3895 .ptp_transmitted = mlxsw_sp_ptp_transmitted, 3896 .profile = &mlxsw_sp2_config_profile, 3897 .sdq_supports_cqe_v2 = true, 3898 }; 3899 3900 static struct mlxsw_driver mlxsw_sp3_driver = { 3901 .kind = mlxsw_sp3_driver_name, 3902 .priv_size = sizeof(struct mlxsw_sp), 3903 .fw_req_rev = &mlxsw_sp3_fw_rev, 3904 .fw_filename = MLXSW_SP3_FW_FILENAME, 3905 .init = mlxsw_sp3_init, 3906 .fini = mlxsw_sp_fini, 3907 .port_split = mlxsw_sp_port_split, 3908 .port_unsplit = mlxsw_sp_port_unsplit, 3909 .ports_remove_selected = mlxsw_sp_ports_remove_selected, 3910 .sb_pool_get = mlxsw_sp_sb_pool_get, 3911 .sb_pool_set = mlxsw_sp_sb_pool_set, 3912 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get, 3913 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set, 3914 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get, 3915 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set, 3916 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot, 3917 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear, 3918 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get, 3919 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get, 3920 .trap_init = mlxsw_sp_trap_init, 3921 .trap_fini = mlxsw_sp_trap_fini, 3922 .trap_action_set = mlxsw_sp_trap_action_set, 3923 .trap_group_init = mlxsw_sp_trap_group_init, 3924 .trap_group_set = mlxsw_sp_trap_group_set, 3925 .trap_policer_init = mlxsw_sp_trap_policer_init, 3926 .trap_policer_fini = mlxsw_sp_trap_policer_fini, 3927 .trap_policer_set = mlxsw_sp_trap_policer_set, 3928 .trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get, 3929 .resources_register = mlxsw_sp2_resources_register, 3930 .ptp_transmitted = mlxsw_sp_ptp_transmitted, 3931 .profile = &mlxsw_sp2_config_profile, 3932 .sdq_supports_cqe_v2 = true, 3933 }; 3934 3935 static struct mlxsw_driver mlxsw_sp4_driver = { 3936 .kind = mlxsw_sp4_driver_name, 3937 .priv_size = sizeof(struct mlxsw_sp), 3938 .init = mlxsw_sp4_init, 3939 .fini = mlxsw_sp_fini, 3940 .port_split = mlxsw_sp_port_split, 3941 .port_unsplit = mlxsw_sp_port_unsplit, 3942 .ports_remove_selected = mlxsw_sp_ports_remove_selected, 3943 .sb_pool_get = mlxsw_sp_sb_pool_get, 3944 .sb_pool_set = mlxsw_sp_sb_pool_set, 3945 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get, 3946 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set, 3947 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get, 3948 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set, 3949 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot, 3950 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear, 3951 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get, 3952 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get, 3953 .trap_init = mlxsw_sp_trap_init, 3954 .trap_fini = mlxsw_sp_trap_fini, 3955 .trap_action_set = mlxsw_sp_trap_action_set, 3956 .trap_group_init = mlxsw_sp_trap_group_init, 3957 .trap_group_set = mlxsw_sp_trap_group_set, 3958 .trap_policer_init = mlxsw_sp_trap_policer_init, 3959 .trap_policer_fini = mlxsw_sp_trap_policer_fini, 3960 .trap_policer_set = mlxsw_sp_trap_policer_set, 3961 .trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get, 3962 .resources_register = mlxsw_sp2_resources_register, 3963 .ptp_transmitted = mlxsw_sp_ptp_transmitted, 3964 .profile = &mlxsw_sp4_config_profile, 3965 .sdq_supports_cqe_v2 = true, 3966 }; 3967 3968 bool mlxsw_sp_port_dev_check(const struct net_device *dev) 3969 { 3970 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops; 3971 } 3972 3973 static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, 3974 struct netdev_nested_priv *priv) 3975 { 3976 int ret = 0; 3977 3978 if (mlxsw_sp_port_dev_check(lower_dev)) { 3979 priv->data = (void *)netdev_priv(lower_dev); 3980 ret = 1; 3981 } 3982 3983 return ret; 3984 } 3985 3986 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev) 3987 { 3988 struct netdev_nested_priv priv = { 3989 .data = NULL, 3990 }; 3991 3992 if (mlxsw_sp_port_dev_check(dev)) 3993 return netdev_priv(dev); 3994 3995 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &priv); 3996 3997 return (struct mlxsw_sp_port *)priv.data; 3998 } 3999 4000 struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev) 4001 { 4002 struct mlxsw_sp_port *mlxsw_sp_port; 4003 4004 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev); 4005 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL; 4006 } 4007 4008 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev) 4009 { 4010 struct netdev_nested_priv priv = { 4011 .data = NULL, 4012 }; 4013 4014 if (mlxsw_sp_port_dev_check(dev)) 4015 return netdev_priv(dev); 4016 4017 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk, 4018 &priv); 4019 4020 return (struct mlxsw_sp_port *)priv.data; 4021 } 4022 4023 int mlxsw_sp_parsing_depth_inc(struct mlxsw_sp *mlxsw_sp) 4024 { 4025 char mprs_pl[MLXSW_REG_MPRS_LEN]; 4026 int err = 0; 4027 4028 mutex_lock(&mlxsw_sp->parsing.lock); 4029 4030 if (refcount_inc_not_zero(&mlxsw_sp->parsing.parsing_depth_ref)) 4031 goto out_unlock; 4032 4033 mlxsw_reg_mprs_pack(mprs_pl, MLXSW_SP_INCREASED_PARSING_DEPTH, 4034 mlxsw_sp->parsing.vxlan_udp_dport); 4035 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl); 4036 if (err) 4037 goto out_unlock; 4038 4039 mlxsw_sp->parsing.parsing_depth = MLXSW_SP_INCREASED_PARSING_DEPTH; 4040 refcount_set(&mlxsw_sp->parsing.parsing_depth_ref, 1); 4041 4042 out_unlock: 4043 mutex_unlock(&mlxsw_sp->parsing.lock); 4044 return err; 4045 } 4046 4047 void mlxsw_sp_parsing_depth_dec(struct mlxsw_sp *mlxsw_sp) 4048 { 4049 char mprs_pl[MLXSW_REG_MPRS_LEN]; 4050 4051 mutex_lock(&mlxsw_sp->parsing.lock); 4052 4053 if (!refcount_dec_and_test(&mlxsw_sp->parsing.parsing_depth_ref)) 4054 goto out_unlock; 4055 4056 mlxsw_reg_mprs_pack(mprs_pl, MLXSW_SP_DEFAULT_PARSING_DEPTH, 4057 mlxsw_sp->parsing.vxlan_udp_dport); 4058 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl); 4059 mlxsw_sp->parsing.parsing_depth = MLXSW_SP_DEFAULT_PARSING_DEPTH; 4060 4061 out_unlock: 4062 mutex_unlock(&mlxsw_sp->parsing.lock); 4063 } 4064 4065 int mlxsw_sp_parsing_vxlan_udp_dport_set(struct mlxsw_sp *mlxsw_sp, 4066 __be16 udp_dport) 4067 { 4068 char mprs_pl[MLXSW_REG_MPRS_LEN]; 4069 int err; 4070 4071 mutex_lock(&mlxsw_sp->parsing.lock); 4072 4073 mlxsw_reg_mprs_pack(mprs_pl, mlxsw_sp->parsing.parsing_depth, 4074 be16_to_cpu(udp_dport)); 4075 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl); 4076 if (err) 4077 goto out_unlock; 4078 4079 mlxsw_sp->parsing.vxlan_udp_dport = be16_to_cpu(udp_dport); 4080 4081 out_unlock: 4082 mutex_unlock(&mlxsw_sp->parsing.lock); 4083 return err; 4084 } 4085 4086 static void 4087 mlxsw_sp_port_lag_uppers_cleanup(struct mlxsw_sp_port *mlxsw_sp_port, 4088 struct net_device *lag_dev) 4089 { 4090 struct net_device *br_dev = netdev_master_upper_dev_get(lag_dev); 4091 struct net_device *upper_dev; 4092 struct list_head *iter; 4093 4094 if (netif_is_bridge_port(lag_dev)) 4095 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, lag_dev, br_dev); 4096 4097 netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) { 4098 if (!netif_is_bridge_port(upper_dev)) 4099 continue; 4100 br_dev = netdev_master_upper_dev_get(upper_dev); 4101 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, br_dev); 4102 } 4103 } 4104 4105 static struct mlxsw_sp_lag * 4106 mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, struct net_device *lag_dev, 4107 struct netlink_ext_ack *extack) 4108 { 4109 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4110 struct mlxsw_sp_lag *lag; 4111 u16 lag_id; 4112 int i, err; 4113 4114 for (i = 0; i < mlxsw_sp->max_lag; i++) { 4115 if (!mlxsw_sp->lags[i].dev) 4116 break; 4117 } 4118 4119 if (i == mlxsw_sp->max_lag) { 4120 NL_SET_ERR_MSG_MOD(extack, 4121 "Exceeded number of supported LAG devices"); 4122 return ERR_PTR(-EBUSY); 4123 } 4124 4125 lag_id = i; 4126 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id); 4127 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4128 if (err) 4129 return ERR_PTR(err); 4130 4131 lag = &mlxsw_sp->lags[lag_id]; 4132 lag->lag_id = lag_id; 4133 lag->dev = lag_dev; 4134 refcount_set(&lag->ref_count, 1); 4135 4136 return lag; 4137 } 4138 4139 static int 4140 mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, struct mlxsw_sp_lag *lag) 4141 { 4142 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4143 4144 lag->dev = NULL; 4145 4146 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag->lag_id); 4147 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4148 } 4149 4150 static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port, 4151 u16 lag_id, u8 port_index) 4152 { 4153 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4154 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4155 4156 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port, 4157 lag_id, port_index); 4158 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4159 } 4160 4161 static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port, 4162 u16 lag_id) 4163 { 4164 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4165 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4166 4167 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port, 4168 lag_id); 4169 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4170 } 4171 4172 static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port, 4173 u16 lag_id) 4174 { 4175 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4176 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4177 4178 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port, 4179 lag_id); 4180 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4181 } 4182 4183 static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port, 4184 u16 lag_id) 4185 { 4186 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4187 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4188 4189 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port, 4190 lag_id); 4191 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4192 } 4193 4194 static struct mlxsw_sp_lag * 4195 mlxsw_sp_lag_find(struct mlxsw_sp *mlxsw_sp, struct net_device *lag_dev) 4196 { 4197 int i; 4198 4199 for (i = 0; i < mlxsw_sp->max_lag; i++) { 4200 if (!mlxsw_sp->lags[i].dev) 4201 continue; 4202 4203 if (mlxsw_sp->lags[i].dev == lag_dev) 4204 return &mlxsw_sp->lags[i]; 4205 } 4206 4207 return NULL; 4208 } 4209 4210 static struct mlxsw_sp_lag * 4211 mlxsw_sp_lag_get(struct mlxsw_sp *mlxsw_sp, struct net_device *lag_dev, 4212 struct netlink_ext_ack *extack) 4213 { 4214 struct mlxsw_sp_lag *lag; 4215 4216 lag = mlxsw_sp_lag_find(mlxsw_sp, lag_dev); 4217 if (lag) { 4218 refcount_inc(&lag->ref_count); 4219 return lag; 4220 } 4221 4222 return mlxsw_sp_lag_create(mlxsw_sp, lag_dev, extack); 4223 } 4224 4225 static void 4226 mlxsw_sp_lag_put(struct mlxsw_sp *mlxsw_sp, struct mlxsw_sp_lag *lag) 4227 { 4228 if (!refcount_dec_and_test(&lag->ref_count)) 4229 return; 4230 4231 mlxsw_sp_lag_destroy(mlxsw_sp, lag); 4232 } 4233 4234 static bool 4235 mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp, 4236 struct net_device *lag_dev, 4237 struct netdev_lag_upper_info *lag_upper_info, 4238 struct netlink_ext_ack *extack) 4239 { 4240 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 4241 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type"); 4242 return false; 4243 } 4244 return true; 4245 } 4246 4247 static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp, 4248 u16 lag_id, u8 *p_port_index) 4249 { 4250 u64 max_lag_members; 4251 int i; 4252 4253 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core, 4254 MAX_LAG_MEMBERS); 4255 for (i = 0; i < max_lag_members; i++) { 4256 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) { 4257 *p_port_index = i; 4258 return 0; 4259 } 4260 } 4261 return -EBUSY; 4262 } 4263 4264 static int mlxsw_sp_lag_uppers_bridge_join(struct mlxsw_sp_port *mlxsw_sp_port, 4265 struct net_device *lag_dev, 4266 struct netlink_ext_ack *extack) 4267 { 4268 struct net_device *upper_dev; 4269 struct net_device *master; 4270 struct list_head *iter; 4271 int done = 0; 4272 int err; 4273 4274 master = netdev_master_upper_dev_get(lag_dev); 4275 if (master && netif_is_bridge_master(master)) { 4276 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port, lag_dev, master, 4277 extack); 4278 if (err) 4279 return err; 4280 } 4281 4282 netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) { 4283 if (!is_vlan_dev(upper_dev)) 4284 continue; 4285 4286 master = netdev_master_upper_dev_get(upper_dev); 4287 if (master && netif_is_bridge_master(master)) { 4288 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port, 4289 upper_dev, master, 4290 extack); 4291 if (err) 4292 goto err_port_bridge_join; 4293 } 4294 4295 ++done; 4296 } 4297 4298 return 0; 4299 4300 err_port_bridge_join: 4301 netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) { 4302 if (!is_vlan_dev(upper_dev)) 4303 continue; 4304 4305 master = netdev_master_upper_dev_get(upper_dev); 4306 if (!master || !netif_is_bridge_master(master)) 4307 continue; 4308 4309 if (!done--) 4310 break; 4311 4312 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, master); 4313 } 4314 4315 master = netdev_master_upper_dev_get(lag_dev); 4316 if (master && netif_is_bridge_master(master)) 4317 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, lag_dev, master); 4318 4319 return err; 4320 } 4321 4322 static void 4323 mlxsw_sp_lag_uppers_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_port, 4324 struct net_device *lag_dev) 4325 { 4326 struct net_device *upper_dev; 4327 struct net_device *master; 4328 struct list_head *iter; 4329 4330 netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) { 4331 if (!is_vlan_dev(upper_dev)) 4332 continue; 4333 4334 master = netdev_master_upper_dev_get(upper_dev); 4335 if (!master) 4336 continue; 4337 4338 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, master); 4339 } 4340 4341 master = netdev_master_upper_dev_get(lag_dev); 4342 if (master) 4343 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, lag_dev, master); 4344 } 4345 4346 static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port, 4347 struct net_device *lag_dev, 4348 struct netlink_ext_ack *extack) 4349 { 4350 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4351 struct mlxsw_sp_lag *lag; 4352 u16 lag_id; 4353 u8 port_index; 4354 int err; 4355 4356 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_dev, extack); 4357 if (IS_ERR(lag)) 4358 return PTR_ERR(lag); 4359 4360 lag_id = lag->lag_id; 4361 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index); 4362 if (err) 4363 goto err_lag_uppers_bridge_join; 4364 4365 err = mlxsw_sp_lag_uppers_bridge_join(mlxsw_sp_port, lag_dev, 4366 extack); 4367 if (err) 4368 goto err_lag_uppers_bridge_join; 4369 4370 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index); 4371 if (err) 4372 goto err_col_port_add; 4373 4374 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index, 4375 mlxsw_sp_port->local_port); 4376 mlxsw_sp_port->lag_id = lag_id; 4377 mlxsw_sp_port->lagged = 1; 4378 4379 err = mlxsw_sp_fid_port_join_lag(mlxsw_sp_port); 4380 if (err) 4381 goto err_fid_port_join_lag; 4382 4383 /* Port is no longer usable as a router interface */ 4384 if (mlxsw_sp_port->default_vlan->fid) 4385 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port->default_vlan); 4386 4387 /* Join a router interface configured on the LAG, if exists */ 4388 err = mlxsw_sp_router_port_join_lag(mlxsw_sp_port, lag_dev, 4389 extack); 4390 if (err) 4391 goto err_router_join; 4392 4393 err = mlxsw_sp_netdevice_enslavement_replay(mlxsw_sp, lag_dev, extack); 4394 if (err) 4395 goto err_replay; 4396 4397 return 0; 4398 4399 err_replay: 4400 mlxsw_sp_router_port_leave_lag(mlxsw_sp_port, lag_dev); 4401 err_router_join: 4402 mlxsw_sp_fid_port_leave_lag(mlxsw_sp_port); 4403 err_fid_port_join_lag: 4404 mlxsw_sp_port->lagged = 0; 4405 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id, 4406 mlxsw_sp_port->local_port); 4407 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id); 4408 err_col_port_add: 4409 mlxsw_sp_lag_uppers_bridge_leave(mlxsw_sp_port, lag_dev); 4410 err_lag_uppers_bridge_join: 4411 mlxsw_sp_lag_put(mlxsw_sp, lag); 4412 return err; 4413 } 4414 4415 static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port, 4416 struct net_device *lag_dev) 4417 { 4418 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4419 u16 lag_id = mlxsw_sp_port->lag_id; 4420 struct mlxsw_sp_lag *lag; 4421 4422 if (!mlxsw_sp_port->lagged) 4423 return; 4424 lag = &mlxsw_sp->lags[lag_id]; 4425 4426 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id); 4427 4428 /* Any VLANs configured on the port are no longer valid */ 4429 mlxsw_sp_port_vlan_flush(mlxsw_sp_port, false); 4430 mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port->default_vlan); 4431 /* Make the LAG and its directly linked uppers leave bridges they 4432 * are memeber in 4433 */ 4434 mlxsw_sp_port_lag_uppers_cleanup(mlxsw_sp_port, lag_dev); 4435 4436 mlxsw_sp_fid_port_leave_lag(mlxsw_sp_port); 4437 4438 mlxsw_sp_lag_put(mlxsw_sp, lag); 4439 4440 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id, 4441 mlxsw_sp_port->local_port); 4442 mlxsw_sp_port->lagged = 0; 4443 4444 /* Make sure untagged frames are allowed to ingress */ 4445 mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID, 4446 ETH_P_8021Q); 4447 } 4448 4449 static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port, 4450 u16 lag_id) 4451 { 4452 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4453 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4454 4455 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id, 4456 mlxsw_sp_port->local_port); 4457 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4458 } 4459 4460 static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port, 4461 u16 lag_id) 4462 { 4463 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4464 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4465 4466 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id, 4467 mlxsw_sp_port->local_port); 4468 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4469 } 4470 4471 static int 4472 mlxsw_sp_port_lag_col_dist_enable(struct mlxsw_sp_port *mlxsw_sp_port) 4473 { 4474 int err; 4475 4476 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, 4477 mlxsw_sp_port->lag_id); 4478 if (err) 4479 return err; 4480 4481 err = mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id); 4482 if (err) 4483 goto err_dist_port_add; 4484 4485 return 0; 4486 4487 err_dist_port_add: 4488 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, mlxsw_sp_port->lag_id); 4489 return err; 4490 } 4491 4492 static int 4493 mlxsw_sp_port_lag_col_dist_disable(struct mlxsw_sp_port *mlxsw_sp_port) 4494 { 4495 int err; 4496 4497 err = mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port, 4498 mlxsw_sp_port->lag_id); 4499 if (err) 4500 return err; 4501 4502 err = mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, 4503 mlxsw_sp_port->lag_id); 4504 if (err) 4505 goto err_col_port_disable; 4506 4507 return 0; 4508 4509 err_col_port_disable: 4510 mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id); 4511 return err; 4512 } 4513 4514 static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port, 4515 struct netdev_lag_lower_state_info *info) 4516 { 4517 if (info->tx_enabled) 4518 return mlxsw_sp_port_lag_col_dist_enable(mlxsw_sp_port); 4519 else 4520 return mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port); 4521 } 4522 4523 static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, 4524 bool enable) 4525 { 4526 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4527 enum mlxsw_reg_spms_state spms_state; 4528 char *spms_pl; 4529 u16 vid; 4530 int err; 4531 4532 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING : 4533 MLXSW_REG_SPMS_STATE_DISCARDING; 4534 4535 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL); 4536 if (!spms_pl) 4537 return -ENOMEM; 4538 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port); 4539 4540 for (vid = 0; vid < VLAN_N_VID; vid++) 4541 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state); 4542 4543 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl); 4544 kfree(spms_pl); 4545 return err; 4546 } 4547 4548 static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port) 4549 { 4550 u16 vid = 1; 4551 int err; 4552 4553 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true); 4554 if (err) 4555 return err; 4556 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true); 4557 if (err) 4558 goto err_port_stp_set; 4559 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2, 4560 true, false); 4561 if (err) 4562 goto err_port_vlan_set; 4563 4564 for (; vid <= VLAN_N_VID - 1; vid++) { 4565 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, 4566 vid, false); 4567 if (err) 4568 goto err_vid_learning_set; 4569 } 4570 4571 return 0; 4572 4573 err_vid_learning_set: 4574 for (vid--; vid >= 1; vid--) 4575 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true); 4576 err_port_vlan_set: 4577 mlxsw_sp_port_stp_set(mlxsw_sp_port, false); 4578 err_port_stp_set: 4579 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false); 4580 return err; 4581 } 4582 4583 static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port) 4584 { 4585 u16 vid; 4586 4587 for (vid = VLAN_N_VID - 1; vid >= 1; vid--) 4588 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, 4589 vid, true); 4590 4591 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2, 4592 false, false); 4593 mlxsw_sp_port_stp_set(mlxsw_sp_port, false); 4594 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false); 4595 } 4596 4597 static bool mlxsw_sp_bridge_has_multiple_vxlans(struct net_device *br_dev) 4598 { 4599 unsigned int num_vxlans = 0; 4600 struct net_device *dev; 4601 struct list_head *iter; 4602 4603 netdev_for_each_lower_dev(br_dev, dev, iter) { 4604 if (netif_is_vxlan(dev)) 4605 num_vxlans++; 4606 } 4607 4608 return num_vxlans > 1; 4609 } 4610 4611 static bool mlxsw_sp_bridge_vxlan_vlan_is_valid(struct net_device *br_dev) 4612 { 4613 DECLARE_BITMAP(vlans, VLAN_N_VID) = {0}; 4614 struct net_device *dev; 4615 struct list_head *iter; 4616 4617 netdev_for_each_lower_dev(br_dev, dev, iter) { 4618 u16 pvid; 4619 int err; 4620 4621 if (!netif_is_vxlan(dev)) 4622 continue; 4623 4624 err = mlxsw_sp_vxlan_mapped_vid(dev, &pvid); 4625 if (err || !pvid) 4626 continue; 4627 4628 if (test_and_set_bit(pvid, vlans)) 4629 return false; 4630 } 4631 4632 return true; 4633 } 4634 4635 static bool mlxsw_sp_bridge_vxlan_is_valid(struct net_device *br_dev, 4636 struct netlink_ext_ack *extack) 4637 { 4638 if (br_multicast_enabled(br_dev)) { 4639 NL_SET_ERR_MSG_MOD(extack, "Multicast can not be enabled on a bridge with a VxLAN device"); 4640 return false; 4641 } 4642 4643 if (!br_vlan_enabled(br_dev) && 4644 mlxsw_sp_bridge_has_multiple_vxlans(br_dev)) { 4645 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices are not supported in a VLAN-unaware bridge"); 4646 return false; 4647 } 4648 4649 if (br_vlan_enabled(br_dev) && 4650 !mlxsw_sp_bridge_vxlan_vlan_is_valid(br_dev)) { 4651 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices cannot have the same VLAN as PVID and egress untagged"); 4652 return false; 4653 } 4654 4655 return true; 4656 } 4657 4658 static bool mlxsw_sp_netdev_is_master(struct net_device *upper_dev, 4659 struct net_device *dev) 4660 { 4661 return upper_dev == netdev_master_upper_dev_get(dev); 4662 } 4663 4664 static int __mlxsw_sp_netdevice_event(struct mlxsw_sp *mlxsw_sp, 4665 unsigned long event, void *ptr, 4666 bool process_foreign); 4667 4668 static int mlxsw_sp_netdevice_validate_uppers(struct mlxsw_sp *mlxsw_sp, 4669 struct net_device *dev, 4670 struct netlink_ext_ack *extack) 4671 { 4672 struct net_device *upper_dev; 4673 struct list_head *iter; 4674 int err; 4675 4676 netdev_for_each_upper_dev_rcu(dev, upper_dev, iter) { 4677 struct netdev_notifier_changeupper_info info = { 4678 .info = { 4679 .dev = dev, 4680 .extack = extack, 4681 }, 4682 .master = mlxsw_sp_netdev_is_master(upper_dev, dev), 4683 .upper_dev = upper_dev, 4684 .linking = true, 4685 4686 /* upper_info is relevant for LAG devices. But we would 4687 * only need this if LAG were a valid upper above 4688 * another upper (e.g. a bridge that is a member of a 4689 * LAG), and that is never a valid configuration. So we 4690 * can keep this as NULL. 4691 */ 4692 .upper_info = NULL, 4693 }; 4694 4695 err = __mlxsw_sp_netdevice_event(mlxsw_sp, 4696 NETDEV_PRECHANGEUPPER, 4697 &info, true); 4698 if (err) 4699 return err; 4700 4701 err = mlxsw_sp_netdevice_validate_uppers(mlxsw_sp, upper_dev, 4702 extack); 4703 if (err) 4704 return err; 4705 } 4706 4707 return 0; 4708 } 4709 4710 static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev, 4711 struct net_device *dev, 4712 unsigned long event, void *ptr, 4713 bool replay_deslavement) 4714 { 4715 struct netdev_notifier_changeupper_info *info; 4716 struct mlxsw_sp_port *mlxsw_sp_port; 4717 struct netlink_ext_ack *extack; 4718 struct net_device *upper_dev; 4719 struct mlxsw_sp *mlxsw_sp; 4720 int err = 0; 4721 u16 proto; 4722 4723 mlxsw_sp_port = netdev_priv(dev); 4724 mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4725 info = ptr; 4726 extack = netdev_notifier_info_to_extack(&info->info); 4727 4728 switch (event) { 4729 case NETDEV_PRECHANGEUPPER: 4730 upper_dev = info->upper_dev; 4731 if (!is_vlan_dev(upper_dev) && 4732 !netif_is_lag_master(upper_dev) && 4733 !netif_is_bridge_master(upper_dev) && 4734 !netif_is_ovs_master(upper_dev) && 4735 !netif_is_macvlan(upper_dev) && 4736 !netif_is_l3_master(upper_dev)) { 4737 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 4738 return -EINVAL; 4739 } 4740 if (!info->linking) 4741 break; 4742 if (netif_is_bridge_master(upper_dev) && 4743 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) && 4744 mlxsw_sp_bridge_has_vxlan(upper_dev) && 4745 !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack)) 4746 return -EOPNOTSUPP; 4747 if (netdev_has_any_upper_dev(upper_dev) && 4748 (!netif_is_bridge_master(upper_dev) || 4749 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, 4750 upper_dev))) { 4751 err = mlxsw_sp_netdevice_validate_uppers(mlxsw_sp, 4752 upper_dev, 4753 extack); 4754 if (err) 4755 return err; 4756 } 4757 if (netif_is_lag_master(upper_dev) && 4758 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev, 4759 info->upper_info, extack)) 4760 return -EINVAL; 4761 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) { 4762 NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN"); 4763 return -EINVAL; 4764 } 4765 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) && 4766 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) { 4767 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port"); 4768 return -EINVAL; 4769 } 4770 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) { 4771 NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN"); 4772 return -EINVAL; 4773 } 4774 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) { 4775 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port"); 4776 return -EINVAL; 4777 } 4778 if (netif_is_bridge_master(upper_dev)) { 4779 br_vlan_get_proto(upper_dev, &proto); 4780 if (br_vlan_enabled(upper_dev) && 4781 proto != ETH_P_8021Q && proto != ETH_P_8021AD) { 4782 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a bridge with unknown VLAN protocol is not supported"); 4783 return -EOPNOTSUPP; 4784 } 4785 if (vlan_uses_dev(lower_dev) && 4786 br_vlan_enabled(upper_dev) && 4787 proto == ETH_P_8021AD) { 4788 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port that already has a VLAN upper to an 802.1ad bridge is not supported"); 4789 return -EOPNOTSUPP; 4790 } 4791 } 4792 if (netif_is_bridge_port(lower_dev) && is_vlan_dev(upper_dev)) { 4793 struct net_device *br_dev = netdev_master_upper_dev_get(lower_dev); 4794 4795 if (br_vlan_enabled(br_dev)) { 4796 br_vlan_get_proto(br_dev, &proto); 4797 if (proto == ETH_P_8021AD) { 4798 NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are not supported on a port enslaved to an 802.1ad bridge"); 4799 return -EOPNOTSUPP; 4800 } 4801 } 4802 } 4803 if (is_vlan_dev(upper_dev) && 4804 ntohs(vlan_dev_vlan_proto(upper_dev)) != ETH_P_8021Q) { 4805 NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are only supported with 802.1q VLAN protocol"); 4806 return -EOPNOTSUPP; 4807 } 4808 if (is_vlan_dev(upper_dev) && mlxsw_sp_port->security) { 4809 NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are not supported on a locked port"); 4810 return -EOPNOTSUPP; 4811 } 4812 break; 4813 case NETDEV_CHANGEUPPER: 4814 upper_dev = info->upper_dev; 4815 if (netif_is_bridge_master(upper_dev)) { 4816 if (info->linking) { 4817 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port, 4818 lower_dev, 4819 upper_dev, 4820 extack); 4821 } else { 4822 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, 4823 lower_dev, 4824 upper_dev); 4825 if (!replay_deslavement) 4826 break; 4827 mlxsw_sp_netdevice_deslavement_replay(mlxsw_sp, 4828 lower_dev); 4829 } 4830 } else if (netif_is_lag_master(upper_dev)) { 4831 if (info->linking) { 4832 err = mlxsw_sp_port_lag_join(mlxsw_sp_port, 4833 upper_dev, extack); 4834 } else { 4835 mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port); 4836 mlxsw_sp_port_lag_leave(mlxsw_sp_port, 4837 upper_dev); 4838 mlxsw_sp_netdevice_deslavement_replay(mlxsw_sp, 4839 dev); 4840 } 4841 } else if (netif_is_ovs_master(upper_dev)) { 4842 if (info->linking) 4843 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port); 4844 else 4845 mlxsw_sp_port_ovs_leave(mlxsw_sp_port); 4846 } else if (netif_is_macvlan(upper_dev)) { 4847 if (!info->linking) 4848 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 4849 } else if (is_vlan_dev(upper_dev)) { 4850 struct net_device *br_dev; 4851 4852 if (!netif_is_bridge_port(upper_dev)) 4853 break; 4854 if (info->linking) 4855 break; 4856 br_dev = netdev_master_upper_dev_get(upper_dev); 4857 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, 4858 br_dev); 4859 } 4860 break; 4861 } 4862 4863 return err; 4864 } 4865 4866 static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev, 4867 unsigned long event, void *ptr) 4868 { 4869 struct netdev_notifier_changelowerstate_info *info; 4870 struct mlxsw_sp_port *mlxsw_sp_port; 4871 int err; 4872 4873 mlxsw_sp_port = netdev_priv(dev); 4874 info = ptr; 4875 4876 switch (event) { 4877 case NETDEV_CHANGELOWERSTATE: 4878 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) { 4879 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port, 4880 info->lower_state_info); 4881 if (err) 4882 netdev_err(dev, "Failed to reflect link aggregation lower state change\n"); 4883 } 4884 break; 4885 } 4886 4887 return 0; 4888 } 4889 4890 static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev, 4891 struct net_device *port_dev, 4892 unsigned long event, void *ptr, 4893 bool replay_deslavement) 4894 { 4895 switch (event) { 4896 case NETDEV_PRECHANGEUPPER: 4897 case NETDEV_CHANGEUPPER: 4898 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev, 4899 event, ptr, 4900 replay_deslavement); 4901 case NETDEV_CHANGELOWERSTATE: 4902 return mlxsw_sp_netdevice_port_lower_event(port_dev, event, 4903 ptr); 4904 } 4905 4906 return 0; 4907 } 4908 4909 /* Called for LAG or its upper VLAN after the per-LAG-lower processing was done, 4910 * to do any per-LAG / per-LAG-upper processing. 4911 */ 4912 static int mlxsw_sp_netdevice_post_lag_event(struct net_device *dev, 4913 unsigned long event, 4914 void *ptr) 4915 { 4916 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(dev); 4917 struct netdev_notifier_changeupper_info *info = ptr; 4918 4919 if (!mlxsw_sp) 4920 return 0; 4921 4922 switch (event) { 4923 case NETDEV_CHANGEUPPER: 4924 if (info->linking) 4925 break; 4926 if (netif_is_bridge_master(info->upper_dev)) 4927 mlxsw_sp_netdevice_deslavement_replay(mlxsw_sp, dev); 4928 break; 4929 } 4930 return 0; 4931 } 4932 4933 static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev, 4934 unsigned long event, void *ptr) 4935 { 4936 struct net_device *dev; 4937 struct list_head *iter; 4938 int ret; 4939 4940 netdev_for_each_lower_dev(lag_dev, dev, iter) { 4941 if (mlxsw_sp_port_dev_check(dev)) { 4942 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event, 4943 ptr, false); 4944 if (ret) 4945 return ret; 4946 } 4947 } 4948 4949 return mlxsw_sp_netdevice_post_lag_event(lag_dev, event, ptr); 4950 } 4951 4952 static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev, 4953 struct net_device *dev, 4954 unsigned long event, void *ptr, 4955 u16 vid, bool replay_deslavement) 4956 { 4957 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 4958 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4959 struct netdev_notifier_changeupper_info *info = ptr; 4960 struct netlink_ext_ack *extack; 4961 struct net_device *upper_dev; 4962 int err = 0; 4963 4964 extack = netdev_notifier_info_to_extack(&info->info); 4965 4966 switch (event) { 4967 case NETDEV_PRECHANGEUPPER: 4968 upper_dev = info->upper_dev; 4969 if (!netif_is_bridge_master(upper_dev) && 4970 !netif_is_macvlan(upper_dev) && 4971 !netif_is_l3_master(upper_dev)) { 4972 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 4973 return -EINVAL; 4974 } 4975 if (!info->linking) 4976 break; 4977 if (netif_is_bridge_master(upper_dev) && 4978 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) && 4979 mlxsw_sp_bridge_has_vxlan(upper_dev) && 4980 !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack)) 4981 return -EOPNOTSUPP; 4982 if (netdev_has_any_upper_dev(upper_dev) && 4983 (!netif_is_bridge_master(upper_dev) || 4984 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, 4985 upper_dev))) { 4986 err = mlxsw_sp_netdevice_validate_uppers(mlxsw_sp, 4987 upper_dev, 4988 extack); 4989 if (err) 4990 return err; 4991 } 4992 break; 4993 case NETDEV_CHANGEUPPER: 4994 upper_dev = info->upper_dev; 4995 if (netif_is_bridge_master(upper_dev)) { 4996 if (info->linking) { 4997 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port, 4998 vlan_dev, 4999 upper_dev, 5000 extack); 5001 } else { 5002 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, 5003 vlan_dev, 5004 upper_dev); 5005 if (!replay_deslavement) 5006 break; 5007 mlxsw_sp_netdevice_deslavement_replay(mlxsw_sp, 5008 vlan_dev); 5009 } 5010 } else if (netif_is_macvlan(upper_dev)) { 5011 if (!info->linking) 5012 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 5013 } 5014 break; 5015 } 5016 5017 return err; 5018 } 5019 5020 static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev, 5021 struct net_device *lag_dev, 5022 unsigned long event, 5023 void *ptr, u16 vid) 5024 { 5025 struct net_device *dev; 5026 struct list_head *iter; 5027 int ret; 5028 5029 netdev_for_each_lower_dev(lag_dev, dev, iter) { 5030 if (mlxsw_sp_port_dev_check(dev)) { 5031 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev, 5032 event, ptr, 5033 vid, false); 5034 if (ret) 5035 return ret; 5036 } 5037 } 5038 5039 return mlxsw_sp_netdevice_post_lag_event(vlan_dev, event, ptr); 5040 } 5041 5042 static int mlxsw_sp_netdevice_bridge_vlan_event(struct mlxsw_sp *mlxsw_sp, 5043 struct net_device *vlan_dev, 5044 struct net_device *br_dev, 5045 unsigned long event, void *ptr, 5046 u16 vid, bool process_foreign) 5047 { 5048 struct netdev_notifier_changeupper_info *info = ptr; 5049 struct netlink_ext_ack *extack; 5050 struct net_device *upper_dev; 5051 5052 if (!process_foreign && !mlxsw_sp_lower_get(vlan_dev)) 5053 return 0; 5054 5055 extack = netdev_notifier_info_to_extack(&info->info); 5056 5057 switch (event) { 5058 case NETDEV_PRECHANGEUPPER: 5059 upper_dev = info->upper_dev; 5060 if (!netif_is_macvlan(upper_dev) && 5061 !netif_is_l3_master(upper_dev)) { 5062 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 5063 return -EOPNOTSUPP; 5064 } 5065 break; 5066 case NETDEV_CHANGEUPPER: 5067 upper_dev = info->upper_dev; 5068 if (info->linking) 5069 break; 5070 if (netif_is_macvlan(upper_dev)) 5071 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 5072 break; 5073 } 5074 5075 return 0; 5076 } 5077 5078 static int mlxsw_sp_netdevice_vlan_event(struct mlxsw_sp *mlxsw_sp, 5079 struct net_device *vlan_dev, 5080 unsigned long event, void *ptr, 5081 bool process_foreign) 5082 { 5083 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev); 5084 u16 vid = vlan_dev_vlan_id(vlan_dev); 5085 5086 if (mlxsw_sp_port_dev_check(real_dev)) 5087 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev, 5088 event, ptr, vid, 5089 true); 5090 else if (netif_is_lag_master(real_dev)) 5091 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev, 5092 real_dev, event, 5093 ptr, vid); 5094 else if (netif_is_bridge_master(real_dev)) 5095 return mlxsw_sp_netdevice_bridge_vlan_event(mlxsw_sp, vlan_dev, 5096 real_dev, event, 5097 ptr, vid, 5098 process_foreign); 5099 5100 return 0; 5101 } 5102 5103 static int mlxsw_sp_netdevice_bridge_event(struct mlxsw_sp *mlxsw_sp, 5104 struct net_device *br_dev, 5105 unsigned long event, void *ptr, 5106 bool process_foreign) 5107 { 5108 struct netdev_notifier_changeupper_info *info = ptr; 5109 struct netlink_ext_ack *extack; 5110 struct net_device *upper_dev; 5111 u16 proto; 5112 5113 if (!process_foreign && !mlxsw_sp_lower_get(br_dev)) 5114 return 0; 5115 5116 extack = netdev_notifier_info_to_extack(&info->info); 5117 5118 switch (event) { 5119 case NETDEV_PRECHANGEUPPER: 5120 upper_dev = info->upper_dev; 5121 if (!is_vlan_dev(upper_dev) && 5122 !netif_is_macvlan(upper_dev) && 5123 !netif_is_l3_master(upper_dev)) { 5124 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 5125 return -EOPNOTSUPP; 5126 } 5127 if (!info->linking) 5128 break; 5129 if (br_vlan_enabled(br_dev)) { 5130 br_vlan_get_proto(br_dev, &proto); 5131 if (proto == ETH_P_8021AD) { 5132 NL_SET_ERR_MSG_MOD(extack, "Upper devices are not supported on top of an 802.1ad bridge"); 5133 return -EOPNOTSUPP; 5134 } 5135 } 5136 if (is_vlan_dev(upper_dev) && 5137 ntohs(vlan_dev_vlan_proto(upper_dev)) != ETH_P_8021Q) { 5138 NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are only supported with 802.1q VLAN protocol"); 5139 return -EOPNOTSUPP; 5140 } 5141 break; 5142 case NETDEV_CHANGEUPPER: 5143 upper_dev = info->upper_dev; 5144 if (info->linking) 5145 break; 5146 if (is_vlan_dev(upper_dev)) 5147 mlxsw_sp_rif_destroy_by_dev(mlxsw_sp, upper_dev); 5148 if (netif_is_macvlan(upper_dev)) 5149 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 5150 break; 5151 } 5152 5153 return 0; 5154 } 5155 5156 static int mlxsw_sp_netdevice_macvlan_event(struct net_device *macvlan_dev, 5157 unsigned long event, void *ptr) 5158 { 5159 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(macvlan_dev); 5160 struct netdev_notifier_changeupper_info *info = ptr; 5161 struct netlink_ext_ack *extack; 5162 struct net_device *upper_dev; 5163 5164 if (!mlxsw_sp || event != NETDEV_PRECHANGEUPPER) 5165 return 0; 5166 5167 extack = netdev_notifier_info_to_extack(&info->info); 5168 upper_dev = info->upper_dev; 5169 5170 if (!netif_is_l3_master(upper_dev)) { 5171 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 5172 return -EOPNOTSUPP; 5173 } 5174 5175 return 0; 5176 } 5177 5178 static int mlxsw_sp_netdevice_vxlan_event(struct mlxsw_sp *mlxsw_sp, 5179 struct net_device *dev, 5180 unsigned long event, void *ptr) 5181 { 5182 struct netdev_notifier_changeupper_info *cu_info; 5183 struct netdev_notifier_info *info = ptr; 5184 struct netlink_ext_ack *extack; 5185 struct net_device *upper_dev; 5186 5187 extack = netdev_notifier_info_to_extack(info); 5188 5189 switch (event) { 5190 case NETDEV_CHANGEUPPER: 5191 cu_info = container_of(info, 5192 struct netdev_notifier_changeupper_info, 5193 info); 5194 upper_dev = cu_info->upper_dev; 5195 if (!netif_is_bridge_master(upper_dev)) 5196 return 0; 5197 if (!mlxsw_sp_lower_get(upper_dev)) 5198 return 0; 5199 if (!mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack)) 5200 return -EOPNOTSUPP; 5201 if (!netif_running(dev)) 5202 return 0; 5203 if (cu_info->linking) 5204 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev, 5205 dev, 0, extack); 5206 else 5207 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev); 5208 break; 5209 case NETDEV_PRE_UP: 5210 upper_dev = netdev_master_upper_dev_get(dev); 5211 if (!upper_dev) 5212 return 0; 5213 if (!netif_is_bridge_master(upper_dev)) 5214 return 0; 5215 if (!mlxsw_sp_lower_get(upper_dev)) 5216 return 0; 5217 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev, dev, 0, 5218 extack); 5219 case NETDEV_DOWN: 5220 upper_dev = netdev_master_upper_dev_get(dev); 5221 if (!upper_dev) 5222 return 0; 5223 if (!netif_is_bridge_master(upper_dev)) 5224 return 0; 5225 if (!mlxsw_sp_lower_get(upper_dev)) 5226 return 0; 5227 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev); 5228 break; 5229 } 5230 5231 return 0; 5232 } 5233 5234 static int __mlxsw_sp_netdevice_event(struct mlxsw_sp *mlxsw_sp, 5235 unsigned long event, void *ptr, 5236 bool process_foreign) 5237 { 5238 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 5239 struct mlxsw_sp_span_entry *span_entry; 5240 int err = 0; 5241 5242 if (event == NETDEV_UNREGISTER) { 5243 span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev); 5244 if (span_entry) 5245 mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry); 5246 } 5247 5248 if (netif_is_vxlan(dev)) 5249 err = mlxsw_sp_netdevice_vxlan_event(mlxsw_sp, dev, event, ptr); 5250 else if (mlxsw_sp_port_dev_check(dev)) 5251 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr, true); 5252 else if (netif_is_lag_master(dev)) 5253 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr); 5254 else if (is_vlan_dev(dev)) 5255 err = mlxsw_sp_netdevice_vlan_event(mlxsw_sp, dev, event, ptr, 5256 process_foreign); 5257 else if (netif_is_bridge_master(dev)) 5258 err = mlxsw_sp_netdevice_bridge_event(mlxsw_sp, dev, event, ptr, 5259 process_foreign); 5260 else if (netif_is_macvlan(dev)) 5261 err = mlxsw_sp_netdevice_macvlan_event(dev, event, ptr); 5262 5263 return err; 5264 } 5265 5266 static int mlxsw_sp_netdevice_event(struct notifier_block *nb, 5267 unsigned long event, void *ptr) 5268 { 5269 struct mlxsw_sp *mlxsw_sp; 5270 int err; 5271 5272 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb); 5273 mlxsw_sp_span_respin(mlxsw_sp); 5274 err = __mlxsw_sp_netdevice_event(mlxsw_sp, event, ptr, false); 5275 5276 return notifier_from_errno(err); 5277 } 5278 5279 static const struct pci_device_id mlxsw_sp1_pci_id_table[] = { 5280 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM) }, 5281 { }, 5282 }; 5283 5284 static struct pci_driver mlxsw_sp1_pci_driver = { 5285 .name = mlxsw_sp1_driver_name, 5286 .id_table = mlxsw_sp1_pci_id_table, 5287 }; 5288 5289 static const struct pci_device_id mlxsw_sp2_pci_id_table[] = { 5290 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM2) }, 5291 { }, 5292 }; 5293 5294 static struct pci_driver mlxsw_sp2_pci_driver = { 5295 .name = mlxsw_sp2_driver_name, 5296 .id_table = mlxsw_sp2_pci_id_table, 5297 }; 5298 5299 static const struct pci_device_id mlxsw_sp3_pci_id_table[] = { 5300 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM3) }, 5301 { }, 5302 }; 5303 5304 static struct pci_driver mlxsw_sp3_pci_driver = { 5305 .name = mlxsw_sp3_driver_name, 5306 .id_table = mlxsw_sp3_pci_id_table, 5307 }; 5308 5309 static const struct pci_device_id mlxsw_sp4_pci_id_table[] = { 5310 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM4) }, 5311 { }, 5312 }; 5313 5314 static struct pci_driver mlxsw_sp4_pci_driver = { 5315 .name = mlxsw_sp4_driver_name, 5316 .id_table = mlxsw_sp4_pci_id_table, 5317 }; 5318 5319 static int __init mlxsw_sp_module_init(void) 5320 { 5321 int err; 5322 5323 err = mlxsw_core_driver_register(&mlxsw_sp1_driver); 5324 if (err) 5325 return err; 5326 5327 err = mlxsw_core_driver_register(&mlxsw_sp2_driver); 5328 if (err) 5329 goto err_sp2_core_driver_register; 5330 5331 err = mlxsw_core_driver_register(&mlxsw_sp3_driver); 5332 if (err) 5333 goto err_sp3_core_driver_register; 5334 5335 err = mlxsw_core_driver_register(&mlxsw_sp4_driver); 5336 if (err) 5337 goto err_sp4_core_driver_register; 5338 5339 err = mlxsw_pci_driver_register(&mlxsw_sp1_pci_driver); 5340 if (err) 5341 goto err_sp1_pci_driver_register; 5342 5343 err = mlxsw_pci_driver_register(&mlxsw_sp2_pci_driver); 5344 if (err) 5345 goto err_sp2_pci_driver_register; 5346 5347 err = mlxsw_pci_driver_register(&mlxsw_sp3_pci_driver); 5348 if (err) 5349 goto err_sp3_pci_driver_register; 5350 5351 err = mlxsw_pci_driver_register(&mlxsw_sp4_pci_driver); 5352 if (err) 5353 goto err_sp4_pci_driver_register; 5354 5355 return 0; 5356 5357 err_sp4_pci_driver_register: 5358 mlxsw_pci_driver_unregister(&mlxsw_sp3_pci_driver); 5359 err_sp3_pci_driver_register: 5360 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver); 5361 err_sp2_pci_driver_register: 5362 mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver); 5363 err_sp1_pci_driver_register: 5364 mlxsw_core_driver_unregister(&mlxsw_sp4_driver); 5365 err_sp4_core_driver_register: 5366 mlxsw_core_driver_unregister(&mlxsw_sp3_driver); 5367 err_sp3_core_driver_register: 5368 mlxsw_core_driver_unregister(&mlxsw_sp2_driver); 5369 err_sp2_core_driver_register: 5370 mlxsw_core_driver_unregister(&mlxsw_sp1_driver); 5371 return err; 5372 } 5373 5374 static void __exit mlxsw_sp_module_exit(void) 5375 { 5376 mlxsw_pci_driver_unregister(&mlxsw_sp4_pci_driver); 5377 mlxsw_pci_driver_unregister(&mlxsw_sp3_pci_driver); 5378 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver); 5379 mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver); 5380 mlxsw_core_driver_unregister(&mlxsw_sp4_driver); 5381 mlxsw_core_driver_unregister(&mlxsw_sp3_driver); 5382 mlxsw_core_driver_unregister(&mlxsw_sp2_driver); 5383 mlxsw_core_driver_unregister(&mlxsw_sp1_driver); 5384 } 5385 5386 module_init(mlxsw_sp_module_init); 5387 module_exit(mlxsw_sp_module_exit); 5388 5389 MODULE_LICENSE("Dual BSD/GPL"); 5390 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>"); 5391 MODULE_DESCRIPTION("Mellanox Spectrum driver"); 5392 MODULE_DEVICE_TABLE(pci, mlxsw_sp1_pci_id_table); 5393 MODULE_DEVICE_TABLE(pci, mlxsw_sp2_pci_id_table); 5394 MODULE_DEVICE_TABLE(pci, mlxsw_sp3_pci_id_table); 5395 MODULE_DEVICE_TABLE(pci, mlxsw_sp4_pci_id_table); 5396 MODULE_FIRMWARE(MLXSW_SP1_FW_FILENAME); 5397 MODULE_FIRMWARE(MLXSW_SP2_FW_FILENAME); 5398 MODULE_FIRMWARE(MLXSW_SP3_FW_FILENAME); 5399 MODULE_FIRMWARE(MLXSW_SP_LINECARDS_INI_BUNDLE_FILENAME); 5400