1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright IBM Corp. 2004, 2011 4 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>, 5 * Holger Smolinski <Holger.Smolinski@de.ibm.com>, 6 * Thomas Spatzier <tspat@de.ibm.com>, 7 * 8 * This file contains interrupt related functions. 9 */ 10 11 #include <linux/kernel_stat.h> 12 #include <linux/cpufeature.h> 13 #include <linux/interrupt.h> 14 #include <linux/seq_file.h> 15 #include <linux/proc_fs.h> 16 #include <linux/profile.h> 17 #include <linux/export.h> 18 #include <linux/kernel.h> 19 #include <linux/ftrace.h> 20 #include <linux/errno.h> 21 #include <linux/slab.h> 22 #include <linux/init.h> 23 #include <linux/cpu.h> 24 #include <linux/irq.h> 25 #include <linux/entry-common.h> 26 #include <asm/irq_regs.h> 27 #include <asm/cputime.h> 28 #include <asm/lowcore.h> 29 #include <asm/machine.h> 30 #include <asm/irq.h> 31 #include <asm/hw_irq.h> 32 #include <asm/stacktrace.h> 33 #include <asm/softirq_stack.h> 34 #include <asm/vtime.h> 35 #include <asm/asm.h> 36 #include <asm/entry-percpu.h> 37 #include "entry.h" 38 39 DEFINE_PER_CPU_SHARED_ALIGNED(struct irq_stat, irq_stat); 40 EXPORT_PER_CPU_SYMBOL_GPL(irq_stat); 41 42 struct irq_class { 43 int irq; 44 char *name; 45 char *desc; 46 }; 47 48 /* 49 * The list of "main" irq classes on s390. This is the list of interrupts 50 * that appear both in /proc/stat ("intr" line) and /proc/interrupts. 51 * Historically only external and I/O interrupts have been part of /proc/stat. 52 * We can't add the split external and I/O sub classes since the first field 53 * in the "intr" line in /proc/stat is supposed to be the sum of all other 54 * fields. 55 * Since the external and I/O interrupt fields are already sums we would end 56 * up with having a sum which accounts each interrupt twice. 57 */ 58 static const struct irq_class irqclass_main_desc[NR_IRQS_BASE] = { 59 {.irq = EXT_INTERRUPT, .name = "EXT"}, 60 {.irq = IO_INTERRUPT, .name = "I/O"}, 61 {.irq = THIN_INTERRUPT, .name = "AIO"}, 62 }; 63 64 /* 65 * The list of split external and I/O interrupts that appear only in 66 * /proc/interrupts. 67 * In addition this list contains non external / I/O events like NMIs. 68 */ 69 static const struct irq_class irqclass_sub_desc[] = { 70 {.irq = IRQEXT_CLK, .name = "CLK", .desc = "[EXT] Clock Comparator"}, 71 {.irq = IRQEXT_EXC, .name = "EXC", .desc = "[EXT] External Call"}, 72 {.irq = IRQEXT_EMS, .name = "EMS", .desc = "[EXT] Emergency Signal"}, 73 {.irq = IRQEXT_TMR, .name = "TMR", .desc = "[EXT] CPU Timer"}, 74 {.irq = IRQEXT_TLA, .name = "TAL", .desc = "[EXT] Timing Alert"}, 75 {.irq = IRQEXT_PFL, .name = "PFL", .desc = "[EXT] Pseudo Page Fault"}, 76 {.irq = IRQEXT_DSD, .name = "DSD", .desc = "[EXT] DASD Diag"}, 77 {.irq = IRQEXT_VRT, .name = "VRT", .desc = "[EXT] Virtio"}, 78 {.irq = IRQEXT_SCP, .name = "SCP", .desc = "[EXT] Service Call"}, 79 {.irq = IRQEXT_IUC, .name = "IUC", .desc = "[EXT] IUCV"}, 80 {.irq = IRQEXT_CMS, .name = "CMS", .desc = "[EXT] CPU-Measurement: Sampling"}, 81 {.irq = IRQEXT_CMC, .name = "CMC", .desc = "[EXT] CPU-Measurement: Counter"}, 82 {.irq = IRQEXT_FTP, .name = "FTP", .desc = "[EXT] HMC FTP Service"}, 83 {.irq = IRQEXT_WTI, .name = "WTI", .desc = "[EXT] Warning Track"}, 84 {.irq = IRQIO_CIO, .name = "CIO", .desc = "[I/O] Common I/O Layer Interrupt"}, 85 {.irq = IRQIO_DAS, .name = "DAS", .desc = "[I/O] DASD"}, 86 {.irq = IRQIO_C15, .name = "C15", .desc = "[I/O] 3215"}, 87 {.irq = IRQIO_C70, .name = "C70", .desc = "[I/O] 3270"}, 88 {.irq = IRQIO_TAP, .name = "TAP", .desc = "[I/O] Tape"}, 89 {.irq = IRQIO_VMR, .name = "VMR", .desc = "[I/O] Unit Record Devices"}, 90 {.irq = IRQIO_CTC, .name = "CTC", .desc = "[I/O] CTC"}, 91 {.irq = IRQIO_ADM, .name = "ADM", .desc = "[I/O] EADM Subchannel"}, 92 {.irq = IRQIO_CSC, .name = "CSC", .desc = "[I/O] CHSC Subchannel"}, 93 {.irq = IRQIO_VIR, .name = "VIR", .desc = "[I/O] Virtual I/O Devices"}, 94 {.irq = IRQIO_QAI, .name = "QAI", .desc = "[AIO] QDIO Adapter Interrupt"}, 95 {.irq = IRQIO_APB, .name = "APB", .desc = "[AIO] AP Bus"}, 96 {.irq = IRQIO_PCF, .name = "PCF", .desc = "[AIO] PCI Floating Interrupt"}, 97 {.irq = IRQIO_PCD, .name = "PCD", .desc = "[AIO] PCI Directed Interrupt"}, 98 {.irq = IRQIO_MSI, .name = "MSI", .desc = "[AIO] MSI Interrupt"}, 99 {.irq = IRQIO_VAI, .name = "VAI", .desc = "[AIO] Virtual I/O Devices AI"}, 100 {.irq = IRQIO_GAL, .name = "GAL", .desc = "[AIO] GIB Alert"}, 101 {.irq = NMI_NMI, .name = "NMI", .desc = "[NMI] Machine Check"}, 102 {.irq = CPU_RST, .name = "RST", .desc = "[CPU] CPU Restart"}, 103 }; 104 105 static void do_IRQ(struct pt_regs *regs, int irq) 106 { 107 if (tod_after_eq(get_lowcore()->int_clock, 108 get_lowcore()->clock_comparator)) 109 /* Serve timer interrupts first. */ 110 clock_comparator_work(); 111 generic_handle_irq(irq); 112 } 113 114 static int on_async_stack(void) 115 { 116 unsigned long frame = current_frame_address(); 117 118 return ((get_lowcore()->async_stack ^ frame) & ~(THREAD_SIZE - 1)) == 0; 119 } 120 121 static void do_irq_async(struct pt_regs *regs, int irq) 122 { 123 if (on_async_stack()) { 124 do_IRQ(regs, irq); 125 } else { 126 call_on_stack(2, get_lowcore()->async_stack, void, do_IRQ, 127 struct pt_regs *, regs, int, irq); 128 } 129 } 130 131 static int irq_pending(struct pt_regs *regs) 132 { 133 int cc; 134 135 asm volatile( 136 " tpi 0\n" 137 CC_IPM(cc) 138 : CC_OUT(cc, cc) 139 : 140 : CC_CLOBBER); 141 return CC_TRANSFORM(cc); 142 } 143 144 void noinstr do_io_irq(struct pt_regs *regs) 145 { 146 bool from_idle, percpu_needs_fixup; 147 struct pt_regs *old_regs; 148 irqentry_state_t state; 149 150 percpu_entry(regs); 151 state = irqentry_enter(regs); 152 old_regs = set_irq_regs(regs); 153 from_idle = test_and_clear_cpu_flag(CIF_ENABLED_WAIT); 154 if (from_idle) 155 update_timer_idle(); 156 157 irq_enter_rcu(); 158 159 if (user_mode(regs)) { 160 update_timer_sys(); 161 if (cpu_has_bear()) 162 current->thread.last_break = regs->last_break; 163 } 164 165 if (from_idle) 166 account_idle_time_irq(); 167 168 set_cpu_flag(CIF_NOHZ_DELAY); 169 do { 170 regs->tpi_info = get_lowcore()->tpi_info; 171 if (get_lowcore()->tpi_info.adapter_IO) 172 do_irq_async(regs, THIN_INTERRUPT); 173 else 174 do_irq_async(regs, IO_INTERRUPT); 175 } while (machine_is_lpar() && irq_pending(regs)); 176 177 percpu_needs_fixup = percpu_code_check(regs); 178 irq_exit_rcu(); 179 set_irq_regs(old_regs); 180 irqentry_exit(regs, state); 181 182 if (from_idle) 183 regs->psw.mask &= ~(PSW_MASK_EXT | PSW_MASK_IO | PSW_MASK_WAIT); 184 percpu_exit(regs, percpu_needs_fixup); 185 } 186 187 void noinstr do_ext_irq(struct pt_regs *regs) 188 { 189 bool from_idle, percpu_needs_fixup; 190 struct pt_regs *old_regs; 191 irqentry_state_t state; 192 193 percpu_entry(regs); 194 state = irqentry_enter(regs); 195 old_regs = set_irq_regs(regs); 196 from_idle = test_and_clear_cpu_flag(CIF_ENABLED_WAIT); 197 if (from_idle) 198 update_timer_idle(); 199 200 irq_enter_rcu(); 201 202 if (user_mode(regs)) { 203 update_timer_sys(); 204 if (cpu_has_bear()) 205 current->thread.last_break = regs->last_break; 206 } 207 208 regs->int_code = get_lowcore()->ext_int_code_addr; 209 regs->int_parm = get_lowcore()->ext_params; 210 regs->int_parm_long = get_lowcore()->ext_params2; 211 212 if (from_idle) 213 account_idle_time_irq(); 214 215 do_irq_async(regs, EXT_INTERRUPT); 216 217 percpu_needs_fixup = percpu_code_check(regs); 218 irq_exit_rcu(); 219 set_irq_regs(old_regs); 220 irqentry_exit(regs, state); 221 222 if (from_idle) 223 regs->psw.mask &= ~(PSW_MASK_EXT | PSW_MASK_IO | PSW_MASK_WAIT); 224 percpu_exit(regs, percpu_needs_fixup); 225 } 226 227 static void show_msi_interrupt(struct seq_file *p, int irq) 228 { 229 struct irq_desc *desc; 230 unsigned long flags; 231 int cpu; 232 233 rcu_read_lock(); 234 desc = irq_to_desc(irq); 235 if (!desc) 236 goto out; 237 238 raw_spin_lock_irqsave(&desc->lock, flags); 239 seq_printf(p, "%3d: ", irq); 240 for_each_online_cpu(cpu) 241 seq_printf(p, "%10u ", irq_desc_kstat_cpu(desc, cpu)); 242 243 if (desc->irq_data.chip) 244 seq_printf(p, " %8s", desc->irq_data.chip->name); 245 246 if (desc->action) 247 seq_printf(p, " %s", desc->action->name); 248 249 seq_putc(p, '\n'); 250 raw_spin_unlock_irqrestore(&desc->lock, flags); 251 out: 252 rcu_read_unlock(); 253 } 254 255 /* 256 * show_interrupts is needed by /proc/interrupts. 257 */ 258 int show_interrupts(struct seq_file *p, void *v) 259 { 260 int index = *(loff_t *) v; 261 int cpu, irq; 262 263 cpus_read_lock(); 264 if (index == 0) { 265 seq_puts(p, " "); 266 for_each_online_cpu(cpu) 267 seq_printf(p, "CPU%-8d", cpu); 268 seq_putc(p, '\n'); 269 } 270 if (index < NR_IRQS_BASE) { 271 seq_printf(p, "%s: ", irqclass_main_desc[index].name); 272 irq = irqclass_main_desc[index].irq; 273 for_each_online_cpu(cpu) 274 seq_printf(p, "%10u ", kstat_irqs_cpu(irq, cpu)); 275 seq_putc(p, '\n'); 276 goto out; 277 } 278 if (index < irq_get_nr_irqs()) { 279 show_msi_interrupt(p, index); 280 goto out; 281 } 282 for (index = 0; index < NR_ARCH_IRQS; index++) { 283 seq_printf(p, "%s: ", irqclass_sub_desc[index].name); 284 irq = irqclass_sub_desc[index].irq; 285 for_each_online_cpu(cpu) 286 seq_printf(p, "%10u ", 287 per_cpu(irq_stat, cpu).irqs[irq]); 288 if (irqclass_sub_desc[index].desc) 289 seq_printf(p, " %s", irqclass_sub_desc[index].desc); 290 seq_putc(p, '\n'); 291 } 292 out: 293 cpus_read_unlock(); 294 return 0; 295 } 296 297 unsigned int arch_dynirq_lower_bound(unsigned int from) 298 { 299 return from < NR_IRQS_BASE ? NR_IRQS_BASE : from; 300 } 301 302 /* 303 * ext_int_hash[index] is the list head for all external interrupts that hash 304 * to this index. 305 */ 306 static struct hlist_head ext_int_hash[32] ____cacheline_aligned; 307 308 struct ext_int_info { 309 ext_int_handler_t handler; 310 struct hlist_node entry; 311 struct rcu_head rcu; 312 u16 code; 313 }; 314 315 /* ext_int_hash_lock protects the handler lists for external interrupts */ 316 static DEFINE_SPINLOCK(ext_int_hash_lock); 317 318 static inline int ext_hash(u16 code) 319 { 320 BUILD_BUG_ON(!is_power_of_2(ARRAY_SIZE(ext_int_hash))); 321 322 return (code + (code >> 9)) & (ARRAY_SIZE(ext_int_hash) - 1); 323 } 324 325 int register_external_irq(u16 code, ext_int_handler_t handler) 326 { 327 struct ext_int_info *p; 328 unsigned long flags; 329 int index; 330 331 p = kmalloc_obj(*p, GFP_ATOMIC); 332 if (!p) 333 return -ENOMEM; 334 p->code = code; 335 p->handler = handler; 336 index = ext_hash(code); 337 338 spin_lock_irqsave(&ext_int_hash_lock, flags); 339 hlist_add_head_rcu(&p->entry, &ext_int_hash[index]); 340 spin_unlock_irqrestore(&ext_int_hash_lock, flags); 341 return 0; 342 } 343 EXPORT_SYMBOL(register_external_irq); 344 345 int unregister_external_irq(u16 code, ext_int_handler_t handler) 346 { 347 struct ext_int_info *p; 348 unsigned long flags; 349 int index = ext_hash(code); 350 351 spin_lock_irqsave(&ext_int_hash_lock, flags); 352 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) { 353 if (p->code == code && p->handler == handler) { 354 hlist_del_rcu(&p->entry); 355 kfree_rcu(p, rcu); 356 } 357 } 358 spin_unlock_irqrestore(&ext_int_hash_lock, flags); 359 return 0; 360 } 361 EXPORT_SYMBOL(unregister_external_irq); 362 363 static irqreturn_t do_ext_interrupt(int irq, void *dummy) 364 { 365 struct pt_regs *regs = get_irq_regs(); 366 struct ext_code ext_code; 367 struct ext_int_info *p; 368 int index; 369 370 ext_code.int_code = regs->int_code; 371 if (ext_code.code != EXT_IRQ_CLK_COMP) 372 set_cpu_flag(CIF_NOHZ_DELAY); 373 374 index = ext_hash(ext_code.code); 375 rcu_read_lock(); 376 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) { 377 if (unlikely(p->code != ext_code.code)) 378 continue; 379 p->handler(ext_code, regs->int_parm, regs->int_parm_long); 380 } 381 rcu_read_unlock(); 382 return IRQ_HANDLED; 383 } 384 385 static void __init init_ext_interrupts(void) 386 { 387 int idx; 388 389 for (idx = 0; idx < ARRAY_SIZE(ext_int_hash); idx++) 390 INIT_HLIST_HEAD(&ext_int_hash[idx]); 391 392 irq_set_chip_and_handler(EXT_INTERRUPT, 393 &dummy_irq_chip, handle_percpu_irq); 394 if (request_irq(EXT_INTERRUPT, do_ext_interrupt, 0, "EXT", NULL)) 395 panic("Failed to register EXT interrupt\n"); 396 } 397 398 void __init init_IRQ(void) 399 { 400 BUILD_BUG_ON(ARRAY_SIZE(irqclass_sub_desc) != NR_ARCH_IRQS); 401 init_cio_interrupts(); 402 init_airq_interrupts(); 403 init_ext_interrupts(); 404 } 405 406 static DEFINE_SPINLOCK(irq_subclass_lock); 407 static unsigned char irq_subclass_refcount[64]; 408 409 void irq_subclass_register(enum irq_subclass subclass) 410 { 411 spin_lock(&irq_subclass_lock); 412 if (!irq_subclass_refcount[subclass]) 413 system_ctl_set_bit(0, subclass); 414 irq_subclass_refcount[subclass]++; 415 spin_unlock(&irq_subclass_lock); 416 } 417 EXPORT_SYMBOL(irq_subclass_register); 418 419 void irq_subclass_unregister(enum irq_subclass subclass) 420 { 421 spin_lock(&irq_subclass_lock); 422 irq_subclass_refcount[subclass]--; 423 if (!irq_subclass_refcount[subclass]) 424 system_ctl_clear_bit(0, subclass); 425 spin_unlock(&irq_subclass_lock); 426 } 427 EXPORT_SYMBOL(irq_subclass_unregister); 428