1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for STMicroelectronics STM32F7 I2C controller 4 * 5 * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc 6 * reference manual. 7 * Please see below a link to the documentation: 8 * http://www.st.com/resource/en/reference_manual/dm00124865.pdf 9 * 10 * Copyright (C) M'boumba Cedric Madianga 2017 11 * Copyright (C) STMicroelectronics 2017 12 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com> 13 * 14 * This driver is based on i2c-stm32f4.c 15 * 16 */ 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/err.h> 20 #include <linux/i2c.h> 21 #include <linux/i2c-smbus.h> 22 #include <linux/interrupt.h> 23 #include <linux/io.h> 24 #include <linux/iopoll.h> 25 #include <linux/mfd/syscon.h> 26 #include <linux/module.h> 27 #include <linux/of.h> 28 #include <linux/of_address.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/pinctrl/consumer.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/pm_wakeirq.h> 34 #include <linux/regmap.h> 35 #include <linux/reset.h> 36 #include <linux/slab.h> 37 #include <linux/string_choices.h> 38 39 #include "i2c-stm32.h" 40 41 /* STM32F7 I2C registers */ 42 #define STM32F7_I2C_CR1 0x00 43 #define STM32F7_I2C_CR2 0x04 44 #define STM32F7_I2C_OAR1 0x08 45 #define STM32F7_I2C_OAR2 0x0C 46 #define STM32F7_I2C_PECR 0x20 47 #define STM32F7_I2C_TIMINGR 0x10 48 #define STM32F7_I2C_ISR 0x18 49 #define STM32F7_I2C_ICR 0x1C 50 #define STM32F7_I2C_RXDR 0x24 51 #define STM32F7_I2C_TXDR 0x28 52 53 /* STM32F7 I2C control 1 */ 54 #define STM32_I2C_CR1_FMP BIT(24) 55 #define STM32F7_I2C_CR1_PECEN BIT(23) 56 #define STM32F7_I2C_CR1_ALERTEN BIT(22) 57 #define STM32F7_I2C_CR1_SMBHEN BIT(20) 58 #define STM32F7_I2C_CR1_WUPEN BIT(18) 59 #define STM32F7_I2C_CR1_SBC BIT(16) 60 #define STM32F7_I2C_CR1_RXDMAEN BIT(15) 61 #define STM32F7_I2C_CR1_TXDMAEN BIT(14) 62 #define STM32F7_I2C_CR1_ANFOFF BIT(12) 63 #define STM32F7_I2C_CR1_DNF_MASK GENMASK(11, 8) 64 #define STM32F7_I2C_CR1_DNF(n) (((n) & 0xf) << 8) 65 #define STM32F7_I2C_CR1_ERRIE BIT(7) 66 #define STM32F7_I2C_CR1_TCIE BIT(6) 67 #define STM32F7_I2C_CR1_STOPIE BIT(5) 68 #define STM32F7_I2C_CR1_NACKIE BIT(4) 69 #define STM32F7_I2C_CR1_ADDRIE BIT(3) 70 #define STM32F7_I2C_CR1_RXIE BIT(2) 71 #define STM32F7_I2C_CR1_TXIE BIT(1) 72 #define STM32F7_I2C_CR1_PE BIT(0) 73 #define STM32F7_I2C_ALL_IRQ_MASK (STM32F7_I2C_CR1_ERRIE \ 74 | STM32F7_I2C_CR1_TCIE \ 75 | STM32F7_I2C_CR1_STOPIE \ 76 | STM32F7_I2C_CR1_NACKIE \ 77 | STM32F7_I2C_CR1_RXIE \ 78 | STM32F7_I2C_CR1_TXIE) 79 #define STM32F7_I2C_XFER_IRQ_MASK (STM32F7_I2C_CR1_TCIE \ 80 | STM32F7_I2C_CR1_STOPIE \ 81 | STM32F7_I2C_CR1_NACKIE \ 82 | STM32F7_I2C_CR1_RXIE \ 83 | STM32F7_I2C_CR1_TXIE) 84 85 /* STM32F7 I2C control 2 */ 86 #define STM32F7_I2C_CR2_PECBYTE BIT(26) 87 #define STM32F7_I2C_CR2_RELOAD BIT(24) 88 #define STM32F7_I2C_CR2_NBYTES_MASK GENMASK(23, 16) 89 #define STM32F7_I2C_CR2_NBYTES(n) (((n) & 0xff) << 16) 90 #define STM32F7_I2C_CR2_NACK BIT(15) 91 #define STM32F7_I2C_CR2_STOP BIT(14) 92 #define STM32F7_I2C_CR2_START BIT(13) 93 #define STM32F7_I2C_CR2_HEAD10R BIT(12) 94 #define STM32F7_I2C_CR2_ADD10 BIT(11) 95 #define STM32F7_I2C_CR2_RD_WRN BIT(10) 96 #define STM32F7_I2C_CR2_SADD10_MASK GENMASK(9, 0) 97 #define STM32F7_I2C_CR2_SADD10(n) (((n) & \ 98 STM32F7_I2C_CR2_SADD10_MASK)) 99 #define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1) 100 #define STM32F7_I2C_CR2_SADD7(n) (((n) & 0x7f) << 1) 101 102 /* STM32F7 I2C Own Address 1 */ 103 #define STM32F7_I2C_OAR1_OA1EN BIT(15) 104 #define STM32F7_I2C_OAR1_OA1MODE BIT(10) 105 #define STM32F7_I2C_OAR1_OA1_10_MASK GENMASK(9, 0) 106 #define STM32F7_I2C_OAR1_OA1_10(n) (((n) & \ 107 STM32F7_I2C_OAR1_OA1_10_MASK)) 108 #define STM32F7_I2C_OAR1_OA1_7_MASK GENMASK(7, 1) 109 #define STM32F7_I2C_OAR1_OA1_7(n) (((n) & 0x7f) << 1) 110 #define STM32F7_I2C_OAR1_MASK (STM32F7_I2C_OAR1_OA1_7_MASK \ 111 | STM32F7_I2C_OAR1_OA1_10_MASK \ 112 | STM32F7_I2C_OAR1_OA1EN \ 113 | STM32F7_I2C_OAR1_OA1MODE) 114 115 /* STM32F7 I2C Own Address 2 */ 116 #define STM32F7_I2C_OAR2_OA2EN BIT(15) 117 #define STM32F7_I2C_OAR2_OA2MSK_MASK GENMASK(10, 8) 118 #define STM32F7_I2C_OAR2_OA2MSK(n) (((n) & 0x7) << 8) 119 #define STM32F7_I2C_OAR2_OA2_7_MASK GENMASK(7, 1) 120 #define STM32F7_I2C_OAR2_OA2_7(n) (((n) & 0x7f) << 1) 121 #define STM32F7_I2C_OAR2_MASK (STM32F7_I2C_OAR2_OA2MSK_MASK \ 122 | STM32F7_I2C_OAR2_OA2_7_MASK \ 123 | STM32F7_I2C_OAR2_OA2EN) 124 125 /* STM32F7 I2C Interrupt Status */ 126 #define STM32F7_I2C_ISR_ADDCODE_MASK GENMASK(23, 17) 127 #define STM32F7_I2C_ISR_ADDCODE_GET(n) \ 128 (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17) 129 #define STM32F7_I2C_ISR_DIR BIT(16) 130 #define STM32F7_I2C_ISR_BUSY BIT(15) 131 #define STM32F7_I2C_ISR_ALERT BIT(13) 132 #define STM32F7_I2C_ISR_PECERR BIT(11) 133 #define STM32F7_I2C_ISR_ARLO BIT(9) 134 #define STM32F7_I2C_ISR_BERR BIT(8) 135 #define STM32F7_I2C_ISR_TCR BIT(7) 136 #define STM32F7_I2C_ISR_TC BIT(6) 137 #define STM32F7_I2C_ISR_STOPF BIT(5) 138 #define STM32F7_I2C_ISR_NACKF BIT(4) 139 #define STM32F7_I2C_ISR_ADDR BIT(3) 140 #define STM32F7_I2C_ISR_RXNE BIT(2) 141 #define STM32F7_I2C_ISR_TXIS BIT(1) 142 #define STM32F7_I2C_ISR_TXE BIT(0) 143 144 /* STM32F7 I2C Interrupt Clear */ 145 #define STM32F7_I2C_ICR_ALERTCF BIT(13) 146 #define STM32F7_I2C_ICR_PECCF BIT(11) 147 #define STM32F7_I2C_ICR_ARLOCF BIT(9) 148 #define STM32F7_I2C_ICR_BERRCF BIT(8) 149 #define STM32F7_I2C_ICR_STOPCF BIT(5) 150 #define STM32F7_I2C_ICR_NACKCF BIT(4) 151 #define STM32F7_I2C_ICR_ADDRCF BIT(3) 152 153 /* STM32F7 I2C Timing */ 154 #define STM32F7_I2C_TIMINGR_PRESC(n) (((n) & 0xf) << 28) 155 #define STM32F7_I2C_TIMINGR_SCLDEL(n) (((n) & 0xf) << 20) 156 #define STM32F7_I2C_TIMINGR_SDADEL(n) (((n) & 0xf) << 16) 157 #define STM32F7_I2C_TIMINGR_SCLH(n) (((n) & 0xff) << 8) 158 #define STM32F7_I2C_TIMINGR_SCLL(n) ((n) & 0xff) 159 160 #define STM32F7_I2C_MAX_LEN 0xff 161 #define STM32F7_I2C_DMA_LEN_MIN 0x16 162 enum { 163 STM32F7_SLAVE_HOSTNOTIFY, 164 STM32F7_SLAVE_7_10_BITS_ADDR, 165 STM32F7_SLAVE_7_BITS_ADDR, 166 STM32F7_I2C_MAX_SLAVE 167 }; 168 169 #define STM32F7_I2C_DNF_DEFAULT 0 170 #define STM32F7_I2C_DNF_MAX 15 171 172 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */ 173 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */ 174 175 #define STM32F7_I2C_RISE_TIME_DEFAULT 25 /* ns */ 176 #define STM32F7_I2C_FALL_TIME_DEFAULT 10 /* ns */ 177 178 #define STM32F7_PRESC_MAX BIT(4) 179 #define STM32F7_SCLDEL_MAX BIT(4) 180 #define STM32F7_SDADEL_MAX BIT(4) 181 #define STM32F7_SCLH_MAX BIT(8) 182 #define STM32F7_SCLL_MAX BIT(8) 183 184 #define STM32F7_AUTOSUSPEND_DELAY (HZ / 100) 185 186 /** 187 * struct stm32f7_i2c_regs - i2c f7 registers backup 188 * @cr1: Control register 1 189 * @cr2: Control register 2 190 * @oar1: Own address 1 register 191 * @oar2: Own address 2 register 192 * @tmgr: Timing register 193 */ 194 struct stm32f7_i2c_regs { 195 u32 cr1; 196 u32 cr2; 197 u32 oar1; 198 u32 oar2; 199 u32 tmgr; 200 }; 201 202 /** 203 * struct stm32f7_i2c_spec - private i2c specification timing 204 * @rate: I2C bus speed (Hz) 205 * @fall_max: Max fall time of both SDA and SCL signals (ns) 206 * @rise_max: Max rise time of both SDA and SCL signals (ns) 207 * @hddat_min: Min data hold time (ns) 208 * @vddat_max: Max data valid time (ns) 209 * @sudat_min: Min data setup time (ns) 210 * @l_min: Min low period of the SCL clock (ns) 211 * @h_min: Min high period of the SCL clock (ns) 212 */ 213 struct stm32f7_i2c_spec { 214 u32 rate; 215 u32 fall_max; 216 u32 rise_max; 217 u32 hddat_min; 218 u32 vddat_max; 219 u32 sudat_min; 220 u32 l_min; 221 u32 h_min; 222 }; 223 224 /** 225 * struct stm32f7_i2c_setup - private I2C timing setup parameters 226 * @speed_freq: I2C speed frequency (Hz) 227 * @clock_src: I2C clock source frequency (Hz) 228 * @rise_time: Rise time (ns) 229 * @fall_time: Fall time (ns) 230 * @fmp_clr_offset: Fast Mode Plus clear register offset from set register 231 * @single_it_line: Only a single IT line is used for both events/errors 232 * @fmp_cr1_bit: Fast Mode Plus control is done via a bit in CR1 233 */ 234 struct stm32f7_i2c_setup { 235 u32 speed_freq; 236 u32 clock_src; 237 u32 rise_time; 238 u32 fall_time; 239 u32 fmp_clr_offset; 240 bool single_it_line; 241 bool fmp_cr1_bit; 242 }; 243 244 /** 245 * struct stm32f7_i2c_timings - private I2C output parameters 246 * @node: List entry 247 * @presc: Prescaler value 248 * @scldel: Data setup time 249 * @sdadel: Data hold time 250 * @sclh: SCL high period (master mode) 251 * @scll: SCL low period (master mode) 252 */ 253 struct stm32f7_i2c_timings { 254 struct list_head node; 255 u8 presc; 256 u8 scldel; 257 u8 sdadel; 258 u8 sclh; 259 u8 scll; 260 }; 261 262 /** 263 * struct stm32f7_i2c_msg - client specific data 264 * @addr: 8-bit or 10-bit slave addr, including r/w bit 265 * @count: number of bytes to be transferred 266 * @buf: data buffer 267 * @result: result of the transfer 268 * @stop: last I2C msg to be sent, i.e. STOP to be generated 269 * @smbus: boolean to know if the I2C IP is used in SMBus mode 270 * @size: type of SMBus protocol 271 * @read_write: direction of SMBus protocol 272 * SMBus block read and SMBus block write - block read process call protocols 273 * @smbus_buf: buffer to be used for SMBus protocol transfer. It will 274 * contain a maximum of 32 bytes of data + byte command + byte count + PEC 275 * This buffer has to be 32-bit aligned to be compliant with memory address 276 * register in DMA mode. 277 */ 278 struct stm32f7_i2c_msg { 279 u16 addr; 280 u32 count; 281 u8 *buf; 282 int result; 283 bool stop; 284 bool smbus; 285 int size; 286 char read_write; 287 u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4); 288 }; 289 290 /** 291 * struct stm32f7_i2c_alert - SMBus alert specific data 292 * @setup: platform data for the smbus_alert i2c client 293 * @ara: I2C slave device used to respond to the SMBus Alert with Alert 294 * Response Address 295 */ 296 struct stm32f7_i2c_alert { 297 struct i2c_smbus_alert_setup setup; 298 struct i2c_client *ara; 299 }; 300 301 /** 302 * struct stm32f7_i2c_dev - private data of the controller 303 * @adap: I2C adapter for this controller 304 * @dev: device for this controller 305 * @base: virtual memory area 306 * @complete: completion of I2C message 307 * @clk: hw i2c clock 308 * @bus_rate: I2C clock frequency of the controller 309 * @msg: Pointer to data to be written 310 * @msg_num: number of I2C messages to be executed 311 * @msg_id: message identifiant 312 * @f7_msg: customized i2c msg for driver usage 313 * @setup: I2C timing input setup 314 * @timing: I2C computed timings 315 * @slave: list of slave devices registered on the I2C bus 316 * @slave_running: slave device currently used 317 * @backup_regs: backup of i2c controller registers (for suspend/resume) 318 * @slave_dir: transfer direction for the current slave device 319 * @master_mode: boolean to know in which mode the I2C is running (master or 320 * slave) 321 * @dma: dma data 322 * @use_dma: boolean to know if dma is used in the current transfer 323 * @regmap: holds SYSCFG phandle for Fast Mode Plus bits 324 * @fmp_sreg: register address for setting Fast Mode Plus bits 325 * @fmp_creg: register address for clearing Fast Mode Plus bits 326 * @fmp_mask: mask for Fast Mode Plus bits in set register 327 * @wakeup_src: boolean to know if the device is a wakeup source 328 * @smbus_mode: states that the controller is configured in SMBus mode 329 * @host_notify_client: SMBus host-notify client 330 * @analog_filter: boolean to indicate enabling of the analog filter 331 * @dnf_dt: value of digital filter requested via dt 332 * @dnf: value of digital filter to apply 333 * @alert: SMBus alert specific data 334 * @atomic: boolean indicating that current transfer is atomic 335 */ 336 struct stm32f7_i2c_dev { 337 struct i2c_adapter adap; 338 struct device *dev; 339 void __iomem *base; 340 struct completion complete; 341 struct clk *clk; 342 unsigned int bus_rate; 343 struct i2c_msg *msg; 344 unsigned int msg_num; 345 unsigned int msg_id; 346 struct stm32f7_i2c_msg f7_msg; 347 struct stm32f7_i2c_setup setup; 348 struct stm32f7_i2c_timings timing; 349 struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE]; 350 struct i2c_client *slave_running; 351 struct stm32f7_i2c_regs backup_regs; 352 u32 slave_dir; 353 bool master_mode; 354 struct stm32_i2c_dma *dma; 355 bool use_dma; 356 struct regmap *regmap; 357 u32 fmp_sreg; 358 u32 fmp_creg; 359 u32 fmp_mask; 360 bool wakeup_src; 361 bool smbus_mode; 362 struct i2c_client *host_notify_client; 363 bool analog_filter; 364 u32 dnf_dt; 365 u32 dnf; 366 struct stm32f7_i2c_alert *alert; 367 bool atomic; 368 }; 369 370 /* 371 * All these values are coming from I2C Specification, Version 6.0, 4th of 372 * April 2014. 373 * 374 * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast, 375 * and Fast-mode Plus I2C-bus devices 376 */ 377 static struct stm32f7_i2c_spec stm32f7_i2c_specs[] = { 378 { 379 .rate = I2C_MAX_STANDARD_MODE_FREQ, 380 .fall_max = 300, 381 .rise_max = 1000, 382 .hddat_min = 0, 383 .vddat_max = 3450, 384 .sudat_min = 250, 385 .l_min = 4700, 386 .h_min = 4000, 387 }, 388 { 389 .rate = I2C_MAX_FAST_MODE_FREQ, 390 .fall_max = 300, 391 .rise_max = 300, 392 .hddat_min = 0, 393 .vddat_max = 900, 394 .sudat_min = 100, 395 .l_min = 1300, 396 .h_min = 600, 397 }, 398 { 399 .rate = I2C_MAX_FAST_MODE_PLUS_FREQ, 400 .fall_max = 100, 401 .rise_max = 120, 402 .hddat_min = 0, 403 .vddat_max = 450, 404 .sudat_min = 50, 405 .l_min = 500, 406 .h_min = 260, 407 }, 408 }; 409 410 static const struct stm32f7_i2c_setup stm32f7_setup = { 411 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT, 412 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT, 413 }; 414 415 static const struct stm32f7_i2c_setup stm32mp15_setup = { 416 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT, 417 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT, 418 .fmp_clr_offset = 0x40, 419 }; 420 421 static const struct stm32f7_i2c_setup stm32mp13_setup = { 422 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT, 423 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT, 424 .fmp_clr_offset = 0x4, 425 }; 426 427 static const struct stm32f7_i2c_setup stm32mp25_setup = { 428 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT, 429 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT, 430 .single_it_line = true, 431 .fmp_cr1_bit = true, 432 }; 433 434 static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask) 435 { 436 writel_relaxed(readl_relaxed(reg) | mask, reg); 437 } 438 439 static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask) 440 { 441 writel_relaxed(readl_relaxed(reg) & ~mask, reg); 442 } 443 444 static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask) 445 { 446 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask); 447 } 448 449 static struct stm32f7_i2c_spec *stm32f7_get_specs(u32 rate) 450 { 451 int i; 452 453 for (i = 0; i < ARRAY_SIZE(stm32f7_i2c_specs); i++) 454 if (rate <= stm32f7_i2c_specs[i].rate) 455 return &stm32f7_i2c_specs[i]; 456 457 return ERR_PTR(-EINVAL); 458 } 459 460 #define RATE_MIN(rate) ((rate) * 8 / 10) 461 static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev, 462 struct stm32f7_i2c_setup *setup, 463 struct stm32f7_i2c_timings *output) 464 { 465 struct stm32f7_i2c_spec *specs; 466 u32 p_prev = STM32F7_PRESC_MAX; 467 u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC, 468 setup->clock_src); 469 u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC, 470 setup->speed_freq); 471 u32 clk_error_prev = i2cbus; 472 u32 tsync; 473 u32 af_delay_min, af_delay_max; 474 u32 dnf_delay; 475 u32 clk_min, clk_max; 476 int sdadel_min, sdadel_max; 477 int scldel_min; 478 struct stm32f7_i2c_timings *v, *_v, *s; 479 struct list_head solutions; 480 u16 p, l, a, h; 481 int ret = 0; 482 483 specs = stm32f7_get_specs(setup->speed_freq); 484 if (specs == ERR_PTR(-EINVAL)) 485 return dev_err_probe(i2c_dev->dev, -EINVAL, "speed out of bound {%d}\n", 486 setup->speed_freq); 487 488 if ((setup->rise_time > specs->rise_max) || 489 (setup->fall_time > specs->fall_max)) 490 return dev_err_probe(i2c_dev->dev, -EINVAL, 491 "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n", 492 setup->rise_time, specs->rise_max, 493 setup->fall_time, specs->fall_max); 494 495 i2c_dev->dnf = DIV_ROUND_CLOSEST(i2c_dev->dnf_dt, i2cclk); 496 if (i2c_dev->dnf > STM32F7_I2C_DNF_MAX) 497 return dev_err_probe(i2c_dev->dev, -EINVAL, 498 "DNF out of bound %d/%d\n", i2c_dev->dnf * i2cclk, 499 STM32F7_I2C_DNF_MAX * i2cclk); 500 501 /* Analog and Digital Filters */ 502 af_delay_min = 503 (i2c_dev->analog_filter ? 504 STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0); 505 af_delay_max = 506 (i2c_dev->analog_filter ? 507 STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0); 508 dnf_delay = i2c_dev->dnf * i2cclk; 509 510 sdadel_min = specs->hddat_min + setup->fall_time - 511 af_delay_min - (i2c_dev->dnf + 3) * i2cclk; 512 513 sdadel_max = specs->vddat_max - setup->rise_time - 514 af_delay_max - (i2c_dev->dnf + 4) * i2cclk; 515 516 scldel_min = setup->rise_time + specs->sudat_min; 517 518 if (sdadel_min < 0) 519 sdadel_min = 0; 520 if (sdadel_max < 0) 521 sdadel_max = 0; 522 523 dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", 524 sdadel_min, sdadel_max, scldel_min); 525 526 INIT_LIST_HEAD(&solutions); 527 /* Compute possible values for PRESC, SCLDEL and SDADEL */ 528 for (p = 0; p < STM32F7_PRESC_MAX; p++) { 529 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) { 530 u32 scldel = (l + 1) * (p + 1) * i2cclk; 531 532 if (scldel < scldel_min) 533 continue; 534 535 for (a = 0; a < STM32F7_SDADEL_MAX; a++) { 536 u32 sdadel = (a * (p + 1) + 1) * i2cclk; 537 538 if (((sdadel >= sdadel_min) && 539 (sdadel <= sdadel_max)) && 540 (p != p_prev)) { 541 v = kmalloc_obj(*v); 542 if (!v) { 543 ret = -ENOMEM; 544 goto exit; 545 } 546 547 v->presc = p; 548 v->scldel = l; 549 v->sdadel = a; 550 p_prev = p; 551 552 list_add_tail(&v->node, 553 &solutions); 554 break; 555 } 556 } 557 558 if (p_prev == p) 559 break; 560 } 561 } 562 563 if (list_empty(&solutions)) { 564 ret = dev_err_probe(i2c_dev->dev, -EPERM, "no Prescaler solution\n"); 565 goto exit; 566 } 567 568 tsync = af_delay_min + dnf_delay + (2 * i2cclk); 569 s = NULL; 570 clk_max = NSEC_PER_SEC / RATE_MIN(setup->speed_freq); 571 clk_min = NSEC_PER_SEC / setup->speed_freq; 572 573 /* 574 * Among Prescaler possibilities discovered above figures out SCL Low 575 * and High Period. Provided: 576 * - SCL Low Period has to be higher than SCL Clock Low Period 577 * defined by I2C Specification. I2C Clock has to be lower than 578 * (SCL Low Period - Analog/Digital filters) / 4. 579 * - SCL High Period has to be lower than SCL Clock High Period 580 * defined by I2C Specification 581 * - I2C Clock has to be lower than SCL High Period 582 */ 583 list_for_each_entry(v, &solutions, node) { 584 u32 prescaler = (v->presc + 1) * i2cclk; 585 586 for (l = 0; l < STM32F7_SCLL_MAX; l++) { 587 u32 tscl_l = (l + 1) * prescaler + tsync; 588 589 if ((tscl_l < specs->l_min) || 590 (i2cclk >= 591 ((tscl_l - af_delay_min - dnf_delay) / 4))) { 592 continue; 593 } 594 595 for (h = 0; h < STM32F7_SCLH_MAX; h++) { 596 u32 tscl_h = (h + 1) * prescaler + tsync; 597 u32 tscl = tscl_l + tscl_h + 598 setup->rise_time + setup->fall_time; 599 600 if ((tscl >= clk_min) && (tscl <= clk_max) && 601 (tscl_h >= specs->h_min) && 602 (i2cclk < tscl_h)) { 603 int clk_error = tscl - i2cbus; 604 605 if (clk_error < 0) 606 clk_error = -clk_error; 607 608 if (clk_error < clk_error_prev) { 609 clk_error_prev = clk_error; 610 v->scll = l; 611 v->sclh = h; 612 s = v; 613 } 614 } 615 } 616 } 617 } 618 619 if (!s) { 620 ret = dev_err_probe(i2c_dev->dev, -EPERM, "no solution at all\n"); 621 goto exit; 622 } 623 624 output->presc = s->presc; 625 output->scldel = s->scldel; 626 output->sdadel = s->sdadel; 627 output->scll = s->scll; 628 output->sclh = s->sclh; 629 630 dev_dbg(i2c_dev->dev, 631 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n", 632 output->presc, 633 output->scldel, output->sdadel, 634 output->scll, output->sclh); 635 636 exit: 637 /* Release list and memory */ 638 list_for_each_entry_safe(v, _v, &solutions, node) { 639 list_del(&v->node); 640 kfree(v); 641 } 642 643 return ret; 644 } 645 646 static u32 stm32f7_get_lower_rate(u32 rate) 647 { 648 int i = ARRAY_SIZE(stm32f7_i2c_specs); 649 650 while (--i) 651 if (stm32f7_i2c_specs[i].rate < rate) 652 break; 653 654 return stm32f7_i2c_specs[i].rate; 655 } 656 657 static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev, 658 struct stm32f7_i2c_setup *setup) 659 { 660 struct i2c_timings timings, *t = &timings; 661 int ret = 0; 662 663 t->bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ; 664 t->scl_rise_ns = i2c_dev->setup.rise_time; 665 t->scl_fall_ns = i2c_dev->setup.fall_time; 666 667 i2c_parse_fw_timings(i2c_dev->dev, t, false); 668 669 if (t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) 670 return dev_err_probe(i2c_dev->dev, -EINVAL, "Invalid bus speed (%i>%i)\n", 671 t->bus_freq_hz, I2C_MAX_FAST_MODE_PLUS_FREQ); 672 673 setup->speed_freq = t->bus_freq_hz; 674 i2c_dev->setup.rise_time = t->scl_rise_ns; 675 i2c_dev->setup.fall_time = t->scl_fall_ns; 676 i2c_dev->dnf_dt = t->digital_filter_width_ns; 677 setup->clock_src = clk_get_rate(i2c_dev->clk); 678 679 if (!setup->clock_src) 680 return dev_err_probe(i2c_dev->dev, -EINVAL, "clock rate is 0\n"); 681 682 if (!of_property_read_bool(i2c_dev->dev->of_node, "i2c-digital-filter")) 683 i2c_dev->dnf_dt = STM32F7_I2C_DNF_DEFAULT; 684 685 i2c_dev->analog_filter = of_property_read_bool(i2c_dev->dev->of_node, 686 "i2c-analog-filter"); 687 688 do { 689 ret = stm32f7_i2c_compute_timing(i2c_dev, setup, 690 &i2c_dev->timing); 691 if (ret) { 692 dev_err_probe(i2c_dev->dev, ret, 693 "failed to compute I2C timings.\n"); 694 if (setup->speed_freq <= I2C_MAX_STANDARD_MODE_FREQ) 695 break; 696 setup->speed_freq = 697 stm32f7_get_lower_rate(setup->speed_freq); 698 dev_warn(i2c_dev->dev, 699 "downgrade I2C Speed Freq to (%i)\n", 700 setup->speed_freq); 701 } 702 } while (ret); 703 704 if (ret) 705 return dev_err_probe(i2c_dev->dev, ret, "Impossible to compute I2C timings.\n"); 706 707 dev_dbg(i2c_dev->dev, "I2C Speed(%i), Clk Source(%i)\n", 708 setup->speed_freq, setup->clock_src); 709 dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n", 710 setup->rise_time, setup->fall_time); 711 dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n", 712 str_on_off(i2c_dev->analog_filter), i2c_dev->dnf); 713 714 i2c_dev->bus_rate = setup->speed_freq; 715 716 return 0; 717 } 718 719 static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev) 720 { 721 void __iomem *base = i2c_dev->base; 722 u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN; 723 724 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); 725 } 726 727 static void stm32f7_i2c_dma_callback(void *arg) 728 { 729 struct stm32f7_i2c_dev *i2c_dev = arg; 730 struct stm32_i2c_dma *dma = i2c_dev->dma; 731 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 732 733 stm32f7_i2c_disable_dma_req(i2c_dev); 734 dmaengine_terminate_async(dma->chan_using); 735 dma_unmap_single(i2c_dev->dev, dma->dma_buf, dma->dma_len, 736 dma->dma_data_dir); 737 if (!f7_msg->smbus) 738 i2c_put_dma_safe_msg_buf(f7_msg->buf, i2c_dev->msg, true); 739 complete(&dma->dma_complete); 740 } 741 742 static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev) 743 { 744 struct stm32f7_i2c_timings *t = &i2c_dev->timing; 745 u32 timing = 0; 746 747 /* Timing settings */ 748 timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc); 749 timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel); 750 timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel); 751 timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh); 752 timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll); 753 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR); 754 755 /* Configure the Analog Filter */ 756 if (i2c_dev->analog_filter) 757 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 758 STM32F7_I2C_CR1_ANFOFF); 759 else 760 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 761 STM32F7_I2C_CR1_ANFOFF); 762 763 /* Program the Digital Filter */ 764 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 765 STM32F7_I2C_CR1_DNF_MASK); 766 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 767 STM32F7_I2C_CR1_DNF(i2c_dev->dnf)); 768 769 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 770 STM32F7_I2C_CR1_PE); 771 } 772 773 static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev) 774 { 775 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 776 void __iomem *base = i2c_dev->base; 777 778 if (f7_msg->count) { 779 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR); 780 f7_msg->count--; 781 } 782 } 783 784 static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev) 785 { 786 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 787 void __iomem *base = i2c_dev->base; 788 789 if (f7_msg->count) { 790 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR); 791 f7_msg->count--; 792 } else { 793 /* Flush RX buffer has no data is expected */ 794 readb_relaxed(base + STM32F7_I2C_RXDR); 795 } 796 } 797 798 static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev) 799 { 800 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 801 u32 cr2; 802 803 if (i2c_dev->use_dma) 804 f7_msg->count -= STM32F7_I2C_MAX_LEN; 805 806 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 807 808 cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK; 809 if (f7_msg->count > STM32F7_I2C_MAX_LEN) { 810 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN); 811 } else { 812 cr2 &= ~STM32F7_I2C_CR2_RELOAD; 813 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 814 } 815 816 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); 817 } 818 819 static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev) 820 { 821 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 822 u32 cr2; 823 u8 *val; 824 825 /* 826 * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first 827 * data received inform us how many data will follow. 828 */ 829 stm32f7_i2c_read_rx_data(i2c_dev); 830 831 /* 832 * Update NBYTES with the value read to continue the transfer 833 */ 834 val = f7_msg->buf - sizeof(u8); 835 f7_msg->count = *val; 836 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 837 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD); 838 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 839 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); 840 } 841 842 static void stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap) 843 { 844 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 845 846 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 847 STM32F7_I2C_CR1_PE); 848 849 stm32f7_i2c_hw_config(i2c_dev); 850 } 851 852 static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev) 853 { 854 u32 status; 855 int ret; 856 857 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR, 858 status, 859 !(status & STM32F7_I2C_ISR_BUSY), 860 10, 1000); 861 if (!ret) 862 return 0; 863 864 stm32f7_i2c_release_bus(&i2c_dev->adap); 865 866 return -EBUSY; 867 } 868 869 static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev, 870 struct i2c_msg *msg) 871 { 872 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 873 void __iomem *base = i2c_dev->base; 874 u8 *dma_buf; 875 u32 cr1, cr2; 876 int ret; 877 878 f7_msg->addr = msg->addr; 879 f7_msg->buf = msg->buf; 880 f7_msg->count = msg->len; 881 f7_msg->result = 0; 882 f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1); 883 884 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); 885 cr2 = readl_relaxed(base + STM32F7_I2C_CR2); 886 887 /* Set transfer direction */ 888 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 889 if (msg->flags & I2C_M_RD) 890 cr2 |= STM32F7_I2C_CR2_RD_WRN; 891 892 /* Set slave address */ 893 cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10); 894 if (msg->flags & I2C_M_TEN) { 895 cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK; 896 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr); 897 cr2 |= STM32F7_I2C_CR2_ADD10; 898 } else { 899 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK; 900 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr); 901 } 902 903 /* Set nb bytes to transfer and reload if needed */ 904 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD); 905 if (f7_msg->count > STM32F7_I2C_MAX_LEN) { 906 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN); 907 cr2 |= STM32F7_I2C_CR2_RELOAD; 908 } else { 909 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 910 } 911 912 /* Enable NACK, STOP, error and transfer complete interrupts */ 913 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE | 914 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE; 915 916 /* Clear DMA req and TX/RX interrupt */ 917 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE | 918 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN); 919 920 /* Configure DMA or enable RX/TX interrupt */ 921 i2c_dev->use_dma = false; 922 if (i2c_dev->dma && !i2c_dev->atomic) { 923 dma_buf = i2c_get_dma_safe_msg_buf(msg, STM32F7_I2C_DMA_LEN_MIN); 924 if (dma_buf) { 925 f7_msg->buf = dma_buf; 926 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, 927 msg->flags & I2C_M_RD, 928 f7_msg->count, f7_msg->buf, 929 stm32f7_i2c_dma_callback, 930 i2c_dev); 931 if (ret) { 932 dev_warn(i2c_dev->dev, "can't use DMA\n"); 933 i2c_put_dma_safe_msg_buf(f7_msg->buf, msg, false); 934 f7_msg->buf = msg->buf; 935 } else { 936 i2c_dev->use_dma = true; 937 } 938 } 939 } 940 941 if (!i2c_dev->use_dma) { 942 if (msg->flags & I2C_M_RD) 943 cr1 |= STM32F7_I2C_CR1_RXIE; 944 else 945 cr1 |= STM32F7_I2C_CR1_TXIE; 946 } else { 947 if (msg->flags & I2C_M_RD) 948 cr1 |= STM32F7_I2C_CR1_RXDMAEN; 949 else 950 cr1 |= STM32F7_I2C_CR1_TXDMAEN; 951 } 952 953 if (i2c_dev->atomic) 954 cr1 &= ~STM32F7_I2C_ALL_IRQ_MASK; /* Disable all interrupts */ 955 956 /* Configure Start/Repeated Start */ 957 cr2 |= STM32F7_I2C_CR2_START; 958 959 i2c_dev->master_mode = true; 960 961 /* Write configurations registers */ 962 writel_relaxed(cr1, base + STM32F7_I2C_CR1); 963 writel_relaxed(cr2, base + STM32F7_I2C_CR2); 964 } 965 966 static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev, 967 unsigned short flags, u8 command, 968 union i2c_smbus_data *data) 969 { 970 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 971 struct device *dev = i2c_dev->dev; 972 void __iomem *base = i2c_dev->base; 973 u32 cr1, cr2; 974 int i, ret; 975 976 f7_msg->result = 0; 977 reinit_completion(&i2c_dev->complete); 978 979 cr2 = readl_relaxed(base + STM32F7_I2C_CR2); 980 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); 981 982 /* Set transfer direction */ 983 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 984 if (f7_msg->read_write) 985 cr2 |= STM32F7_I2C_CR2_RD_WRN; 986 987 /* Set slave address */ 988 cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK); 989 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr); 990 991 f7_msg->smbus_buf[0] = command; 992 switch (f7_msg->size) { 993 case I2C_SMBUS_QUICK: 994 f7_msg->stop = true; 995 f7_msg->count = 0; 996 break; 997 case I2C_SMBUS_BYTE: 998 f7_msg->stop = true; 999 f7_msg->count = 1; 1000 break; 1001 case I2C_SMBUS_BYTE_DATA: 1002 if (f7_msg->read_write) { 1003 f7_msg->stop = false; 1004 f7_msg->count = 1; 1005 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 1006 } else { 1007 f7_msg->stop = true; 1008 f7_msg->count = 2; 1009 f7_msg->smbus_buf[1] = data->byte; 1010 } 1011 break; 1012 case I2C_SMBUS_WORD_DATA: 1013 if (f7_msg->read_write) { 1014 f7_msg->stop = false; 1015 f7_msg->count = 1; 1016 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 1017 } else { 1018 f7_msg->stop = true; 1019 f7_msg->count = 3; 1020 f7_msg->smbus_buf[1] = data->word & 0xff; 1021 f7_msg->smbus_buf[2] = data->word >> 8; 1022 } 1023 break; 1024 case I2C_SMBUS_BLOCK_DATA: 1025 if (f7_msg->read_write) { 1026 f7_msg->stop = false; 1027 f7_msg->count = 1; 1028 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 1029 } else { 1030 f7_msg->stop = true; 1031 if (data->block[0] > I2C_SMBUS_BLOCK_MAX || 1032 !data->block[0]) { 1033 dev_err(dev, "Invalid block write size %d\n", 1034 data->block[0]); 1035 return -EINVAL; 1036 } 1037 f7_msg->count = data->block[0] + 2; 1038 for (i = 1; i < f7_msg->count; i++) 1039 f7_msg->smbus_buf[i] = data->block[i - 1]; 1040 } 1041 break; 1042 case I2C_SMBUS_PROC_CALL: 1043 f7_msg->stop = false; 1044 f7_msg->count = 3; 1045 f7_msg->smbus_buf[1] = data->word & 0xff; 1046 f7_msg->smbus_buf[2] = data->word >> 8; 1047 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 1048 f7_msg->read_write = I2C_SMBUS_READ; 1049 break; 1050 case I2C_SMBUS_BLOCK_PROC_CALL: 1051 f7_msg->stop = false; 1052 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) { 1053 dev_err(dev, "Invalid block write size %d\n", 1054 data->block[0]); 1055 return -EINVAL; 1056 } 1057 f7_msg->count = data->block[0] + 2; 1058 for (i = 1; i < f7_msg->count; i++) 1059 f7_msg->smbus_buf[i] = data->block[i - 1]; 1060 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 1061 f7_msg->read_write = I2C_SMBUS_READ; 1062 break; 1063 case I2C_SMBUS_I2C_BLOCK_DATA: 1064 /* Rely on emulated i2c transfer (through master_xfer) */ 1065 return -EOPNOTSUPP; 1066 default: 1067 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size); 1068 return -EOPNOTSUPP; 1069 } 1070 1071 f7_msg->buf = f7_msg->smbus_buf; 1072 1073 /* Configure PEC */ 1074 if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) { 1075 cr1 |= STM32F7_I2C_CR1_PECEN; 1076 if (!f7_msg->read_write) { 1077 cr2 |= STM32F7_I2C_CR2_PECBYTE; 1078 f7_msg->count++; 1079 } 1080 } else { 1081 cr1 &= ~STM32F7_I2C_CR1_PECEN; 1082 cr2 &= ~STM32F7_I2C_CR2_PECBYTE; 1083 } 1084 1085 /* Set number of bytes to be transferred */ 1086 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD); 1087 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 1088 1089 /* Enable NACK, STOP, error and transfer complete interrupts */ 1090 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE | 1091 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE; 1092 1093 /* Clear DMA req and TX/RX interrupt */ 1094 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE | 1095 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN); 1096 1097 /* Configure DMA or enable RX/TX interrupt */ 1098 i2c_dev->use_dma = false; 1099 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) { 1100 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, 1101 cr2 & STM32F7_I2C_CR2_RD_WRN, 1102 f7_msg->count, f7_msg->buf, 1103 stm32f7_i2c_dma_callback, 1104 i2c_dev); 1105 if (!ret) 1106 i2c_dev->use_dma = true; 1107 else 1108 dev_warn(i2c_dev->dev, "can't use DMA\n"); 1109 } 1110 1111 if (!i2c_dev->use_dma) { 1112 if (cr2 & STM32F7_I2C_CR2_RD_WRN) 1113 cr1 |= STM32F7_I2C_CR1_RXIE; 1114 else 1115 cr1 |= STM32F7_I2C_CR1_TXIE; 1116 } else { 1117 if (cr2 & STM32F7_I2C_CR2_RD_WRN) 1118 cr1 |= STM32F7_I2C_CR1_RXDMAEN; 1119 else 1120 cr1 |= STM32F7_I2C_CR1_TXDMAEN; 1121 } 1122 1123 /* Set Start bit */ 1124 cr2 |= STM32F7_I2C_CR2_START; 1125 1126 i2c_dev->master_mode = true; 1127 1128 /* Write configurations registers */ 1129 writel_relaxed(cr1, base + STM32F7_I2C_CR1); 1130 writel_relaxed(cr2, base + STM32F7_I2C_CR2); 1131 1132 return 0; 1133 } 1134 1135 static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev) 1136 { 1137 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1138 void __iomem *base = i2c_dev->base; 1139 u32 cr1, cr2; 1140 int ret; 1141 1142 cr2 = readl_relaxed(base + STM32F7_I2C_CR2); 1143 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); 1144 1145 /* Set transfer direction */ 1146 cr2 |= STM32F7_I2C_CR2_RD_WRN; 1147 1148 switch (f7_msg->size) { 1149 case I2C_SMBUS_BYTE_DATA: 1150 f7_msg->count = 1; 1151 break; 1152 case I2C_SMBUS_WORD_DATA: 1153 case I2C_SMBUS_PROC_CALL: 1154 f7_msg->count = 2; 1155 break; 1156 case I2C_SMBUS_BLOCK_DATA: 1157 case I2C_SMBUS_BLOCK_PROC_CALL: 1158 f7_msg->count = 1; 1159 cr2 |= STM32F7_I2C_CR2_RELOAD; 1160 break; 1161 } 1162 1163 f7_msg->buf = f7_msg->smbus_buf; 1164 f7_msg->stop = true; 1165 1166 /* Add one byte for PEC if needed */ 1167 if (cr1 & STM32F7_I2C_CR1_PECEN) { 1168 cr2 |= STM32F7_I2C_CR2_PECBYTE; 1169 f7_msg->count++; 1170 } 1171 1172 /* Set number of bytes to be transferred */ 1173 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK); 1174 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 1175 1176 /* 1177 * Configure RX/TX interrupt: 1178 */ 1179 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE); 1180 cr1 |= STM32F7_I2C_CR1_RXIE; 1181 1182 /* 1183 * Configure DMA or enable RX/TX interrupt: 1184 * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use 1185 * dma as we don't know in advance how many data will be received 1186 */ 1187 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE | 1188 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN); 1189 1190 i2c_dev->use_dma = false; 1191 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN && 1192 f7_msg->size != I2C_SMBUS_BLOCK_DATA && 1193 f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) { 1194 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, 1195 cr2 & STM32F7_I2C_CR2_RD_WRN, 1196 f7_msg->count, f7_msg->buf, 1197 stm32f7_i2c_dma_callback, 1198 i2c_dev); 1199 1200 if (!ret) 1201 i2c_dev->use_dma = true; 1202 else 1203 dev_warn(i2c_dev->dev, "can't use DMA\n"); 1204 } 1205 1206 if (!i2c_dev->use_dma) 1207 cr1 |= STM32F7_I2C_CR1_RXIE; 1208 else 1209 cr1 |= STM32F7_I2C_CR1_RXDMAEN; 1210 1211 /* Configure Repeated Start */ 1212 cr2 |= STM32F7_I2C_CR2_START; 1213 1214 /* Write configurations registers */ 1215 writel_relaxed(cr1, base + STM32F7_I2C_CR1); 1216 writel_relaxed(cr2, base + STM32F7_I2C_CR2); 1217 } 1218 1219 static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev) 1220 { 1221 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1222 u8 count, internal_pec, received_pec; 1223 1224 internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR); 1225 1226 switch (f7_msg->size) { 1227 case I2C_SMBUS_BYTE: 1228 case I2C_SMBUS_BYTE_DATA: 1229 received_pec = f7_msg->smbus_buf[1]; 1230 break; 1231 case I2C_SMBUS_WORD_DATA: 1232 case I2C_SMBUS_PROC_CALL: 1233 received_pec = f7_msg->smbus_buf[2]; 1234 break; 1235 case I2C_SMBUS_BLOCK_DATA: 1236 case I2C_SMBUS_BLOCK_PROC_CALL: 1237 count = f7_msg->smbus_buf[0]; 1238 received_pec = f7_msg->smbus_buf[count]; 1239 break; 1240 default: 1241 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n"); 1242 return -EINVAL; 1243 } 1244 1245 if (internal_pec != received_pec) { 1246 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n", 1247 internal_pec, received_pec); 1248 return -EBADMSG; 1249 } 1250 1251 return 0; 1252 } 1253 1254 static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode) 1255 { 1256 u32 addr; 1257 1258 if (!slave) 1259 return false; 1260 1261 if (slave->flags & I2C_CLIENT_TEN) { 1262 /* 1263 * For 10-bit addr, addcode = 11110XY with 1264 * X = Bit 9 of slave address 1265 * Y = Bit 8 of slave address 1266 */ 1267 addr = slave->addr >> 8; 1268 addr |= 0x78; 1269 if (addr == addcode) 1270 return true; 1271 } else { 1272 addr = slave->addr & 0x7f; 1273 if (addr == addcode) 1274 return true; 1275 } 1276 1277 return false; 1278 } 1279 1280 static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev) 1281 { 1282 struct i2c_client *slave = i2c_dev->slave_running; 1283 void __iomem *base = i2c_dev->base; 1284 u32 mask; 1285 u8 value = 0; 1286 1287 if (i2c_dev->slave_dir) { 1288 /* Notify i2c slave that new read transfer is starting */ 1289 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value); 1290 1291 /* 1292 * Disable slave TX config in case of I2C combined message 1293 * (I2C Write followed by I2C Read) 1294 */ 1295 mask = STM32F7_I2C_CR2_RELOAD; 1296 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask); 1297 mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE | 1298 STM32F7_I2C_CR1_TCIE; 1299 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); 1300 1301 /* Enable TX empty, STOP, NACK interrupts */ 1302 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE | 1303 STM32F7_I2C_CR1_TXIE; 1304 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1305 1306 /* Write 1st data byte */ 1307 writel_relaxed(value, base + STM32F7_I2C_TXDR); 1308 } else { 1309 /* Notify i2c slave that new write transfer is starting */ 1310 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value); 1311 1312 /* Set reload mode to be able to ACK/NACK each received byte */ 1313 mask = STM32F7_I2C_CR2_RELOAD; 1314 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); 1315 1316 /* 1317 * Set STOP, NACK, RX empty and transfer complete interrupts.* 1318 * Set Slave Byte Control to be able to ACK/NACK each data 1319 * byte received 1320 */ 1321 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE | 1322 STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE | 1323 STM32F7_I2C_CR1_TCIE; 1324 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1325 } 1326 } 1327 1328 static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev) 1329 { 1330 void __iomem *base = i2c_dev->base; 1331 u32 isr, addcode, dir, mask; 1332 int i; 1333 1334 isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1335 addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr); 1336 dir = isr & STM32F7_I2C_ISR_DIR; 1337 1338 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1339 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) { 1340 i2c_dev->slave_running = i2c_dev->slave[i]; 1341 i2c_dev->slave_dir = dir; 1342 1343 /* Start I2C slave processing */ 1344 stm32f7_i2c_slave_start(i2c_dev); 1345 1346 /* Clear ADDR flag */ 1347 mask = STM32F7_I2C_ICR_ADDRCF; 1348 writel_relaxed(mask, base + STM32F7_I2C_ICR); 1349 break; 1350 } 1351 } 1352 } 1353 1354 static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev, 1355 struct i2c_client *slave, int *id) 1356 { 1357 int i; 1358 1359 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1360 if (i2c_dev->slave[i] == slave) { 1361 *id = i; 1362 return 0; 1363 } 1364 } 1365 1366 dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr); 1367 1368 return -ENODEV; 1369 } 1370 1371 static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev, 1372 struct i2c_client *slave, int *id) 1373 { 1374 struct device *dev = i2c_dev->dev; 1375 int i; 1376 1377 /* 1378 * slave[STM32F7_SLAVE_HOSTNOTIFY] support only SMBus Host address (0x8) 1379 * slave[STM32F7_SLAVE_7_10_BITS_ADDR] supports 7-bit and 10-bit slave address 1380 * slave[STM32F7_SLAVE_7_BITS_ADDR] supports 7-bit slave address only 1381 */ 1382 if (i2c_dev->smbus_mode && (slave->addr == 0x08)) { 1383 if (i2c_dev->slave[STM32F7_SLAVE_HOSTNOTIFY]) 1384 goto fail; 1385 *id = STM32F7_SLAVE_HOSTNOTIFY; 1386 return 0; 1387 } 1388 1389 for (i = STM32F7_I2C_MAX_SLAVE - 1; i > STM32F7_SLAVE_HOSTNOTIFY; i--) { 1390 if ((i == STM32F7_SLAVE_7_BITS_ADDR) && 1391 (slave->flags & I2C_CLIENT_TEN)) 1392 continue; 1393 if (!i2c_dev->slave[i]) { 1394 *id = i; 1395 return 0; 1396 } 1397 } 1398 1399 fail: 1400 dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr); 1401 1402 return -EINVAL; 1403 } 1404 1405 static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev) 1406 { 1407 int i; 1408 1409 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1410 if (i2c_dev->slave[i]) 1411 return true; 1412 } 1413 1414 return false; 1415 } 1416 1417 static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev) 1418 { 1419 int i, busy; 1420 1421 busy = 0; 1422 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1423 if (i2c_dev->slave[i]) 1424 busy++; 1425 } 1426 1427 return i == busy; 1428 } 1429 1430 static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev, u32 status) 1431 { 1432 void __iomem *base = i2c_dev->base; 1433 u32 cr2, mask; 1434 u8 val; 1435 int ret; 1436 1437 /* Slave transmitter mode */ 1438 if (status & STM32F7_I2C_ISR_TXIS) { 1439 i2c_slave_event(i2c_dev->slave_running, 1440 I2C_SLAVE_READ_PROCESSED, 1441 &val); 1442 1443 /* Write data byte */ 1444 writel_relaxed(val, base + STM32F7_I2C_TXDR); 1445 } 1446 1447 /* Transfer Complete Reload for Slave receiver mode */ 1448 if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) { 1449 /* 1450 * Read data byte then set NBYTES to receive next byte or NACK 1451 * the current received byte 1452 */ 1453 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR); 1454 ret = i2c_slave_event(i2c_dev->slave_running, 1455 I2C_SLAVE_WRITE_RECEIVED, 1456 &val); 1457 if (!ret) { 1458 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 1459 cr2 |= STM32F7_I2C_CR2_NBYTES(1); 1460 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); 1461 } else { 1462 mask = STM32F7_I2C_CR2_NACK; 1463 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); 1464 } 1465 } 1466 1467 /* NACK received */ 1468 if (status & STM32F7_I2C_ISR_NACKF) { 1469 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__); 1470 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR); 1471 } 1472 1473 /* STOP received */ 1474 if (status & STM32F7_I2C_ISR_STOPF) { 1475 /* Disable interrupts */ 1476 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK); 1477 1478 if (i2c_dev->slave_dir) { 1479 /* 1480 * Flush TX buffer in order to not used the byte in 1481 * TXDR for the next transfer 1482 */ 1483 mask = STM32F7_I2C_ISR_TXE; 1484 stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask); 1485 } 1486 1487 /* Clear STOP flag */ 1488 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR); 1489 1490 /* Notify i2c slave that a STOP flag has been detected */ 1491 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val); 1492 1493 i2c_dev->slave_running = NULL; 1494 } 1495 1496 /* Address match received */ 1497 if (status & STM32F7_I2C_ISR_ADDR) 1498 stm32f7_i2c_slave_addr(i2c_dev); 1499 1500 return IRQ_HANDLED; 1501 } 1502 1503 static irqreturn_t stm32f7_i2c_handle_isr_errs(struct stm32f7_i2c_dev *i2c_dev, u32 status) 1504 { 1505 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1506 u16 addr = f7_msg->addr; 1507 void __iomem *base = i2c_dev->base; 1508 struct device *dev = i2c_dev->dev; 1509 1510 /* Bus error */ 1511 if (status & STM32F7_I2C_ISR_BERR) { 1512 dev_err(dev, "Bus error accessing addr 0x%x\n", addr); 1513 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR); 1514 stm32f7_i2c_release_bus(&i2c_dev->adap); 1515 f7_msg->result = -EIO; 1516 } 1517 1518 /* Arbitration loss */ 1519 if (status & STM32F7_I2C_ISR_ARLO) { 1520 dev_dbg(dev, "Arbitration loss accessing addr 0x%x\n", addr); 1521 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR); 1522 f7_msg->result = -EAGAIN; 1523 } 1524 1525 if (status & STM32F7_I2C_ISR_PECERR) { 1526 dev_err(dev, "PEC error in reception accessing addr 0x%x\n", addr); 1527 writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR); 1528 f7_msg->result = -EINVAL; 1529 } 1530 1531 if (status & STM32F7_I2C_ISR_ALERT) { 1532 dev_dbg(dev, "SMBus alert received\n"); 1533 writel_relaxed(STM32F7_I2C_ICR_ALERTCF, base + STM32F7_I2C_ICR); 1534 i2c_handle_smbus_alert(i2c_dev->alert->ara); 1535 return IRQ_HANDLED; 1536 } 1537 1538 if (!i2c_dev->slave_running) { 1539 u32 mask; 1540 /* Disable interrupts */ 1541 if (stm32f7_i2c_is_slave_registered(i2c_dev)) 1542 mask = STM32F7_I2C_XFER_IRQ_MASK; 1543 else 1544 mask = STM32F7_I2C_ALL_IRQ_MASK; 1545 stm32f7_i2c_disable_irq(i2c_dev, mask); 1546 } 1547 1548 /* Disable dma */ 1549 if (i2c_dev->use_dma) 1550 stm32f7_i2c_dma_callback(i2c_dev); 1551 1552 i2c_dev->master_mode = false; 1553 complete(&i2c_dev->complete); 1554 1555 return IRQ_HANDLED; 1556 } 1557 1558 #define STM32F7_ERR_EVENTS (STM32F7_I2C_ISR_BERR | STM32F7_I2C_ISR_ARLO |\ 1559 STM32F7_I2C_ISR_PECERR | STM32F7_I2C_ISR_ALERT) 1560 static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data) 1561 { 1562 struct stm32f7_i2c_dev *i2c_dev = data; 1563 u32 status; 1564 1565 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1566 1567 /* 1568 * Check if the interrupt is for a slave device or related 1569 * to errors flags (in case of single it line mode) 1570 */ 1571 if (!i2c_dev->master_mode || 1572 (i2c_dev->setup.single_it_line && (status & STM32F7_ERR_EVENTS))) 1573 return IRQ_WAKE_THREAD; 1574 1575 /* Tx empty */ 1576 if (status & STM32F7_I2C_ISR_TXIS) 1577 stm32f7_i2c_write_tx_data(i2c_dev); 1578 1579 /* RX not empty */ 1580 if (status & STM32F7_I2C_ISR_RXNE) 1581 stm32f7_i2c_read_rx_data(i2c_dev); 1582 1583 /* Wake up the thread if other flags are raised */ 1584 if (status & 1585 (STM32F7_I2C_ISR_NACKF | STM32F7_I2C_ISR_STOPF | 1586 STM32F7_I2C_ISR_TC | STM32F7_I2C_ISR_TCR)) 1587 return IRQ_WAKE_THREAD; 1588 1589 return IRQ_HANDLED; 1590 } 1591 1592 static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data) 1593 { 1594 struct stm32f7_i2c_dev *i2c_dev = data; 1595 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1596 void __iomem *base = i2c_dev->base; 1597 u32 status, mask; 1598 int ret; 1599 1600 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1601 1602 if (!i2c_dev->master_mode) 1603 return stm32f7_i2c_slave_isr_event(i2c_dev, status); 1604 1605 /* Handle errors in case of this handler is used for events/errors */ 1606 if (i2c_dev->setup.single_it_line && (status & STM32F7_ERR_EVENTS)) 1607 return stm32f7_i2c_handle_isr_errs(i2c_dev, status); 1608 1609 /* NACK received */ 1610 if (status & STM32F7_I2C_ISR_NACKF) { 1611 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK (addr %x)\n", 1612 __func__, f7_msg->addr); 1613 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR); 1614 if (i2c_dev->use_dma) 1615 stm32f7_i2c_dma_callback(i2c_dev); 1616 f7_msg->result = -ENXIO; 1617 } 1618 1619 if (status & STM32F7_I2C_ISR_TCR) { 1620 if (f7_msg->smbus) 1621 stm32f7_i2c_smbus_reload(i2c_dev); 1622 else 1623 stm32f7_i2c_reload(i2c_dev); 1624 } 1625 1626 /* Transfer complete */ 1627 if (status & STM32F7_I2C_ISR_TC) { 1628 /* Wait for dma transfer completion before sending next message */ 1629 if (i2c_dev->use_dma && !f7_msg->result) { 1630 ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ); 1631 if (!ret) { 1632 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__); 1633 stm32f7_i2c_dma_callback(i2c_dev); 1634 f7_msg->result = -ETIMEDOUT; 1635 } 1636 } 1637 if (f7_msg->stop) { 1638 mask = STM32F7_I2C_CR2_STOP; 1639 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); 1640 } else if (f7_msg->smbus) { 1641 stm32f7_i2c_smbus_rep_start(i2c_dev); 1642 } else { 1643 i2c_dev->msg_id++; 1644 i2c_dev->msg++; 1645 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg); 1646 } 1647 } 1648 1649 /* STOP detection flag */ 1650 if (status & STM32F7_I2C_ISR_STOPF) { 1651 /* Disable interrupts */ 1652 if (stm32f7_i2c_is_slave_registered(i2c_dev)) 1653 mask = STM32F7_I2C_XFER_IRQ_MASK; 1654 else 1655 mask = STM32F7_I2C_ALL_IRQ_MASK; 1656 stm32f7_i2c_disable_irq(i2c_dev, mask); 1657 1658 /* Clear STOP flag */ 1659 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR); 1660 1661 i2c_dev->master_mode = false; 1662 complete(&i2c_dev->complete); 1663 } 1664 1665 return IRQ_HANDLED; 1666 } 1667 1668 static irqreturn_t stm32f7_i2c_isr_error_thread(int irq, void *data) 1669 { 1670 struct stm32f7_i2c_dev *i2c_dev = data; 1671 u32 status; 1672 1673 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1674 1675 return stm32f7_i2c_handle_isr_errs(i2c_dev, status); 1676 } 1677 1678 static int stm32f7_i2c_wait_polling(struct stm32f7_i2c_dev *i2c_dev) 1679 { 1680 ktime_t timeout = ktime_add_ms(ktime_get(), i2c_dev->adap.timeout); 1681 1682 while (ktime_compare(ktime_get(), timeout) < 0) { 1683 udelay(5); 1684 stm32f7_i2c_isr_event(0, i2c_dev); 1685 1686 if (completion_done(&i2c_dev->complete)) 1687 return 1; 1688 } 1689 1690 return 0; 1691 } 1692 1693 static int stm32f7_i2c_xfer_core(struct i2c_adapter *i2c_adap, 1694 struct i2c_msg msgs[], int num) 1695 { 1696 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 1697 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1698 struct stm32_i2c_dma *dma = i2c_dev->dma; 1699 unsigned long time_left; 1700 int ret; 1701 1702 i2c_dev->msg = msgs; 1703 i2c_dev->msg_num = num; 1704 i2c_dev->msg_id = 0; 1705 f7_msg->smbus = false; 1706 1707 ret = pm_runtime_resume_and_get(i2c_dev->dev); 1708 if (ret < 0) 1709 return ret; 1710 1711 ret = stm32f7_i2c_wait_free_bus(i2c_dev); 1712 if (ret) 1713 goto pm_free; 1714 1715 reinit_completion(&i2c_dev->complete); 1716 1717 stm32f7_i2c_xfer_msg(i2c_dev, msgs); 1718 1719 if (!i2c_dev->atomic) 1720 time_left = wait_for_completion_timeout(&i2c_dev->complete, 1721 i2c_dev->adap.timeout); 1722 else 1723 time_left = stm32f7_i2c_wait_polling(i2c_dev); 1724 1725 ret = f7_msg->result; 1726 if (ret) { 1727 if (i2c_dev->use_dma) 1728 dmaengine_synchronize(dma->chan_using); 1729 1730 /* 1731 * It is possible that some unsent data have already been 1732 * written into TXDR. To avoid sending old data in a 1733 * further transfer, flush TXDR in case of any error 1734 */ 1735 writel_relaxed(STM32F7_I2C_ISR_TXE, 1736 i2c_dev->base + STM32F7_I2C_ISR); 1737 goto pm_free; 1738 } 1739 1740 if (!time_left) { 1741 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n", 1742 i2c_dev->msg->addr); 1743 if (i2c_dev->use_dma) 1744 dmaengine_terminate_sync(dma->chan_using); 1745 stm32f7_i2c_wait_free_bus(i2c_dev); 1746 ret = -ETIMEDOUT; 1747 } 1748 1749 pm_free: 1750 pm_runtime_put_autosuspend(i2c_dev->dev); 1751 1752 return (ret < 0) ? ret : num; 1753 } 1754 1755 static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap, 1756 struct i2c_msg msgs[], int num) 1757 { 1758 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 1759 1760 i2c_dev->atomic = false; 1761 return stm32f7_i2c_xfer_core(i2c_adap, msgs, num); 1762 } 1763 1764 static int stm32f7_i2c_xfer_atomic(struct i2c_adapter *i2c_adap, 1765 struct i2c_msg msgs[], int num) 1766 { 1767 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 1768 1769 i2c_dev->atomic = true; 1770 return stm32f7_i2c_xfer_core(i2c_adap, msgs, num); 1771 } 1772 1773 static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr, 1774 unsigned short flags, char read_write, 1775 u8 command, int size, 1776 union i2c_smbus_data *data) 1777 { 1778 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter); 1779 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1780 struct stm32_i2c_dma *dma = i2c_dev->dma; 1781 struct device *dev = i2c_dev->dev; 1782 unsigned long time_left; 1783 int i, ret; 1784 1785 f7_msg->addr = addr; 1786 f7_msg->size = size; 1787 f7_msg->read_write = read_write; 1788 f7_msg->smbus = true; 1789 1790 ret = pm_runtime_resume_and_get(dev); 1791 if (ret < 0) 1792 return ret; 1793 1794 ret = stm32f7_i2c_wait_free_bus(i2c_dev); 1795 if (ret) 1796 goto pm_free; 1797 1798 ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data); 1799 if (ret) 1800 goto pm_free; 1801 1802 time_left = wait_for_completion_timeout(&i2c_dev->complete, 1803 i2c_dev->adap.timeout); 1804 ret = f7_msg->result; 1805 if (ret) { 1806 if (i2c_dev->use_dma) 1807 dmaengine_synchronize(dma->chan_using); 1808 1809 /* 1810 * It is possible that some unsent data have already been 1811 * written into TXDR. To avoid sending old data in a 1812 * further transfer, flush TXDR in case of any error 1813 */ 1814 writel_relaxed(STM32F7_I2C_ISR_TXE, 1815 i2c_dev->base + STM32F7_I2C_ISR); 1816 goto pm_free; 1817 } 1818 1819 if (!time_left) { 1820 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr); 1821 if (i2c_dev->use_dma) 1822 dmaengine_terminate_sync(dma->chan_using); 1823 stm32f7_i2c_wait_free_bus(i2c_dev); 1824 ret = -ETIMEDOUT; 1825 goto pm_free; 1826 } 1827 1828 /* Check PEC */ 1829 if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) { 1830 ret = stm32f7_i2c_smbus_check_pec(i2c_dev); 1831 if (ret) 1832 goto pm_free; 1833 } 1834 1835 if (read_write && size != I2C_SMBUS_QUICK) { 1836 switch (size) { 1837 case I2C_SMBUS_BYTE: 1838 case I2C_SMBUS_BYTE_DATA: 1839 data->byte = f7_msg->smbus_buf[0]; 1840 break; 1841 case I2C_SMBUS_WORD_DATA: 1842 case I2C_SMBUS_PROC_CALL: 1843 data->word = f7_msg->smbus_buf[0] | 1844 (f7_msg->smbus_buf[1] << 8); 1845 break; 1846 case I2C_SMBUS_BLOCK_DATA: 1847 case I2C_SMBUS_BLOCK_PROC_CALL: 1848 for (i = 0; i <= f7_msg->smbus_buf[0]; i++) 1849 data->block[i] = f7_msg->smbus_buf[i]; 1850 break; 1851 default: 1852 dev_err(dev, "Unsupported smbus transaction\n"); 1853 ret = -EINVAL; 1854 } 1855 } 1856 1857 pm_free: 1858 pm_runtime_put_autosuspend(dev); 1859 return ret; 1860 } 1861 1862 static void stm32f7_i2c_enable_wakeup(struct stm32f7_i2c_dev *i2c_dev, 1863 bool enable) 1864 { 1865 void __iomem *base = i2c_dev->base; 1866 u32 mask = STM32F7_I2C_CR1_WUPEN; 1867 1868 if (!i2c_dev->wakeup_src) 1869 return; 1870 1871 if (enable) { 1872 device_set_wakeup_enable(i2c_dev->dev, true); 1873 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1874 } else { 1875 device_set_wakeup_enable(i2c_dev->dev, false); 1876 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); 1877 } 1878 } 1879 1880 static int stm32f7_i2c_reg_slave(struct i2c_client *slave) 1881 { 1882 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter); 1883 void __iomem *base = i2c_dev->base; 1884 struct device *dev = i2c_dev->dev; 1885 u32 oar1, oar2, mask; 1886 int id, ret; 1887 1888 if (slave->flags & I2C_CLIENT_PEC) { 1889 dev_err(dev, "SMBus PEC not supported in slave mode\n"); 1890 return -EINVAL; 1891 } 1892 1893 if (stm32f7_i2c_is_slave_busy(i2c_dev)) { 1894 dev_err(dev, "Too much slave registered\n"); 1895 return -EBUSY; 1896 } 1897 1898 ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id); 1899 if (ret) 1900 return ret; 1901 1902 ret = pm_runtime_resume_and_get(dev); 1903 if (ret < 0) 1904 return ret; 1905 1906 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) 1907 stm32f7_i2c_enable_wakeup(i2c_dev, true); 1908 1909 switch (id) { 1910 case 0: 1911 /* Slave SMBus Host */ 1912 i2c_dev->slave[id] = slave; 1913 break; 1914 1915 case 1: 1916 /* Configure Own Address 1 */ 1917 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1); 1918 oar1 &= ~STM32F7_I2C_OAR1_MASK; 1919 if (slave->flags & I2C_CLIENT_TEN) { 1920 oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr); 1921 oar1 |= STM32F7_I2C_OAR1_OA1MODE; 1922 } else { 1923 oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr); 1924 } 1925 oar1 |= STM32F7_I2C_OAR1_OA1EN; 1926 i2c_dev->slave[id] = slave; 1927 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1); 1928 break; 1929 1930 case 2: 1931 /* Configure Own Address 2 */ 1932 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2); 1933 oar2 &= ~STM32F7_I2C_OAR2_MASK; 1934 if (slave->flags & I2C_CLIENT_TEN) { 1935 ret = -EOPNOTSUPP; 1936 goto pm_free; 1937 } 1938 1939 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr); 1940 oar2 |= STM32F7_I2C_OAR2_OA2EN; 1941 i2c_dev->slave[id] = slave; 1942 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2); 1943 break; 1944 1945 default: 1946 dev_err(dev, "I2C slave id not supported\n"); 1947 ret = -ENODEV; 1948 goto pm_free; 1949 } 1950 1951 /* Enable ACK */ 1952 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK); 1953 1954 /* Enable Address match interrupt, error interrupt and enable I2C */ 1955 mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE | 1956 STM32F7_I2C_CR1_PE; 1957 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1958 1959 ret = 0; 1960 pm_free: 1961 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) 1962 stm32f7_i2c_enable_wakeup(i2c_dev, false); 1963 1964 pm_runtime_put_autosuspend(dev); 1965 1966 return ret; 1967 } 1968 1969 static int stm32f7_i2c_unreg_slave(struct i2c_client *slave) 1970 { 1971 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter); 1972 void __iomem *base = i2c_dev->base; 1973 u32 mask; 1974 int id, ret; 1975 1976 ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id); 1977 if (ret) 1978 return ret; 1979 1980 WARN_ON(!i2c_dev->slave[id]); 1981 1982 ret = pm_runtime_resume_and_get(i2c_dev->dev); 1983 if (ret < 0) 1984 return ret; 1985 1986 if (id == 1) { 1987 mask = STM32F7_I2C_OAR1_OA1EN; 1988 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask); 1989 } else if (id == 2) { 1990 mask = STM32F7_I2C_OAR2_OA2EN; 1991 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask); 1992 } 1993 1994 i2c_dev->slave[id] = NULL; 1995 1996 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) { 1997 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK); 1998 stm32f7_i2c_enable_wakeup(i2c_dev, false); 1999 } 2000 2001 pm_runtime_put_autosuspend(i2c_dev->dev); 2002 2003 return 0; 2004 } 2005 2006 static int stm32f7_i2c_write_fm_plus_bits(struct stm32f7_i2c_dev *i2c_dev, 2007 bool enable) 2008 { 2009 int ret = 0; 2010 2011 if (i2c_dev->bus_rate <= I2C_MAX_FAST_MODE_FREQ || 2012 (!i2c_dev->setup.fmp_cr1_bit && IS_ERR_OR_NULL(i2c_dev->regmap))) 2013 /* Optional */ 2014 return 0; 2015 2016 if (i2c_dev->setup.fmp_cr1_bit) { 2017 if (enable) 2018 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, STM32_I2C_CR1_FMP); 2019 else 2020 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, STM32_I2C_CR1_FMP); 2021 } else { 2022 if (i2c_dev->fmp_sreg == i2c_dev->fmp_creg) 2023 ret = regmap_update_bits(i2c_dev->regmap, i2c_dev->fmp_sreg, 2024 i2c_dev->fmp_mask, enable ? i2c_dev->fmp_mask : 0); 2025 else 2026 ret = regmap_write(i2c_dev->regmap, 2027 enable ? i2c_dev->fmp_sreg : i2c_dev->fmp_creg, 2028 i2c_dev->fmp_mask); 2029 } 2030 2031 return ret; 2032 } 2033 2034 static int stm32f7_i2c_setup_fm_plus_bits(struct platform_device *pdev, 2035 struct stm32f7_i2c_dev *i2c_dev) 2036 { 2037 struct device_node *np = pdev->dev.of_node; 2038 int ret; 2039 2040 i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp"); 2041 if (IS_ERR(i2c_dev->regmap)) 2042 /* Optional */ 2043 return 0; 2044 2045 ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1, 2046 &i2c_dev->fmp_sreg); 2047 if (ret) 2048 return ret; 2049 2050 i2c_dev->fmp_creg = i2c_dev->fmp_sreg + 2051 i2c_dev->setup.fmp_clr_offset; 2052 2053 return of_property_read_u32_index(np, "st,syscfg-fmp", 2, 2054 &i2c_dev->fmp_mask); 2055 } 2056 2057 static int stm32f7_i2c_enable_smbus_host(struct stm32f7_i2c_dev *i2c_dev) 2058 { 2059 struct i2c_adapter *adap = &i2c_dev->adap; 2060 void __iomem *base = i2c_dev->base; 2061 struct i2c_client *client; 2062 2063 client = i2c_new_slave_host_notify_device(adap); 2064 if (IS_ERR(client)) 2065 return PTR_ERR(client); 2066 2067 i2c_dev->host_notify_client = client; 2068 2069 /* Enable SMBus Host address */ 2070 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_SMBHEN); 2071 2072 return 0; 2073 } 2074 2075 static void stm32f7_i2c_disable_smbus_host(struct stm32f7_i2c_dev *i2c_dev) 2076 { 2077 void __iomem *base = i2c_dev->base; 2078 2079 if (i2c_dev->host_notify_client) { 2080 /* Disable SMBus Host address */ 2081 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, 2082 STM32F7_I2C_CR1_SMBHEN); 2083 i2c_free_slave_host_notify_device(i2c_dev->host_notify_client); 2084 } 2085 } 2086 2087 static int stm32f7_i2c_enable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev) 2088 { 2089 struct stm32f7_i2c_alert *alert; 2090 struct i2c_adapter *adap = &i2c_dev->adap; 2091 struct device *dev = i2c_dev->dev; 2092 void __iomem *base = i2c_dev->base; 2093 2094 alert = devm_kzalloc(dev, sizeof(*alert), GFP_KERNEL); 2095 if (!alert) 2096 return -ENOMEM; 2097 2098 alert->ara = i2c_new_smbus_alert_device(adap, &alert->setup); 2099 if (IS_ERR(alert->ara)) 2100 return PTR_ERR(alert->ara); 2101 2102 i2c_dev->alert = alert; 2103 2104 /* Enable SMBus Alert */ 2105 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_ALERTEN); 2106 2107 return 0; 2108 } 2109 2110 static void stm32f7_i2c_disable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev) 2111 { 2112 struct stm32f7_i2c_alert *alert = i2c_dev->alert; 2113 void __iomem *base = i2c_dev->base; 2114 2115 if (alert) { 2116 /* Disable SMBus Alert */ 2117 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, 2118 STM32F7_I2C_CR1_ALERTEN); 2119 i2c_unregister_device(alert->ara); 2120 } 2121 } 2122 2123 static u32 stm32f7_i2c_func(struct i2c_adapter *adap) 2124 { 2125 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 2126 2127 u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE | 2128 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 2129 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 2130 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL | 2131 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC | 2132 I2C_FUNC_SMBUS_I2C_BLOCK; 2133 2134 if (i2c_dev->smbus_mode) 2135 func |= I2C_FUNC_SMBUS_HOST_NOTIFY; 2136 2137 return func; 2138 } 2139 2140 static const struct i2c_algorithm stm32f7_i2c_algo = { 2141 .xfer = stm32f7_i2c_xfer, 2142 .xfer_atomic = stm32f7_i2c_xfer_atomic, 2143 .smbus_xfer = stm32f7_i2c_smbus_xfer, 2144 .functionality = stm32f7_i2c_func, 2145 .reg_slave = stm32f7_i2c_reg_slave, 2146 .unreg_slave = stm32f7_i2c_unreg_slave, 2147 }; 2148 2149 static int stm32f7_i2c_probe(struct platform_device *pdev) 2150 { 2151 struct stm32f7_i2c_dev *i2c_dev; 2152 const struct stm32f7_i2c_setup *setup; 2153 struct resource *res; 2154 struct i2c_adapter *adap; 2155 struct reset_control *rst; 2156 dma_addr_t phy_addr; 2157 int irq_error, irq_event, ret; 2158 2159 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 2160 if (!i2c_dev) 2161 return -ENOMEM; 2162 2163 setup = of_device_get_match_data(&pdev->dev); 2164 if (!setup) 2165 return dev_err_probe(&pdev->dev, -ENODEV, "Can't get device data\n"); 2166 i2c_dev->setup = *setup; 2167 2168 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2169 if (IS_ERR(i2c_dev->base)) 2170 return PTR_ERR(i2c_dev->base); 2171 phy_addr = (dma_addr_t)res->start; 2172 2173 irq_event = platform_get_irq(pdev, 0); 2174 if (irq_event < 0) 2175 return irq_event; 2176 2177 i2c_dev->wakeup_src = of_property_read_bool(pdev->dev.of_node, 2178 "wakeup-source"); 2179 2180 i2c_dev->clk = devm_clk_get_enabled(&pdev->dev, NULL); 2181 if (IS_ERR(i2c_dev->clk)) 2182 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_dev->clk), 2183 "Failed to enable controller clock\n"); 2184 2185 rst = devm_reset_control_get(&pdev->dev, NULL); 2186 if (IS_ERR(rst)) 2187 return dev_err_probe(&pdev->dev, PTR_ERR(rst), 2188 "Error: Missing reset ctrl\n"); 2189 2190 reset_control_assert(rst); 2191 udelay(2); 2192 reset_control_deassert(rst); 2193 2194 i2c_dev->dev = &pdev->dev; 2195 2196 ret = devm_request_threaded_irq(&pdev->dev, irq_event, 2197 stm32f7_i2c_isr_event, 2198 stm32f7_i2c_isr_event_thread, 2199 IRQF_ONESHOT, 2200 pdev->name, i2c_dev); 2201 if (ret) 2202 return dev_err_probe(&pdev->dev, ret, "Failed to request irq event\n"); 2203 2204 if (!i2c_dev->setup.single_it_line) { 2205 irq_error = platform_get_irq(pdev, 1); 2206 if (irq_error < 0) 2207 return irq_error; 2208 2209 ret = devm_request_threaded_irq(&pdev->dev, irq_error, 2210 NULL, 2211 stm32f7_i2c_isr_error_thread, 2212 IRQF_ONESHOT, 2213 pdev->name, i2c_dev); 2214 if (ret) 2215 return dev_err_probe(&pdev->dev, ret, "Failed to request irq error\n"); 2216 } 2217 2218 ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup); 2219 if (ret) 2220 return ret; 2221 2222 /* Setup Fast mode plus if necessary */ 2223 if (i2c_dev->bus_rate > I2C_MAX_FAST_MODE_FREQ) { 2224 if (!i2c_dev->setup.fmp_cr1_bit) { 2225 ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev); 2226 if (ret) 2227 return ret; 2228 } 2229 2230 ret = stm32f7_i2c_write_fm_plus_bits(i2c_dev, true); 2231 if (ret) 2232 return ret; 2233 } 2234 2235 adap = &i2c_dev->adap; 2236 i2c_set_adapdata(adap, i2c_dev); 2237 snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)", 2238 &res->start); 2239 adap->owner = THIS_MODULE; 2240 adap->timeout = 8 * HZ; 2241 adap->retries = 3; 2242 adap->algo = &stm32f7_i2c_algo; 2243 adap->dev.parent = &pdev->dev; 2244 adap->dev.of_node = pdev->dev.of_node; 2245 2246 init_completion(&i2c_dev->complete); 2247 2248 /* Init DMA config if supported */ 2249 i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr, 2250 STM32F7_I2C_TXDR, 2251 STM32F7_I2C_RXDR); 2252 if (IS_ERR(i2c_dev->dma)) { 2253 ret = PTR_ERR(i2c_dev->dma); 2254 /* DMA support is optional, only report other errors */ 2255 if (ret != -ENODEV) 2256 goto fmp_clear; 2257 dev_dbg(i2c_dev->dev, "No DMA option: fallback using interrupts\n"); 2258 i2c_dev->dma = NULL; 2259 } 2260 2261 if (i2c_dev->wakeup_src) { 2262 device_set_wakeup_capable(i2c_dev->dev, true); 2263 2264 ret = dev_pm_set_wake_irq(i2c_dev->dev, irq_event); 2265 if (ret) { 2266 dev_err_probe(i2c_dev->dev, ret, "Failed to set wake up irq\n"); 2267 goto clr_wakeup_capable; 2268 } 2269 } 2270 2271 platform_set_drvdata(pdev, i2c_dev); 2272 2273 pm_runtime_set_autosuspend_delay(i2c_dev->dev, 2274 STM32F7_AUTOSUSPEND_DELAY); 2275 pm_runtime_use_autosuspend(i2c_dev->dev); 2276 pm_runtime_set_active(i2c_dev->dev); 2277 pm_runtime_enable(i2c_dev->dev); 2278 2279 pm_runtime_get_noresume(&pdev->dev); 2280 2281 stm32f7_i2c_hw_config(i2c_dev); 2282 2283 i2c_dev->smbus_mode = of_property_read_bool(pdev->dev.of_node, "smbus"); 2284 2285 ret = i2c_add_adapter(adap); 2286 if (ret) 2287 goto pm_disable; 2288 2289 if (i2c_dev->smbus_mode) { 2290 ret = stm32f7_i2c_enable_smbus_host(i2c_dev); 2291 if (ret) { 2292 dev_err_probe(i2c_dev->dev, ret, 2293 "failed to enable SMBus Host-Notify protocol\n"); 2294 goto i2c_adapter_remove; 2295 } 2296 } 2297 2298 if (of_property_read_bool(pdev->dev.of_node, "smbus-alert")) { 2299 ret = stm32f7_i2c_enable_smbus_alert(i2c_dev); 2300 if (ret) { 2301 dev_err_probe(i2c_dev->dev, ret, 2302 "failed to enable SMBus alert protocol\n"); 2303 goto i2c_disable_smbus_host; 2304 } 2305 } 2306 2307 dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr); 2308 2309 pm_runtime_put_autosuspend(i2c_dev->dev); 2310 2311 return 0; 2312 2313 i2c_disable_smbus_host: 2314 stm32f7_i2c_disable_smbus_host(i2c_dev); 2315 2316 i2c_adapter_remove: 2317 i2c_del_adapter(adap); 2318 2319 pm_disable: 2320 pm_runtime_put_noidle(i2c_dev->dev); 2321 pm_runtime_disable(i2c_dev->dev); 2322 pm_runtime_set_suspended(i2c_dev->dev); 2323 pm_runtime_dont_use_autosuspend(i2c_dev->dev); 2324 2325 if (i2c_dev->wakeup_src) 2326 dev_pm_clear_wake_irq(i2c_dev->dev); 2327 2328 clr_wakeup_capable: 2329 if (i2c_dev->wakeup_src) 2330 device_set_wakeup_capable(i2c_dev->dev, false); 2331 2332 if (i2c_dev->dma) { 2333 stm32_i2c_dma_free(i2c_dev->dma); 2334 i2c_dev->dma = NULL; 2335 } 2336 2337 fmp_clear: 2338 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false); 2339 2340 return ret; 2341 } 2342 2343 static void stm32f7_i2c_remove(struct platform_device *pdev) 2344 { 2345 struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 2346 2347 stm32f7_i2c_disable_smbus_alert(i2c_dev); 2348 stm32f7_i2c_disable_smbus_host(i2c_dev); 2349 2350 i2c_del_adapter(&i2c_dev->adap); 2351 pm_runtime_get_sync(i2c_dev->dev); 2352 2353 if (i2c_dev->wakeup_src) { 2354 dev_pm_clear_wake_irq(i2c_dev->dev); 2355 /* 2356 * enforce that wakeup is disabled and that the device 2357 * is marked as non wakeup capable 2358 */ 2359 device_init_wakeup(i2c_dev->dev, false); 2360 } 2361 2362 pm_runtime_put_noidle(i2c_dev->dev); 2363 pm_runtime_disable(i2c_dev->dev); 2364 pm_runtime_set_suspended(i2c_dev->dev); 2365 pm_runtime_dont_use_autosuspend(i2c_dev->dev); 2366 2367 if (i2c_dev->dma) { 2368 stm32_i2c_dma_free(i2c_dev->dma); 2369 i2c_dev->dma = NULL; 2370 } 2371 2372 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false); 2373 } 2374 2375 static int __maybe_unused stm32f7_i2c_runtime_suspend(struct device *dev) 2376 { 2377 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2378 2379 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) 2380 clk_disable(i2c_dev->clk); 2381 2382 return 0; 2383 } 2384 2385 static int __maybe_unused stm32f7_i2c_runtime_resume(struct device *dev) 2386 { 2387 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2388 int ret; 2389 2390 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) { 2391 ret = clk_enable(i2c_dev->clk); 2392 if (ret) { 2393 dev_err(dev, "failed to enable clock\n"); 2394 return ret; 2395 } 2396 } 2397 2398 return 0; 2399 } 2400 2401 static int __maybe_unused stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev *i2c_dev) 2402 { 2403 int ret; 2404 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs; 2405 2406 ret = pm_runtime_resume_and_get(i2c_dev->dev); 2407 if (ret < 0) 2408 return ret; 2409 2410 backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1); 2411 backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 2412 backup_regs->oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1); 2413 backup_regs->oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2); 2414 backup_regs->tmgr = readl_relaxed(i2c_dev->base + STM32F7_I2C_TIMINGR); 2415 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false); 2416 2417 pm_runtime_put_sync(i2c_dev->dev); 2418 2419 return ret; 2420 } 2421 2422 static int __maybe_unused stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev *i2c_dev) 2423 { 2424 u32 cr1; 2425 int ret; 2426 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs; 2427 2428 ret = pm_runtime_resume_and_get(i2c_dev->dev); 2429 if (ret < 0) 2430 return ret; 2431 2432 cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1); 2433 if (cr1 & STM32F7_I2C_CR1_PE) 2434 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 2435 STM32F7_I2C_CR1_PE); 2436 2437 writel_relaxed(backup_regs->tmgr, i2c_dev->base + STM32F7_I2C_TIMINGR); 2438 writel_relaxed(backup_regs->cr1 & ~STM32F7_I2C_CR1_PE, 2439 i2c_dev->base + STM32F7_I2C_CR1); 2440 if (backup_regs->cr1 & STM32F7_I2C_CR1_PE) 2441 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 2442 STM32F7_I2C_CR1_PE); 2443 writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2); 2444 writel_relaxed(backup_regs->oar1, i2c_dev->base + STM32F7_I2C_OAR1); 2445 writel_relaxed(backup_regs->oar2, i2c_dev->base + STM32F7_I2C_OAR2); 2446 stm32f7_i2c_write_fm_plus_bits(i2c_dev, true); 2447 2448 pm_runtime_put_sync(i2c_dev->dev); 2449 2450 return ret; 2451 } 2452 2453 static int __maybe_unused stm32f7_i2c_suspend(struct device *dev) 2454 { 2455 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2456 int ret; 2457 2458 i2c_mark_adapter_suspended(&i2c_dev->adap); 2459 2460 if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) { 2461 ret = stm32f7_i2c_regs_backup(i2c_dev); 2462 if (ret < 0) { 2463 i2c_mark_adapter_resumed(&i2c_dev->adap); 2464 return ret; 2465 } 2466 2467 pinctrl_pm_select_sleep_state(dev); 2468 pm_runtime_force_suspend(dev); 2469 } 2470 2471 return 0; 2472 } 2473 2474 static int __maybe_unused stm32f7_i2c_resume(struct device *dev) 2475 { 2476 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2477 int ret; 2478 2479 if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) { 2480 ret = pm_runtime_force_resume(dev); 2481 if (ret < 0) 2482 return ret; 2483 pinctrl_pm_select_default_state(dev); 2484 2485 ret = stm32f7_i2c_regs_restore(i2c_dev); 2486 if (ret < 0) 2487 return ret; 2488 } 2489 2490 i2c_mark_adapter_resumed(&i2c_dev->adap); 2491 2492 return 0; 2493 } 2494 2495 static const struct dev_pm_ops stm32f7_i2c_pm_ops = { 2496 SET_RUNTIME_PM_OPS(stm32f7_i2c_runtime_suspend, 2497 stm32f7_i2c_runtime_resume, NULL) 2498 SET_SYSTEM_SLEEP_PM_OPS(stm32f7_i2c_suspend, stm32f7_i2c_resume) 2499 }; 2500 2501 static const struct of_device_id stm32f7_i2c_match[] = { 2502 { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup}, 2503 { .compatible = "st,stm32mp15-i2c", .data = &stm32mp15_setup}, 2504 { .compatible = "st,stm32mp13-i2c", .data = &stm32mp13_setup}, 2505 { .compatible = "st,stm32mp25-i2c", .data = &stm32mp25_setup}, 2506 {}, 2507 }; 2508 MODULE_DEVICE_TABLE(of, stm32f7_i2c_match); 2509 2510 static struct platform_driver stm32f7_i2c_driver = { 2511 .driver = { 2512 .name = "stm32f7-i2c", 2513 .of_match_table = stm32f7_i2c_match, 2514 .pm = &stm32f7_i2c_pm_ops, 2515 }, 2516 .probe = stm32f7_i2c_probe, 2517 .remove = stm32f7_i2c_remove, 2518 }; 2519 2520 module_platform_driver(stm32f7_i2c_driver); 2521 2522 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>"); 2523 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver"); 2524 MODULE_LICENSE("GPL v2"); 2525