1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2023 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #ifndef __DISPLAY_MODE_CORE_STRUCT_H__ 28 #define __DISPLAY_MODE_CORE_STRUCT_H__ 29 30 #include "display_mode_lib_defines.h" 31 32 enum dml_project_id { 33 dml_project_invalid = 0, 34 dml_project_default = 1, 35 dml_project_dcn32 = dml_project_default, 36 dml_project_dcn321 = 2, 37 dml_project_dcn35 = 3, 38 dml_project_dcn351 = 4, 39 dml_project_dcn401 = 5, 40 }; 41 enum dml_prefetch_modes { 42 dml_prefetch_support_uclk_fclk_and_stutter_if_possible = 0, 43 dml_prefetch_support_uclk_fclk_and_stutter = 1, 44 dml_prefetch_support_fclk_and_stutter = 2, 45 dml_prefetch_support_stutter = 3, 46 dml_prefetch_support_none = 4 47 }; 48 enum dml_use_mall_for_pstate_change_mode { 49 dml_use_mall_pstate_change_disable = 0, 50 dml_use_mall_pstate_change_full_frame = 1, 51 dml_use_mall_pstate_change_sub_viewport = 2, 52 dml_use_mall_pstate_change_phantom_pipe = 3 53 }; 54 enum dml_use_mall_for_static_screen_mode { 55 dml_use_mall_static_screen_disable = 0, 56 dml_use_mall_static_screen_enable = 1, 57 dml_use_mall_static_screen_optimize = 2 58 }; 59 enum dml_output_encoder_class { 60 dml_dp = 0, 61 dml_edp = 1, 62 dml_dp2p0 = 2, 63 dml_hdmi = 3, 64 dml_hdmifrl = 4, 65 dml_none = 5 66 }; 67 enum dml_output_link_dp_rate{ 68 dml_dp_rate_na = 0, 69 dml_dp_rate_hbr = 1, 70 dml_dp_rate_hbr2 = 2, 71 dml_dp_rate_hbr3 = 3, 72 dml_dp_rate_uhbr10 = 4, 73 dml_dp_rate_uhbr13p5 = 5, 74 dml_dp_rate_uhbr20 = 6 75 }; 76 enum dml_output_type_and_rate__type{ 77 dml_output_type_unknown = 0, 78 dml_output_type_dp = 1, 79 dml_output_type_edp = 2, 80 dml_output_type_dp2p0 = 3, 81 dml_output_type_hdmi = 4, 82 dml_output_type_hdmifrl = 5 83 }; 84 enum dml_output_type_and_rate__rate { 85 dml_output_rate_unknown = 0, 86 dml_output_rate_dp_rate_hbr = 1, 87 dml_output_rate_dp_rate_hbr2 = 2, 88 dml_output_rate_dp_rate_hbr3 = 3, 89 dml_output_rate_dp_rate_uhbr10 = 4, 90 dml_output_rate_dp_rate_uhbr13p5 = 5, 91 dml_output_rate_dp_rate_uhbr20 = 6, 92 dml_output_rate_hdmi_rate_3x3 = 7, 93 dml_output_rate_hdmi_rate_6x3 = 8, 94 dml_output_rate_hdmi_rate_6x4 = 9, 95 dml_output_rate_hdmi_rate_8x4 = 10, 96 dml_output_rate_hdmi_rate_10x4 = 11, 97 dml_output_rate_hdmi_rate_12x4 = 12 98 }; 99 enum dml_output_format_class { 100 dml_444 = 0, 101 dml_s422 = 1, 102 dml_n422 = 2, 103 dml_420 = 3 104 }; 105 enum dml_source_format_class { 106 dml_444_8 = 0, 107 dml_444_16 = 1, 108 dml_444_32 = 2, 109 dml_444_64 = 3, 110 dml_420_8 = 4, 111 dml_420_10 = 5, 112 dml_420_12 = 6, 113 dml_422_8 = 7, 114 dml_422_10 = 8, 115 dml_rgbe_alpha = 9, 116 dml_rgbe = 10, 117 dml_mono_8 = 11, 118 dml_mono_16 = 12 119 }; 120 enum dml_output_bpc_class { 121 dml_out_6 = 0, 122 dml_out_8 = 1, 123 dml_out_10 = 2, 124 dml_out_12 = 3, 125 dml_out_16 = 4 126 }; 127 enum dml_output_standard_class { 128 dml_std_cvt = 0, 129 dml_std_cea = 1, 130 dml_std_cvtr2 = 2 131 }; 132 enum dml_rotation_angle { 133 dml_rotation_0 = 0, 134 dml_rotation_90 = 1, 135 dml_rotation_180 = 2, 136 dml_rotation_270 = 3, 137 dml_rotation_0m = 4, 138 dml_rotation_90m = 5, 139 dml_rotation_180m = 6, 140 dml_rotation_270m = 7 141 }; 142 enum dml_swizzle_mode { 143 dml_sw_linear = 0, 144 dml_sw_256b_s = 1, 145 dml_sw_256b_d = 2, 146 dml_sw_256b_r = 3, 147 dml_sw_4kb_z = 4, 148 dml_sw_4kb_s = 5, 149 dml_sw_4kb_d = 6, 150 dml_sw_4kb_r = 7, 151 dml_sw_64kb_z = 8, 152 dml_sw_64kb_s = 9, 153 dml_sw_64kb_d = 10, 154 dml_sw_64kb_r = 11, 155 dml_sw_256kb_z = 12, 156 dml_sw_256kb_s = 13, 157 dml_sw_256kb_d = 14, 158 dml_sw_256kb_r = 15, 159 dml_sw_64kb_z_t = 16, 160 dml_sw_64kb_s_t = 17, 161 dml_sw_64kb_d_t = 18, 162 dml_sw_64kb_r_t = 19, 163 dml_sw_4kb_z_x = 20, 164 dml_sw_4kb_s_x = 21, 165 dml_sw_4kb_d_x = 22, 166 dml_sw_4kb_r_x = 23, 167 dml_sw_64kb_z_x = 24, 168 dml_sw_64kb_s_x = 25, 169 dml_sw_64kb_d_x = 26, 170 dml_sw_64kb_r_x = 27, 171 dml_sw_256kb_z_x = 28, 172 dml_sw_256kb_s_x = 29, 173 dml_sw_256kb_d_x = 30, 174 dml_sw_256kb_r_x = 31 175 }; 176 enum dml_lb_depth { 177 dml_lb_6 = 0, 178 dml_lb_8 = 1, 179 dml_lb_10 = 2, 180 dml_lb_12 = 3, 181 dml_lb_16 = 4 182 }; 183 enum dml_voltage_state { 184 dml_vmin_lv = 0, 185 dml_vmin = 1, 186 dml_vmid = 2, 187 dml_vnom = 3, 188 dml_vmax = 4 189 }; 190 enum dml_source_macro_tile_size { 191 dml_4k_tile = 0, 192 dml_64k_tile = 1, 193 dml_256k_tile = 2 194 }; 195 enum dml_cursor_bpp { 196 dml_cur_2bit = 0, 197 dml_cur_32bit = 1, 198 dml_cur_64bit = 2 199 }; 200 enum dml_dram_clock_change_support { 201 dml_dram_clock_change_vactive = 0, 202 dml_dram_clock_change_vblank = 1, 203 dml_dram_clock_change_vblank_drr = 2, 204 dml_dram_clock_change_vactive_w_mall_full_frame = 3, 205 dml_dram_clock_change_vactive_w_mall_sub_vp = 4, 206 dml_dram_clock_change_vblank_w_mall_full_frame = 5, 207 dml_dram_clock_change_vblank_drr_w_mall_full_frame = 6, 208 dml_dram_clock_change_vblank_w_mall_sub_vp = 7, 209 dml_dram_clock_change_vblank_drr_w_mall_sub_vp = 8, 210 dml_dram_clock_change_unsupported = 9 211 }; 212 enum dml_fclock_change_support { 213 dml_fclock_change_vactive = 0, 214 dml_fclock_change_vblank = 1, 215 dml_fclock_change_unsupported = 2 216 }; 217 enum dml_dsc_enable { 218 dml_dsc_disable = 0, 219 dml_dsc_enable = 1, 220 dml_dsc_enable_if_necessary = 2 221 }; 222 enum dml_mpc_use_policy { 223 dml_mpc_disabled = 0, 224 dml_mpc_as_possible = 1, 225 dml_mpc_as_needed_for_voltage = 2, 226 dml_mpc_as_needed_for_pstate_and_voltage = 3 227 }; 228 enum dml_odm_use_policy { 229 dml_odm_use_policy_bypass = 0, 230 dml_odm_use_policy_combine_as_needed = 1, 231 dml_odm_use_policy_combine_2to1 = 2, 232 dml_odm_use_policy_combine_4to1 = 3, 233 dml_odm_use_policy_split_1to2 = 4, 234 dml_odm_use_policy_mso_1to2 = 5, 235 dml_odm_use_policy_mso_1to4 = 6 236 }; 237 enum dml_odm_mode { 238 dml_odm_mode_bypass = 0, 239 dml_odm_mode_combine_2to1 = 1, 240 dml_odm_mode_combine_4to1 = 2, 241 dml_odm_mode_split_1to2 = 3, 242 dml_odm_mode_mso_1to2 = 4, 243 dml_odm_mode_mso_1to4 = 5 244 }; 245 enum dml_writeback_configuration { 246 dml_whole_buffer_for_single_stream_no_interleave = 0, 247 dml_whole_buffer_for_single_stream_interleave = 1 248 }; 249 enum dml_immediate_flip_requirement { 250 dml_immediate_flip_not_required = 0, 251 dml_immediate_flip_required = 1, 252 dml_immediate_flip_if_possible = 2 253 }; 254 enum dml_unbounded_requesting_policy { 255 dml_unbounded_requesting_enable = 0, 256 dml_unbounded_requesting_edp_only = 1, 257 dml_unbounded_requesting_disable = 2 258 }; 259 enum dml_clk_cfg_policy { 260 dml_use_required_freq = 0, 261 dml_use_override_freq = 1, 262 dml_use_state_freq = 2 263 }; 264 265 266 struct soc_state_bounding_box_st { 267 dml_float_t socclk_mhz; 268 dml_float_t dscclk_mhz; 269 dml_float_t phyclk_mhz; 270 dml_float_t phyclk_d18_mhz; 271 dml_float_t phyclk_d32_mhz; 272 dml_float_t dtbclk_mhz; 273 dml_float_t fabricclk_mhz; 274 dml_float_t dcfclk_mhz; 275 dml_float_t dispclk_mhz; 276 dml_float_t dppclk_mhz; 277 dml_float_t dram_speed_mts; 278 dml_float_t urgent_latency_pixel_data_only_us; 279 dml_float_t urgent_latency_pixel_mixed_with_vm_data_us; 280 dml_float_t urgent_latency_vm_data_only_us; 281 dml_float_t writeback_latency_us; 282 dml_float_t urgent_latency_adjustment_fabric_clock_component_us; 283 dml_float_t urgent_latency_adjustment_fabric_clock_reference_mhz; 284 dml_float_t sr_exit_time_us; 285 dml_float_t sr_enter_plus_exit_time_us; 286 dml_float_t sr_exit_z8_time_us; 287 dml_float_t sr_enter_plus_exit_z8_time_us; 288 dml_float_t dram_clock_change_latency_us; 289 dml_float_t fclk_change_latency_us; 290 dml_float_t usr_retraining_latency_us; 291 dml_bool_t use_ideal_dram_bw_strobe; 292 }; 293 294 struct soc_bounding_box_st { 295 dml_float_t dprefclk_mhz; 296 dml_float_t xtalclk_mhz; 297 dml_float_t pcierefclk_mhz; 298 dml_float_t refclk_mhz; 299 dml_float_t amclk_mhz; 300 dml_float_t max_outstanding_reqs; 301 dml_float_t pct_ideal_sdp_bw_after_urgent; 302 dml_float_t pct_ideal_fabric_bw_after_urgent; 303 dml_float_t pct_ideal_dram_bw_after_urgent_pixel_only; 304 dml_float_t pct_ideal_dram_bw_after_urgent_pixel_and_vm; 305 dml_float_t pct_ideal_dram_bw_after_urgent_vm_only; 306 dml_float_t pct_ideal_dram_bw_after_urgent_strobe; 307 dml_float_t max_avg_sdp_bw_use_normal_percent; 308 dml_float_t max_avg_fabric_bw_use_normal_percent; 309 dml_float_t max_avg_dram_bw_use_normal_percent; 310 dml_float_t max_avg_dram_bw_use_normal_strobe_percent; 311 dml_uint_t round_trip_ping_latency_dcfclk_cycles; 312 dml_uint_t urgent_out_of_order_return_per_channel_pixel_only_bytes; 313 dml_uint_t urgent_out_of_order_return_per_channel_pixel_and_vm_bytes; 314 dml_uint_t urgent_out_of_order_return_per_channel_vm_only_bytes; 315 dml_uint_t num_chans; 316 dml_uint_t return_bus_width_bytes; 317 dml_uint_t dram_channel_width_bytes; 318 dml_uint_t fabric_datapath_to_dcn_data_return_bytes; 319 dml_uint_t hostvm_min_page_size_kbytes; 320 dml_uint_t gpuvm_min_page_size_kbytes; 321 dml_float_t phy_downspread_percent; 322 dml_float_t dcn_downspread_percent; 323 dml_float_t smn_latency_us; 324 dml_uint_t mall_allocated_for_dcn_mbytes; 325 dml_float_t dispclk_dppclk_vco_speed_mhz; 326 dml_bool_t do_urgent_latency_adjustment; 327 }; 328 329 struct ip_params_st { 330 dml_uint_t vblank_nom_default_us; 331 dml_uint_t rob_buffer_size_kbytes; 332 dml_uint_t config_return_buffer_size_in_kbytes; 333 dml_uint_t config_return_buffer_segment_size_in_kbytes; 334 dml_uint_t compressed_buffer_segment_size_in_kbytes; 335 dml_uint_t meta_fifo_size_in_kentries; 336 dml_uint_t zero_size_buffer_entries; 337 dml_uint_t dpte_buffer_size_in_pte_reqs_luma; 338 dml_uint_t dpte_buffer_size_in_pte_reqs_chroma; 339 dml_uint_t dcc_meta_buffer_size_bytes; 340 dml_bool_t gpuvm_enable; 341 dml_bool_t hostvm_enable; 342 dml_uint_t gpuvm_max_page_table_levels; 343 dml_uint_t hostvm_max_page_table_levels; 344 dml_uint_t pixel_chunk_size_kbytes; 345 dml_uint_t alpha_pixel_chunk_size_kbytes; 346 dml_uint_t min_pixel_chunk_size_bytes; 347 dml_uint_t meta_chunk_size_kbytes; 348 dml_uint_t min_meta_chunk_size_bytes; 349 dml_uint_t writeback_chunk_size_kbytes; 350 dml_uint_t line_buffer_size_bits; 351 dml_uint_t max_line_buffer_lines; 352 dml_uint_t writeback_interface_buffer_size_kbytes; 353 dml_uint_t max_num_dpp; 354 dml_uint_t max_num_otg; 355 dml_uint_t max_num_wb; 356 dml_uint_t max_dchub_pscl_bw_pix_per_clk; 357 dml_uint_t max_pscl_lb_bw_pix_per_clk; 358 dml_uint_t max_lb_vscl_bw_pix_per_clk; 359 dml_uint_t max_vscl_hscl_bw_pix_per_clk; 360 dml_float_t max_hscl_ratio; 361 dml_float_t max_vscl_ratio; 362 dml_uint_t max_hscl_taps; 363 dml_uint_t max_vscl_taps; 364 dml_uint_t num_dsc; 365 dml_uint_t maximum_dsc_bits_per_component; 366 dml_uint_t maximum_pixels_per_line_per_dsc_unit; 367 dml_bool_t dsc422_native_support; 368 dml_bool_t cursor_64bpp_support; 369 dml_float_t dispclk_ramp_margin_percent; 370 dml_uint_t dppclk_delay_subtotal; 371 dml_uint_t dppclk_delay_scl; 372 dml_uint_t dppclk_delay_scl_lb_only; 373 dml_uint_t dppclk_delay_cnvc_formatter; 374 dml_uint_t dppclk_delay_cnvc_cursor; 375 dml_uint_t cursor_buffer_size; 376 dml_uint_t cursor_chunk_size; 377 dml_uint_t dispclk_delay_subtotal; 378 dml_bool_t dynamic_metadata_vm_enabled; 379 dml_uint_t max_inter_dcn_tile_repeaters; 380 dml_uint_t max_num_hdmi_frl_outputs; 381 dml_uint_t max_num_dp2p0_outputs; 382 dml_uint_t max_num_dp2p0_streams; 383 dml_bool_t dcc_supported; 384 dml_bool_t ptoi_supported; 385 dml_float_t writeback_max_hscl_ratio; 386 dml_float_t writeback_max_vscl_ratio; 387 dml_float_t writeback_min_hscl_ratio; 388 dml_float_t writeback_min_vscl_ratio; 389 dml_uint_t writeback_max_hscl_taps; 390 dml_uint_t writeback_max_vscl_taps; 391 dml_uint_t writeback_line_buffer_buffer_size; 392 }; 393 394 struct DmlPipe { 395 dml_float_t Dppclk; 396 dml_float_t Dispclk; 397 dml_float_t PixelClock; 398 dml_float_t DCFClkDeepSleep; 399 dml_uint_t DPPPerSurface; 400 dml_bool_t ScalerEnabled; 401 enum dml_rotation_angle SourceScan; 402 dml_uint_t ViewportHeight; 403 dml_uint_t ViewportHeightChroma; 404 dml_uint_t BlockWidth256BytesY; 405 dml_uint_t BlockHeight256BytesY; 406 dml_uint_t BlockWidth256BytesC; 407 dml_uint_t BlockHeight256BytesC; 408 dml_uint_t BlockWidthY; 409 dml_uint_t BlockHeightY; 410 dml_uint_t BlockWidthC; 411 dml_uint_t BlockHeightC; 412 dml_uint_t InterlaceEnable; 413 dml_uint_t NumberOfCursors; 414 dml_uint_t VBlank; 415 dml_uint_t HTotal; 416 dml_uint_t HActive; 417 dml_bool_t DCCEnable; 418 enum dml_odm_mode ODMMode; 419 enum dml_source_format_class SourcePixelFormat; 420 enum dml_swizzle_mode SurfaceTiling; 421 dml_uint_t BytePerPixelY; 422 dml_uint_t BytePerPixelC; 423 dml_bool_t ProgressiveToInterlaceUnitInOPP; 424 dml_float_t VRatio; 425 dml_float_t VRatioChroma; 426 dml_uint_t VTaps; 427 dml_uint_t VTapsChroma; 428 dml_uint_t PitchY; 429 dml_uint_t DCCMetaPitchY; 430 dml_uint_t PitchC; 431 dml_uint_t DCCMetaPitchC; 432 dml_bool_t ViewportStationary; 433 dml_uint_t ViewportXStart; 434 dml_uint_t ViewportYStart; 435 dml_uint_t ViewportXStartC; 436 dml_uint_t ViewportYStartC; 437 dml_bool_t FORCE_ONE_ROW_FOR_FRAME; 438 dml_uint_t SwathHeightY; 439 dml_uint_t SwathHeightC; 440 }; 441 442 struct Watermarks { 443 dml_float_t UrgentWatermark; 444 dml_float_t WritebackUrgentWatermark; 445 dml_float_t DRAMClockChangeWatermark; 446 dml_float_t FCLKChangeWatermark; 447 dml_float_t WritebackDRAMClockChangeWatermark; 448 dml_float_t WritebackFCLKChangeWatermark; 449 dml_float_t StutterExitWatermark; 450 dml_float_t StutterEnterPlusExitWatermark; 451 dml_float_t Z8StutterExitWatermark; 452 dml_float_t Z8StutterEnterPlusExitWatermark; 453 dml_float_t USRRetrainingWatermark; 454 }; 455 456 struct SOCParametersList { 457 dml_float_t UrgentLatency; 458 dml_float_t ExtraLatency; 459 dml_float_t WritebackLatency; 460 dml_float_t DRAMClockChangeLatency; 461 dml_float_t FCLKChangeLatency; 462 dml_float_t SRExitTime; 463 dml_float_t SREnterPlusExitTime; 464 dml_float_t SRExitZ8Time; 465 dml_float_t SREnterPlusExitZ8Time; 466 dml_float_t USRRetrainingLatency; 467 dml_float_t SMNLatency; 468 }; 469 470 /// @brief Struct that represent Plane configration of a display cfg 471 struct dml_plane_cfg_st { 472 // 473 // Pipe/Surface Parameters 474 // 475 dml_bool_t GPUVMEnable; /// <brief Set if any pipe has GPUVM enable 476 dml_bool_t HostVMEnable; /// <brief Set if any pipe has HostVM enable 477 478 dml_uint_t GPUVMMaxPageTableLevels; /// <brief GPUVM level; max of all pipes' 479 dml_uint_t HostVMMaxPageTableLevels; /// <brief HostVM level; max of all pipes'; that is the number of non-cache HVM level 480 481 dml_uint_t GPUVMMinPageSizeKBytes[__DML_NUM_PLANES__]; 482 dml_bool_t ForceOneRowForFrame[__DML_NUM_PLANES__]; 483 dml_bool_t PTEBufferModeOverrideEn[__DML_NUM_PLANES__]; //< brief when override enable; the DML will only check the given pte buffer and will use the pte buffer mode as is 484 dml_bool_t PTEBufferMode[__DML_NUM_PLANES__]; 485 dml_uint_t ViewportWidth[__DML_NUM_PLANES__]; 486 dml_uint_t ViewportHeight[__DML_NUM_PLANES__]; 487 dml_uint_t ViewportWidthChroma[__DML_NUM_PLANES__]; 488 dml_uint_t ViewportHeightChroma[__DML_NUM_PLANES__]; 489 dml_uint_t ViewportXStart[__DML_NUM_PLANES__]; 490 dml_uint_t ViewportXStartC[__DML_NUM_PLANES__]; 491 dml_uint_t ViewportYStart[__DML_NUM_PLANES__]; 492 dml_uint_t ViewportYStartC[__DML_NUM_PLANES__]; 493 dml_bool_t ViewportStationary[__DML_NUM_PLANES__]; 494 495 dml_bool_t ScalerEnabled[__DML_NUM_PLANES__]; 496 dml_float_t HRatio[__DML_NUM_PLANES__]; 497 dml_float_t VRatio[__DML_NUM_PLANES__]; 498 dml_float_t HRatioChroma[__DML_NUM_PLANES__]; 499 dml_float_t VRatioChroma[__DML_NUM_PLANES__]; 500 dml_uint_t HTaps[__DML_NUM_PLANES__]; 501 dml_uint_t VTaps[__DML_NUM_PLANES__]; 502 dml_uint_t HTapsChroma[__DML_NUM_PLANES__]; 503 dml_uint_t VTapsChroma[__DML_NUM_PLANES__]; 504 dml_uint_t LBBitPerPixel[__DML_NUM_PLANES__]; 505 506 enum dml_rotation_angle SourceScan[__DML_NUM_PLANES__]; 507 dml_uint_t ScalerRecoutWidth[__DML_NUM_PLANES__]; 508 509 dml_bool_t DynamicMetadataEnable[__DML_NUM_PLANES__]; 510 dml_uint_t DynamicMetadataLinesBeforeActiveRequired[__DML_NUM_PLANES__]; 511 dml_uint_t DynamicMetadataTransmittedBytes[__DML_NUM_PLANES__]; 512 dml_uint_t DETSizeOverride[__DML_NUM_PLANES__]; /// <brief user can specify the desire DET buffer usage per-plane 513 514 dml_uint_t NumberOfCursors[__DML_NUM_PLANES__]; 515 dml_uint_t CursorWidth[__DML_NUM_PLANES__]; 516 dml_uint_t CursorBPP[__DML_NUM_PLANES__]; 517 518 enum dml_use_mall_for_static_screen_mode UseMALLForStaticScreen[__DML_NUM_PLANES__]; 519 enum dml_use_mall_for_pstate_change_mode UseMALLForPStateChange[__DML_NUM_PLANES__]; 520 521 dml_uint_t BlendingAndTiming[__DML_NUM_PLANES__]; /// <brief From which timing group (like OTG) that this plane is getting its timing from. Mode check also need this info for example to check num OTG; encoder; dsc etc. 522 }; // dml_plane_cfg_st; 523 524 /// @brief Surface Parameters 525 struct dml_surface_cfg_st { 526 enum dml_swizzle_mode SurfaceTiling[__DML_NUM_PLANES__]; 527 enum dml_source_format_class SourcePixelFormat[__DML_NUM_PLANES__]; 528 dml_uint_t PitchY[__DML_NUM_PLANES__]; 529 dml_uint_t SurfaceWidthY[__DML_NUM_PLANES__]; 530 dml_uint_t SurfaceHeightY[__DML_NUM_PLANES__]; 531 dml_uint_t PitchC[__DML_NUM_PLANES__]; 532 dml_uint_t SurfaceWidthC[__DML_NUM_PLANES__]; 533 dml_uint_t SurfaceHeightC[__DML_NUM_PLANES__]; 534 535 dml_bool_t DCCEnable[__DML_NUM_PLANES__]; 536 dml_uint_t DCCMetaPitchY[__DML_NUM_PLANES__]; 537 dml_uint_t DCCMetaPitchC[__DML_NUM_PLANES__]; 538 539 dml_float_t DCCRateLuma[__DML_NUM_PLANES__]; 540 dml_float_t DCCRateChroma[__DML_NUM_PLANES__]; 541 dml_float_t DCCFractionOfZeroSizeRequestsLuma[__DML_NUM_PLANES__]; 542 dml_float_t DCCFractionOfZeroSizeRequestsChroma[__DML_NUM_PLANES__]; 543 }; // dml_surface_cfg_st 544 545 /// @brief structure that represents the timing configuration 546 struct dml_timing_cfg_st { 547 dml_uint_t HTotal[__DML_NUM_PLANES__]; 548 dml_uint_t VTotal[__DML_NUM_PLANES__]; 549 dml_uint_t HBlankEnd[__DML_NUM_PLANES__]; 550 dml_uint_t VBlankEnd[__DML_NUM_PLANES__]; 551 dml_uint_t RefreshRate[__DML_NUM_PLANES__]; 552 dml_uint_t VFrontPorch[__DML_NUM_PLANES__]; 553 dml_float_t PixelClock[__DML_NUM_PLANES__]; 554 dml_uint_t HActive[__DML_NUM_PLANES__]; 555 dml_uint_t VActive[__DML_NUM_PLANES__]; 556 dml_bool_t Interlace[__DML_NUM_PLANES__]; 557 dml_bool_t DRRDisplay[__DML_NUM_PLANES__]; 558 dml_uint_t VBlankNom[__DML_NUM_PLANES__]; 559 }; // dml_timing_cfg_st; 560 561 /// @brief structure that represents the output stream 562 struct dml_output_cfg_st { 563 // Output Setting 564 dml_uint_t DSCInputBitPerComponent[__DML_NUM_PLANES__]; 565 enum dml_output_format_class OutputFormat[__DML_NUM_PLANES__]; 566 enum dml_output_encoder_class OutputEncoder[__DML_NUM_PLANES__]; 567 dml_uint_t OutputMultistreamId[__DML_NUM_PLANES__]; 568 dml_bool_t OutputMultistreamEn[__DML_NUM_PLANES__]; 569 dml_float_t OutputBpp[__DML_NUM_PLANES__]; //< brief Use by mode_programming to specify a output bpp; user can use the output from mode_support (support.OutputBpp) 570 dml_float_t PixelClockBackEnd[__DML_NUM_PLANES__]; 571 enum dml_dsc_enable DSCEnable[__DML_NUM_PLANES__]; //< brief for mode support check; use to determine if dsc is required 572 dml_uint_t OutputLinkDPLanes[__DML_NUM_PLANES__]; 573 enum dml_output_link_dp_rate OutputLinkDPRate[__DML_NUM_PLANES__]; 574 dml_float_t ForcedOutputLinkBPP[__DML_NUM_PLANES__]; 575 dml_uint_t AudioSampleRate[__DML_NUM_PLANES__]; 576 dml_uint_t AudioSampleLayout[__DML_NUM_PLANES__]; 577 dml_bool_t OutputDisabled[__DML_NUM_PLANES__]; 578 dml_uint_t DSCSlices[__DML_NUM_PLANES__]; 579 }; // dml_timing_cfg_st; 580 581 /// @brief Writeback Setting 582 struct dml_writeback_cfg_st { 583 enum dml_source_format_class WritebackPixelFormat[__DML_NUM_PLANES__]; 584 dml_bool_t WritebackEnable[__DML_NUM_PLANES__]; 585 dml_uint_t ActiveWritebacksPerSurface[__DML_NUM_PLANES__]; 586 dml_uint_t WritebackDestinationWidth[__DML_NUM_PLANES__]; 587 dml_uint_t WritebackDestinationHeight[__DML_NUM_PLANES__]; 588 dml_uint_t WritebackSourceWidth[__DML_NUM_PLANES__]; 589 dml_uint_t WritebackSourceHeight[__DML_NUM_PLANES__]; 590 dml_uint_t WritebackHTaps[__DML_NUM_PLANES__]; 591 dml_uint_t WritebackVTaps[__DML_NUM_PLANES__]; 592 dml_float_t WritebackHRatio[__DML_NUM_PLANES__]; 593 dml_float_t WritebackVRatio[__DML_NUM_PLANES__]; 594 }; // dml_writeback_cfg_st; 595 596 /// @brief Hardware resource specific; mainly used by mode_programming when test/sw wants to do some specific setting 597 /// which are not the same as what the mode support stage derive. When call mode_support with mode_programm; the hw-specific 598 // resource will be set to what the mode_support layer recommends 599 struct dml_hw_resource_st { 600 enum dml_odm_mode ODMMode[__DML_NUM_PLANES__]; /// <brief ODM mode that is chosen in the mode check stage and will be used in mode programming stage 601 dml_uint_t DPPPerSurface[__DML_NUM_PLANES__]; /// <brief How many DPPs are needed drive the surface to output. If MPCC or ODMC could be 2 or 4. 602 dml_bool_t DSCEnabled[__DML_NUM_PLANES__]; /// <brief Indicate if the DSC is enabled; used in mode_programming 603 dml_uint_t NumberOfDSCSlices[__DML_NUM_PLANES__]; /// <brief Indicate how many slices needed to support the given mode 604 dml_float_t DLGRefClkFreqMHz; /// <brief DLG Global Reference timer 605 }; 606 607 /// @brief DML display configuration. 608 /// Describe how to display a surface in multi-plane setup and output to different output and writeback using the specified timgin 609 struct dml_display_cfg_st { 610 struct dml_surface_cfg_st surface; 611 struct dml_plane_cfg_st plane; 612 struct dml_timing_cfg_st timing; 613 struct dml_output_cfg_st output; 614 struct dml_writeback_cfg_st writeback; 615 unsigned int num_surfaces; 616 unsigned int num_timings; 617 618 struct dml_hw_resource_st hw; //< brief for mode programming 619 }; // dml_display_cfg_st 620 621 /// @brief To control the clk usage for model programming 622 struct dml_clk_cfg_st { 623 enum dml_clk_cfg_policy dcfclk_option; ///< brief Use for mode_program; user can select between use the min require clk req as calculated by DML or use the test-specific freq 624 enum dml_clk_cfg_policy dispclk_option; ///< brief Use for mode_program; user can select between use the min require clk req as calculated by DML or use the test-specific freq 625 enum dml_clk_cfg_policy dppclk_option[__DML_NUM_PLANES__]; 626 627 dml_float_t dcfclk_freq_mhz; 628 dml_float_t dispclk_freq_mhz; 629 dml_float_t dppclk_freq_mhz[__DML_NUM_PLANES__]; 630 }; // dml_clk_cfg_st 631 632 /// @brief DML mode evaluation and programming policy 633 /// Those knobs that affect mode support and mode programming 634 struct dml_mode_eval_policy_st { 635 // ------------------- 636 // Policy 637 // ------------------- 638 enum dml_mpc_use_policy MPCCombineUse[__DML_NUM_PLANES__]; /// <brief MPC Combine mode as selected by the user; used in mode check stage 639 enum dml_odm_use_policy ODMUse[__DML_NUM_PLANES__]; /// <brief ODM mode as selected by the user; used in mode check stage 640 enum dml_unbounded_requesting_policy UseUnboundedRequesting; ///< brief Unbounded request mode preference 641 enum dml_immediate_flip_requirement ImmediateFlipRequirement[__DML_NUM_PLANES__]; /// <brief Is immediate flip a requirement for this plane. When host vm is present iflip is needed regardless 642 enum dml_prefetch_modes AllowForPStateChangeOrStutterInVBlank[__DML_NUM_PLANES__]; /// <brief To specify if the DML should calculate the values for support different pwr saving features (cstate; pstate; etc.) during vblank 643 644 enum dml_prefetch_modes AllowForPStateChangeOrStutterInVBlankFinal; 645 bool UseOnlyMaxPrefetchModes; 646 dml_bool_t UseMinimumRequiredDCFCLK; //<brief When set the mode_check stage will figure the min DCFCLK freq to support the given display configuration. User can tell use the output DCFCLK for mode programming. 647 dml_bool_t DRAMClockChangeRequirementFinal; 648 dml_bool_t FCLKChangeRequirementFinal; 649 dml_bool_t USRRetrainingRequiredFinal; 650 dml_bool_t EnhancedPrefetchScheduleAccelerationFinal; 651 652 dml_bool_t NomDETInKByteOverrideEnable; //<brief Nomimal DET buffer size for a pipe. If this size fit the required 2 swathes; DML will use this DET size 653 dml_uint_t NomDETInKByteOverrideValue; 654 655 dml_bool_t DCCProgrammingAssumesScanDirectionUnknownFinal; 656 dml_bool_t SynchronizeTimingsFinal; 657 dml_bool_t SynchronizeDRRDisplaysForUCLKPStateChangeFinal; 658 dml_bool_t AssumeModeSupportAtMaxPwrStateEvenDRAMClockChangeNotSupported; //<brief if set; the mode support will say mode is supported even though the DRAM clock change is not support (assuming the soc will be stay in max power state) 659 dml_bool_t AssumeModeSupportAtMaxPwrStateEvenFClockChangeNotSupported; //<brief if set; the mode support will say mode is supported even though the Fabric clock change is not support (assuming the soc will be stay in max power state 660 }; 661 662 /// @brief Contains important information after the mode support steps. Also why a mode is not supported. 663 struct dml_mode_support_info_st { 664 //----------------- 665 // Mode Support Information 666 //----------------- 667 dml_bool_t ModeIsSupported; //<brief Is the mode support any voltage and combine setting 668 dml_bool_t ImmediateFlipSupport; //<brief Means mode support immediate flip at the max combine setting; determine in mode support and used in mode programming 669 dml_uint_t MaximumMPCCombine; //<brief If using MPC combine helps the power saving support; then this will be set to 1 670 dml_bool_t UnboundedRequestEnabled; 671 dml_uint_t CompressedBufferSizeInkByte; 672 673 /* Mode Support Reason */ 674 dml_bool_t WritebackLatencySupport; 675 dml_bool_t ScaleRatioAndTapsSupport; 676 dml_bool_t SourceFormatPixelAndScanSupport; 677 dml_bool_t MPCCombineMethodIncompatible; 678 dml_bool_t P2IWith420; 679 dml_bool_t DSCOnlyIfNecessaryWithBPP; 680 dml_bool_t DSC422NativeNotSupported; 681 dml_bool_t LinkRateDoesNotMatchDPVersion; 682 dml_bool_t LinkRateForMultistreamNotIndicated; 683 dml_bool_t BPPForMultistreamNotIndicated; 684 dml_bool_t MultistreamWithHDMIOreDP; 685 dml_bool_t MSOOrODMSplitWithNonDPLink; 686 dml_bool_t NotEnoughLanesForMSO; 687 dml_bool_t NumberOfOTGSupport; 688 dml_bool_t NumberOfHDMIFRLSupport; 689 dml_bool_t NumberOfDP2p0Support; 690 dml_bool_t NonsupportedDSCInputBPC; 691 dml_bool_t WritebackScaleRatioAndTapsSupport; 692 dml_bool_t CursorSupport; 693 dml_bool_t PitchSupport; 694 dml_bool_t ViewportExceedsSurface; 695 dml_bool_t ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified; 696 dml_bool_t ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe; 697 dml_bool_t InvalidCombinationOfMALLUseForPStateAndStaticScreen; 698 dml_bool_t InvalidCombinationOfMALLUseForPState; 699 dml_bool_t ExceededMALLSize; 700 dml_bool_t EnoughWritebackUnits; 701 702 dml_bool_t ExceededMultistreamSlots; 703 dml_bool_t ODMCombineTwoToOneSupportCheckOK; 704 dml_bool_t ODMCombineFourToOneSupportCheckOK; 705 dml_bool_t NotEnoughDSCUnits; 706 dml_bool_t NotEnoughDSCSlices; 707 dml_bool_t PixelsPerLinePerDSCUnitSupport; 708 dml_bool_t DSCCLKRequiredMoreThanSupported; 709 dml_bool_t DTBCLKRequiredMoreThanSupported; 710 dml_bool_t LinkCapacitySupport; 711 712 dml_bool_t ROBSupport[2]; 713 dml_bool_t PTEBufferSizeNotExceeded[2]; 714 dml_bool_t DCCMetaBufferSizeNotExceeded[2]; 715 dml_bool_t TotalVerticalActiveBandwidthSupport[2]; 716 enum dml_dram_clock_change_support DRAMClockChangeSupport[2]; 717 dml_float_t ActiveDRAMClockChangeLatencyMargin[__DML_NUM_PLANES__]; 718 dml_uint_t SubViewportLinesNeededInMALL[__DML_NUM_PLANES__]; 719 enum dml_fclock_change_support FCLKChangeSupport[2]; 720 dml_bool_t USRRetrainingSupport[2]; 721 dml_bool_t VActiveBandwithSupport[2]; 722 dml_bool_t PrefetchSupported[2]; 723 dml_bool_t DynamicMetadataSupported[2]; 724 dml_bool_t VRatioInPrefetchSupported[2]; 725 dml_bool_t DISPCLK_DPPCLK_Support[2]; 726 dml_bool_t TotalAvailablePipesSupport[2]; 727 dml_bool_t ModeSupport[2]; 728 dml_bool_t ViewportSizeSupport[2]; 729 dml_bool_t ImmediateFlipSupportedForState[2]; 730 731 dml_bool_t NoTimeForPrefetch[2][__DML_NUM_PLANES__]; 732 dml_bool_t NoTimeForDynamicMetadata[2][__DML_NUM_PLANES__]; 733 734 dml_bool_t MPCCombineEnable[__DML_NUM_PLANES__]; /// <brief Indicate if the MPC Combine enable in the given state and optimize mpc combine setting 735 enum dml_odm_mode ODMMode[__DML_NUM_PLANES__]; /// <brief ODM mode that is chosen in the mode check stage and will be used in mode programming stage 736 dml_uint_t DPPPerSurface[__DML_NUM_PLANES__]; /// <brief How many DPPs are needed drive the surface to output. If MPCC or ODMC could be 2 or 4. 737 dml_bool_t DSCEnabled[__DML_NUM_PLANES__]; /// <brief Indicate if the DSC is actually required; used in mode_programming 738 dml_bool_t FECEnabled[__DML_NUM_PLANES__]; /// <brief Indicate if the FEC is actually required 739 dml_uint_t NumberOfDSCSlices[__DML_NUM_PLANES__]; /// <brief Indicate how many slices needed to support the given mode 740 741 dml_float_t OutputBpp[__DML_NUM_PLANES__]; 742 enum dml_output_type_and_rate__type OutputType[__DML_NUM_PLANES__]; 743 enum dml_output_type_and_rate__rate OutputRate[__DML_NUM_PLANES__]; 744 745 dml_float_t AlignedDCCMetaPitchY[__DML_NUM_PLANES__]; /// <brief Pitch value that is aligned to tiling setting 746 dml_float_t AlignedDCCMetaPitchC[__DML_NUM_PLANES__]; 747 dml_float_t AlignedYPitch[__DML_NUM_PLANES__]; 748 dml_float_t AlignedCPitch[__DML_NUM_PLANES__]; 749 dml_float_t MaxTotalVerticalActiveAvailableBandwidth[2]; /// <brief nominal bw available for display 750 }; // dml_mode_support_info_st 751 752 /// @brief Treat this as the intermediate values and outputs of mode check function. User can query the content of the struct to know more about the result of mode evaluation. 753 struct mode_support_st { 754 struct ip_params_st ip; 755 struct soc_bounding_box_st soc; 756 struct soc_state_bounding_box_st state; //<brief Per-state bbox values; only 1 state per compute 757 struct dml_mode_eval_policy_st policy; 758 759 dml_uint_t state_idx; //<brief The power state idx for the power state under this computation 760 dml_uint_t max_state_idx; //<brief The MAX power state idx 761 struct soc_state_bounding_box_st max_state; //<brief The MAX power state; some algo needs to know the max state info to determine if 762 struct dml_display_cfg_st cache_display_cfg; // <brief A copy of the current display cfg in consideration 763 764 // Physical info; only using for programming 765 dml_uint_t num_active_planes; // <brief As determined by either e2e_pipe_param or display_cfg 766 767 // Calculated Clocks 768 dml_float_t RequiredDISPCLK[2]; /// <brief Required DISPCLK; depends on pixel rate; odm mode etc. 769 dml_float_t RequiredDPPCLKThisState[__DML_NUM_PLANES__]; 770 dml_float_t DCFCLKState[2]; /// <brief recommended DCFCLK freq; calculated by DML. If UseMinimumRequiredDCFCLK is not set; then it will be just the state DCFCLK; else it will min DCFCLK for support 771 dml_float_t RequiredDISPCLKPerSurface[2][__DML_NUM_PLANES__]; 772 dml_float_t RequiredDPPCLKPerSurface[2][__DML_NUM_PLANES__]; 773 774 dml_float_t FabricClock; /// <brief Basically just the clock freq at the min (or given) state 775 dml_float_t DRAMSpeed; /// <brief Basically just the clock freq at the min (or given) state 776 dml_float_t SOCCLK; /// <brief Basically just the clock freq at the min (or given) state 777 dml_float_t DCFCLK; /// <brief Basically just the clock freq at the min (or given) state and max combine setting 778 dml_float_t GlobalDPPCLK; /// <brief the Max DPPCLK freq out of all pipes 779 780 // ---------------------------------- 781 // Mode Support Info and fail reason 782 // ---------------------------------- 783 struct dml_mode_support_info_st support; 784 785 // These are calculated before the ModeSupport and ModeProgram step 786 // They represent the bound for the return buffer sizing 787 dml_uint_t MaxTotalDETInKByte; 788 dml_uint_t NomDETInKByte; 789 dml_uint_t MinCompressedBufferSizeInKByte; 790 791 // Info obtained at the end of mode support calculations 792 // The reported info is at the "optimal" state and combine setting 793 dml_float_t ReturnBW; 794 dml_float_t ReturnDRAMBW; 795 dml_uint_t DETBufferSizeInKByte[__DML_NUM_PLANES__]; // <brief Recommended DET size configuration for this plane. All pipes under this plane should program the DET buffer size to the calculated value. 796 dml_uint_t DETBufferSizeY[__DML_NUM_PLANES__]; 797 dml_uint_t DETBufferSizeC[__DML_NUM_PLANES__]; 798 dml_uint_t SwathHeightY[__DML_NUM_PLANES__]; 799 dml_uint_t SwathHeightC[__DML_NUM_PLANES__]; 800 801 // ---------------------------------- 802 // Intermediates/Informational 803 // ---------------------------------- 804 dml_uint_t TotImmediateFlipBytes; 805 dml_bool_t DCCEnabledInAnySurface; 806 dml_float_t WritebackRequiredDISPCLK; 807 dml_float_t TimeCalc; 808 dml_float_t TWait; 809 810 dml_uint_t SwathWidthYAllStates[2][__DML_NUM_PLANES__]; 811 dml_uint_t SwathWidthCAllStates[2][__DML_NUM_PLANES__]; 812 dml_uint_t SwathHeightYAllStates[2][__DML_NUM_PLANES__]; 813 dml_uint_t SwathHeightCAllStates[2][__DML_NUM_PLANES__]; 814 dml_uint_t SwathWidthYThisState[__DML_NUM_PLANES__]; 815 dml_uint_t SwathWidthCThisState[__DML_NUM_PLANES__]; 816 dml_uint_t SwathHeightYThisState[__DML_NUM_PLANES__]; 817 dml_uint_t SwathHeightCThisState[__DML_NUM_PLANES__]; 818 dml_uint_t DETBufferSizeInKByteAllStates[2][__DML_NUM_PLANES__]; 819 dml_uint_t DETBufferSizeYAllStates[2][__DML_NUM_PLANES__]; 820 dml_uint_t DETBufferSizeCAllStates[2][__DML_NUM_PLANES__]; 821 dml_bool_t UnboundedRequestEnabledAllStates[2]; 822 dml_uint_t CompressedBufferSizeInkByteAllStates[2]; 823 dml_bool_t UnboundedRequestEnabledThisState; 824 dml_uint_t CompressedBufferSizeInkByteThisState; 825 dml_uint_t DETBufferSizeInKByteThisState[__DML_NUM_PLANES__]; 826 dml_uint_t DETBufferSizeYThisState[__DML_NUM_PLANES__]; 827 dml_uint_t DETBufferSizeCThisState[__DML_NUM_PLANES__]; 828 dml_float_t VRatioPreY[2][__DML_NUM_PLANES__]; 829 dml_float_t VRatioPreC[2][__DML_NUM_PLANES__]; 830 dml_uint_t swath_width_luma_ub_all_states[2][__DML_NUM_PLANES__]; 831 dml_uint_t swath_width_chroma_ub_all_states[2][__DML_NUM_PLANES__]; 832 dml_uint_t swath_width_luma_ub_this_state[__DML_NUM_PLANES__]; 833 dml_uint_t swath_width_chroma_ub_this_state[__DML_NUM_PLANES__]; 834 dml_uint_t RequiredSlots[__DML_NUM_PLANES__]; 835 dml_uint_t PDEAndMetaPTEBytesPerFrame[2][__DML_NUM_PLANES__]; 836 dml_uint_t MetaRowBytes[2][__DML_NUM_PLANES__]; 837 dml_uint_t DPTEBytesPerRow[2][__DML_NUM_PLANES__]; 838 dml_uint_t PrefetchLinesY[2][__DML_NUM_PLANES__]; 839 dml_uint_t PrefetchLinesC[2][__DML_NUM_PLANES__]; 840 dml_uint_t MaxNumSwY[__DML_NUM_PLANES__]; /// <brief Max number of swath for prefetch 841 dml_uint_t MaxNumSwC[__DML_NUM_PLANES__]; /// <brief Max number of swath for prefetch 842 dml_uint_t PrefillY[__DML_NUM_PLANES__]; 843 dml_uint_t PrefillC[__DML_NUM_PLANES__]; 844 845 dml_uint_t PrefetchLinesYThisState[__DML_NUM_PLANES__]; 846 dml_uint_t PrefetchLinesCThisState[__DML_NUM_PLANES__]; 847 dml_uint_t DPTEBytesPerRowThisState[__DML_NUM_PLANES__]; 848 dml_uint_t PDEAndMetaPTEBytesPerFrameThisState[__DML_NUM_PLANES__]; 849 dml_uint_t MetaRowBytesThisState[__DML_NUM_PLANES__]; 850 dml_bool_t use_one_row_for_frame[2][__DML_NUM_PLANES__]; 851 dml_bool_t use_one_row_for_frame_flip[2][__DML_NUM_PLANES__]; 852 dml_bool_t use_one_row_for_frame_this_state[__DML_NUM_PLANES__]; 853 dml_bool_t use_one_row_for_frame_flip_this_state[__DML_NUM_PLANES__]; 854 855 dml_float_t LineTimesForPrefetch[__DML_NUM_PLANES__]; 856 dml_float_t LinesForMetaPTE[__DML_NUM_PLANES__]; 857 dml_float_t LinesForMetaAndDPTERow[__DML_NUM_PLANES__]; 858 dml_float_t SwathWidthYSingleDPP[__DML_NUM_PLANES__]; 859 dml_float_t SwathWidthCSingleDPP[__DML_NUM_PLANES__]; 860 dml_uint_t BytePerPixelY[__DML_NUM_PLANES__]; 861 dml_uint_t BytePerPixelC[__DML_NUM_PLANES__]; 862 dml_float_t BytePerPixelInDETY[__DML_NUM_PLANES__]; 863 dml_float_t BytePerPixelInDETC[__DML_NUM_PLANES__]; 864 865 dml_uint_t Read256BlockHeightY[__DML_NUM_PLANES__]; 866 dml_uint_t Read256BlockWidthY[__DML_NUM_PLANES__]; 867 dml_uint_t Read256BlockHeightC[__DML_NUM_PLANES__]; 868 dml_uint_t Read256BlockWidthC[__DML_NUM_PLANES__]; 869 dml_uint_t MacroTileHeightY[__DML_NUM_PLANES__]; 870 dml_uint_t MacroTileHeightC[__DML_NUM_PLANES__]; 871 dml_uint_t MacroTileWidthY[__DML_NUM_PLANES__]; 872 dml_uint_t MacroTileWidthC[__DML_NUM_PLANES__]; 873 dml_float_t PSCL_FACTOR[__DML_NUM_PLANES__]; 874 dml_float_t PSCL_FACTOR_CHROMA[__DML_NUM_PLANES__]; 875 dml_float_t MaximumSwathWidthLuma[__DML_NUM_PLANES__]; 876 dml_float_t MaximumSwathWidthChroma[__DML_NUM_PLANES__]; 877 dml_float_t Tno_bw[__DML_NUM_PLANES__]; 878 dml_float_t DestinationLinesToRequestVMInImmediateFlip[__DML_NUM_PLANES__]; 879 dml_float_t DestinationLinesToRequestRowInImmediateFlip[__DML_NUM_PLANES__]; 880 dml_float_t WritebackDelayTime[__DML_NUM_PLANES__]; 881 dml_uint_t dpte_group_bytes[__DML_NUM_PLANES__]; 882 dml_uint_t dpte_row_height[__DML_NUM_PLANES__]; 883 dml_uint_t dpte_row_height_chroma[__DML_NUM_PLANES__]; 884 dml_uint_t meta_row_height[__DML_NUM_PLANES__]; 885 dml_uint_t meta_row_height_chroma[__DML_NUM_PLANES__]; 886 dml_float_t UrgLatency; 887 dml_float_t UrgentBurstFactorCursor[__DML_NUM_PLANES__]; 888 dml_float_t UrgentBurstFactorCursorPre[__DML_NUM_PLANES__]; 889 dml_float_t UrgentBurstFactorLuma[__DML_NUM_PLANES__]; 890 dml_float_t UrgentBurstFactorLumaPre[__DML_NUM_PLANES__]; 891 dml_float_t UrgentBurstFactorChroma[__DML_NUM_PLANES__]; 892 dml_float_t UrgentBurstFactorChromaPre[__DML_NUM_PLANES__]; 893 dml_float_t MaximumSwathWidthInLineBufferLuma; 894 dml_float_t MaximumSwathWidthInLineBufferChroma; 895 dml_float_t ExtraLatency; 896 897 // Backend 898 dml_bool_t RequiresDSC[__DML_NUM_PLANES__]; 899 dml_bool_t RequiresFEC[__DML_NUM_PLANES__]; 900 dml_float_t OutputBppPerState[__DML_NUM_PLANES__]; 901 dml_uint_t DSCDelayPerState[__DML_NUM_PLANES__]; 902 enum dml_output_type_and_rate__type OutputTypePerState[__DML_NUM_PLANES__]; 903 enum dml_output_type_and_rate__rate OutputRatePerState[__DML_NUM_PLANES__]; 904 905 // Bandwidth Related Info 906 dml_float_t BandwidthAvailableForImmediateFlip; 907 dml_float_t ReadBandwidthLuma[__DML_NUM_PLANES__]; 908 dml_float_t ReadBandwidthChroma[__DML_NUM_PLANES__]; 909 dml_float_t WriteBandwidth[__DML_NUM_PLANES__]; 910 dml_float_t RequiredPrefetchPixelDataBWLuma[__DML_NUM_PLANES__]; 911 dml_float_t RequiredPrefetchPixelDataBWChroma[__DML_NUM_PLANES__]; 912 dml_float_t cursor_bw[__DML_NUM_PLANES__]; 913 dml_float_t cursor_bw_pre[__DML_NUM_PLANES__]; 914 dml_float_t prefetch_vmrow_bw[__DML_NUM_PLANES__]; 915 dml_float_t final_flip_bw[__DML_NUM_PLANES__]; 916 dml_float_t meta_row_bandwidth_this_state[__DML_NUM_PLANES__]; 917 dml_float_t dpte_row_bandwidth_this_state[__DML_NUM_PLANES__]; 918 dml_float_t ReturnBWPerState[2]; 919 dml_float_t ReturnDRAMBWPerState[2]; 920 dml_float_t meta_row_bandwidth[2][__DML_NUM_PLANES__]; 921 dml_float_t dpte_row_bandwidth[2][__DML_NUM_PLANES__]; 922 923 // Something that should be feedback to caller 924 enum dml_odm_mode ODMModePerState[__DML_NUM_PLANES__]; 925 enum dml_odm_mode ODMModeThisState[__DML_NUM_PLANES__]; 926 dml_uint_t SurfaceSizeInMALL[__DML_NUM_PLANES__]; 927 dml_uint_t NoOfDPP[2][__DML_NUM_PLANES__]; 928 dml_uint_t NoOfDPPThisState[__DML_NUM_PLANES__]; 929 dml_bool_t MPCCombine[2][__DML_NUM_PLANES__]; 930 dml_bool_t MPCCombineThisState[__DML_NUM_PLANES__]; 931 dml_float_t ProjectedDCFCLKDeepSleep[2]; 932 dml_float_t MinDPPCLKUsingSingleDPP[__DML_NUM_PLANES__]; 933 dml_bool_t SingleDPPViewportSizeSupportPerSurface[__DML_NUM_PLANES__]; 934 dml_bool_t ImmediateFlipSupportedForPipe[__DML_NUM_PLANES__]; 935 dml_bool_t NotUrgentLatencyHiding[__DML_NUM_PLANES__]; 936 dml_bool_t NotUrgentLatencyHidingPre[__DML_NUM_PLANES__]; 937 dml_bool_t PTEBufferSizeNotExceededPerState[__DML_NUM_PLANES__]; 938 dml_bool_t DCCMetaBufferSizeNotExceededPerState[__DML_NUM_PLANES__]; 939 dml_uint_t PrefetchMode[__DML_NUM_PLANES__]; 940 dml_uint_t TotalNumberOfActiveDPP[2]; 941 dml_uint_t TotalNumberOfSingleDPPSurfaces[2]; 942 dml_uint_t TotalNumberOfDCCActiveDPP[2]; 943 944 dml_uint_t SubViewportLinesNeededInMALL[__DML_NUM_PLANES__]; 945 946 }; // mode_support_st 947 948 /// @brief A mega structure that houses various info for model programming step. 949 struct mode_program_st { 950 951 //------------- 952 // Intermediate/Informational 953 //------------- 954 dml_float_t UrgentLatency; 955 dml_float_t UrgentLatencyWithUSRRetraining; 956 dml_uint_t VInitPreFillY[__DML_NUM_PLANES__]; 957 dml_uint_t VInitPreFillC[__DML_NUM_PLANES__]; 958 dml_uint_t MaxNumSwathY[__DML_NUM_PLANES__]; 959 dml_uint_t MaxNumSwathC[__DML_NUM_PLANES__]; 960 961 dml_float_t BytePerPixelDETY[__DML_NUM_PLANES__]; 962 dml_float_t BytePerPixelDETC[__DML_NUM_PLANES__]; 963 dml_uint_t BytePerPixelY[__DML_NUM_PLANES__]; 964 dml_uint_t BytePerPixelC[__DML_NUM_PLANES__]; 965 dml_uint_t SwathWidthY[__DML_NUM_PLANES__]; 966 dml_uint_t SwathWidthC[__DML_NUM_PLANES__]; 967 dml_uint_t SwathWidthSingleDPPY[__DML_NUM_PLANES__]; 968 dml_uint_t SwathWidthSingleDPPC[__DML_NUM_PLANES__]; 969 dml_float_t ReadBandwidthSurfaceLuma[__DML_NUM_PLANES__]; 970 dml_float_t ReadBandwidthSurfaceChroma[__DML_NUM_PLANES__]; 971 972 dml_uint_t PixelPTEBytesPerRow[__DML_NUM_PLANES__]; 973 dml_uint_t PDEAndMetaPTEBytesFrame[__DML_NUM_PLANES__]; 974 dml_uint_t MetaRowByte[__DML_NUM_PLANES__]; 975 dml_uint_t PrefetchSourceLinesY[__DML_NUM_PLANES__]; 976 dml_float_t RequiredPrefetchPixDataBWLuma[__DML_NUM_PLANES__]; 977 dml_float_t RequiredPrefetchPixDataBWChroma[__DML_NUM_PLANES__]; 978 dml_uint_t PrefetchSourceLinesC[__DML_NUM_PLANES__]; 979 dml_float_t PSCL_THROUGHPUT[__DML_NUM_PLANES__]; 980 dml_float_t PSCL_THROUGHPUT_CHROMA[__DML_NUM_PLANES__]; 981 dml_uint_t DSCDelay[__DML_NUM_PLANES__]; 982 dml_float_t DPPCLKUsingSingleDPP[__DML_NUM_PLANES__]; 983 984 dml_uint_t MacroTileWidthY[__DML_NUM_PLANES__]; 985 dml_uint_t MacroTileWidthC[__DML_NUM_PLANES__]; 986 dml_uint_t BlockHeight256BytesY[__DML_NUM_PLANES__]; 987 dml_uint_t BlockHeight256BytesC[__DML_NUM_PLANES__]; 988 dml_uint_t BlockWidth256BytesY[__DML_NUM_PLANES__]; 989 dml_uint_t BlockWidth256BytesC[__DML_NUM_PLANES__]; 990 991 dml_uint_t BlockHeightY[__DML_NUM_PLANES__]; 992 dml_uint_t BlockHeightC[__DML_NUM_PLANES__]; 993 dml_uint_t BlockWidthY[__DML_NUM_PLANES__]; 994 dml_uint_t BlockWidthC[__DML_NUM_PLANES__]; 995 996 dml_uint_t SurfaceSizeInTheMALL[__DML_NUM_PLANES__]; 997 dml_float_t VRatioPrefetchY[__DML_NUM_PLANES__]; 998 dml_float_t VRatioPrefetchC[__DML_NUM_PLANES__]; 999 dml_float_t Tno_bw[__DML_NUM_PLANES__]; 1000 dml_float_t final_flip_bw[__DML_NUM_PLANES__]; 1001 dml_float_t prefetch_vmrow_bw[__DML_NUM_PLANES__]; 1002 dml_float_t cursor_bw[__DML_NUM_PLANES__]; 1003 dml_float_t cursor_bw_pre[__DML_NUM_PLANES__]; 1004 dml_float_t WritebackDelay[__DML_NUM_PLANES__]; 1005 dml_uint_t dpte_row_height[__DML_NUM_PLANES__]; 1006 dml_uint_t dpte_row_height_linear[__DML_NUM_PLANES__]; 1007 dml_uint_t meta_req_width[__DML_NUM_PLANES__]; 1008 dml_uint_t meta_req_height[__DML_NUM_PLANES__]; 1009 dml_uint_t meta_row_width[__DML_NUM_PLANES__]; 1010 dml_uint_t meta_row_height[__DML_NUM_PLANES__]; 1011 dml_uint_t dpte_row_width_luma_ub[__DML_NUM_PLANES__]; 1012 dml_uint_t dpte_row_width_chroma_ub[__DML_NUM_PLANES__]; 1013 dml_uint_t dpte_row_height_chroma[__DML_NUM_PLANES__]; 1014 dml_uint_t dpte_row_height_linear_chroma[__DML_NUM_PLANES__]; 1015 dml_uint_t meta_req_width_chroma[__DML_NUM_PLANES__]; 1016 dml_uint_t meta_req_height_chroma[__DML_NUM_PLANES__]; 1017 dml_uint_t meta_row_width_chroma[__DML_NUM_PLANES__]; 1018 dml_uint_t meta_row_height_chroma[__DML_NUM_PLANES__]; 1019 dml_uint_t vm_group_bytes[__DML_NUM_PLANES__]; 1020 dml_uint_t dpte_group_bytes[__DML_NUM_PLANES__]; 1021 dml_float_t meta_row_bw[__DML_NUM_PLANES__]; 1022 dml_float_t dpte_row_bw[__DML_NUM_PLANES__]; 1023 dml_float_t UrgBurstFactorCursor[__DML_NUM_PLANES__]; 1024 dml_float_t UrgBurstFactorCursorPre[__DML_NUM_PLANES__]; 1025 dml_float_t UrgBurstFactorLuma[__DML_NUM_PLANES__]; 1026 dml_float_t UrgBurstFactorLumaPre[__DML_NUM_PLANES__]; 1027 dml_float_t UrgBurstFactorChroma[__DML_NUM_PLANES__]; 1028 dml_float_t UrgBurstFactorChromaPre[__DML_NUM_PLANES__]; 1029 1030 dml_uint_t swath_width_luma_ub[__DML_NUM_PLANES__]; 1031 dml_uint_t swath_width_chroma_ub[__DML_NUM_PLANES__]; 1032 dml_uint_t PixelPTEReqWidthY[__DML_NUM_PLANES__]; 1033 dml_uint_t PixelPTEReqHeightY[__DML_NUM_PLANES__]; 1034 dml_uint_t PTERequestSizeY[__DML_NUM_PLANES__]; 1035 dml_uint_t PixelPTEReqWidthC[__DML_NUM_PLANES__]; 1036 dml_uint_t PixelPTEReqHeightC[__DML_NUM_PLANES__]; 1037 dml_uint_t PTERequestSizeC[__DML_NUM_PLANES__]; 1038 1039 dml_float_t Tdmdl_vm[__DML_NUM_PLANES__]; 1040 dml_float_t Tdmdl[__DML_NUM_PLANES__]; 1041 dml_float_t TSetup[__DML_NUM_PLANES__]; 1042 dml_uint_t dpde0_bytes_per_frame_ub_l[__DML_NUM_PLANES__]; 1043 dml_uint_t meta_pte_bytes_per_frame_ub_l[__DML_NUM_PLANES__]; 1044 dml_uint_t dpde0_bytes_per_frame_ub_c[__DML_NUM_PLANES__]; 1045 dml_uint_t meta_pte_bytes_per_frame_ub_c[__DML_NUM_PLANES__]; 1046 1047 dml_bool_t UnboundedRequestEnabled; 1048 dml_uint_t compbuf_reserved_space_64b; 1049 dml_uint_t compbuf_reserved_space_zs; 1050 dml_uint_t CompressedBufferSizeInkByte; 1051 1052 dml_bool_t NoUrgentLatencyHiding[__DML_NUM_PLANES__]; 1053 dml_bool_t NoUrgentLatencyHidingPre[__DML_NUM_PLANES__]; 1054 dml_float_t UrgentExtraLatency; 1055 dml_bool_t PrefetchAndImmediateFlipSupported; 1056 dml_float_t TotalDataReadBandwidth; 1057 dml_float_t BandwidthAvailableForImmediateFlip; 1058 dml_bool_t NotEnoughTimeForDynamicMetadata[__DML_NUM_PLANES__]; 1059 1060 dml_float_t ReadBandwidthLuma[__DML_NUM_PLANES__]; 1061 dml_float_t ReadBandwidthChroma[__DML_NUM_PLANES__]; 1062 1063 dml_float_t total_dcn_read_bw_with_flip; 1064 dml_float_t total_dcn_read_bw_with_flip_no_urgent_burst; 1065 dml_float_t TotalDataReadBandwidthNotIncludingMALLPrefetch; 1066 dml_float_t total_dcn_read_bw_with_flip_not_including_MALL_prefetch; 1067 dml_float_t non_urgent_total_dcn_read_bw_with_flip; 1068 dml_float_t non_urgent_total_dcn_read_bw_with_flip_not_including_MALL_prefetch; 1069 1070 dml_bool_t use_one_row_for_frame[__DML_NUM_PLANES__]; 1071 dml_bool_t use_one_row_for_frame_flip[__DML_NUM_PLANES__]; 1072 1073 dml_float_t TCalc; 1074 dml_uint_t TotImmediateFlipBytes; 1075 1076 // ------------------- 1077 // Output 1078 // ------------------- 1079 dml_uint_t pipe_plane[__DML_NUM_PLANES__]; // <brief used mainly by dv to map the pipe inst to plane index within DML core; the plane idx of a pipe 1080 dml_uint_t num_active_pipes; 1081 1082 dml_bool_t NoTimeToPrefetch[__DML_NUM_PLANES__]; /// <brief Prefetch schedule calculation result 1083 1084 // Support 1085 dml_uint_t PrefetchMode[__DML_NUM_PLANES__]; /// <brief prefetch mode used for prefetch support check in mode programming step 1086 dml_bool_t PrefetchModeSupported; /// <brief Is the prefetch mode (bandwidth and latency) supported 1087 dml_bool_t ImmediateFlipSupported; 1088 dml_bool_t ImmediateFlipSupportedForPipe[__DML_NUM_PLANES__]; 1089 1090 // Clock 1091 dml_float_t Dcfclk; 1092 dml_float_t Dispclk; /// <brief dispclk being used in mode programming 1093 dml_float_t Dppclk[__DML_NUM_PLANES__]; /// <brief dppclk being used in mode programming 1094 dml_float_t WritebackDISPCLK; 1095 dml_float_t GlobalDPPCLK; 1096 1097 //@ brief These "calculated" dispclk and dppclk clocks are calculated in the mode programming step. 1098 // Depends on the dml_clk_cfg_st option; these calculated values may not used in subsequent calculation. 1099 // Possible DV usage: Calculated values fetched by test once after mode_programming step and then possibly 1100 // use the values as min and adjust the actual freq used for the 2nd pass 1101 dml_float_t Dispclk_calculated; 1102 dml_float_t Dppclk_calculated[__DML_NUM_PLANES__]; 1103 1104 dml_float_t DSCCLK_calculated[__DML_NUM_PLANES__]; //< brief Required DSCCLK freq. Backend; not used in any subsequent calculations for now 1105 dml_float_t DCFCLKDeepSleep; 1106 1107 // ARB reg 1108 dml_bool_t DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE; 1109 struct Watermarks Watermark; 1110 1111 // DCC compression control 1112 dml_uint_t DCCYMaxUncompressedBlock[__DML_NUM_PLANES__]; 1113 dml_uint_t DCCYMaxCompressedBlock[__DML_NUM_PLANES__]; 1114 dml_uint_t DCCYIndependentBlock[__DML_NUM_PLANES__]; 1115 dml_uint_t DCCCMaxUncompressedBlock[__DML_NUM_PLANES__]; 1116 dml_uint_t DCCCMaxCompressedBlock[__DML_NUM_PLANES__]; 1117 dml_uint_t DCCCIndependentBlock[__DML_NUM_PLANES__]; 1118 1119 // Stutter Efficiency 1120 dml_float_t StutterEfficiency; 1121 dml_float_t StutterEfficiencyNotIncludingVBlank; 1122 dml_uint_t NumberOfStutterBurstsPerFrame; 1123 dml_float_t Z8StutterEfficiency; 1124 dml_uint_t Z8NumberOfStutterBurstsPerFrame; 1125 dml_float_t Z8StutterEfficiencyNotIncludingVBlank; 1126 dml_float_t StutterPeriod; 1127 dml_float_t Z8StutterEfficiencyBestCase; 1128 dml_uint_t Z8NumberOfStutterBurstsPerFrameBestCase; 1129 dml_float_t Z8StutterEfficiencyNotIncludingVBlankBestCase; 1130 dml_float_t StutterPeriodBestCase; 1131 1132 // DLG TTU reg 1133 dml_float_t MIN_DST_Y_NEXT_START[__DML_NUM_PLANES__]; 1134 dml_bool_t VREADY_AT_OR_AFTER_VSYNC[__DML_NUM_PLANES__]; 1135 dml_uint_t DSTYAfterScaler[__DML_NUM_PLANES__]; 1136 dml_uint_t DSTXAfterScaler[__DML_NUM_PLANES__]; 1137 dml_float_t DestinationLinesForPrefetch[__DML_NUM_PLANES__]; 1138 dml_float_t DestinationLinesToRequestVMInVBlank[__DML_NUM_PLANES__]; 1139 dml_float_t DestinationLinesToRequestRowInVBlank[__DML_NUM_PLANES__]; 1140 dml_float_t DestinationLinesToRequestVMInImmediateFlip[__DML_NUM_PLANES__]; 1141 dml_float_t DestinationLinesToRequestRowInImmediateFlip[__DML_NUM_PLANES__]; 1142 dml_float_t MinTTUVBlank[__DML_NUM_PLANES__]; 1143 dml_float_t DisplayPipeLineDeliveryTimeLuma[__DML_NUM_PLANES__]; 1144 dml_float_t DisplayPipeLineDeliveryTimeChroma[__DML_NUM_PLANES__]; 1145 dml_float_t DisplayPipeLineDeliveryTimeLumaPrefetch[__DML_NUM_PLANES__]; 1146 dml_float_t DisplayPipeLineDeliveryTimeChromaPrefetch[__DML_NUM_PLANES__]; 1147 dml_float_t DisplayPipeRequestDeliveryTimeLuma[__DML_NUM_PLANES__]; 1148 dml_float_t DisplayPipeRequestDeliveryTimeChroma[__DML_NUM_PLANES__]; 1149 dml_float_t DisplayPipeRequestDeliveryTimeLumaPrefetch[__DML_NUM_PLANES__]; 1150 dml_float_t DisplayPipeRequestDeliveryTimeChromaPrefetch[__DML_NUM_PLANES__]; 1151 dml_float_t CursorRequestDeliveryTime[__DML_NUM_PLANES__]; 1152 dml_float_t CursorRequestDeliveryTimePrefetch[__DML_NUM_PLANES__]; 1153 1154 dml_float_t DST_Y_PER_PTE_ROW_NOM_L[__DML_NUM_PLANES__]; 1155 dml_float_t DST_Y_PER_PTE_ROW_NOM_C[__DML_NUM_PLANES__]; 1156 dml_float_t DST_Y_PER_META_ROW_NOM_L[__DML_NUM_PLANES__]; 1157 dml_float_t DST_Y_PER_META_ROW_NOM_C[__DML_NUM_PLANES__]; 1158 dml_float_t TimePerMetaChunkNominal[__DML_NUM_PLANES__]; 1159 dml_float_t TimePerChromaMetaChunkNominal[__DML_NUM_PLANES__]; 1160 dml_float_t TimePerMetaChunkVBlank[__DML_NUM_PLANES__]; 1161 dml_float_t TimePerChromaMetaChunkVBlank[__DML_NUM_PLANES__]; 1162 dml_float_t TimePerMetaChunkFlip[__DML_NUM_PLANES__]; 1163 dml_float_t TimePerChromaMetaChunkFlip[__DML_NUM_PLANES__]; 1164 dml_float_t time_per_pte_group_nom_luma[__DML_NUM_PLANES__]; 1165 dml_float_t time_per_pte_group_nom_chroma[__DML_NUM_PLANES__]; 1166 dml_float_t time_per_pte_group_vblank_luma[__DML_NUM_PLANES__]; 1167 dml_float_t time_per_pte_group_vblank_chroma[__DML_NUM_PLANES__]; 1168 dml_float_t time_per_pte_group_flip_luma[__DML_NUM_PLANES__]; 1169 dml_float_t time_per_pte_group_flip_chroma[__DML_NUM_PLANES__]; 1170 dml_float_t TimePerVMGroupVBlank[__DML_NUM_PLANES__]; 1171 dml_float_t TimePerVMGroupFlip[__DML_NUM_PLANES__]; 1172 dml_float_t TimePerVMRequestVBlank[__DML_NUM_PLANES__]; 1173 dml_float_t TimePerVMRequestFlip[__DML_NUM_PLANES__]; 1174 1175 dml_float_t FractionOfUrgentBandwidth; 1176 dml_float_t FractionOfUrgentBandwidthImmediateFlip; 1177 1178 // RQ registers 1179 dml_bool_t PTE_BUFFER_MODE[__DML_NUM_PLANES__]; 1180 dml_uint_t BIGK_FRAGMENT_SIZE[__DML_NUM_PLANES__]; 1181 1182 dml_uint_t SubViewportLinesNeededInMALL[__DML_NUM_PLANES__]; 1183 dml_bool_t UsesMALLForStaticScreen[__DML_NUM_PLANES__]; 1184 1185 // OTG 1186 dml_uint_t VStartupMin[__DML_NUM_PLANES__]; /// <brief Minimum vstartup to meet the prefetch schedule (i.e. the prefetch solution can be found at this vstartup time); not the actual global sync vstartup pos. 1187 dml_uint_t VStartup[__DML_NUM_PLANES__]; /// <brief The vstartup value for OTG programming (will set to max vstartup; but now bounded by min(vblank_nom. actual vblank)) 1188 dml_uint_t VUpdateOffsetPix[__DML_NUM_PLANES__]; 1189 dml_uint_t VUpdateWidthPix[__DML_NUM_PLANES__]; 1190 dml_uint_t VReadyOffsetPix[__DML_NUM_PLANES__]; 1191 1192 // Latency and Support 1193 dml_float_t MaxActiveFCLKChangeLatencySupported; 1194 dml_bool_t USRRetrainingSupport; 1195 enum dml_fclock_change_support FCLKChangeSupport; 1196 enum dml_dram_clock_change_support DRAMClockChangeSupport; 1197 dml_float_t MaxActiveDRAMClockChangeLatencySupported[__DML_NUM_PLANES__]; 1198 dml_float_t WritebackAllowFCLKChangeEndPosition[__DML_NUM_PLANES__]; 1199 dml_float_t WritebackAllowDRAMClockChangeEndPosition[__DML_NUM_PLANES__]; 1200 1201 // buffer sizing 1202 dml_uint_t DETBufferSizeInKByte[__DML_NUM_PLANES__]; // <brief Recommended DET size configuration for this plane. All pipes under this plane should program the DET buffer size to the calculated value. 1203 dml_uint_t DETBufferSizeY[__DML_NUM_PLANES__]; 1204 dml_uint_t DETBufferSizeC[__DML_NUM_PLANES__]; 1205 dml_uint_t SwathHeightY[__DML_NUM_PLANES__]; 1206 dml_uint_t SwathHeightC[__DML_NUM_PLANES__]; 1207 }; // mode_program_st 1208 1209 struct soc_states_st { 1210 dml_uint_t num_states; /// <brief num of soc pwr states 1211 struct soc_state_bounding_box_st state_array[__DML_MAX_STATE_ARRAY_SIZE__]; /// <brief fixed size array that holds states struct 1212 }; 1213 1214 struct UseMinimumDCFCLK_params_st { 1215 enum dml_use_mall_for_pstate_change_mode *UseMALLForPStateChange; 1216 dml_bool_t *DRRDisplay; 1217 dml_bool_t SynchronizeDRRDisplaysForUCLKPStateChangeFinal; 1218 dml_uint_t MaxInterDCNTileRepeaters; 1219 dml_uint_t MaxPrefetchMode; 1220 dml_float_t DRAMClockChangeLatencyFinal; 1221 dml_float_t FCLKChangeLatency; 1222 dml_float_t SREnterPlusExitTime; 1223 dml_uint_t ReturnBusWidth; 1224 dml_uint_t RoundTripPingLatencyCycles; 1225 dml_uint_t ReorderingBytes; 1226 dml_uint_t PixelChunkSizeInKByte; 1227 dml_uint_t MetaChunkSize; 1228 dml_bool_t GPUVMEnable; 1229 dml_uint_t GPUVMMaxPageTableLevels; 1230 dml_bool_t HostVMEnable; 1231 dml_uint_t NumberOfActiveSurfaces; 1232 dml_uint_t HostVMMinPageSize; 1233 dml_uint_t HostVMMaxNonCachedPageTableLevels; 1234 dml_bool_t DynamicMetadataVMEnabled; 1235 dml_bool_t ImmediateFlipRequirement; 1236 dml_bool_t ProgressiveToInterlaceUnitInOPP; 1237 dml_float_t MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation; 1238 dml_float_t PercentOfIdealSDPPortBWReceivedAfterUrgLatency; 1239 dml_uint_t *VTotal; 1240 dml_uint_t *VActive; 1241 dml_uint_t *DynamicMetadataTransmittedBytes; 1242 dml_uint_t *DynamicMetadataLinesBeforeActiveRequired; 1243 dml_bool_t *Interlace; 1244 dml_float_t (*RequiredDPPCLKPerSurface)[__DML_NUM_PLANES__]; 1245 dml_float_t *RequiredDISPCLK; 1246 dml_float_t UrgLatency; 1247 dml_uint_t (*NoOfDPP)[__DML_NUM_PLANES__]; 1248 dml_float_t *ProjectedDCFCLKDeepSleep; 1249 dml_uint_t (*MaximumVStartup)[__DML_NUM_PLANES__]; 1250 dml_uint_t *TotalNumberOfActiveDPP; 1251 dml_uint_t *TotalNumberOfDCCActiveDPP; 1252 dml_uint_t *dpte_group_bytes; 1253 dml_uint_t (*PrefetchLinesY)[__DML_NUM_PLANES__]; 1254 dml_uint_t (*PrefetchLinesC)[__DML_NUM_PLANES__]; 1255 dml_uint_t (*swath_width_luma_ub_all_states)[__DML_NUM_PLANES__]; 1256 dml_uint_t (*swath_width_chroma_ub_all_states)[__DML_NUM_PLANES__]; 1257 dml_uint_t *BytePerPixelY; 1258 dml_uint_t *BytePerPixelC; 1259 dml_uint_t *HTotal; 1260 dml_float_t *PixelClock; 1261 dml_uint_t (*PDEAndMetaPTEBytesPerFrame)[__DML_NUM_PLANES__]; 1262 dml_uint_t (*DPTEBytesPerRow)[__DML_NUM_PLANES__]; 1263 dml_uint_t (*MetaRowBytes)[__DML_NUM_PLANES__]; 1264 dml_bool_t *DynamicMetadataEnable; 1265 dml_float_t *ReadBandwidthLuma; 1266 dml_float_t *ReadBandwidthChroma; 1267 dml_float_t DCFCLKPerState; 1268 dml_float_t *DCFCLKState; 1269 }; 1270 1271 struct CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params_st { 1272 dml_bool_t USRRetrainingRequiredFinal; 1273 enum dml_use_mall_for_pstate_change_mode *UseMALLForPStateChange; 1274 dml_uint_t *PrefetchMode; 1275 dml_uint_t NumberOfActiveSurfaces; 1276 dml_uint_t MaxLineBufferLines; 1277 dml_uint_t LineBufferSize; 1278 dml_uint_t WritebackInterfaceBufferSize; 1279 dml_float_t DCFCLK; 1280 dml_float_t ReturnBW; 1281 dml_bool_t SynchronizeTimingsFinal; 1282 dml_bool_t SynchronizeDRRDisplaysForUCLKPStateChangeFinal; 1283 dml_bool_t *DRRDisplay; 1284 dml_uint_t *dpte_group_bytes; 1285 dml_uint_t *meta_row_height; 1286 dml_uint_t *meta_row_height_chroma; 1287 struct SOCParametersList mmSOCParameters; 1288 dml_uint_t WritebackChunkSize; 1289 dml_float_t SOCCLK; 1290 dml_float_t DCFClkDeepSleep; 1291 dml_uint_t *DETBufferSizeY; 1292 dml_uint_t *DETBufferSizeC; 1293 dml_uint_t *SwathHeightY; 1294 dml_uint_t *SwathHeightC; 1295 dml_uint_t *LBBitPerPixel; 1296 dml_uint_t *SwathWidthY; 1297 dml_uint_t *SwathWidthC; 1298 dml_float_t *HRatio; 1299 dml_float_t *HRatioChroma; 1300 dml_uint_t *VTaps; 1301 dml_uint_t *VTapsChroma; 1302 dml_float_t *VRatio; 1303 dml_float_t *VRatioChroma; 1304 dml_uint_t *HTotal; 1305 dml_uint_t *VTotal; 1306 dml_uint_t *VActive; 1307 dml_float_t *PixelClock; 1308 dml_uint_t *BlendingAndTiming; 1309 dml_uint_t *DPPPerSurface; 1310 dml_float_t *BytePerPixelDETY; 1311 dml_float_t *BytePerPixelDETC; 1312 dml_uint_t *DSTXAfterScaler; 1313 dml_uint_t *DSTYAfterScaler; 1314 dml_bool_t *WritebackEnable; 1315 enum dml_source_format_class *WritebackPixelFormat; 1316 dml_uint_t *WritebackDestinationWidth; 1317 dml_uint_t *WritebackDestinationHeight; 1318 dml_uint_t *WritebackSourceHeight; 1319 dml_bool_t UnboundedRequestEnabled; 1320 dml_uint_t CompressedBufferSizeInkByte; 1321 1322 // Output 1323 struct Watermarks *Watermark; 1324 enum dml_dram_clock_change_support *DRAMClockChangeSupport; 1325 dml_float_t *MaxActiveDRAMClockChangeLatencySupported; 1326 dml_uint_t *SubViewportLinesNeededInMALL; 1327 enum dml_fclock_change_support *FCLKChangeSupport; 1328 dml_float_t *MaxActiveFCLKChangeLatencySupported; 1329 dml_bool_t *USRRetrainingSupport; 1330 dml_float_t *ActiveDRAMClockChangeLatencyMargin; 1331 }; 1332 1333 struct CalculateVMRowAndSwath_params_st { 1334 dml_uint_t NumberOfActiveSurfaces; 1335 struct DmlPipe *myPipe; 1336 dml_uint_t *SurfaceSizeInMALL; 1337 dml_uint_t PTEBufferSizeInRequestsLuma; 1338 dml_uint_t PTEBufferSizeInRequestsChroma; 1339 dml_uint_t DCCMetaBufferSizeBytes; 1340 enum dml_use_mall_for_static_screen_mode *UseMALLForStaticScreen; 1341 enum dml_use_mall_for_pstate_change_mode *UseMALLForPStateChange; 1342 dml_uint_t MALLAllocatedForDCN; 1343 dml_uint_t *SwathWidthY; 1344 dml_uint_t *SwathWidthC; 1345 dml_bool_t GPUVMEnable; 1346 dml_bool_t HostVMEnable; 1347 dml_uint_t HostVMMaxNonCachedPageTableLevels; 1348 dml_uint_t GPUVMMaxPageTableLevels; 1349 dml_uint_t *GPUVMMinPageSizeKBytes; 1350 dml_uint_t HostVMMinPageSize; 1351 dml_bool_t *PTEBufferModeOverrideEn; 1352 dml_bool_t *PTEBufferModeOverrideVal; 1353 1354 // Output 1355 dml_bool_t *PTEBufferSizeNotExceeded; 1356 dml_bool_t *DCCMetaBufferSizeNotExceeded; 1357 dml_uint_t *dpte_row_width_luma_ub; 1358 dml_uint_t *dpte_row_width_chroma_ub; 1359 dml_uint_t *dpte_row_height_luma; 1360 dml_uint_t *dpte_row_height_chroma; 1361 dml_uint_t *dpte_row_height_linear_luma; // VBA_DELTA 1362 dml_uint_t *dpte_row_height_linear_chroma; // VBA_DELTA 1363 dml_uint_t *meta_req_width; 1364 dml_uint_t *meta_req_width_chroma; 1365 dml_uint_t *meta_req_height; 1366 dml_uint_t *meta_req_height_chroma; 1367 dml_uint_t *meta_row_width; 1368 dml_uint_t *meta_row_width_chroma; 1369 dml_uint_t *meta_row_height; 1370 dml_uint_t *meta_row_height_chroma; 1371 dml_uint_t *vm_group_bytes; 1372 dml_uint_t *dpte_group_bytes; 1373 dml_uint_t *PixelPTEReqWidthY; 1374 dml_uint_t *PixelPTEReqHeightY; 1375 dml_uint_t *PTERequestSizeY; 1376 dml_uint_t *PixelPTEReqWidthC; 1377 dml_uint_t *PixelPTEReqHeightC; 1378 dml_uint_t *PTERequestSizeC; 1379 dml_uint_t *dpde0_bytes_per_frame_ub_l; 1380 dml_uint_t *meta_pte_bytes_per_frame_ub_l; 1381 dml_uint_t *dpde0_bytes_per_frame_ub_c; 1382 dml_uint_t *meta_pte_bytes_per_frame_ub_c; 1383 dml_uint_t *PrefetchSourceLinesY; 1384 dml_uint_t *PrefetchSourceLinesC; 1385 dml_uint_t *VInitPreFillY; 1386 dml_uint_t *VInitPreFillC; 1387 dml_uint_t *MaxNumSwathY; 1388 dml_uint_t *MaxNumSwathC; 1389 dml_float_t *meta_row_bw; 1390 dml_float_t *dpte_row_bw; 1391 dml_uint_t *PixelPTEBytesPerRow; 1392 dml_uint_t *PDEAndMetaPTEBytesFrame; 1393 dml_uint_t *MetaRowByte; 1394 dml_bool_t *use_one_row_for_frame; 1395 dml_bool_t *use_one_row_for_frame_flip; 1396 dml_bool_t *UsesMALLForStaticScreen; 1397 dml_bool_t *PTE_BUFFER_MODE; 1398 dml_uint_t *BIGK_FRAGMENT_SIZE; 1399 }; 1400 1401 struct CalculateSwathAndDETConfiguration_params_st { 1402 dml_uint_t *DETSizeOverride; 1403 enum dml_use_mall_for_pstate_change_mode *UseMALLForPStateChange; 1404 dml_uint_t ConfigReturnBufferSizeInKByte; 1405 dml_uint_t ROBBufferSizeInKByte; 1406 dml_uint_t MaxTotalDETInKByte; 1407 dml_uint_t MinCompressedBufferSizeInKByte; 1408 dml_uint_t PixelChunkSizeInKByte; 1409 dml_bool_t ForceSingleDPP; 1410 dml_uint_t NumberOfActiveSurfaces; 1411 dml_uint_t nomDETInKByte; 1412 enum dml_unbounded_requesting_policy UseUnboundedRequestingFinal; 1413 dml_uint_t ConfigReturnBufferSegmentSizeInkByte; 1414 dml_uint_t CompressedBufferSegmentSizeInkByteFinal; 1415 enum dml_output_encoder_class *Output; 1416 dml_float_t *ReadBandwidthLuma; 1417 dml_float_t *ReadBandwidthChroma; 1418 dml_float_t *MaximumSwathWidthLuma; 1419 dml_float_t *MaximumSwathWidthChroma; 1420 enum dml_rotation_angle *SourceScan; 1421 dml_bool_t *ViewportStationary; 1422 enum dml_source_format_class *SourcePixelFormat; 1423 enum dml_swizzle_mode *SurfaceTiling; 1424 dml_uint_t *ViewportWidth; 1425 dml_uint_t *ViewportHeight; 1426 dml_uint_t *ViewportXStart; 1427 dml_uint_t *ViewportYStart; 1428 dml_uint_t *ViewportXStartC; 1429 dml_uint_t *ViewportYStartC; 1430 dml_uint_t *SurfaceWidthY; 1431 dml_uint_t *SurfaceWidthC; 1432 dml_uint_t *SurfaceHeightY; 1433 dml_uint_t *SurfaceHeightC; 1434 dml_uint_t *Read256BytesBlockHeightY; 1435 dml_uint_t *Read256BytesBlockHeightC; 1436 dml_uint_t *Read256BytesBlockWidthY; 1437 dml_uint_t *Read256BytesBlockWidthC; 1438 enum dml_odm_mode *ODMMode; 1439 dml_uint_t *BlendingAndTiming; 1440 dml_uint_t *BytePerPixY; 1441 dml_uint_t *BytePerPixC; 1442 dml_float_t *BytePerPixDETY; 1443 dml_float_t *BytePerPixDETC; 1444 dml_uint_t *HActive; 1445 dml_float_t *HRatio; 1446 dml_float_t *HRatioChroma; 1447 dml_uint_t *DPPPerSurface; 1448 dml_uint_t *swath_width_luma_ub; 1449 dml_uint_t *swath_width_chroma_ub; 1450 dml_uint_t *SwathWidth; 1451 dml_uint_t *SwathWidthChroma; 1452 dml_uint_t *SwathHeightY; 1453 dml_uint_t *SwathHeightC; 1454 dml_uint_t *DETBufferSizeInKByte; 1455 dml_uint_t *DETBufferSizeY; 1456 dml_uint_t *DETBufferSizeC; 1457 dml_bool_t *UnboundedRequestEnabled; 1458 dml_uint_t *compbuf_reserved_space_64b; 1459 dml_uint_t *compbuf_reserved_space_zs; 1460 dml_uint_t *CompressedBufferSizeInkByte; 1461 dml_bool_t *ViewportSizeSupportPerSurface; 1462 dml_bool_t *ViewportSizeSupport; 1463 }; 1464 1465 struct CalculateStutterEfficiency_params_st { 1466 dml_uint_t CompressedBufferSizeInkByte; 1467 enum dml_use_mall_for_pstate_change_mode *UseMALLForPStateChange; 1468 dml_bool_t UnboundedRequestEnabled; 1469 dml_uint_t MetaFIFOSizeInKEntries; 1470 dml_uint_t ZeroSizeBufferEntries; 1471 dml_uint_t PixelChunkSizeInKByte; 1472 dml_uint_t NumberOfActiveSurfaces; 1473 dml_uint_t ROBBufferSizeInKByte; 1474 dml_float_t TotalDataReadBandwidth; 1475 dml_float_t DCFCLK; 1476 dml_float_t ReturnBW; 1477 dml_uint_t CompbufReservedSpace64B; 1478 dml_uint_t CompbufReservedSpaceZs; 1479 dml_float_t SRExitTime; 1480 dml_float_t SRExitZ8Time; 1481 dml_bool_t SynchronizeTimingsFinal; 1482 dml_uint_t *BlendingAndTiming; 1483 dml_float_t StutterEnterPlusExitWatermark; 1484 dml_float_t Z8StutterEnterPlusExitWatermark; 1485 dml_bool_t ProgressiveToInterlaceUnitInOPP; 1486 dml_bool_t *Interlace; 1487 dml_float_t *MinTTUVBlank; 1488 dml_uint_t *DPPPerSurface; 1489 dml_uint_t *DETBufferSizeY; 1490 dml_uint_t *BytePerPixelY; 1491 dml_float_t *BytePerPixelDETY; 1492 dml_uint_t *SwathWidthY; 1493 dml_uint_t *SwathHeightY; 1494 dml_uint_t *SwathHeightC; 1495 dml_float_t *NetDCCRateLuma; 1496 dml_float_t *NetDCCRateChroma; 1497 dml_float_t *DCCFractionOfZeroSizeRequestsLuma; 1498 dml_float_t *DCCFractionOfZeroSizeRequestsChroma; 1499 dml_uint_t *HTotal; 1500 dml_uint_t *VTotal; 1501 dml_float_t *PixelClock; 1502 dml_float_t *VRatio; 1503 enum dml_rotation_angle *SourceScan; 1504 dml_uint_t *BlockHeight256BytesY; 1505 dml_uint_t *BlockWidth256BytesY; 1506 dml_uint_t *BlockHeight256BytesC; 1507 dml_uint_t *BlockWidth256BytesC; 1508 dml_uint_t *DCCYMaxUncompressedBlock; 1509 dml_uint_t *DCCCMaxUncompressedBlock; 1510 dml_uint_t *VActive; 1511 dml_bool_t *DCCEnable; 1512 dml_bool_t *WritebackEnable; 1513 dml_float_t *ReadBandwidthSurfaceLuma; 1514 dml_float_t *ReadBandwidthSurfaceChroma; 1515 dml_float_t *meta_row_bw; 1516 dml_float_t *dpte_row_bw; 1517 dml_float_t *StutterEfficiencyNotIncludingVBlank; 1518 dml_float_t *StutterEfficiency; 1519 dml_uint_t *NumberOfStutterBurstsPerFrame; 1520 dml_float_t *Z8StutterEfficiencyNotIncludingVBlank; 1521 dml_float_t *Z8StutterEfficiency; 1522 dml_uint_t *Z8NumberOfStutterBurstsPerFrame; 1523 dml_float_t *StutterPeriod; 1524 dml_bool_t *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE; 1525 }; 1526 1527 struct CalculatePrefetchSchedule_params_st { 1528 dml_bool_t EnhancedPrefetchScheduleAccelerationFinal; 1529 dml_float_t HostVMInefficiencyFactor; 1530 struct DmlPipe *myPipe; 1531 dml_uint_t DSCDelay; 1532 dml_float_t DPPCLKDelaySubtotalPlusCNVCFormater; 1533 dml_float_t DPPCLKDelaySCL; 1534 dml_float_t DPPCLKDelaySCLLBOnly; 1535 dml_float_t DPPCLKDelayCNVCCursor; 1536 dml_float_t DISPCLKDelaySubtotal; 1537 dml_uint_t DPP_RECOUT_WIDTH; 1538 enum dml_output_format_class OutputFormat; 1539 dml_uint_t MaxInterDCNTileRepeaters; 1540 dml_uint_t VStartup; 1541 dml_uint_t MaxVStartup; 1542 dml_uint_t GPUVMPageTableLevels; 1543 dml_bool_t GPUVMEnable; 1544 dml_bool_t HostVMEnable; 1545 dml_uint_t HostVMMaxNonCachedPageTableLevels; 1546 dml_uint_t HostVMMinPageSize; 1547 dml_bool_t DynamicMetadataEnable; 1548 dml_bool_t DynamicMetadataVMEnabled; 1549 int DynamicMetadataLinesBeforeActiveRequired; 1550 dml_uint_t DynamicMetadataTransmittedBytes; 1551 dml_float_t UrgentLatency; 1552 dml_float_t UrgentExtraLatency; 1553 dml_float_t TCalc; 1554 dml_uint_t PDEAndMetaPTEBytesFrame; 1555 dml_uint_t MetaRowByte; 1556 dml_uint_t PixelPTEBytesPerRow; 1557 dml_float_t PrefetchSourceLinesY; 1558 dml_uint_t VInitPreFillY; 1559 dml_uint_t MaxNumSwathY; 1560 dml_float_t PrefetchSourceLinesC; 1561 dml_uint_t VInitPreFillC; 1562 dml_uint_t MaxNumSwathC; 1563 dml_uint_t swath_width_luma_ub; 1564 dml_uint_t swath_width_chroma_ub; 1565 dml_uint_t SwathHeightY; 1566 dml_uint_t SwathHeightC; 1567 dml_float_t TWait; 1568 dml_uint_t *DSTXAfterScaler; 1569 dml_uint_t *DSTYAfterScaler; 1570 dml_float_t *DestinationLinesForPrefetch; 1571 dml_float_t *DestinationLinesToRequestVMInVBlank; 1572 dml_float_t *DestinationLinesToRequestRowInVBlank; 1573 dml_float_t *VRatioPrefetchY; 1574 dml_float_t *VRatioPrefetchC; 1575 dml_float_t *RequiredPrefetchPixDataBWLuma; 1576 dml_float_t *RequiredPrefetchPixDataBWChroma; 1577 dml_bool_t *NotEnoughTimeForDynamicMetadata; 1578 dml_float_t *Tno_bw; 1579 dml_float_t *prefetch_vmrow_bw; 1580 dml_float_t *Tdmdl_vm; 1581 dml_float_t *Tdmdl; 1582 dml_float_t *TSetup; 1583 dml_uint_t *VUpdateOffsetPix; 1584 dml_uint_t *VUpdateWidthPix; 1585 dml_uint_t *VReadyOffsetPix; 1586 }; 1587 1588 struct dml_core_mode_support_locals_st { 1589 dml_bool_t dummy_boolean[2]; 1590 dml_uint_t dummy_integer[3]; 1591 dml_uint_t dummy_integer_array[22][__DML_NUM_PLANES__]; 1592 enum dml_odm_mode dummy_odm_mode[__DML_NUM_PLANES__]; 1593 dml_bool_t dummy_boolean_array[2][__DML_NUM_PLANES__]; 1594 dml_uint_t MaxVStartupAllPlanes[2]; 1595 dml_uint_t MaximumVStartup[2][__DML_NUM_PLANES__]; 1596 dml_uint_t DSTYAfterScaler[__DML_NUM_PLANES__]; 1597 dml_uint_t DSTXAfterScaler[__DML_NUM_PLANES__]; 1598 dml_uint_t NextPrefetchMode[__DML_NUM_PLANES__]; 1599 dml_uint_t MinPrefetchMode[__DML_NUM_PLANES__]; 1600 dml_uint_t MaxPrefetchMode[__DML_NUM_PLANES__]; 1601 dml_float_t dummy_single[3]; 1602 dml_float_t dummy_single_array[__DML_NUM_PLANES__]; 1603 struct Watermarks dummy_watermark; 1604 struct SOCParametersList mSOCParameters; 1605 struct DmlPipe myPipe; 1606 struct DmlPipe SurfParameters[__DML_NUM_PLANES__]; 1607 dml_uint_t TotalNumberOfActiveWriteback; 1608 dml_uint_t MaximumSwathWidthSupportLuma; 1609 dml_uint_t MaximumSwathWidthSupportChroma; 1610 dml_bool_t MPCCombineMethodAsNeededForPStateChangeAndVoltage; 1611 dml_bool_t MPCCombineMethodAsPossible; 1612 dml_bool_t TotalAvailablePipesSupportNoDSC; 1613 dml_uint_t NumberOfDPPNoDSC; 1614 enum dml_odm_mode ODMModeNoDSC; 1615 dml_float_t RequiredDISPCLKPerSurfaceNoDSC; 1616 dml_bool_t TotalAvailablePipesSupportDSC; 1617 dml_uint_t NumberOfDPPDSC; 1618 enum dml_odm_mode ODMModeDSC; 1619 dml_float_t RequiredDISPCLKPerSurfaceDSC; 1620 dml_bool_t NoChromaOrLinear; 1621 dml_float_t BWOfNonCombinedSurfaceOfMaximumBandwidth; 1622 dml_uint_t NumberOfNonCombinedSurfaceOfMaximumBandwidth; 1623 dml_uint_t TotalNumberOfActiveOTG; 1624 dml_uint_t TotalNumberOfActiveHDMIFRL; 1625 dml_uint_t TotalNumberOfActiveDP2p0; 1626 dml_uint_t TotalNumberOfActiveDP2p0Outputs; 1627 dml_uint_t TotalSlots; 1628 dml_uint_t DSCFormatFactor; 1629 dml_uint_t TotalDSCUnitsRequired; 1630 dml_uint_t ReorderingBytes; 1631 dml_bool_t ImmediateFlipRequiredFinal; 1632 dml_bool_t FullFrameMALLPStateMethod; 1633 dml_bool_t SubViewportMALLPStateMethod; 1634 dml_bool_t PhantomPipeMALLPStateMethod; 1635 dml_bool_t SubViewportMALLRefreshGreaterThan120Hz; 1636 dml_float_t MaxTotalVActiveRDBandwidth; 1637 dml_float_t VMDataOnlyReturnBWPerState; 1638 dml_float_t HostVMInefficiencyFactor; 1639 dml_uint_t NextMaxVStartup; 1640 dml_uint_t MaxVStartup; 1641 dml_bool_t AllPrefetchModeTested; 1642 dml_bool_t AnyLinesForVMOrRowTooLarge; 1643 dml_bool_t is_max_pwr_state; 1644 dml_bool_t is_max_dram_pwr_state; 1645 dml_bool_t dram_clock_change_support; 1646 dml_bool_t f_clock_change_support; 1647 }; 1648 1649 struct dml_core_mode_programming_locals_st { 1650 dml_uint_t DSCFormatFactor; 1651 dml_uint_t dummy_integer_array[2][__DML_NUM_PLANES__]; 1652 enum dml_output_encoder_class dummy_output_encoder_array[__DML_NUM_PLANES__]; 1653 dml_float_t dummy_single_array[2][__DML_NUM_PLANES__]; 1654 dml_uint_t dummy_long_array[4][__DML_NUM_PLANES__]; 1655 dml_bool_t dummy_boolean_array[2][__DML_NUM_PLANES__]; 1656 dml_bool_t dummy_boolean[1]; 1657 struct DmlPipe SurfaceParameters[__DML_NUM_PLANES__]; 1658 dml_uint_t ReorderBytes; 1659 dml_float_t VMDataOnlyReturnBW; 1660 dml_float_t HostVMInefficiencyFactor; 1661 dml_uint_t TotalDCCActiveDPP; 1662 dml_uint_t TotalActiveDPP; 1663 dml_uint_t VStartupLines; 1664 dml_uint_t MaxVStartupLines[__DML_NUM_PLANES__]; /// <brief more like vblank for the plane's OTG 1665 dml_uint_t MaxVStartupAllPlanes; 1666 dml_bool_t ImmediateFlipRequirementFinal; 1667 int iteration; 1668 dml_float_t MaxTotalRDBandwidth; 1669 dml_float_t MaxTotalRDBandwidthNoUrgentBurst; 1670 dml_bool_t DestinationLineTimesForPrefetchLessThan2; 1671 dml_bool_t VRatioPrefetchMoreThanMax; 1672 dml_float_t MaxTotalRDBandwidthNotIncludingMALLPrefetch; 1673 dml_uint_t NextPrefetchMode[__DML_NUM_PLANES__]; 1674 dml_uint_t MinPrefetchMode[__DML_NUM_PLANES__]; 1675 dml_uint_t MaxPrefetchMode[__DML_NUM_PLANES__]; 1676 dml_bool_t AllPrefetchModeTested; 1677 dml_float_t dummy_unit_vector[__DML_NUM_PLANES__]; 1678 dml_float_t NonUrgentMaxTotalRDBandwidth; 1679 dml_float_t NonUrgentMaxTotalRDBandwidthNotIncludingMALLPrefetch; 1680 dml_float_t dummy_single[2]; 1681 struct SOCParametersList mmSOCParameters; 1682 dml_float_t Tvstartup_margin; 1683 dml_float_t dlg_vblank_start; 1684 dml_float_t LSetup; 1685 dml_float_t blank_lines_remaining; 1686 dml_float_t old_MIN_DST_Y_NEXT_START; 1687 dml_float_t TotalWRBandwidth; 1688 dml_float_t WRBandwidth; 1689 struct Watermarks dummy_watermark; 1690 struct DmlPipe myPipe; 1691 }; 1692 1693 struct CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals_st { 1694 dml_float_t ActiveDRAMClockChangeLatencyMargin[__DML_NUM_PLANES__]; 1695 dml_float_t ActiveFCLKChangeLatencyMargin[__DML_NUM_PLANES__]; 1696 dml_float_t USRRetrainingLatencyMargin[__DML_NUM_PLANES__]; 1697 1698 dml_bool_t SynchronizedSurfaces[__DML_NUM_PLANES__][__DML_NUM_PLANES__]; 1699 dml_float_t EffectiveLBLatencyHidingY; 1700 dml_float_t EffectiveLBLatencyHidingC; 1701 dml_float_t LinesInDETY[__DML_NUM_PLANES__]; 1702 dml_float_t LinesInDETC[__DML_NUM_PLANES__]; 1703 dml_uint_t LinesInDETYRoundedDownToSwath[__DML_NUM_PLANES__]; 1704 dml_uint_t LinesInDETCRoundedDownToSwath[__DML_NUM_PLANES__]; 1705 dml_float_t FullDETBufferingTimeY; 1706 dml_float_t FullDETBufferingTimeC; 1707 dml_float_t WritebackDRAMClockChangeLatencyMargin; 1708 dml_float_t WritebackFCLKChangeLatencyMargin; 1709 dml_float_t WritebackLatencyHiding; 1710 1711 dml_uint_t TotalActiveWriteback; 1712 dml_uint_t LBLatencyHidingSourceLinesY[__DML_NUM_PLANES__]; 1713 dml_uint_t LBLatencyHidingSourceLinesC[__DML_NUM_PLANES__]; 1714 dml_float_t TotalPixelBW; 1715 dml_float_t EffectiveDETBufferSizeY; 1716 dml_float_t ActiveClockChangeLatencyHidingY; 1717 dml_float_t ActiveClockChangeLatencyHidingC; 1718 dml_float_t ActiveClockChangeLatencyHiding; 1719 dml_bool_t FoundCriticalSurface; 1720 dml_uint_t LastSurfaceWithoutMargin; 1721 dml_uint_t FCLKChangeSupportNumber; 1722 dml_uint_t DRAMClockChangeMethod; 1723 dml_uint_t DRAMClockChangeSupportNumber; 1724 dml_uint_t dst_y_pstate; 1725 dml_uint_t src_y_pstate_l; 1726 dml_uint_t src_y_pstate_c; 1727 dml_uint_t src_y_ahead_l; 1728 dml_uint_t src_y_ahead_c; 1729 dml_uint_t sub_vp_lines_l; 1730 dml_uint_t sub_vp_lines_c; 1731 }; 1732 1733 struct CalculateVMRowAndSwath_locals_st { 1734 dml_uint_t PTEBufferSizeInRequestsForLuma[__DML_NUM_PLANES__]; 1735 dml_uint_t PTEBufferSizeInRequestsForChroma[__DML_NUM_PLANES__]; 1736 dml_uint_t PDEAndMetaPTEBytesFrameY; 1737 dml_uint_t PDEAndMetaPTEBytesFrameC; 1738 dml_uint_t MetaRowByteY[__DML_NUM_PLANES__]; 1739 dml_uint_t MetaRowByteC[__DML_NUM_PLANES__]; 1740 dml_uint_t PixelPTEBytesPerRowY[__DML_NUM_PLANES__]; 1741 dml_uint_t PixelPTEBytesPerRowC[__DML_NUM_PLANES__]; 1742 dml_uint_t PixelPTEBytesPerRowStorageY[__DML_NUM_PLANES__]; 1743 dml_uint_t PixelPTEBytesPerRowStorageC[__DML_NUM_PLANES__]; 1744 dml_uint_t PixelPTEBytesPerRowY_one_row_per_frame[__DML_NUM_PLANES__]; 1745 dml_uint_t PixelPTEBytesPerRowC_one_row_per_frame[__DML_NUM_PLANES__]; 1746 dml_uint_t dpte_row_width_luma_ub_one_row_per_frame[__DML_NUM_PLANES__]; 1747 dml_uint_t dpte_row_height_luma_one_row_per_frame[__DML_NUM_PLANES__]; 1748 dml_uint_t dpte_row_width_chroma_ub_one_row_per_frame[__DML_NUM_PLANES__]; 1749 dml_uint_t dpte_row_height_chroma_one_row_per_frame[__DML_NUM_PLANES__]; 1750 dml_bool_t one_row_per_frame_fits_in_buffer[__DML_NUM_PLANES__]; 1751 1752 dml_uint_t HostVMDynamicLevels; 1753 }; 1754 1755 struct UseMinimumDCFCLK_locals_st { 1756 dml_uint_t dummy1; 1757 dml_uint_t dummy2; 1758 dml_uint_t dummy3; 1759 dml_float_t NormalEfficiency; 1760 dml_float_t TotalMaxPrefetchFlipDPTERowBandwidth[2]; 1761 1762 dml_float_t PixelDCFCLKCyclesRequiredInPrefetch[__DML_NUM_PLANES__]; 1763 dml_float_t PrefetchPixelLinesTime[__DML_NUM_PLANES__]; 1764 dml_float_t DCFCLKRequiredForPeakBandwidthPerSurface[__DML_NUM_PLANES__]; 1765 dml_float_t DynamicMetadataVMExtraLatency[__DML_NUM_PLANES__]; 1766 dml_float_t MinimumTWait; 1767 dml_float_t DPTEBandwidth; 1768 dml_float_t DCFCLKRequiredForAverageBandwidth; 1769 dml_uint_t ExtraLatencyBytes; 1770 dml_float_t ExtraLatencyCycles; 1771 dml_float_t DCFCLKRequiredForPeakBandwidth; 1772 dml_uint_t NoOfDPPState[__DML_NUM_PLANES__]; 1773 dml_float_t MinimumTvmPlus2Tr0; 1774 }; 1775 1776 struct CalculatePrefetchSchedule_locals_st { 1777 dml_bool_t MyError; 1778 dml_uint_t DPPCycles; 1779 dml_uint_t DISPCLKCycles; 1780 dml_float_t DSTTotalPixelsAfterScaler; 1781 dml_float_t LineTime; 1782 dml_float_t dst_y_prefetch_equ; 1783 dml_float_t prefetch_bw_oto; 1784 dml_float_t Tvm_oto; 1785 dml_float_t Tr0_oto; 1786 dml_float_t Tvm_oto_lines; 1787 dml_float_t Tr0_oto_lines; 1788 dml_float_t dst_y_prefetch_oto; 1789 dml_float_t TimeForFetchingMetaPTE; 1790 dml_float_t TimeForFetchingRowInVBlank; 1791 dml_float_t LinesToRequestPrefetchPixelData; 1792 dml_uint_t HostVMDynamicLevelsTrips; 1793 dml_float_t trip_to_mem; 1794 dml_float_t Tvm_trips; 1795 dml_float_t Tr0_trips; 1796 dml_float_t Tvm_trips_rounded; 1797 dml_float_t Tr0_trips_rounded; 1798 dml_float_t max_Tsw; 1799 dml_float_t Lsw_oto; 1800 dml_float_t Tpre_rounded; 1801 dml_float_t prefetch_bw_equ; 1802 dml_float_t Tvm_equ; 1803 dml_float_t Tr0_equ; 1804 dml_float_t Tdmbf; 1805 dml_float_t Tdmec; 1806 dml_float_t Tdmsks; 1807 dml_float_t prefetch_sw_bytes; 1808 dml_float_t prefetch_bw_pr; 1809 dml_float_t bytes_pp; 1810 dml_float_t dep_bytes; 1811 dml_float_t min_Lsw_oto; 1812 dml_float_t Tsw_est1; 1813 dml_float_t Tsw_est3; 1814 dml_float_t PrefetchBandwidth1; 1815 dml_float_t PrefetchBandwidth2; 1816 dml_float_t PrefetchBandwidth3; 1817 dml_float_t PrefetchBandwidth4; 1818 }; 1819 1820 /// @brief To minimize stack usage; function locals are instead placed into this scratch structure which is allocated per context 1821 struct display_mode_lib_scratch_st { 1822 // Scratch space for function locals 1823 struct dml_core_mode_support_locals_st dml_core_mode_support_locals; 1824 struct dml_core_mode_programming_locals_st dml_core_mode_programming_locals; 1825 struct CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals_st CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals; 1826 struct CalculateVMRowAndSwath_locals_st CalculateVMRowAndSwath_locals; 1827 struct UseMinimumDCFCLK_locals_st UseMinimumDCFCLK_locals; 1828 struct CalculatePrefetchSchedule_locals_st CalculatePrefetchSchedule_locals; 1829 1830 // Scratch space for function params 1831 struct CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params_st CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params; 1832 struct CalculateVMRowAndSwath_params_st CalculateVMRowAndSwath_params; 1833 struct UseMinimumDCFCLK_params_st UseMinimumDCFCLK_params; 1834 struct CalculateSwathAndDETConfiguration_params_st CalculateSwathAndDETConfiguration_params; 1835 struct CalculateStutterEfficiency_params_st CalculateStutterEfficiency_params; 1836 struct CalculatePrefetchSchedule_params_st CalculatePrefetchSchedule_params; 1837 }; 1838 1839 /// @brief Represent the overall soc/ip enviroment. It contains data structure represent the soc/ip characteristic and also structures that hold calculation output 1840 struct display_mode_lib_st { 1841 dml_uint_t project; 1842 1843 //@brief Mode evaluation and programming policy 1844 struct dml_mode_eval_policy_st policy; 1845 1846 //@brief IP/SOC characteristic 1847 struct ip_params_st ip; 1848 struct soc_bounding_box_st soc; 1849 struct soc_states_st states; 1850 1851 //@brief Mode Support and Mode programming struct 1852 // Used to hold input; intermediate and output of the calculations 1853 struct mode_support_st ms; // struct for mode support 1854 struct mode_program_st mp; // struct for mode programming 1855 1856 struct display_mode_lib_scratch_st scratch; 1857 }; 1858 1859 struct dml_mode_support_ex_params_st { 1860 struct display_mode_lib_st *mode_lib; 1861 const struct dml_display_cfg_st *in_display_cfg; 1862 dml_uint_t out_lowest_state_idx; 1863 struct dml_mode_support_info_st *out_evaluation_info; 1864 }; 1865 1866 typedef struct _vcs_dpi_dml_display_rq_regs_st dml_display_rq_regs_st; 1867 typedef struct _vcs_dpi_dml_display_dlg_regs_st dml_display_dlg_regs_st; 1868 typedef struct _vcs_dpi_dml_display_ttu_regs_st dml_display_ttu_regs_st; 1869 typedef struct _vcs_dpi_dml_display_arb_params_st dml_display_arb_params_st; 1870 typedef struct _vcs_dpi_dml_display_plane_rq_regs_st dml_display_plane_rq_regs_st; 1871 1872 struct _vcs_dpi_dml_display_dlg_regs_st { 1873 dml_uint_t refcyc_h_blank_end; 1874 dml_uint_t dlg_vblank_end; 1875 dml_uint_t min_dst_y_next_start; 1876 dml_uint_t refcyc_per_htotal; 1877 dml_uint_t refcyc_x_after_scaler; 1878 dml_uint_t dst_y_after_scaler; 1879 dml_uint_t dst_y_prefetch; 1880 dml_uint_t dst_y_per_vm_vblank; 1881 dml_uint_t dst_y_per_row_vblank; 1882 dml_uint_t dst_y_per_vm_flip; 1883 dml_uint_t dst_y_per_row_flip; 1884 dml_uint_t ref_freq_to_pix_freq; 1885 dml_uint_t vratio_prefetch; 1886 dml_uint_t vratio_prefetch_c; 1887 dml_uint_t refcyc_per_pte_group_vblank_l; 1888 dml_uint_t refcyc_per_pte_group_vblank_c; 1889 dml_uint_t refcyc_per_meta_chunk_vblank_l; 1890 dml_uint_t refcyc_per_meta_chunk_vblank_c; 1891 dml_uint_t refcyc_per_pte_group_flip_l; 1892 dml_uint_t refcyc_per_pte_group_flip_c; 1893 dml_uint_t refcyc_per_meta_chunk_flip_l; 1894 dml_uint_t refcyc_per_meta_chunk_flip_c; 1895 dml_uint_t dst_y_per_pte_row_nom_l; 1896 dml_uint_t dst_y_per_pte_row_nom_c; 1897 dml_uint_t refcyc_per_pte_group_nom_l; 1898 dml_uint_t refcyc_per_pte_group_nom_c; 1899 dml_uint_t dst_y_per_meta_row_nom_l; 1900 dml_uint_t dst_y_per_meta_row_nom_c; 1901 dml_uint_t refcyc_per_meta_chunk_nom_l; 1902 dml_uint_t refcyc_per_meta_chunk_nom_c; 1903 dml_uint_t refcyc_per_line_delivery_pre_l; 1904 dml_uint_t refcyc_per_line_delivery_pre_c; 1905 dml_uint_t refcyc_per_line_delivery_l; 1906 dml_uint_t refcyc_per_line_delivery_c; 1907 dml_uint_t refcyc_per_vm_group_vblank; 1908 dml_uint_t refcyc_per_vm_group_flip; 1909 dml_uint_t refcyc_per_vm_req_vblank; 1910 dml_uint_t refcyc_per_vm_req_flip; 1911 dml_uint_t dst_y_offset_cur0; 1912 dml_uint_t chunk_hdl_adjust_cur0; 1913 dml_uint_t dst_y_offset_cur1; 1914 dml_uint_t chunk_hdl_adjust_cur1; 1915 dml_uint_t vready_after_vcount0; 1916 dml_uint_t dst_y_delta_drq_limit; 1917 dml_uint_t refcyc_per_vm_dmdata; 1918 dml_uint_t dmdata_dl_delta; 1919 }; 1920 1921 struct _vcs_dpi_dml_display_ttu_regs_st { 1922 dml_uint_t qos_level_low_wm; 1923 dml_uint_t qos_level_high_wm; 1924 dml_uint_t min_ttu_vblank; 1925 dml_uint_t qos_level_flip; 1926 dml_uint_t refcyc_per_req_delivery_l; 1927 dml_uint_t refcyc_per_req_delivery_c; 1928 dml_uint_t refcyc_per_req_delivery_cur0; 1929 dml_uint_t refcyc_per_req_delivery_cur1; 1930 dml_uint_t refcyc_per_req_delivery_pre_l; 1931 dml_uint_t refcyc_per_req_delivery_pre_c; 1932 dml_uint_t refcyc_per_req_delivery_pre_cur0; 1933 dml_uint_t refcyc_per_req_delivery_pre_cur1; 1934 dml_uint_t qos_level_fixed_l; 1935 dml_uint_t qos_level_fixed_c; 1936 dml_uint_t qos_level_fixed_cur0; 1937 dml_uint_t qos_level_fixed_cur1; 1938 dml_uint_t qos_ramp_disable_l; 1939 dml_uint_t qos_ramp_disable_c; 1940 dml_uint_t qos_ramp_disable_cur0; 1941 dml_uint_t qos_ramp_disable_cur1; 1942 }; 1943 1944 struct _vcs_dpi_dml_display_arb_params_st { 1945 dml_uint_t max_req_outstanding; 1946 dml_uint_t min_req_outstanding; 1947 dml_uint_t sat_level_us; 1948 dml_uint_t hvm_max_qos_commit_threshold; 1949 dml_uint_t hvm_min_req_outstand_commit_threshold; 1950 dml_uint_t compbuf_reserved_space_kbytes; 1951 }; 1952 1953 struct _vcs_dpi_dml_display_plane_rq_regs_st { 1954 dml_uint_t chunk_size; 1955 dml_uint_t min_chunk_size; 1956 dml_uint_t meta_chunk_size; 1957 dml_uint_t min_meta_chunk_size; 1958 dml_uint_t dpte_group_size; 1959 dml_uint_t mpte_group_size; 1960 dml_uint_t swath_height; 1961 dml_uint_t pte_row_height_linear; 1962 }; 1963 1964 struct _vcs_dpi_dml_display_rq_regs_st { 1965 dml_display_plane_rq_regs_st rq_regs_l; 1966 dml_display_plane_rq_regs_st rq_regs_c; 1967 dml_uint_t drq_expansion_mode; 1968 dml_uint_t prq_expansion_mode; 1969 dml_uint_t mrq_expansion_mode; 1970 dml_uint_t crq_expansion_mode; 1971 dml_uint_t plane1_base_address; 1972 }; 1973 1974 #endif 1975