1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _CORE_TYPES_H_ 27 #define _CORE_TYPES_H_ 28 29 #include "dc.h" 30 #include "dce_calcs.h" 31 #include "dcn_calcs.h" 32 #include "ddc_service_types.h" 33 #include "dc_bios_types.h" 34 #include "mem_input.h" 35 #include "hubp.h" 36 #include "mpc.h" 37 #include "dwb.h" 38 #include "hw/dio.h" 39 #include "mcif_wb.h" 40 #include "panel_cntl.h" 41 #include "dmub/inc/dmub_cmd.h" 42 #include "pg_cntl.h" 43 #include "sspl/dc_spl.h" 44 45 #define MAX_CLOCK_SOURCES 7 46 #define MAX_SVP_PHANTOM_STREAMS 2 47 #define MAX_SVP_PHANTOM_PLANES 2 48 49 #include "grph_object_id.h" 50 #include "link_encoder.h" 51 #include "stream_encoder.h" 52 #include "clock_source.h" 53 #include "audio.h" 54 #include "dm_pp_smu.h" 55 #include "dm_cp_psp.h" 56 #include "link_hwss.h" 57 58 /********** DAL Core*********************/ 59 #include "transform.h" 60 #include "dpp.h" 61 62 #include "dml2_0/dml21/inc/dml_top_dchub_registers.h" 63 #include "dml2_0/dml21/inc/dml_top_types.h" 64 65 struct resource_pool; 66 struct dc_state; 67 struct resource_context; 68 struct clk_bw_params; 69 struct dc_mcache_params; 70 71 #define MAX_RMCM_INST 2 72 73 struct resource_funcs { 74 enum engine_id (*get_preferred_eng_id_dpia)(unsigned int dpia_index); 75 void (*destroy)(struct resource_pool **pool); 76 void (*link_init)(struct dc_link *link); 77 struct panel_cntl*(*panel_cntl_create)( 78 const struct panel_cntl_init_data *panel_cntl_init_data); 79 struct link_encoder *(*link_enc_create)( 80 struct dc_context *ctx, 81 const struct encoder_init_data *init); 82 /* Create a minimal link encoder object with no dc_link object 83 * associated with it. */ 84 struct link_encoder *(*link_enc_create_minimal)(struct dc_context *ctx, enum engine_id eng_id); 85 enum dc_status (*validate_bandwidth)( 86 struct dc *dc, 87 struct dc_state *context, 88 enum dc_validate_mode validate_mode); 89 void (*calculate_wm_and_dlg)( 90 struct dc *dc, struct dc_state *context, 91 display_e2e_pipe_params_st *pipes, 92 int pipe_cnt, 93 int vlevel); 94 void (*update_soc_for_wm_a)( 95 struct dc *dc, struct dc_state *context); 96 97 unsigned int (*calculate_mall_ways_from_bytes)( 98 const struct dc *dc, 99 unsigned int total_size_in_mall_bytes); 100 void (*prepare_mcache_programming)( 101 struct dc *dc, 102 struct dc_state *context); 103 /** 104 * @populate_dml_pipes - Populate pipe data struct 105 * 106 * Returns: 107 * Total of pipes available in the specific ASIC. 108 */ 109 int (*populate_dml_pipes)( 110 struct dc *dc, 111 struct dc_state *context, 112 display_e2e_pipe_params_st *pipes, 113 enum dc_validate_mode validate_mode); 114 115 /* 116 * Algorithm for assigning available link encoders to links. 117 * 118 * Update link_enc_assignments table and link_enc_avail list accordingly in 119 * struct resource_context. 120 */ 121 void (*link_encs_assign)( 122 struct dc *dc, 123 struct dc_state *state, 124 struct dc_stream_state *streams[], 125 uint8_t stream_count); 126 /* 127 * Unassign a link encoder from a stream. 128 * 129 * Update link_enc_assignments table and link_enc_avail list accordingly in 130 * struct resource_context. 131 */ 132 void (*link_enc_unassign)( 133 struct dc_state *state, 134 struct dc_stream_state *stream); 135 136 enum dc_status (*validate_global)( 137 struct dc *dc, 138 struct dc_state *context); 139 140 struct pipe_ctx *(*acquire_free_pipe_as_secondary_dpp_pipe)( 141 const struct dc_state *cur_ctx, 142 struct dc_state *new_ctx, 143 const struct resource_pool *pool, 144 const struct pipe_ctx *opp_head_pipe); 145 146 struct pipe_ctx *(*acquire_free_pipe_as_secondary_opp_head)( 147 const struct dc_state *cur_ctx, 148 struct dc_state *new_ctx, 149 const struct resource_pool *pool, 150 const struct pipe_ctx *otg_master); 151 152 void (*release_pipe)(struct dc_state *context, 153 struct pipe_ctx *pipe, 154 const struct resource_pool *pool); 155 156 enum dc_status (*validate_plane)( 157 const struct dc_plane_state *plane_state, 158 struct dc_caps *caps); 159 160 enum dc_status (*add_stream_to_ctx)( 161 struct dc *dc, 162 struct dc_state *new_ctx, 163 struct dc_stream_state *dc_stream); 164 165 enum dc_status (*remove_stream_from_ctx)( 166 struct dc *dc, 167 struct dc_state *new_ctx, 168 struct dc_stream_state *stream); 169 170 enum dc_status (*patch_unknown_plane_state)( 171 struct dc_plane_state *plane_state); 172 173 struct stream_encoder *(*find_first_free_match_stream_enc_for_link)( 174 struct resource_context *res_ctx, 175 const struct resource_pool *pool, 176 struct dc_stream_state *stream); 177 178 void (*populate_dml_writeback_from_context)( 179 struct dc *dc, 180 struct resource_context *res_ctx, 181 display_e2e_pipe_params_st *pipes); 182 183 void (*set_mcif_arb_params)( 184 struct dc *dc, 185 struct dc_state *context, 186 display_e2e_pipe_params_st *pipes, 187 int pipe_cnt); 188 189 void (*update_bw_bounding_box)( 190 struct dc *dc, 191 struct clk_bw_params *bw_params); 192 bool (*acquire_post_bldn_3dlut)( 193 struct resource_context *res_ctx, 194 const struct resource_pool *pool, 195 int mpcc_id, 196 struct dc_3dlut **lut, 197 struct dc_transfer_func **shaper); 198 199 bool (*release_post_bldn_3dlut)( 200 struct resource_context *res_ctx, 201 const struct resource_pool *pool, 202 struct dc_3dlut **lut, 203 struct dc_transfer_func **shaper); 204 205 enum dc_status (*add_dsc_to_stream_resource)( 206 struct dc *dc, struct dc_state *state, 207 struct dc_stream_state *stream); 208 209 void (*add_phantom_pipes)( 210 struct dc *dc, 211 struct dc_state *context, 212 display_e2e_pipe_params_st *pipes, 213 unsigned int pipe_cnt, 214 unsigned int index); 215 216 void (*get_panel_config_defaults)(struct dc_panel_config *panel_config); 217 void (*build_pipe_pix_clk_params)(struct pipe_ctx *pipe_ctx); 218 /* 219 * Get indicator of power from a context that went through full validation 220 */ 221 int (*get_power_profile)(const struct dc_state *context); 222 unsigned int (*get_det_buffer_size)(const struct dc_state *context); 223 unsigned int (*get_vstartup_for_pipe)(struct pipe_ctx *pipe_ctx); 224 unsigned int (*get_max_hw_cursor_size)(const struct dc *dc, 225 struct dc_state *state, 226 const struct dc_stream_state *stream); 227 bool (*program_mcache_pipe_config)(struct dc_state *context, 228 const struct dc_mcache_params *mcache_params); 229 enum dc_status (*update_dc_state_for_encoder_switch)(struct dc_link *link, 230 struct dc_link_settings *link_setting, 231 uint8_t pipe_count, 232 struct pipe_ctx *pipes, 233 struct audio_output *audio_output); 234 }; 235 236 struct audio_support{ 237 bool dp_audio; 238 bool hdmi_audio_on_dongle; 239 bool hdmi_audio_native; 240 }; 241 242 #define NO_UNDERLAY_PIPE -1 243 244 struct resource_pool { 245 struct mem_input *mis[MAX_PIPES]; 246 struct hubp *hubps[MAX_PIPES]; 247 struct input_pixel_processor *ipps[MAX_PIPES]; 248 struct transform *transforms[MAX_PIPES]; 249 struct dpp *dpps[MAX_PIPES]; 250 struct output_pixel_processor *opps[MAX_PIPES]; 251 struct timing_generator *timing_generators[MAX_PIPES]; 252 struct stream_encoder *stream_enc[MAX_PIPES * 2]; 253 struct hubbub *hubbub; 254 struct dio *dio; 255 struct mpc *mpc; 256 struct pp_smu_funcs *pp_smu; 257 struct dce_aux *engines[MAX_PIPES]; 258 struct dce_i2c_hw *hw_i2cs[MAX_PIPES]; 259 struct dce_i2c_sw *sw_i2cs[MAX_PIPES]; 260 bool i2c_hw_buffer_in_use; 261 262 struct dwbc *dwbc[MAX_DWB_PIPES]; 263 struct mcif_wb *mcif_wb[MAX_DWB_PIPES]; 264 struct { 265 unsigned int gsl_0:1; 266 unsigned int gsl_1:1; 267 unsigned int gsl_2:1; 268 } gsl_groups; 269 270 struct display_stream_compressor *dscs[MAX_PIPES]; 271 272 unsigned int pipe_count; 273 unsigned int underlay_pipe_index; 274 unsigned int stream_enc_count; 275 276 /* An array for accessing the link encoder objects that have been created. 277 * Index in array corresponds to engine ID - viz. 0: ENGINE_ID_DIGA 278 */ 279 struct link_encoder *link_encoders[MAX_LINK_ENCODERS]; 280 /* Number of DIG link encoder objects created - i.e. number of valid 281 * entries in link_encoders array. 282 */ 283 unsigned int dig_link_enc_count; 284 /* Number of USB4 DPIA (DisplayPort Input Adapter) link objects created.*/ 285 unsigned int usb4_dpia_count; 286 287 unsigned int hpo_dp_stream_enc_count; 288 struct hpo_dp_stream_encoder *hpo_dp_stream_enc[MAX_HPO_DP2_ENCODERS]; 289 unsigned int hpo_dp_link_enc_count; 290 struct hpo_dp_link_encoder *hpo_dp_link_enc[MAX_HPO_DP2_LINK_ENCODERS]; 291 struct dc_3dlut *mpc_lut[MAX_PIPES]; 292 struct dc_transfer_func *mpc_shaper[MAX_PIPES]; 293 struct dc_rmcm_3dlut rmcm_3dlut[MAX_RMCM_INST]; 294 295 struct { 296 unsigned int xtalin_clock_inKhz; 297 unsigned int dccg_ref_clock_inKhz; 298 unsigned int dchub_ref_clock_inKhz; 299 } ref_clocks; 300 unsigned int timing_generator_count; 301 unsigned int mpcc_count; 302 303 unsigned int writeback_pipe_count; 304 /* 305 * reserved clock source for DP 306 */ 307 struct clock_source *dp_clock_source; 308 309 struct clock_source *clock_sources[MAX_CLOCK_SOURCES]; 310 unsigned int clk_src_count; 311 312 struct audio *audios[MAX_AUDIOS]; 313 unsigned int audio_count; 314 struct audio_support audio_support; 315 316 struct dccg *dccg; 317 struct pg_cntl *pg_cntl; 318 struct irq_service *irqs; 319 320 struct abm *abm; 321 struct dmcu *dmcu; 322 struct dmub_psr *psr; 323 struct dmub_replay *replay; 324 325 struct abm *multiple_abms[MAX_PIPES]; 326 327 const struct resource_funcs *funcs; 328 const struct resource_caps *res_cap; 329 330 struct ddc_service *oem_device; 331 }; 332 333 struct dcn_fe_bandwidth { 334 int dppclk_khz; 335 336 }; 337 338 /* Parameters needed to call set_disp_pattern_generator */ 339 struct test_pattern_params { 340 enum controller_dp_test_pattern test_pattern; 341 enum controller_dp_color_space color_space; 342 enum dc_color_depth color_depth; 343 int width; 344 int height; 345 int offset; 346 }; 347 348 struct stream_resource { 349 struct output_pixel_processor *opp; 350 struct display_stream_compressor *dsc; 351 struct timing_generator *tg; 352 struct stream_encoder *stream_enc; 353 struct hpo_dp_stream_encoder *hpo_dp_stream_enc; 354 struct audio *audio; 355 356 struct pixel_clk_params pix_clk_params; 357 struct encoder_info_frame encoder_info_frame; 358 359 struct abm *abm; 360 /* There are only (num_pipes+1)/2 groups. 0 means unassigned, 361 * otherwise it's using group number 'gsl_group-1' 362 */ 363 uint8_t gsl_group; 364 365 struct test_pattern_params test_pattern_params; 366 }; 367 368 struct plane_resource { 369 /* scl_data is scratch space required to program a plane */ 370 struct scaler_data scl_data; 371 /* Below pointers to hw objects are required to enable the plane */ 372 /* spl_in and spl_out are the input and output structures for SPL 373 * which are required when using Scaler Programming Library 374 * these are scratch spaces needed when programming a plane 375 */ 376 struct spl_in spl_in; 377 struct spl_out spl_out; 378 /* Below pointers to hw objects are required to enable the plane */ 379 struct hubp *hubp; 380 struct mem_input *mi; 381 struct input_pixel_processor *ipp; 382 struct transform *xfm; 383 struct dpp *dpp; 384 uint8_t mpcc_inst; 385 386 struct dcn_fe_bandwidth bw; 387 }; 388 389 #define LINK_RES_HPO_DP_REC_MAP__MASK 0xFFFF 390 #define LINK_RES_HPO_DP_REC_MAP__SHIFT 0 391 392 /* all mappable hardware resources used to enable a link */ 393 struct link_resource { 394 struct link_encoder *dio_link_enc; 395 struct hpo_dp_link_encoder *hpo_dp_link_enc; 396 }; 397 398 struct link_config { 399 struct dc_link_settings dp_link_settings; 400 struct dc_tunnel_settings dp_tunnel_settings; 401 }; 402 403 union pipe_update_flags { 404 struct { 405 uint32_t enable : 1; 406 uint32_t disable : 1; 407 uint32_t odm : 1; 408 uint32_t global_sync : 1; 409 uint32_t opp_changed : 1; 410 uint32_t tg_changed : 1; 411 uint32_t mpcc : 1; 412 uint32_t dppclk : 1; 413 uint32_t hubp_interdependent : 1; 414 uint32_t hubp_rq_dlg_ttu : 1; 415 uint32_t gamut_remap : 1; 416 uint32_t scaler : 1; 417 uint32_t viewport : 1; 418 uint32_t plane_changed : 1; 419 uint32_t det_size : 1; 420 uint32_t unbounded_req : 1; 421 uint32_t test_pattern_changed : 1; 422 } bits; 423 uint32_t raw; 424 }; 425 426 struct pixel_rate_divider { 427 uint32_t div_factor1; 428 uint32_t div_factor2; 429 }; 430 431 enum p_state_switch_method { 432 P_STATE_UNKNOWN = 0, 433 P_STATE_V_BLANK = 1, 434 P_STATE_FPO, 435 P_STATE_V_ACTIVE, 436 P_STATE_SUB_VP, 437 P_STATE_DRR_SUB_VP, 438 P_STATE_V_BLANK_SUB_VP, 439 }; 440 441 struct dsc_padding_params { 442 /* pixels borrowed from hblank to hactive */ 443 uint8_t dsc_hactive_padding; 444 uint32_t dsc_htotal_padding; 445 uint32_t dsc_pix_clk_100hz; 446 }; 447 448 struct pipe_ctx { 449 struct dc_plane_state *plane_state; 450 struct dc_stream_state *stream; 451 452 struct plane_resource plane_res; 453 454 /** 455 * @stream_res: Reference to DCN resource components such OPP and DSC. 456 */ 457 struct stream_resource stream_res; 458 struct link_resource link_res; 459 460 struct clock_source *clock_source; 461 462 struct pll_settings pll_settings; 463 464 /** 465 * @link_config: 466 * 467 * link config records software decision for what link config should be 468 * enabled given current link capability and stream during hw resource 469 * mapping. This is to decouple the dependency on link capability during 470 * dc commit or update. 471 */ 472 struct link_config link_config; 473 474 uint8_t pipe_idx; 475 uint8_t pipe_idx_syncd; 476 477 struct pipe_ctx *top_pipe; 478 struct pipe_ctx *bottom_pipe; 479 struct pipe_ctx *next_odm_pipe; 480 struct pipe_ctx *prev_odm_pipe; 481 482 struct _vcs_dpi_display_dlg_regs_st dlg_regs; 483 struct _vcs_dpi_display_ttu_regs_st ttu_regs; 484 struct _vcs_dpi_display_rq_regs_st rq_regs; 485 struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; 486 struct _vcs_dpi_display_rq_params_st dml_rq_param; 487 struct _vcs_dpi_display_dlg_sys_params_st dml_dlg_sys_param; 488 struct _vcs_dpi_display_e2e_pipe_params_st dml_input; 489 int det_buffer_size_kb; 490 bool unbounded_req; 491 unsigned int surface_size_in_mall_bytes; 492 struct dml2_dchub_per_pipe_register_set hubp_regs; 493 struct dml2_hubp_pipe_mcache_regs mcache_regs; 494 union dml2_global_sync_programming global_sync; 495 496 struct dwbc *dwbc; 497 struct mcif_wb *mcif_wb; 498 union pipe_update_flags update_flags; 499 enum p_state_switch_method p_state_type; 500 struct tg_color visual_confirm_color; 501 bool has_vactive_margin; 502 /* subvp_index: only valid if the pipe is a SUBVP_MAIN*/ 503 uint8_t subvp_index; 504 struct pixel_rate_divider pixel_rate_divider; 505 struct dsc_padding_params dsc_padding_params; 506 /* next vupdate */ 507 uint32_t next_vupdate; 508 uint32_t wait_frame_count; 509 bool wait_is_required; 510 }; 511 512 /* Data used for dynamic link encoder assignment. 513 * Tracks current and future assignments; available link encoders; 514 * and mode of operation (whether to use current or future assignments). 515 */ 516 struct link_enc_cfg_context { 517 enum link_enc_cfg_mode mode; 518 struct link_enc_assignment link_enc_assignments[MAX_PIPES]; 519 enum engine_id link_enc_avail[MAX_LINK_ENCODERS]; 520 struct link_enc_assignment transient_assignments[MAX_PIPES]; 521 }; 522 523 struct resource_context { 524 struct pipe_ctx pipe_ctx[MAX_PIPES]; 525 bool is_stream_enc_acquired[MAX_PIPES * 2]; 526 bool is_audio_acquired[MAX_PIPES]; 527 uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; 528 uint8_t dp_clock_source_ref_count; 529 bool is_dsc_acquired[MAX_PIPES]; 530 struct link_enc_cfg_context link_enc_cfg_ctx; 531 unsigned int dio_link_enc_to_link_idx[MAX_LINK_ENCODERS]; 532 int dio_link_enc_ref_cnts[MAX_LINK_ENCODERS]; 533 bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS]; 534 unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS]; 535 int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS]; 536 bool is_mpc_3dlut_acquired[MAX_PIPES]; 537 /* used to build scalar data in dml2 and for edp backlight programming */ 538 struct pipe_ctx temp_pipe; 539 }; 540 541 struct dce_bw_output { 542 bool cpuc_state_change_enable; 543 bool cpup_state_change_enable; 544 bool stutter_mode_enable; 545 bool nbp_state_change_enable; 546 bool all_displays_in_sync; 547 struct dce_watermarks urgent_wm_ns[MAX_PIPES]; 548 struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES]; 549 struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES]; 550 struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES]; 551 int sclk_khz; 552 int sclk_deep_sleep_khz; 553 int yclk_khz; 554 int dispclk_khz; 555 int blackout_recovery_time_us; 556 }; 557 558 struct dcn_bw_writeback { 559 struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES]; 560 }; 561 562 struct dcn_bw_output { 563 struct dc_clocks clk; 564 union dcn_watermark_set watermarks; 565 struct dcn_bw_writeback bw_writeback; 566 int compbuf_size_kb; 567 unsigned int mall_ss_size_bytes; 568 unsigned int mall_ss_psr_active_size_bytes; 569 unsigned int mall_subvp_size_bytes; 570 unsigned int legacy_svp_drr_stream_index; 571 bool legacy_svp_drr_stream_index_valid; 572 struct dml2_mcache_surface_allocation mcache_allocations[DML2_MAX_PLANES]; 573 struct dmub_cmd_fams2_global_config fams2_global_config; 574 union dmub_cmd_fams2_config fams2_stream_base_params[DML2_MAX_PLANES]; 575 union { 576 union dmub_cmd_fams2_config fams2_stream_sub_params[DML2_MAX_PLANES]; 577 union dmub_fams2_stream_static_sub_state_v2 fams2_stream_sub_params_v2[DML2_MAX_PLANES]; 578 }; 579 struct dml2_display_arb_regs arb_regs; 580 }; 581 582 union bw_output { 583 struct dcn_bw_output dcn; 584 struct dce_bw_output dce; 585 }; 586 587 struct bw_context { 588 union bw_output bw; 589 struct display_mode_lib dml; 590 struct dml2_context *dml2; 591 struct dml2_context *dml2_dc_power_source; 592 }; 593 594 struct dc_dmub_cmd { 595 union dmub_rb_cmd dmub_cmd; 596 enum dm_dmub_wait_type wait_type; 597 }; 598 599 /** 600 * struct dc_state - The full description of a state requested by users 601 */ 602 struct dc_state { 603 /** 604 * @streams: Stream state properties 605 */ 606 struct dc_stream_state *streams[MAX_PIPES]; 607 608 /** 609 * @stream_status: Planes status on a given stream 610 */ 611 struct dc_stream_status stream_status[MAX_PIPES]; 612 /** 613 * @phantom_streams: Stream state properties for phantoms 614 */ 615 struct dc_stream_state *phantom_streams[MAX_PHANTOM_PIPES]; 616 /** 617 * @phantom_planes: Planes state properties for phantoms 618 */ 619 struct dc_plane_state *phantom_planes[MAX_PHANTOM_PIPES]; 620 621 /** 622 * @stream_count: Total of streams in use 623 */ 624 uint8_t stream_count; 625 uint8_t stream_mask; 626 627 /** 628 * @stream_count: Total phantom streams in use 629 */ 630 uint8_t phantom_stream_count; 631 /** 632 * @stream_count: Total phantom planes in use 633 */ 634 uint8_t phantom_plane_count; 635 /** 636 * @res_ctx: Persistent state of resources 637 */ 638 struct resource_context res_ctx; 639 640 /** 641 * @pp_display_cfg: PowerPlay clocks and settings 642 * Note: this is a big struct, do *not* put on stack! 643 */ 644 struct dm_pp_display_configuration pp_display_cfg; 645 646 /** 647 * @dcn_bw_vars: non-stack memory to support bandwidth calculations 648 * Note: this is a big struct, do *not* put on stack! 649 */ 650 struct dcn_bw_internal_vars dcn_bw_vars; 651 652 struct clk_mgr *clk_mgr; 653 654 /** 655 * @bw_ctx: The output from bandwidth and watermark calculations and the DML 656 * 657 * Each context must have its own instance of VBA, and in order to 658 * initialize and obtain IP and SOC, the base DML instance from DC is 659 * initially copied into every context. 660 */ 661 struct bw_context bw_ctx; 662 663 struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE]; 664 unsigned int block_sequence_steps; 665 struct dc_dmub_cmd dc_dmub_cmd[10]; 666 unsigned int dmub_cmd_count; 667 668 /** 669 * @refcount: refcount reference 670 * 671 * Notice that dc_state is used around the code to capture the current 672 * context, so we need to pass it everywhere. That's why we want to use 673 * kref in this struct. 674 */ 675 struct kref refcount; 676 677 struct { 678 unsigned int stutter_period_us; 679 } perf_params; 680 681 enum dc_power_source_type power_source; 682 }; 683 684 struct replay_context { 685 /* ddc line */ 686 enum channel_id aux_inst; 687 /* Transmitter id */ 688 enum transmitter digbe_inst; 689 /* Engine Id is used for Dig Be source select */ 690 enum engine_id digfe_inst; 691 /* Controller Id used for Dig Fe source select */ 692 enum controller_id controllerId; 693 unsigned int line_time_in_ns; 694 bool os_request_force_ffu; 695 }; 696 697 enum dc_replay_enable { 698 DC_REPLAY_DISABLE = 0, 699 DC_REPLAY_ENABLE = 1, 700 }; 701 702 struct dc_bounding_box_max_clk { 703 int max_dcfclk_mhz; 704 int max_dispclk_mhz; 705 int max_dppclk_mhz; 706 int max_phyclk_mhz; 707 }; 708 709 struct memory_qos { 710 uint32_t peak_bw_mbps; 711 uint32_t avg_bw_mbps; 712 uint32_t max_latency_ns; 713 uint32_t min_latency_ns; 714 uint32_t avg_latency_ns; 715 }; 716 717 #endif /* _CORE_TYPES_H_ */ 718