1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2022 Intel Corporation 7 8 #include <sound/pcm_params.h> 9 #include <sound/hdaudio_ext.h> 10 #include <sound/hda_register.h> 11 #include <sound/hda-mlink.h> 12 #include <sound/sof/ipc4/header.h> 13 #include <uapi/sound/sof/header.h> 14 #include "../ipc4-priv.h" 15 #include "../ipc4-topology.h" 16 #include "../sof-priv.h" 17 #include "../sof-audio.h" 18 #include "hda.h" 19 20 /* These ops are only applicable for the HDA DAI's in their current form */ 21 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_LINK) 22 /* 23 * This function checks if the host dma channel corresponding 24 * to the link DMA stream_tag argument is assigned to one 25 * of the FEs connected to the BE DAI. 26 */ 27 static bool hda_check_fes(struct snd_soc_pcm_runtime *rtd, 28 int dir, int stream_tag) 29 { 30 struct snd_pcm_substream *fe_substream; 31 struct hdac_stream *fe_hstream; 32 struct snd_soc_dpcm *dpcm; 33 34 for_each_dpcm_fe(rtd, dir, dpcm) { 35 fe_substream = snd_soc_dpcm_get_substream(dpcm->fe, dir); 36 fe_hstream = fe_substream->runtime->private_data; 37 if (fe_hstream->stream_tag == stream_tag) 38 return true; 39 } 40 41 return false; 42 } 43 44 static struct hdac_ext_stream * 45 hda_link_stream_assign(struct hdac_bus *bus, struct snd_pcm_substream *substream) 46 { 47 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 48 struct sof_intel_hda_stream *hda_stream; 49 const struct sof_intel_dsp_desc *chip; 50 struct snd_sof_dev *sdev; 51 struct hdac_ext_stream *res = NULL; 52 struct hdac_stream *hstream = NULL; 53 54 int stream_dir = substream->stream; 55 56 if (!bus->ppcap) { 57 dev_err(bus->dev, "stream type not supported\n"); 58 return NULL; 59 } 60 61 guard(spinlock_irq)(&bus->reg_lock); 62 list_for_each_entry(hstream, &bus->stream_list, list) { 63 struct hdac_ext_stream *hext_stream = 64 stream_to_hdac_ext_stream(hstream); 65 if (hstream->direction != substream->stream) 66 continue; 67 68 hda_stream = hstream_to_sof_hda_stream(hext_stream); 69 sdev = hda_stream->sdev; 70 chip = get_chip_info(sdev->pdata); 71 72 /* check if link is available */ 73 if (!hext_stream->link_locked) { 74 /* 75 * choose the first available link for platforms that do not have the 76 * PROCEN_FMT_QUIRK set. 77 */ 78 if (!(chip->quirks & SOF_INTEL_PROCEN_FMT_QUIRK)) { 79 res = hext_stream; 80 break; 81 } 82 83 if (hstream->opened) { 84 /* 85 * check if the stream tag matches the stream 86 * tag of one of the connected FEs 87 */ 88 if (hda_check_fes(rtd, stream_dir, 89 hstream->stream_tag)) { 90 res = hext_stream; 91 break; 92 } 93 } else { 94 res = hext_stream; 95 96 /* 97 * This must be a hostless stream. 98 * So reserve the host DMA channel. 99 */ 100 hda_stream->host_reserved = 1; 101 break; 102 } 103 } 104 } 105 106 if (res) { 107 /* Make sure that host and link DMA is decoupled. */ 108 snd_hdac_ext_stream_decouple_locked(bus, res, true); 109 110 res->link_locked = 1; 111 res->link_substream = substream; 112 } 113 114 return res; 115 } 116 117 static struct hdac_ext_stream *hda_get_hext_stream(struct snd_sof_dev *sdev, 118 struct snd_soc_dai *cpu_dai, 119 struct snd_pcm_substream *substream) 120 { 121 return snd_soc_dai_get_dma_data(cpu_dai, substream); 122 } 123 124 static struct hdac_ext_stream *hda_ipc4_get_hext_stream(struct snd_sof_dev *sdev, 125 struct snd_soc_dai *cpu_dai, 126 struct snd_pcm_substream *substream) 127 { 128 struct snd_sof_widget *pipe_widget; 129 struct sof_ipc4_pipeline *pipeline; 130 struct snd_sof_widget *swidget; 131 struct snd_soc_dapm_widget *w; 132 133 w = snd_soc_dai_get_widget(cpu_dai, substream->stream); 134 swidget = w->dobj.private; 135 pipe_widget = swidget->spipe->pipe_widget; 136 pipeline = pipe_widget->private; 137 138 /* mark pipeline so that it can be skipped during FE trigger */ 139 pipeline->skip_during_fe_trigger = true; 140 141 return snd_soc_dai_get_dma_data(cpu_dai, substream); 142 } 143 144 static struct hdac_ext_stream *hda_assign_hext_stream(struct snd_sof_dev *sdev, 145 struct snd_soc_dai *cpu_dai, 146 struct snd_pcm_substream *substream) 147 { 148 struct hdac_ext_stream *hext_stream; 149 150 hext_stream = hda_link_stream_assign(sof_to_bus(sdev), substream); 151 if (!hext_stream) 152 return NULL; 153 154 snd_soc_dai_set_dma_data(cpu_dai, substream, (void *)hext_stream); 155 156 return hext_stream; 157 } 158 159 static void hda_release_hext_stream(struct snd_sof_dev *sdev, struct snd_soc_dai *cpu_dai, 160 struct snd_pcm_substream *substream) 161 { 162 struct hdac_ext_stream *hext_stream = hda_get_hext_stream(sdev, cpu_dai, substream); 163 164 snd_soc_dai_set_dma_data(cpu_dai, substream, NULL); 165 snd_hdac_ext_stream_release(hext_stream, HDAC_EXT_STREAM_TYPE_LINK); 166 } 167 168 static void hda_setup_hext_stream(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream, 169 unsigned int format_val) 170 { 171 snd_hdac_ext_stream_setup(hext_stream, format_val); 172 } 173 174 static void hda_reset_hext_stream(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream) 175 { 176 snd_hdac_ext_stream_reset(hext_stream); 177 } 178 179 static void hda_codec_dai_set_stream(struct snd_sof_dev *sdev, 180 struct snd_pcm_substream *substream, 181 struct hdac_stream *hstream) 182 { 183 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 184 struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0); 185 186 /* set the hdac_stream in the codec dai */ 187 snd_soc_dai_set_stream(codec_dai, hstream, substream->stream); 188 } 189 190 static unsigned int hda_calc_stream_format(struct snd_sof_dev *sdev, 191 struct snd_pcm_substream *substream, 192 struct snd_pcm_hw_params *params) 193 { 194 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 195 struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0); 196 unsigned int link_bps; 197 unsigned int format_val; 198 unsigned int bits; 199 200 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 201 link_bps = codec_dai->driver->playback.sig_bits; 202 else 203 link_bps = codec_dai->driver->capture.sig_bits; 204 205 bits = snd_hdac_stream_format_bits(params_format(params), SNDRV_PCM_SUBFORMAT_STD, 206 link_bps); 207 format_val = snd_hdac_stream_format(params_channels(params), bits, params_rate(params)); 208 209 dev_dbg(sdev->dev, "format_val=%#x, rate=%d, ch=%d, format=%d\n", format_val, 210 params_rate(params), params_channels(params), params_format(params)); 211 212 return format_val; 213 } 214 215 static struct hdac_ext_link *hda_get_hlink(struct snd_sof_dev *sdev, 216 struct snd_pcm_substream *substream) 217 { 218 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 219 struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0); 220 struct hdac_bus *bus = sof_to_bus(sdev); 221 222 return snd_hdac_ext_bus_get_hlink_by_name(bus, codec_dai->component->name); 223 } 224 225 static unsigned int generic_calc_stream_format(struct snd_sof_dev *sdev, 226 struct snd_pcm_substream *substream, 227 struct snd_pcm_hw_params *params) 228 { 229 unsigned int format_val; 230 unsigned int bits; 231 232 bits = snd_hdac_stream_format_bits(params_format(params), SNDRV_PCM_SUBFORMAT_STD, 233 params_physical_width(params)); 234 format_val = snd_hdac_stream_format(params_channels(params), bits, params_rate(params)); 235 236 dev_dbg(sdev->dev, "format_val=%#x, rate=%d, ch=%d, format=%d\n", format_val, 237 params_rate(params), params_channels(params), params_format(params)); 238 239 return format_val; 240 } 241 242 static unsigned int dmic_calc_stream_format(struct snd_sof_dev *sdev, 243 struct snd_pcm_substream *substream, 244 struct snd_pcm_hw_params *params) 245 { 246 unsigned int format_val; 247 snd_pcm_format_t format; 248 unsigned int channels; 249 unsigned int width; 250 unsigned int bits; 251 252 channels = params_channels(params); 253 format = params_format(params); 254 width = params_physical_width(params); 255 256 if (format == SNDRV_PCM_FORMAT_S16_LE) { 257 format = SNDRV_PCM_FORMAT_S32_LE; 258 channels /= 2; 259 width = 32; 260 } 261 262 bits = snd_hdac_stream_format_bits(format, SNDRV_PCM_SUBFORMAT_STD, width); 263 format_val = snd_hdac_stream_format(channels, bits, params_rate(params)); 264 265 dev_dbg(sdev->dev, "format_val=%#x, rate=%d, ch=%d, format=%d\n", format_val, 266 params_rate(params), channels, format); 267 268 return format_val; 269 } 270 271 static struct hdac_ext_link *ssp_get_hlink(struct snd_sof_dev *sdev, 272 struct snd_pcm_substream *substream) 273 { 274 struct hdac_bus *bus = sof_to_bus(sdev); 275 276 return hdac_bus_eml_ssp_get_hlink(bus); 277 } 278 279 static struct hdac_ext_link *dmic_get_hlink(struct snd_sof_dev *sdev, 280 struct snd_pcm_substream *substream) 281 { 282 struct hdac_bus *bus = sof_to_bus(sdev); 283 284 return hdac_bus_eml_dmic_get_hlink(bus); 285 } 286 287 static struct hdac_ext_link *sdw_get_hlink(struct snd_sof_dev *sdev, 288 struct snd_pcm_substream *substream) 289 { 290 struct hdac_bus *bus = sof_to_bus(sdev); 291 292 return hdac_bus_eml_sdw_get_hlink(bus); 293 } 294 295 static int hda_ipc4_pre_trigger(struct snd_sof_dev *sdev, struct snd_soc_dai *cpu_dai, 296 struct snd_pcm_substream *substream, int cmd) 297 { 298 struct sof_ipc4_fw_data *ipc4_data = sdev->private; 299 struct snd_sof_widget *pipe_widget; 300 struct sof_ipc4_pipeline *pipeline; 301 struct snd_sof_widget *swidget; 302 struct snd_soc_dapm_widget *w; 303 int ret = 0; 304 305 w = snd_soc_dai_get_widget(cpu_dai, substream->stream); 306 swidget = w->dobj.private; 307 pipe_widget = swidget->spipe->pipe_widget; 308 pipeline = pipe_widget->private; 309 310 if (pipe_widget->instance_id < 0) 311 return 0; 312 313 guard(mutex)(&ipc4_data->pipeline_state_mutex); 314 315 switch (cmd) { 316 case SNDRV_PCM_TRIGGER_START: 317 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 318 break; 319 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 320 case SNDRV_PCM_TRIGGER_SUSPEND: 321 case SNDRV_PCM_TRIGGER_STOP: 322 ret = sof_ipc4_set_pipeline_state(sdev, pipe_widget->instance_id, 323 SOF_IPC4_PIPE_PAUSED); 324 if (ret < 0) 325 return ret; 326 327 pipeline->state = SOF_IPC4_PIPE_PAUSED; 328 329 break; 330 default: 331 dev_err(sdev->dev, "unknown trigger command %d\n", cmd); 332 ret = -EINVAL; 333 } 334 335 return ret; 336 } 337 338 static int hda_trigger(struct snd_sof_dev *sdev, struct snd_soc_dai *cpu_dai, 339 struct snd_pcm_substream *substream, int cmd) 340 { 341 struct hdac_ext_stream *hext_stream = snd_soc_dai_get_dma_data(cpu_dai, substream); 342 343 switch (cmd) { 344 case SNDRV_PCM_TRIGGER_START: 345 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 346 snd_hdac_ext_stream_start(hext_stream); 347 break; 348 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 349 /* 350 * Save the LLP registers since in case of PAUSE the LLP 351 * register are not reset to 0, the delay calculation will use 352 * the saved offsets for compensating the delay calculation. 353 */ 354 hext_stream->pplcllpl = readl(hext_stream->pplc_addr + AZX_REG_PPLCLLPL); 355 hext_stream->pplcllpu = readl(hext_stream->pplc_addr + AZX_REG_PPLCLLPU); 356 snd_hdac_ext_stream_clear(hext_stream); 357 break; 358 case SNDRV_PCM_TRIGGER_SUSPEND: 359 case SNDRV_PCM_TRIGGER_STOP: 360 hext_stream->pplcllpl = 0; 361 hext_stream->pplcllpu = 0; 362 snd_hdac_ext_stream_clear(hext_stream); 363 break; 364 default: 365 dev_err(sdev->dev, "unknown trigger command %d\n", cmd); 366 return -EINVAL; 367 } 368 369 return 0; 370 } 371 372 static int hda_ipc4_post_trigger(struct snd_sof_dev *sdev, struct snd_soc_dai *cpu_dai, 373 struct snd_pcm_substream *substream, int cmd) 374 { 375 struct sof_ipc4_fw_data *ipc4_data = sdev->private; 376 struct snd_sof_widget *pipe_widget; 377 struct sof_ipc4_pipeline *pipeline; 378 struct snd_sof_widget *swidget; 379 struct snd_soc_dapm_widget *w; 380 int ret = 0; 381 382 w = snd_soc_dai_get_widget(cpu_dai, substream->stream); 383 swidget = w->dobj.private; 384 pipe_widget = swidget->spipe->pipe_widget; 385 pipeline = pipe_widget->private; 386 387 if (pipe_widget->instance_id < 0) 388 return 0; 389 390 guard(mutex)(&ipc4_data->pipeline_state_mutex); 391 392 switch (cmd) { 393 case SNDRV_PCM_TRIGGER_START: 394 if (pipeline->state != SOF_IPC4_PIPE_PAUSED) { 395 ret = sof_ipc4_set_pipeline_state(sdev, pipe_widget->instance_id, 396 SOF_IPC4_PIPE_PAUSED); 397 if (ret < 0) 398 return ret; 399 400 pipeline->state = SOF_IPC4_PIPE_PAUSED; 401 } 402 403 ret = sof_ipc4_set_pipeline_state(sdev, pipe_widget->instance_id, 404 SOF_IPC4_PIPE_RUNNING); 405 if (ret < 0) 406 return ret; 407 408 pipeline->state = SOF_IPC4_PIPE_RUNNING; 409 swidget->spipe->started_count++; 410 break; 411 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 412 ret = sof_ipc4_set_pipeline_state(sdev, pipe_widget->instance_id, 413 SOF_IPC4_PIPE_RUNNING); 414 if (ret < 0) 415 return ret; 416 417 pipeline->state = SOF_IPC4_PIPE_RUNNING; 418 break; 419 case SNDRV_PCM_TRIGGER_SUSPEND: 420 case SNDRV_PCM_TRIGGER_STOP: 421 /* 422 * STOP/SUSPEND trigger is invoked only once when all users of this pipeline have 423 * been stopped. So, clear the started_count so that the pipeline can be reset 424 */ 425 swidget->spipe->started_count = 0; 426 break; 427 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 428 break; 429 default: 430 dev_err(sdev->dev, "unknown trigger command %d\n", cmd); 431 ret = -EINVAL; 432 break; 433 } 434 435 return ret; 436 } 437 438 static const struct hda_dai_widget_dma_ops hda_ipc4_dma_ops = { 439 .get_hext_stream = hda_ipc4_get_hext_stream, 440 .assign_hext_stream = hda_assign_hext_stream, 441 .release_hext_stream = hda_release_hext_stream, 442 .setup_hext_stream = hda_setup_hext_stream, 443 .reset_hext_stream = hda_reset_hext_stream, 444 .pre_trigger = hda_ipc4_pre_trigger, 445 .trigger = hda_trigger, 446 .post_trigger = hda_ipc4_post_trigger, 447 .codec_dai_set_stream = hda_codec_dai_set_stream, 448 .calc_stream_format = hda_calc_stream_format, 449 .get_hlink = hda_get_hlink, 450 }; 451 452 static const struct hda_dai_widget_dma_ops ssp_ipc4_dma_ops = { 453 .get_hext_stream = hda_ipc4_get_hext_stream, 454 .assign_hext_stream = hda_assign_hext_stream, 455 .release_hext_stream = hda_release_hext_stream, 456 .setup_hext_stream = hda_setup_hext_stream, 457 .reset_hext_stream = hda_reset_hext_stream, 458 .pre_trigger = hda_ipc4_pre_trigger, 459 .trigger = hda_trigger, 460 .post_trigger = hda_ipc4_post_trigger, 461 .calc_stream_format = generic_calc_stream_format, 462 .get_hlink = ssp_get_hlink, 463 }; 464 465 static const struct hda_dai_widget_dma_ops dmic_ipc4_dma_ops = { 466 .get_hext_stream = hda_ipc4_get_hext_stream, 467 .assign_hext_stream = hda_assign_hext_stream, 468 .release_hext_stream = hda_release_hext_stream, 469 .setup_hext_stream = hda_setup_hext_stream, 470 .reset_hext_stream = hda_reset_hext_stream, 471 .pre_trigger = hda_ipc4_pre_trigger, 472 .trigger = hda_trigger, 473 .post_trigger = hda_ipc4_post_trigger, 474 .calc_stream_format = dmic_calc_stream_format, 475 .get_hlink = dmic_get_hlink, 476 }; 477 478 static const struct hda_dai_widget_dma_ops sdw_ipc4_dma_ops = { 479 .get_hext_stream = hda_ipc4_get_hext_stream, 480 .assign_hext_stream = hda_assign_hext_stream, 481 .release_hext_stream = hda_release_hext_stream, 482 .setup_hext_stream = hda_setup_hext_stream, 483 .reset_hext_stream = hda_reset_hext_stream, 484 .pre_trigger = hda_ipc4_pre_trigger, 485 .trigger = hda_trigger, 486 .post_trigger = hda_ipc4_post_trigger, 487 .calc_stream_format = generic_calc_stream_format, 488 .get_hlink = sdw_get_hlink, 489 }; 490 491 static const struct hda_dai_widget_dma_ops hda_ipc4_chain_dma_ops = { 492 .get_hext_stream = hda_get_hext_stream, 493 .assign_hext_stream = hda_assign_hext_stream, 494 .release_hext_stream = hda_release_hext_stream, 495 .setup_hext_stream = hda_setup_hext_stream, 496 .reset_hext_stream = hda_reset_hext_stream, 497 .trigger = hda_trigger, 498 .codec_dai_set_stream = hda_codec_dai_set_stream, 499 .calc_stream_format = hda_calc_stream_format, 500 .get_hlink = hda_get_hlink, 501 }; 502 503 static const struct hda_dai_widget_dma_ops sdw_ipc4_chain_dma_ops = { 504 .get_hext_stream = hda_get_hext_stream, 505 .assign_hext_stream = hda_assign_hext_stream, 506 .release_hext_stream = hda_release_hext_stream, 507 .setup_hext_stream = hda_setup_hext_stream, 508 .reset_hext_stream = hda_reset_hext_stream, 509 .trigger = hda_trigger, 510 .calc_stream_format = generic_calc_stream_format, 511 .get_hlink = sdw_get_hlink, 512 }; 513 514 static int hda_ipc3_post_trigger(struct snd_sof_dev *sdev, struct snd_soc_dai *cpu_dai, 515 struct snd_pcm_substream *substream, int cmd) 516 { 517 struct snd_soc_dapm_widget *w = snd_soc_dai_get_widget(cpu_dai, substream->stream); 518 519 switch (cmd) { 520 case SNDRV_PCM_TRIGGER_SUSPEND: 521 case SNDRV_PCM_TRIGGER_STOP: 522 { 523 struct snd_sof_dai_config_data data = { 0 }; 524 int ret; 525 526 data.dai_data = DMA_CHAN_INVALID; 527 ret = hda_dai_config(w, SOF_DAI_CONFIG_FLAGS_HW_FREE, &data); 528 if (ret < 0) 529 return ret; 530 531 break; 532 } 533 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 534 return hda_dai_config(w, SOF_DAI_CONFIG_FLAGS_PAUSE, NULL); 535 default: 536 break; 537 } 538 539 return 0; 540 } 541 542 static const struct hda_dai_widget_dma_ops hda_ipc3_dma_ops = { 543 .get_hext_stream = hda_get_hext_stream, 544 .assign_hext_stream = hda_assign_hext_stream, 545 .release_hext_stream = hda_release_hext_stream, 546 .setup_hext_stream = hda_setup_hext_stream, 547 .reset_hext_stream = hda_reset_hext_stream, 548 .trigger = hda_trigger, 549 .post_trigger = hda_ipc3_post_trigger, 550 .codec_dai_set_stream = hda_codec_dai_set_stream, 551 .calc_stream_format = hda_calc_stream_format, 552 .get_hlink = hda_get_hlink, 553 }; 554 555 static struct hdac_ext_stream * 556 hda_dspless_get_hext_stream(struct snd_sof_dev *sdev, struct snd_soc_dai *cpu_dai, 557 struct snd_pcm_substream *substream) 558 { 559 struct hdac_stream *hstream = substream->runtime->private_data; 560 561 return stream_to_hdac_ext_stream(hstream); 562 } 563 564 static void hda_dspless_setup_hext_stream(struct snd_sof_dev *sdev, 565 struct hdac_ext_stream *hext_stream, 566 unsigned int format_val) 567 { 568 /* 569 * Save the format_val which was adjusted by the maxbps of the codec. 570 * This information is not available on the FE side since there we are 571 * using dummy_codec. 572 */ 573 hext_stream->hstream.format_val = format_val; 574 } 575 576 static const struct hda_dai_widget_dma_ops hda_dspless_dma_ops = { 577 .get_hext_stream = hda_dspless_get_hext_stream, 578 .setup_hext_stream = hda_dspless_setup_hext_stream, 579 .codec_dai_set_stream = hda_codec_dai_set_stream, 580 .calc_stream_format = hda_calc_stream_format, 581 .get_hlink = hda_get_hlink, 582 }; 583 584 static const struct hda_dai_widget_dma_ops sdw_dspless_dma_ops = { 585 .get_hext_stream = hda_dspless_get_hext_stream, 586 .setup_hext_stream = hda_dspless_setup_hext_stream, 587 .calc_stream_format = generic_calc_stream_format, 588 .get_hlink = sdw_get_hlink, 589 }; 590 591 #endif 592 593 const struct hda_dai_widget_dma_ops * 594 hda_select_dai_widget_ops(struct snd_sof_dev *sdev, struct snd_sof_widget *swidget) 595 { 596 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_LINK) 597 struct snd_sof_dai *sdai; 598 const struct sof_intel_dsp_desc *chip; 599 600 chip = get_chip_info(sdev->pdata); 601 sdai = swidget->private; 602 603 if (sdev->dspless_mode_selected) { 604 switch (sdai->type) { 605 case SOF_DAI_INTEL_HDA: 606 return &hda_dspless_dma_ops; 607 case SOF_DAI_INTEL_ALH: 608 if (chip->hw_ip_version < SOF_INTEL_ACE_2_0) 609 return NULL; 610 return &sdw_dspless_dma_ops; 611 default: 612 return NULL; 613 } 614 } 615 616 switch (sdev->pdata->ipc_type) { 617 case SOF_IPC_TYPE_3: 618 { 619 struct sof_dai_private_data *private = sdai->private; 620 621 if (private->dai_config->type == SOF_DAI_INTEL_HDA) 622 return &hda_ipc3_dma_ops; 623 break; 624 } 625 case SOF_IPC_TYPE_4: 626 { 627 struct snd_sof_widget *pipe_widget = swidget->spipe->pipe_widget; 628 struct sof_ipc4_pipeline *pipeline = pipe_widget->private; 629 630 switch (sdai->type) { 631 case SOF_DAI_INTEL_HDA: 632 if (pipeline->use_chain_dma) 633 return &hda_ipc4_chain_dma_ops; 634 635 return &hda_ipc4_dma_ops; 636 case SOF_DAI_INTEL_SSP: 637 if (chip->hw_ip_version < SOF_INTEL_ACE_2_0) 638 return NULL; 639 return &ssp_ipc4_dma_ops; 640 case SOF_DAI_INTEL_DMIC: 641 if (chip->hw_ip_version < SOF_INTEL_ACE_2_0) 642 return NULL; 643 return &dmic_ipc4_dma_ops; 644 case SOF_DAI_INTEL_ALH: 645 if (chip->hw_ip_version < SOF_INTEL_ACE_2_0) 646 return NULL; 647 if (pipeline->use_chain_dma) 648 return &sdw_ipc4_chain_dma_ops; 649 return &sdw_ipc4_dma_ops; 650 651 default: 652 break; 653 } 654 break; 655 } 656 default: 657 break; 658 } 659 #endif 660 return NULL; 661 } 662