1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/debugfs.h> 26 #include <linux/firmware.h> 27 #include <drm/drm_vblank.h> 28 29 #include <drm/drm_file.h> 30 #include <drm/drm_print.h> 31 32 #include "intel_crtc.h" 33 #include "intel_de.h" 34 #include "intel_display_power_well.h" 35 #include "intel_display_regs.h" 36 #include "intel_display_rpm.h" 37 #include "intel_display_types.h" 38 #include "intel_display_utils.h" 39 #include "intel_dmc.h" 40 #include "intel_dmc_regs.h" 41 #include "intel_flipq.h" 42 43 /** 44 * DOC: DMC Firmware Support 45 * 46 * From gen9 onwards we have newly added DMC (Display microcontroller) in display 47 * engine to save and restore the state of display engine when it enter into 48 * low-power state and comes back to normal. 49 */ 50 51 #define INTEL_DMC_FIRMWARE_URL "https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git" 52 53 enum intel_dmc_id { 54 DMC_FW_MAIN = 0, 55 DMC_FW_PIPEA, 56 DMC_FW_PIPEB, 57 DMC_FW_PIPEC, 58 DMC_FW_PIPED, 59 DMC_FW_MAX 60 }; 61 62 struct intel_dmc { 63 struct intel_display *display; 64 struct work_struct work; 65 const char *fw_path; 66 u32 max_fw_size; /* bytes */ 67 u32 version; 68 struct { 69 u32 dc5_start; 70 u32 count; 71 } dc6_allowed; 72 struct dmc_fw_info { 73 u32 mmio_count; 74 intel_reg_t mmioaddr[20]; 75 u32 mmiodata[20]; 76 u32 dmc_offset; 77 u32 start_mmioaddr; 78 u32 dmc_fw_size; /*dwords */ 79 u32 *payload; 80 bool present; 81 } dmc_info[DMC_FW_MAX]; 82 }; 83 84 /* Note: This may be NULL. */ 85 static struct intel_dmc *display_to_dmc(struct intel_display *display) 86 { 87 return display->dmc.dmc; 88 } 89 90 static const char *dmc_firmware_param(struct intel_display *display) 91 { 92 const char *p = display->params.dmc_firmware_path; 93 94 return p && *p ? p : NULL; 95 } 96 97 static bool dmc_firmware_param_disabled(struct intel_display *display) 98 { 99 const char *p = dmc_firmware_param(display); 100 101 /* Magic path to indicate disabled */ 102 return p && !strcmp(p, "/dev/null"); 103 } 104 105 #define DMC_VERSION(major, minor) ((major) << 16 | (minor)) 106 #define DMC_VERSION_MAJOR(version) ((version) >> 16) 107 #define DMC_VERSION_MINOR(version) ((version) & 0xffff) 108 109 #define DMC_PATH(platform) \ 110 "i915/" __stringify(platform) "_dmc.bin" 111 112 /* 113 * New DMC additions should not use this. This is used solely to remain 114 * compatible with systems that have not yet updated DMC blobs to use 115 * unversioned file names. 116 */ 117 #define DMC_LEGACY_PATH(platform, major, minor) \ 118 "i915/" \ 119 __stringify(platform) "_dmc_ver" \ 120 __stringify(major) "_" \ 121 __stringify(minor) ".bin" 122 123 #define XE2LPD_DMC_MAX_FW_SIZE 0x8000 124 #define XELPDP_DMC_MAX_FW_SIZE 0x7000 125 #define DISPLAY_VER13_DMC_MAX_FW_SIZE 0x20000 126 #define DISPLAY_VER12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE 127 128 #define XE3P_LPD_DMC_PATH DMC_PATH(xe3p_lpd) 129 MODULE_FIRMWARE(XE3P_LPD_DMC_PATH); 130 131 #define XE3LPD_3002_DMC_PATH DMC_PATH(xe3lpd_3002) 132 MODULE_FIRMWARE(XE3LPD_3002_DMC_PATH); 133 134 #define XE3LPD_DMC_PATH DMC_PATH(xe3lpd) 135 MODULE_FIRMWARE(XE3LPD_DMC_PATH); 136 137 #define XE2LPD_DMC_PATH DMC_PATH(xe2lpd) 138 MODULE_FIRMWARE(XE2LPD_DMC_PATH); 139 140 #define BMG_DMC_PATH DMC_PATH(bmg) 141 MODULE_FIRMWARE(BMG_DMC_PATH); 142 143 #define MTL_DMC_PATH DMC_PATH(mtl) 144 MODULE_FIRMWARE(MTL_DMC_PATH); 145 146 #define DG2_DMC_PATH DMC_LEGACY_PATH(dg2, 2, 08) 147 MODULE_FIRMWARE(DG2_DMC_PATH); 148 149 #define ADLP_DMC_PATH DMC_PATH(adlp) 150 #define ADLP_DMC_FALLBACK_PATH DMC_LEGACY_PATH(adlp, 2, 16) 151 MODULE_FIRMWARE(ADLP_DMC_PATH); 152 MODULE_FIRMWARE(ADLP_DMC_FALLBACK_PATH); 153 154 #define ADLS_DMC_PATH DMC_LEGACY_PATH(adls, 2, 01) 155 MODULE_FIRMWARE(ADLS_DMC_PATH); 156 157 #define DG1_DMC_PATH DMC_LEGACY_PATH(dg1, 2, 02) 158 MODULE_FIRMWARE(DG1_DMC_PATH); 159 160 #define RKL_DMC_PATH DMC_LEGACY_PATH(rkl, 2, 03) 161 MODULE_FIRMWARE(RKL_DMC_PATH); 162 163 #define TGL_DMC_PATH DMC_LEGACY_PATH(tgl, 2, 12) 164 MODULE_FIRMWARE(TGL_DMC_PATH); 165 166 #define ICL_DMC_PATH DMC_LEGACY_PATH(icl, 1, 09) 167 #define ICL_DMC_MAX_FW_SIZE 0x6000 168 MODULE_FIRMWARE(ICL_DMC_PATH); 169 170 #define GLK_DMC_PATH DMC_LEGACY_PATH(glk, 1, 04) 171 #define GLK_DMC_MAX_FW_SIZE 0x4000 172 MODULE_FIRMWARE(GLK_DMC_PATH); 173 174 #define KBL_DMC_PATH DMC_LEGACY_PATH(kbl, 1, 04) 175 #define KBL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 176 MODULE_FIRMWARE(KBL_DMC_PATH); 177 178 #define SKL_DMC_PATH DMC_LEGACY_PATH(skl, 1, 27) 179 #define SKL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 180 MODULE_FIRMWARE(SKL_DMC_PATH); 181 182 #define BXT_DMC_PATH DMC_LEGACY_PATH(bxt, 1, 07) 183 #define BXT_DMC_MAX_FW_SIZE 0x3000 184 MODULE_FIRMWARE(BXT_DMC_PATH); 185 186 static const char *dmc_firmware_default(struct intel_display *display, u32 *size) 187 { 188 const char *fw_path = NULL; 189 u32 max_fw_size = 0; 190 191 if (DISPLAY_VERx100(display) == 3500) { 192 fw_path = XE3P_LPD_DMC_PATH; 193 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 194 } else if (DISPLAY_VERx100(display) == 3002) { 195 fw_path = XE3LPD_3002_DMC_PATH; 196 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 197 } else if (DISPLAY_VERx100(display) == 3000) { 198 fw_path = XE3LPD_DMC_PATH; 199 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 200 } else if (DISPLAY_VERx100(display) == 2000) { 201 fw_path = XE2LPD_DMC_PATH; 202 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 203 } else if (DISPLAY_VERx100(display) == 1401) { 204 fw_path = BMG_DMC_PATH; 205 max_fw_size = XELPDP_DMC_MAX_FW_SIZE; 206 } else if (DISPLAY_VERx100(display) == 1400) { 207 fw_path = MTL_DMC_PATH; 208 max_fw_size = XELPDP_DMC_MAX_FW_SIZE; 209 } else if (display->platform.dg2) { 210 fw_path = DG2_DMC_PATH; 211 max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 212 } else if (display->platform.alderlake_p) { 213 fw_path = ADLP_DMC_PATH; 214 max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 215 } else if (display->platform.alderlake_s) { 216 fw_path = ADLS_DMC_PATH; 217 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 218 } else if (display->platform.dg1) { 219 fw_path = DG1_DMC_PATH; 220 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 221 } else if (display->platform.rocketlake) { 222 fw_path = RKL_DMC_PATH; 223 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 224 } else if (display->platform.tigerlake) { 225 fw_path = TGL_DMC_PATH; 226 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 227 } else if (DISPLAY_VER(display) == 11) { 228 fw_path = ICL_DMC_PATH; 229 max_fw_size = ICL_DMC_MAX_FW_SIZE; 230 } else if (display->platform.geminilake) { 231 fw_path = GLK_DMC_PATH; 232 max_fw_size = GLK_DMC_MAX_FW_SIZE; 233 } else if (display->platform.kabylake || 234 display->platform.coffeelake || 235 display->platform.cometlake) { 236 fw_path = KBL_DMC_PATH; 237 max_fw_size = KBL_DMC_MAX_FW_SIZE; 238 } else if (display->platform.skylake) { 239 fw_path = SKL_DMC_PATH; 240 max_fw_size = SKL_DMC_MAX_FW_SIZE; 241 } else if (display->platform.broxton) { 242 fw_path = BXT_DMC_PATH; 243 max_fw_size = BXT_DMC_MAX_FW_SIZE; 244 } 245 246 *size = max_fw_size; 247 248 return fw_path; 249 } 250 251 #define DMC_DEFAULT_FW_OFFSET 0xFFFFFFFF 252 #define PACKAGE_MAX_FW_INFO_ENTRIES 20 253 #define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32 254 #define DMC_V1_MAX_MMIO_COUNT 8 255 #define DMC_V3_MAX_MMIO_COUNT 20 256 #define DMC_V1_MMIO_START_RANGE 0x80000 257 258 #define PIPE_TO_DMC_ID(pipe) (DMC_FW_PIPEA + ((pipe) - PIPE_A)) 259 260 struct intel_css_header { 261 /* 0x09 for DMC */ 262 u32 module_type; 263 264 /* Includes the DMC specific header in dwords */ 265 u32 header_len; 266 267 /* always value would be 0x10000 */ 268 u32 header_ver; 269 270 /* Not used */ 271 u32 module_id; 272 273 /* Not used */ 274 u32 module_vendor; 275 276 /* in YYYYMMDD format */ 277 u32 date; 278 279 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */ 280 u32 size; 281 282 /* Not used */ 283 u32 key_size; 284 285 /* Not used */ 286 u32 modulus_size; 287 288 /* Not used */ 289 u32 exponent_size; 290 291 /* Not used */ 292 u32 reserved1[12]; 293 294 /* Major Minor */ 295 u32 version; 296 297 /* Not used */ 298 u32 reserved2[8]; 299 300 /* Not used */ 301 u32 kernel_header_info; 302 } __packed; 303 304 struct intel_fw_info { 305 u8 reserved1; 306 307 /* reserved on package_header version 1, must be 0 on version 2 */ 308 u8 dmc_id; 309 310 /* Stepping (A, B, C, ..., *). * is a wildcard */ 311 char stepping; 312 313 /* Sub-stepping (0, 1, ..., *). * is a wildcard */ 314 char substepping; 315 316 u32 offset; 317 u32 reserved2; 318 } __packed; 319 320 struct intel_package_header { 321 /* DMC container header length in dwords */ 322 u8 header_len; 323 324 /* 0x01, 0x02 */ 325 u8 header_ver; 326 327 u8 reserved[10]; 328 329 /* Number of valid entries in the FWInfo array below */ 330 u32 num_entries; 331 } __packed; 332 333 struct intel_dmc_header_base { 334 /* always value would be 0x40403E3E */ 335 u32 signature; 336 337 /* DMC binary header length */ 338 u8 header_len; 339 340 /* 0x01 */ 341 u8 header_ver; 342 343 /* Reserved */ 344 u16 dmcc_ver; 345 346 /* Major, Minor */ 347 u32 project; 348 349 /* Firmware program size (excluding header) in dwords */ 350 u32 fw_size; 351 352 /* Major Minor version */ 353 u32 fw_version; 354 } __packed; 355 356 struct intel_dmc_header_v1 { 357 struct intel_dmc_header_base base; 358 359 /* Number of valid MMIO cycles present. */ 360 u32 mmio_count; 361 362 /* MMIO address */ 363 u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT]; 364 365 /* MMIO data */ 366 u32 mmiodata[DMC_V1_MAX_MMIO_COUNT]; 367 368 /* FW filename */ 369 char dfile[32]; 370 371 u32 reserved1[2]; 372 } __packed; 373 374 struct intel_dmc_header_v3 { 375 struct intel_dmc_header_base base; 376 377 /* DMC RAM start MMIO address */ 378 u32 start_mmioaddr; 379 380 u32 reserved[9]; 381 382 /* FW filename */ 383 char dfile[32]; 384 385 /* Number of valid MMIO cycles present. */ 386 u32 mmio_count; 387 388 /* MMIO address */ 389 u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT]; 390 391 /* MMIO data */ 392 u32 mmiodata[DMC_V3_MAX_MMIO_COUNT]; 393 } __packed; 394 395 struct stepping_info { 396 char stepping; 397 char substepping; 398 }; 399 400 #define for_each_dmc_id(__dmc_id) \ 401 for ((__dmc_id) = DMC_FW_MAIN; (__dmc_id) < DMC_FW_MAX; (__dmc_id)++) 402 403 static bool is_valid_dmc_id(enum intel_dmc_id dmc_id) 404 { 405 return dmc_id >= DMC_FW_MAIN && dmc_id < DMC_FW_MAX; 406 } 407 408 static bool has_dmc_id_fw(struct intel_display *display, enum intel_dmc_id dmc_id) 409 { 410 struct intel_dmc *dmc = display_to_dmc(display); 411 412 return dmc && dmc->dmc_info[dmc_id].payload; 413 } 414 415 bool intel_dmc_has_payload(struct intel_display *display) 416 { 417 return has_dmc_id_fw(display, DMC_FW_MAIN); 418 } 419 420 static void initialize_stepping_info(struct intel_display *display, struct stepping_info *si) 421 { 422 const char *step_name = DISPLAY_RUNTIME_INFO(display)->step_name; 423 424 si->stepping = step_name[0] ?: '*'; 425 si->substepping = step_name[1] ?: '*'; 426 } 427 428 static void gen9_set_dc_state_debugmask(struct intel_display *display) 429 { 430 /* The below bit doesn't need to be cleared ever afterwards */ 431 intel_de_rmw(display, DC_STATE_DEBUG, 0, 432 DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP); 433 intel_de_posting_read(display, DC_STATE_DEBUG); 434 } 435 436 static void disable_event_handler(struct intel_display *display, 437 intel_reg_t ctl_reg, intel_reg_t htp_reg) 438 { 439 intel_de_write(display, ctl_reg, 440 REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 441 DMC_EVT_CTL_TYPE_EDGE_0_1) | 442 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 443 DMC_EVENT_FALSE)); 444 intel_de_write(display, htp_reg, 0); 445 } 446 447 static void disable_all_event_handlers(struct intel_display *display, 448 enum intel_dmc_id dmc_id) 449 { 450 int handler; 451 452 /* TODO: disable the event handlers on pre-GEN12 platforms as well */ 453 if (DISPLAY_VER(display) < 12) 454 return; 455 456 if (!has_dmc_id_fw(display, dmc_id)) 457 return; 458 459 for (handler = 0; handler < DMC_EVENT_HANDLER_COUNT_GEN12; handler++) 460 disable_event_handler(display, 461 DMC_EVT_CTL(display, dmc_id, handler), 462 DMC_EVT_HTP(display, dmc_id, handler)); 463 } 464 465 static void adlp_pipedmc_clock_gating_wa(struct intel_display *display, bool enable) 466 { 467 enum pipe pipe; 468 469 /* 470 * Wa_16015201720:adl-p,dg2 471 * The WA requires clock gating to be disabled all the time 472 * for pipe A and B. 473 * For pipe C and D clock gating needs to be disabled only 474 * during initializing the firmware. 475 */ 476 if (enable) 477 for (pipe = PIPE_A; pipe <= PIPE_D; pipe++) 478 intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe), 479 0, PIPEDMC_GATING_DIS); 480 else 481 for (pipe = PIPE_C; pipe <= PIPE_D; pipe++) 482 intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe), 483 PIPEDMC_GATING_DIS, 0); 484 } 485 486 static void mtl_pipedmc_clock_gating_wa(struct intel_display *display) 487 { 488 /* 489 * Wa_16015201720 490 * The WA requires clock gating to be disabled all the time 491 * for pipe A and B. 492 */ 493 intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0, 494 MTL_PIPEDMC_GATING_DIS(PIPE_A) | 495 MTL_PIPEDMC_GATING_DIS(PIPE_B)); 496 } 497 498 static void pipedmc_clock_gating_wa(struct intel_display *display, bool enable) 499 { 500 if (display->platform.meteorlake && enable) 501 mtl_pipedmc_clock_gating_wa(display); 502 else if (DISPLAY_VER(display) == 13) 503 adlp_pipedmc_clock_gating_wa(display, enable); 504 } 505 506 static u32 pipedmc_interrupt_mask(struct intel_display *display) 507 { 508 /* 509 * TODO: Check if PIPEDMC_ERROR bit enabling causes errors 510 * on PTL, enable it if validation passes 511 */ 512 if (DISPLAY_VER(display) >= 35) 513 return PIPEDMC_FLIPQ_PROG_DONE | 514 PIPEDMC_ERROR; 515 516 /* 517 * FIXME PIPEDMC_ERROR not enabled for now due to LNL pipe B 518 * triggering it during the first DC state transition. Figure 519 * out what is going on... 520 */ 521 return PIPEDMC_FLIPQ_PROG_DONE | 522 PIPEDMC_GTT_FAULT | 523 PIPEDMC_ATS_FAULT; 524 } 525 526 static u32 dmc_evt_ctl_disable(u32 dmc_evt_ctl) 527 { 528 /* 529 * DMC_EVT_CTL_ENABLE cannot be cleared once set. Always 530 * configure it based on the original event definition to 531 * avoid mismatches in assert_dmc_loaded(). 532 */ 533 return (dmc_evt_ctl & DMC_EVT_CTL_ENABLE) | 534 REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 535 DMC_EVT_CTL_TYPE_EDGE_0_1) | 536 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 537 DMC_EVENT_FALSE); 538 } 539 540 static bool is_dmc_evt_ctl_reg(struct intel_display *display, 541 enum intel_dmc_id dmc_id, intel_reg_t reg) 542 { 543 u32 offset = intel_reg_offset(reg); 544 u32 start = intel_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)); 545 u32 end = intel_reg_offset(DMC_EVT_CTL(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); 546 547 return offset >= start && offset < end; 548 } 549 550 static bool is_dmc_evt_htp_reg(struct intel_display *display, 551 enum intel_dmc_id dmc_id, intel_reg_t reg) 552 { 553 u32 offset = intel_reg_offset(reg); 554 u32 start = intel_reg_offset(DMC_EVT_HTP(display, dmc_id, 0)); 555 u32 end = intel_reg_offset(DMC_EVT_HTP(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); 556 557 return offset >= start && offset < end; 558 } 559 560 static bool is_event_handler(struct intel_display *display, 561 enum intel_dmc_id dmc_id, 562 unsigned int event_id, 563 intel_reg_t reg, u32 data) 564 { 565 return is_dmc_evt_ctl_reg(display, dmc_id, reg) && 566 REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == event_id; 567 } 568 569 static bool fixup_dmc_evt(struct intel_display *display, 570 enum intel_dmc_id dmc_id, 571 intel_reg_t reg_ctl, u32 *data_ctl, 572 intel_reg_t reg_htp, u32 *data_htp) 573 { 574 if (!is_dmc_evt_ctl_reg(display, dmc_id, reg_ctl)) 575 return false; 576 577 if (!is_dmc_evt_htp_reg(display, dmc_id, reg_htp)) 578 return false; 579 580 /* make sure reg_ctl and reg_htp are for the same event */ 581 if (intel_reg_offset(reg_ctl) - intel_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)) != 582 intel_reg_offset(reg_htp) - intel_reg_offset(DMC_EVT_HTP(display, dmc_id, 0))) 583 return false; 584 585 /* 586 * On ADL-S the HRR event handler is not restored after DC6. 587 * Clear it to zero from the beginning to avoid mismatches later. 588 */ 589 if (display->platform.alderlake_s && dmc_id == DMC_FW_MAIN && 590 is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_A, reg_ctl, *data_ctl)) { 591 *data_ctl = 0; 592 *data_htp = 0; 593 return true; 594 } 595 596 /* 597 * TGL/ADL-S DMC firmware incorrectly uses the undelayed vblank 598 * event for the HRR handler, when it should be using the delayed 599 * vblank event instead. Fixed firmware was never released 600 * so the Windows driver just hacks around it by overriding 601 * the event ID. Do the same. 602 */ 603 if ((display->platform.tigerlake || display->platform.alderlake_s) && 604 is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_A, reg_ctl, *data_ctl)) { 605 *data_ctl &= ~DMC_EVT_CTL_EVENT_ID_MASK; 606 *data_ctl |= REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 607 MAINDMC_EVENT_VBLANK_DELAYED_A); 608 return true; 609 } 610 611 return false; 612 } 613 614 static bool disable_dmc_evt(struct intel_display *display, 615 enum intel_dmc_id dmc_id, 616 intel_reg_t reg, u32 data) 617 { 618 if (!is_dmc_evt_ctl_reg(display, dmc_id, reg)) 619 return false; 620 621 /* keep all pipe DMC events disabled by default */ 622 if (dmc_id != DMC_FW_MAIN) 623 return true; 624 625 /* also disable the flip queue event on the main DMC on TGL */ 626 if (display->platform.tigerlake && 627 is_event_handler(display, dmc_id, MAINDMC_EVENT_CLK_MSEC, reg, data)) 628 return true; 629 630 /* also disable the HRR event on the main DMC on TGL/ADLS */ 631 if ((display->platform.tigerlake || display->platform.alderlake_s) && 632 is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_DELAYED_A, reg, data)) 633 return true; 634 635 return false; 636 } 637 638 static u32 dmc_mmiodata(struct intel_display *display, 639 struct intel_dmc *dmc, 640 enum intel_dmc_id dmc_id, int i) 641 { 642 if (disable_dmc_evt(display, dmc_id, 643 dmc->dmc_info[dmc_id].mmioaddr[i], 644 dmc->dmc_info[dmc_id].mmiodata[i])) 645 return dmc_evt_ctl_disable(dmc->dmc_info[dmc_id].mmiodata[i]); 646 else 647 return dmc->dmc_info[dmc_id].mmiodata[i]; 648 } 649 650 static void dmc_load_mmio(struct intel_display *display, enum intel_dmc_id dmc_id) 651 { 652 struct intel_dmc *dmc = display_to_dmc(display); 653 int i; 654 655 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { 656 intel_de_write(display, dmc->dmc_info[dmc_id].mmioaddr[i], 657 dmc_mmiodata(display, dmc, dmc_id, i)); 658 } 659 } 660 661 static void dmc_load_program(struct intel_display *display, enum intel_dmc_id dmc_id) 662 { 663 struct intel_dmc *dmc = display_to_dmc(display); 664 int i; 665 666 disable_all_event_handlers(display, dmc_id); 667 668 preempt_disable(); 669 670 for (i = 0; i < dmc->dmc_info[dmc_id].dmc_fw_size; i++) { 671 intel_de_write_fw(display, 672 DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, i), 673 dmc->dmc_info[dmc_id].payload[i]); 674 } 675 676 preempt_enable(); 677 678 dmc_load_mmio(display, dmc_id); 679 } 680 681 static void assert_dmc_loaded(struct intel_display *display, 682 enum intel_dmc_id dmc_id) 683 { 684 struct intel_dmc *dmc = display_to_dmc(display); 685 u32 expected, found; 686 int i; 687 688 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) 689 return; 690 691 found = intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, 0)); 692 expected = dmc->dmc_info[dmc_id].payload[0]; 693 694 drm_WARN(display->drm, found != expected, 695 "DMC %d program storage start incorrect (expected 0x%x, current 0x%x)\n", 696 dmc_id, expected, found); 697 698 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { 699 intel_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i]; 700 701 found = intel_de_read(display, reg); 702 expected = dmc_mmiodata(display, dmc, dmc_id, i); 703 704 drm_WARN(display->drm, found != expected, 705 "DMC %d mmio[%d]/0x%x incorrect (expected 0x%x, current 0x%x)\n", 706 dmc_id, i, intel_reg_offset(reg), expected, found); 707 } 708 } 709 710 void assert_main_dmc_loaded(struct intel_display *display) 711 { 712 assert_dmc_loaded(display, DMC_FW_MAIN); 713 } 714 715 static bool need_pipedmc_load_program(struct intel_display *display) 716 { 717 /* On TGL/derivatives pipe DMC state is lost when PG1 is disabled */ 718 return DISPLAY_VER(display) == 12; 719 } 720 721 static bool need_pipedmc_load_mmio(struct intel_display *display, enum pipe pipe) 722 { 723 /* 724 * Xe3_LPD/Xe3p_LPD: 725 * - pipe A/B DMC doesn't need save/restore 726 * - pipe C/D DMC is in PG0, needs manual save/restore 727 */ 728 if (IS_DISPLAY_VER(display, 30, 35)) 729 return pipe >= PIPE_C; 730 731 /* 732 * FIXME LNL unclear, main DMC firmware has the pipe DMC A/B PG0 733 * save/restore, but so far unable to see the loss of pipe DMC state 734 * in action. Are we just failing to turn off PG0 due to some other 735 * SoC level stuff? 736 */ 737 if (DISPLAY_VER(display) == 20) 738 return false; 739 740 /* 741 * FIXME BMG untested, main DMC firmware has the 742 * pipe DMC A/B PG0 save/restore... 743 */ 744 if (display->platform.battlemage) 745 return false; 746 747 /* 748 * DG2: 749 * - Pipe DMCs presumably in PG0? 750 * - No DC6, and even DC9 doesn't seem to result 751 * in loss of DMC state for whatever reason 752 */ 753 if (display->platform.dg2) 754 return false; 755 756 /* 757 * ADL/MTL: 758 * - pipe A/B DMC is in PG0, saved/restored by the main DMC 759 * - pipe C/D DMC is in PG0, needs manual save/restore 760 */ 761 if (IS_DISPLAY_VER(display, 13, 14)) 762 return pipe >= PIPE_C; 763 764 return false; 765 } 766 767 static bool can_enable_pipedmc(const struct intel_crtc_state *crtc_state) 768 { 769 struct intel_display *display = to_intel_display(crtc_state); 770 771 /* 772 * On TGL/derivatives pipe DMC state is lost when PG1 is disabled. 773 * Do not even enable the pipe DMC when that can happen outside 774 * of driver control (PSR+DC5/6). 775 */ 776 if (DISPLAY_VER(display) == 12 && crtc_state->has_psr) 777 return false; 778 779 return true; 780 } 781 782 void intel_dmc_enable_pipe(const struct intel_crtc_state *crtc_state) 783 { 784 struct intel_display *display = to_intel_display(crtc_state); 785 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 786 enum pipe pipe = crtc->pipe; 787 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 788 789 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) 790 return; 791 792 if (!can_enable_pipedmc(crtc_state)) { 793 intel_dmc_disable_pipe(crtc_state); 794 return; 795 } 796 797 if (need_pipedmc_load_program(display)) 798 dmc_load_program(display, dmc_id); 799 else if (need_pipedmc_load_mmio(display, pipe)) 800 dmc_load_mmio(display, dmc_id); 801 802 assert_dmc_loaded(display, dmc_id); 803 804 if (DISPLAY_VER(display) >= 20) { 805 intel_flipq_reset(display, pipe); 806 807 intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display)); 808 intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~pipedmc_interrupt_mask(display)); 809 } 810 811 if (DISPLAY_VER(display) >= 14) 812 intel_de_rmw(display, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe)); 813 else 814 intel_de_rmw(display, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE); 815 } 816 817 void intel_dmc_disable_pipe(const struct intel_crtc_state *crtc_state) 818 { 819 struct intel_display *display = to_intel_display(crtc_state); 820 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 821 enum pipe pipe = crtc->pipe; 822 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 823 824 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) 825 return; 826 827 if (DISPLAY_VER(display) >= 14) 828 intel_de_rmw(display, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0); 829 else 830 intel_de_rmw(display, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0); 831 832 if (DISPLAY_VER(display) >= 20) { 833 intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~0); 834 intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display)); 835 836 intel_flipq_reset(display, pipe); 837 } 838 } 839 840 static void dmc_configure_event(struct intel_display *display, 841 enum intel_dmc_id dmc_id, 842 unsigned int event_id, 843 bool enable) 844 { 845 struct intel_dmc *dmc = display_to_dmc(display); 846 int num_handlers = 0; 847 int i; 848 849 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { 850 intel_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i]; 851 u32 data = dmc->dmc_info[dmc_id].mmiodata[i]; 852 853 if (!is_event_handler(display, dmc_id, event_id, reg, data)) 854 continue; 855 856 intel_de_write(display, reg, enable ? data : dmc_evt_ctl_disable(data)); 857 num_handlers++; 858 } 859 860 drm_WARN_ONCE(display->drm, num_handlers != 1, 861 "DMC %d has %d handlers for event 0x%x\n", 862 dmc_id, num_handlers, event_id); 863 } 864 865 void intel_dmc_configure_dc_balance_event(struct intel_display *display, 866 enum pipe pipe, bool enable) 867 { 868 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 869 870 dmc_configure_event(display, dmc_id, PIPEDMC_EVENT_ADAPTIVE_DCB_TRIGGER, enable); 871 } 872 873 /** 874 * intel_dmc_block_pkgc() - block PKG C-state 875 * @display: display instance 876 * @pipe: pipe which register use to block 877 * @block: block/unblock 878 * 879 * This interface is target for Wa_16025596647 usage. I.e. to set/clear 880 * PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS bit in PIPEDMC_BLOCK_PKGC_SW register. 881 */ 882 void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe, 883 bool block) 884 { 885 intel_de_rmw(display, PIPEDMC_BLOCK_PKGC_SW(pipe), 886 PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS, block ? 887 PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS : 0); 888 } 889 890 /** 891 * intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank() - start of PKG 892 * C-state exit 893 * @display: display instance 894 * @pipe: pipe which register use to block 895 * @enable: enable/disable 896 * 897 * This interface is target for Wa_16025596647 usage. I.e. start the package C 898 * exit at the start of the undelayed vblank 899 */ 900 void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display *display, 901 enum pipe pipe, bool enable) 902 { 903 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 904 905 dmc_configure_event(display, dmc_id, PIPEDMC_EVENT_VBLANK, enable); 906 } 907 908 /** 909 * intel_dmc_load_program() - write the firmware from memory to register. 910 * @display: display instance 911 * 912 * DMC firmware is read from a .bin file and kept in internal memory one time. 913 * Everytime display comes back from low power state this function is called to 914 * copy the firmware from internal memory to registers. 915 */ 916 void intel_dmc_load_program(struct intel_display *display) 917 { 918 struct i915_power_domains *power_domains = &display->power.domains; 919 enum intel_dmc_id dmc_id; 920 921 if (!intel_dmc_has_payload(display)) 922 return; 923 924 assert_display_rpm_held(display); 925 926 pipedmc_clock_gating_wa(display, true); 927 928 for_each_dmc_id(dmc_id) { 929 dmc_load_program(display, dmc_id); 930 assert_dmc_loaded(display, dmc_id); 931 } 932 933 if (DISPLAY_VER(display) >= 20) 934 intel_de_write(display, DMC_FQ_W2_PTS_CFG_SEL, 935 PIPE_D_DMC_W2_PTS_CONFIG_SELECT(PIPE_D) | 936 PIPE_C_DMC_W2_PTS_CONFIG_SELECT(PIPE_C) | 937 PIPE_B_DMC_W2_PTS_CONFIG_SELECT(PIPE_B) | 938 PIPE_A_DMC_W2_PTS_CONFIG_SELECT(PIPE_A)); 939 940 power_domains->dc_state = 0; 941 942 gen9_set_dc_state_debugmask(display); 943 944 pipedmc_clock_gating_wa(display, false); 945 } 946 947 /** 948 * intel_dmc_disable_program() - disable the firmware 949 * @display: display instance 950 * 951 * Disable all event handlers in the firmware, making sure the firmware is 952 * inactive after the display is uninitialized. 953 */ 954 void intel_dmc_disable_program(struct intel_display *display) 955 { 956 enum intel_dmc_id dmc_id; 957 958 if (!intel_dmc_has_payload(display)) 959 return; 960 961 pipedmc_clock_gating_wa(display, true); 962 963 for_each_dmc_id(dmc_id) 964 disable_all_event_handlers(display, dmc_id); 965 966 pipedmc_clock_gating_wa(display, false); 967 } 968 969 static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info, 970 const struct stepping_info *si) 971 { 972 if ((fw_info->substepping == '*' && si->stepping == fw_info->stepping) || 973 (si->stepping == fw_info->stepping && si->substepping == fw_info->substepping) || 974 /* 975 * If we don't find a more specific one from above two checks, we 976 * then check for the generic one to be sure to work even with 977 * "broken firmware" 978 */ 979 (si->stepping == '*' && si->substepping == fw_info->substepping) || 980 (fw_info->stepping == '*' && fw_info->substepping == '*')) 981 return true; 982 983 return false; 984 } 985 986 /* 987 * Search fw_info table for dmc_offset to find firmware binary: num_entries is 988 * already sanitized. 989 */ 990 static void dmc_set_fw_offset(struct intel_dmc *dmc, 991 const struct intel_fw_info *fw_info, 992 unsigned int num_entries, 993 const struct stepping_info *si, 994 u8 package_ver) 995 { 996 struct intel_display *display = dmc->display; 997 enum intel_dmc_id dmc_id; 998 unsigned int i; 999 1000 for (i = 0; i < num_entries; i++) { 1001 dmc_id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id; 1002 1003 if (!is_valid_dmc_id(dmc_id)) { 1004 drm_dbg(display->drm, "Unsupported firmware id: %u\n", dmc_id); 1005 continue; 1006 } 1007 1008 /* More specific versions come first, so we don't even have to 1009 * check for the stepping since we already found a previous FW 1010 * for this id. 1011 */ 1012 if (dmc->dmc_info[dmc_id].present) 1013 continue; 1014 1015 if (fw_info_matches_stepping(&fw_info[i], si)) { 1016 dmc->dmc_info[dmc_id].present = true; 1017 dmc->dmc_info[dmc_id].dmc_offset = fw_info[i].offset; 1018 } 1019 } 1020 } 1021 1022 static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc, 1023 const u32 *mmioaddr, u32 mmio_count, 1024 int header_ver, enum intel_dmc_id dmc_id) 1025 { 1026 struct intel_display *display = dmc->display; 1027 u32 start_range, end_range; 1028 int i; 1029 1030 if (header_ver == 1) { 1031 start_range = DMC_MMIO_START_RANGE; 1032 end_range = DMC_MMIO_END_RANGE; 1033 } else if (dmc_id == DMC_FW_MAIN) { 1034 start_range = TGL_MAIN_MMIO_START; 1035 end_range = TGL_MAIN_MMIO_END; 1036 } else if (DISPLAY_VER(display) >= 13) { 1037 start_range = ADLP_PIPE_MMIO_START; 1038 end_range = ADLP_PIPE_MMIO_END; 1039 } else if (DISPLAY_VER(display) >= 12) { 1040 start_range = TGL_PIPE_MMIO_START(dmc_id); 1041 end_range = TGL_PIPE_MMIO_END(dmc_id); 1042 } else { 1043 drm_warn(display->drm, "Unknown mmio range for sanity check"); 1044 return false; 1045 } 1046 1047 for (i = 0; i < mmio_count; i++) { 1048 if (mmioaddr[i] < start_range || mmioaddr[i] > end_range) 1049 return false; 1050 } 1051 1052 return true; 1053 } 1054 1055 static u32 parse_dmc_fw_header(struct intel_dmc *dmc, 1056 const struct intel_dmc_header_base *dmc_header, 1057 size_t rem_size, enum intel_dmc_id dmc_id) 1058 { 1059 struct intel_display *display = dmc->display; 1060 struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id]; 1061 unsigned int header_len_bytes, dmc_header_size, payload_size, i; 1062 const u32 *mmioaddr, *mmiodata; 1063 u32 mmio_count, mmio_count_max, start_mmioaddr; 1064 u8 *payload; 1065 1066 BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT || 1067 ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT); 1068 1069 /* 1070 * Check if we can access common fields, we will checkc again below 1071 * after we have read the version 1072 */ 1073 if (rem_size < sizeof(struct intel_dmc_header_base)) 1074 goto error_truncated; 1075 1076 /* Cope with small differences between v1 and v3 */ 1077 if (dmc_header->header_ver == 3) { 1078 const struct intel_dmc_header_v3 *v3 = 1079 (const struct intel_dmc_header_v3 *)dmc_header; 1080 1081 if (rem_size < sizeof(struct intel_dmc_header_v3)) 1082 goto error_truncated; 1083 1084 mmioaddr = v3->mmioaddr; 1085 mmiodata = v3->mmiodata; 1086 mmio_count = v3->mmio_count; 1087 mmio_count_max = DMC_V3_MAX_MMIO_COUNT; 1088 /* header_len is in dwords */ 1089 header_len_bytes = dmc_header->header_len * 4; 1090 start_mmioaddr = v3->start_mmioaddr; 1091 dmc_header_size = sizeof(*v3); 1092 } else if (dmc_header->header_ver == 1) { 1093 const struct intel_dmc_header_v1 *v1 = 1094 (const struct intel_dmc_header_v1 *)dmc_header; 1095 1096 if (rem_size < sizeof(struct intel_dmc_header_v1)) 1097 goto error_truncated; 1098 1099 mmioaddr = v1->mmioaddr; 1100 mmiodata = v1->mmiodata; 1101 mmio_count = v1->mmio_count; 1102 mmio_count_max = DMC_V1_MAX_MMIO_COUNT; 1103 header_len_bytes = dmc_header->header_len; 1104 start_mmioaddr = DMC_V1_MMIO_START_RANGE; 1105 dmc_header_size = sizeof(*v1); 1106 } else { 1107 drm_err(display->drm, "Unknown DMC fw header version: %u\n", 1108 dmc_header->header_ver); 1109 return 0; 1110 } 1111 1112 if (header_len_bytes != dmc_header_size) { 1113 drm_err(display->drm, "DMC firmware has wrong dmc header length " 1114 "(%u bytes)\n", header_len_bytes); 1115 return 0; 1116 } 1117 1118 /* Cache the dmc header info. */ 1119 if (mmio_count > mmio_count_max) { 1120 drm_err(display->drm, "DMC firmware has wrong mmio count %u\n", mmio_count); 1121 return 0; 1122 } 1123 1124 if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count, 1125 dmc_header->header_ver, dmc_id)) { 1126 drm_err(display->drm, "DMC firmware has Wrong MMIO Addresses\n"); 1127 return 0; 1128 } 1129 1130 drm_dbg_kms(display->drm, "DMC %d:\n", dmc_id); 1131 for (i = 0; i < mmio_count; i++) { 1132 dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]); 1133 dmc_info->mmiodata[i] = mmiodata[i]; 1134 } 1135 1136 for (i = 0; i < mmio_count - 1; i++) { 1137 u32 orig_mmiodata[2] = { 1138 dmc_info->mmiodata[i], 1139 dmc_info->mmiodata[i+1], 1140 }; 1141 1142 if (!fixup_dmc_evt(display, dmc_id, 1143 dmc_info->mmioaddr[i], &dmc_info->mmiodata[i], 1144 dmc_info->mmioaddr[i+1], &dmc_info->mmiodata[i+1])) 1145 continue; 1146 1147 drm_dbg_kms(display->drm, 1148 " mmio[%d]: 0x%x = 0x%x->0x%x (EVT_CTL)\n", 1149 i, intel_reg_offset(dmc_info->mmioaddr[i]), 1150 orig_mmiodata[0], dmc_info->mmiodata[i]); 1151 drm_dbg_kms(display->drm, 1152 " mmio[%d]: 0x%x = 0x%x->0x%x (EVT_HTP)\n", 1153 i+1, intel_reg_offset(dmc_info->mmioaddr[i+1]), 1154 orig_mmiodata[1], dmc_info->mmiodata[i+1]); 1155 } 1156 1157 for (i = 0; i < mmio_count; i++) { 1158 drm_dbg_kms(display->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n", 1159 i, intel_reg_offset(dmc_info->mmioaddr[i]), dmc_info->mmiodata[i], 1160 is_dmc_evt_ctl_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" : 1161 is_dmc_evt_htp_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "", 1162 disable_dmc_evt(display, dmc_id, dmc_info->mmioaddr[i], 1163 dmc_info->mmiodata[i]) ? " (disabling)" : ""); 1164 } 1165 dmc_info->mmio_count = mmio_count; 1166 dmc_info->start_mmioaddr = start_mmioaddr; 1167 1168 rem_size -= header_len_bytes; 1169 1170 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */ 1171 payload_size = dmc_header->fw_size * 4; 1172 if (rem_size < payload_size) 1173 goto error_truncated; 1174 1175 if (payload_size > dmc->max_fw_size) { 1176 drm_err(display->drm, "DMC FW too big (%u bytes)\n", payload_size); 1177 return 0; 1178 } 1179 dmc_info->dmc_fw_size = dmc_header->fw_size; 1180 1181 dmc_info->payload = kmalloc(payload_size, GFP_KERNEL); 1182 if (!dmc_info->payload) 1183 return 0; 1184 1185 payload = (u8 *)(dmc_header) + header_len_bytes; 1186 memcpy(dmc_info->payload, payload, payload_size); 1187 1188 return header_len_bytes + payload_size; 1189 1190 error_truncated: 1191 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); 1192 return 0; 1193 } 1194 1195 static u32 1196 parse_dmc_fw_package(struct intel_dmc *dmc, 1197 const struct intel_package_header *package_header, 1198 const struct stepping_info *si, 1199 size_t rem_size) 1200 { 1201 struct intel_display *display = dmc->display; 1202 u32 package_size = sizeof(struct intel_package_header); 1203 u32 num_entries, max_entries; 1204 const struct intel_fw_info *fw_info; 1205 1206 if (rem_size < package_size) 1207 goto error_truncated; 1208 1209 if (package_header->header_ver == 1) { 1210 max_entries = PACKAGE_MAX_FW_INFO_ENTRIES; 1211 } else if (package_header->header_ver == 2) { 1212 max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES; 1213 } else { 1214 drm_err(display->drm, "DMC firmware has unknown header version %u\n", 1215 package_header->header_ver); 1216 return 0; 1217 } 1218 1219 /* 1220 * We should always have space for max_entries, 1221 * even if not all are used 1222 */ 1223 package_size += max_entries * sizeof(struct intel_fw_info); 1224 if (rem_size < package_size) 1225 goto error_truncated; 1226 1227 if (package_header->header_len * 4 != package_size) { 1228 drm_err(display->drm, "DMC firmware has wrong package header length " 1229 "(%u bytes)\n", package_size); 1230 return 0; 1231 } 1232 1233 num_entries = package_header->num_entries; 1234 if (WARN_ON(num_entries > max_entries)) 1235 num_entries = max_entries; 1236 1237 fw_info = (const struct intel_fw_info *) 1238 ((u8 *)package_header + sizeof(*package_header)); 1239 dmc_set_fw_offset(dmc, fw_info, num_entries, si, 1240 package_header->header_ver); 1241 1242 /* dmc_offset is in dwords */ 1243 return package_size; 1244 1245 error_truncated: 1246 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); 1247 return 0; 1248 } 1249 1250 /* Return number of bytes parsed or 0 on error */ 1251 static u32 parse_dmc_fw_css(struct intel_dmc *dmc, 1252 struct intel_css_header *css_header, 1253 size_t rem_size) 1254 { 1255 struct intel_display *display = dmc->display; 1256 1257 if (rem_size < sizeof(struct intel_css_header)) { 1258 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); 1259 return 0; 1260 } 1261 1262 if (sizeof(struct intel_css_header) != 1263 (css_header->header_len * 4)) { 1264 drm_err(display->drm, "DMC firmware has wrong CSS header length " 1265 "(%u bytes)\n", 1266 (css_header->header_len * 4)); 1267 return 0; 1268 } 1269 1270 dmc->version = css_header->version; 1271 1272 return sizeof(struct intel_css_header); 1273 } 1274 1275 static int parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw) 1276 { 1277 struct intel_display *display = dmc->display; 1278 struct intel_css_header *css_header; 1279 struct intel_package_header *package_header; 1280 struct intel_dmc_header_base *dmc_header; 1281 struct stepping_info si = {}; 1282 enum intel_dmc_id dmc_id; 1283 u32 readcount = 0; 1284 u32 r, offset; 1285 1286 if (!fw) 1287 return -EINVAL; 1288 1289 initialize_stepping_info(display, &si); 1290 1291 /* Extract CSS Header information */ 1292 css_header = (struct intel_css_header *)fw->data; 1293 r = parse_dmc_fw_css(dmc, css_header, fw->size); 1294 if (!r) 1295 return -EINVAL; 1296 1297 readcount += r; 1298 1299 /* Extract Package Header information */ 1300 package_header = (struct intel_package_header *)&fw->data[readcount]; 1301 r = parse_dmc_fw_package(dmc, package_header, &si, fw->size - readcount); 1302 if (!r) 1303 return -EINVAL; 1304 1305 readcount += r; 1306 1307 for_each_dmc_id(dmc_id) { 1308 if (!dmc->dmc_info[dmc_id].present) 1309 continue; 1310 1311 offset = readcount + dmc->dmc_info[dmc_id].dmc_offset * 4; 1312 if (offset > fw->size) { 1313 drm_err(display->drm, "Reading beyond the fw_size\n"); 1314 continue; 1315 } 1316 1317 dmc_header = (struct intel_dmc_header_base *)&fw->data[offset]; 1318 parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, dmc_id); 1319 } 1320 1321 if (!intel_dmc_has_payload(display)) { 1322 drm_err(display->drm, "DMC firmware main program not found\n"); 1323 return -ENOENT; 1324 } 1325 1326 return 0; 1327 } 1328 1329 static void intel_dmc_runtime_pm_get(struct intel_display *display) 1330 { 1331 drm_WARN_ON(display->drm, display->dmc.wakeref); 1332 display->dmc.wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT); 1333 } 1334 1335 static void intel_dmc_runtime_pm_put(struct intel_display *display) 1336 { 1337 struct ref_tracker *wakeref __maybe_unused = 1338 fetch_and_zero(&display->dmc.wakeref); 1339 1340 intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); 1341 } 1342 1343 static const char *dmc_fallback_path(struct intel_display *display) 1344 { 1345 if (display->platform.alderlake_p) 1346 return ADLP_DMC_FALLBACK_PATH; 1347 1348 return NULL; 1349 } 1350 1351 static void dmc_load_work_fn(struct work_struct *work) 1352 { 1353 struct intel_dmc *dmc = container_of(work, typeof(*dmc), work); 1354 struct intel_display *display = dmc->display; 1355 const struct firmware *fw = NULL; 1356 const char *fallback_path; 1357 int err; 1358 1359 err = request_firmware(&fw, dmc->fw_path, display->drm->dev); 1360 1361 if (err == -ENOENT && !dmc_firmware_param(display)) { 1362 fallback_path = dmc_fallback_path(display); 1363 if (fallback_path) { 1364 drm_dbg_kms(display->drm, "%s not found, falling back to %s\n", 1365 dmc->fw_path, fallback_path); 1366 err = request_firmware(&fw, fallback_path, display->drm->dev); 1367 if (err == 0) 1368 dmc->fw_path = fallback_path; 1369 } 1370 } 1371 1372 if (err) { 1373 drm_notice(display->drm, 1374 "Failed to load DMC firmware %s (%pe). Disabling runtime power management.\n", 1375 dmc->fw_path, ERR_PTR(err)); 1376 drm_notice(display->drm, "DMC firmware homepage: %s", 1377 INTEL_DMC_FIRMWARE_URL); 1378 return; 1379 } 1380 1381 err = parse_dmc_fw(dmc, fw); 1382 if (err) { 1383 drm_notice(display->drm, 1384 "Failed to parse DMC firmware %s (%pe). Disabling runtime power management.\n", 1385 dmc->fw_path, ERR_PTR(err)); 1386 goto out; 1387 } 1388 1389 intel_dmc_load_program(display); 1390 intel_dmc_runtime_pm_put(display); 1391 1392 drm_info(display->drm, "Finished loading DMC firmware %s (v%u.%u)\n", 1393 dmc->fw_path, DMC_VERSION_MAJOR(dmc->version), 1394 DMC_VERSION_MINOR(dmc->version)); 1395 1396 out: 1397 release_firmware(fw); 1398 } 1399 1400 /** 1401 * intel_dmc_init() - initialize the firmware loading. 1402 * @display: display instance 1403 * 1404 * This function is called at the time of loading the display driver to read 1405 * firmware from a .bin file and copied into a internal memory. 1406 */ 1407 void intel_dmc_init(struct intel_display *display) 1408 { 1409 struct intel_dmc *dmc; 1410 1411 if (!HAS_DMC(display)) 1412 return; 1413 1414 /* 1415 * Obtain a runtime pm reference, until DMC is loaded, to avoid entering 1416 * runtime-suspend. 1417 * 1418 * On error, we return with the rpm wakeref held to prevent runtime 1419 * suspend as runtime suspend *requires* a working DMC for whatever 1420 * reason. 1421 */ 1422 intel_dmc_runtime_pm_get(display); 1423 1424 dmc = kzalloc_obj(*dmc); 1425 if (!dmc) 1426 return; 1427 1428 dmc->display = display; 1429 1430 INIT_WORK(&dmc->work, dmc_load_work_fn); 1431 1432 dmc->fw_path = dmc_firmware_default(display, &dmc->max_fw_size); 1433 1434 if (dmc_firmware_param_disabled(display)) { 1435 drm_info(display->drm, "Disabling DMC firmware and runtime PM\n"); 1436 goto out; 1437 } 1438 1439 if (dmc_firmware_param(display)) 1440 dmc->fw_path = dmc_firmware_param(display); 1441 1442 if (!dmc->fw_path) { 1443 drm_dbg_kms(display->drm, 1444 "No known DMC firmware for platform, disabling runtime PM\n"); 1445 goto out; 1446 } 1447 1448 display->dmc.dmc = dmc; 1449 1450 drm_dbg_kms(display->drm, "Loading %s\n", dmc->fw_path); 1451 queue_work(display->wq.unordered, &dmc->work); 1452 1453 return; 1454 1455 out: 1456 kfree(dmc); 1457 } 1458 1459 /** 1460 * intel_dmc_suspend() - prepare DMC firmware before system suspend 1461 * @display: display instance 1462 * 1463 * Prepare the DMC firmware before entering system suspend. This includes 1464 * flushing pending work items and releasing any resources acquired during 1465 * init. 1466 */ 1467 void intel_dmc_suspend(struct intel_display *display) 1468 { 1469 struct intel_dmc *dmc = display_to_dmc(display); 1470 1471 if (!HAS_DMC(display)) 1472 return; 1473 1474 if (dmc) 1475 flush_work(&dmc->work); 1476 1477 /* Drop the reference held in case DMC isn't loaded. */ 1478 if (!intel_dmc_has_payload(display)) 1479 intel_dmc_runtime_pm_put(display); 1480 } 1481 1482 void intel_dmc_wait_fw_load(struct intel_display *display) 1483 { 1484 struct intel_dmc *dmc = display_to_dmc(display); 1485 1486 if (!HAS_DMC(display)) 1487 return; 1488 1489 if (dmc) 1490 flush_work(&dmc->work); 1491 } 1492 1493 /** 1494 * intel_dmc_resume() - init DMC firmware during system resume 1495 * @display: display instance 1496 * 1497 * Reinitialize the DMC firmware during system resume, reacquiring any 1498 * resources released in intel_dmc_suspend(). 1499 */ 1500 void intel_dmc_resume(struct intel_display *display) 1501 { 1502 if (!HAS_DMC(display)) 1503 return; 1504 1505 /* 1506 * Reacquire the reference to keep RPM disabled in case DMC isn't 1507 * loaded. 1508 */ 1509 if (!intel_dmc_has_payload(display)) 1510 intel_dmc_runtime_pm_get(display); 1511 } 1512 1513 /** 1514 * intel_dmc_fini() - unload the DMC firmware. 1515 * @display: display instance 1516 * 1517 * Firmmware unloading includes freeing the internal memory and reset the 1518 * firmware loading status. 1519 */ 1520 void intel_dmc_fini(struct intel_display *display) 1521 { 1522 struct intel_dmc *dmc = display_to_dmc(display); 1523 enum intel_dmc_id dmc_id; 1524 1525 if (!HAS_DMC(display)) 1526 return; 1527 1528 intel_dmc_suspend(display); 1529 drm_WARN_ON(display->drm, display->dmc.wakeref); 1530 1531 if (dmc) { 1532 for_each_dmc_id(dmc_id) 1533 kfree(dmc->dmc_info[dmc_id].payload); 1534 1535 kfree(dmc); 1536 display->dmc.dmc = NULL; 1537 } 1538 } 1539 1540 struct intel_dmc_snapshot { 1541 bool initialized; 1542 bool loaded; 1543 u32 version; 1544 }; 1545 1546 struct intel_dmc_snapshot *intel_dmc_snapshot_capture(struct intel_display *display) 1547 { 1548 struct intel_dmc *dmc = display_to_dmc(display); 1549 struct intel_dmc_snapshot *snapshot; 1550 1551 if (!HAS_DMC(display)) 1552 return NULL; 1553 1554 snapshot = kzalloc_obj(*snapshot, GFP_ATOMIC); 1555 if (!snapshot) 1556 return NULL; 1557 1558 snapshot->initialized = dmc; 1559 snapshot->loaded = intel_dmc_has_payload(display); 1560 if (dmc) 1561 snapshot->version = dmc->version; 1562 1563 return snapshot; 1564 } 1565 1566 void intel_dmc_snapshot_print(const struct intel_dmc_snapshot *snapshot, struct drm_printer *p) 1567 { 1568 if (!snapshot) 1569 return; 1570 1571 drm_printf(p, "DMC initialized: %s\n", str_yes_no(snapshot->initialized)); 1572 drm_printf(p, "DMC loaded: %s\n", str_yes_no(snapshot->loaded)); 1573 if (snapshot->initialized) 1574 drm_printf(p, "DMC fw version: %d.%d\n", 1575 DMC_VERSION_MAJOR(snapshot->version), 1576 DMC_VERSION_MINOR(snapshot->version)); 1577 } 1578 1579 void intel_dmc_update_dc6_allowed_count(struct intel_display *display, 1580 bool start_tracking) 1581 { 1582 struct intel_dmc *dmc = display_to_dmc(display); 1583 u32 dc5_cur_count; 1584 1585 if (DISPLAY_VER(display) < 14) 1586 return; 1587 1588 dc5_cur_count = intel_de_read(display, DG1_DMC_DEBUG_DC5_COUNT); 1589 1590 if (!start_tracking) 1591 dmc->dc6_allowed.count += dc5_cur_count - dmc->dc6_allowed.dc5_start; 1592 1593 dmc->dc6_allowed.dc5_start = dc5_cur_count; 1594 } 1595 1596 static bool intel_dmc_get_dc6_allowed_count(struct intel_display *display, u32 *count) 1597 { 1598 struct i915_power_domains *power_domains = &display->power.domains; 1599 struct intel_dmc *dmc = display_to_dmc(display); 1600 bool dc6_enabled; 1601 1602 if (DISPLAY_VER(display) < 14) 1603 return false; 1604 1605 mutex_lock(&power_domains->lock); 1606 dc6_enabled = power_domains->dc_state & DC_STATE_EN_UPTO_DC6; 1607 if (dc6_enabled) 1608 intel_dmc_update_dc6_allowed_count(display, false); 1609 1610 *count = dmc->dc6_allowed.count; 1611 mutex_unlock(&power_domains->lock); 1612 1613 return true; 1614 } 1615 1616 static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) 1617 { 1618 struct intel_display *display = m->private; 1619 struct intel_dmc *dmc = display_to_dmc(display); 1620 struct ref_tracker *wakeref; 1621 intel_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG; 1622 u32 dc6_allowed_count; 1623 1624 if (!HAS_DMC(display)) 1625 return -ENODEV; 1626 1627 wakeref = intel_display_rpm_get(display); 1628 1629 seq_printf(m, "DMC initialized: %s\n", str_yes_no(dmc)); 1630 seq_printf(m, "fw loaded: %s\n", 1631 str_yes_no(intel_dmc_has_payload(display))); 1632 seq_printf(m, "path: %s\n", dmc ? dmc->fw_path : "N/A"); 1633 seq_printf(m, "Pipe A fw needed: %s\n", 1634 str_yes_no(DISPLAY_VER(display) >= 12)); 1635 seq_printf(m, "Pipe A fw loaded: %s\n", 1636 str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEA))); 1637 seq_printf(m, "Pipe B fw needed: %s\n", 1638 str_yes_no(display->platform.alderlake_p || 1639 DISPLAY_VER(display) >= 14)); 1640 seq_printf(m, "Pipe B fw loaded: %s\n", 1641 str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEB))); 1642 1643 if (!intel_dmc_has_payload(display)) 1644 goto out; 1645 1646 seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version), 1647 DMC_VERSION_MINOR(dmc->version)); 1648 1649 if (DISPLAY_VER(display) >= 12) { 1650 intel_reg_t dc3co_reg; 1651 1652 if (display->platform.dgfx || DISPLAY_VER(display) >= 14) { 1653 dc3co_reg = DG1_DMC_DEBUG3; 1654 dc5_reg = DG1_DMC_DEBUG_DC5_COUNT; 1655 } else { 1656 dc3co_reg = TGL_DMC_DEBUG3; 1657 dc5_reg = TGL_DMC_DEBUG_DC5_COUNT; 1658 dc6_reg = TGL_DMC_DEBUG_DC6_COUNT; 1659 } 1660 1661 seq_printf(m, "DC3CO count: %d\n", 1662 intel_de_read(display, dc3co_reg)); 1663 } else { 1664 dc5_reg = display->platform.broxton ? BXT_DMC_DC3_DC5_COUNT : 1665 SKL_DMC_DC3_DC5_COUNT; 1666 if (!display->platform.geminilake && !display->platform.broxton) 1667 dc6_reg = SKL_DMC_DC5_DC6_COUNT; 1668 } 1669 1670 seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg)); 1671 1672 if (intel_dmc_get_dc6_allowed_count(display, &dc6_allowed_count)) 1673 seq_printf(m, "DC5 -> DC6 allowed count: %d\n", 1674 dc6_allowed_count); 1675 else if (intel_reg_valid(dc6_reg)) 1676 seq_printf(m, "DC5 -> DC6 count: %d\n", 1677 intel_de_read(display, dc6_reg)); 1678 1679 seq_printf(m, "program base: 0x%08x\n", 1680 intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0))); 1681 1682 out: 1683 seq_printf(m, "ssp base: 0x%08x\n", 1684 intel_de_read(display, DMC_SSP_BASE)); 1685 seq_printf(m, "htp: 0x%08x\n", intel_de_read(display, DMC_HTP_SKL)); 1686 1687 intel_display_rpm_put(display, wakeref); 1688 1689 return 0; 1690 } 1691 1692 DEFINE_SHOW_ATTRIBUTE(intel_dmc_debugfs_status); 1693 1694 void intel_dmc_debugfs_register(struct intel_display *display) 1695 { 1696 debugfs_create_file("i915_dmc_info", 0444, display->drm->debugfs_root, 1697 display, &intel_dmc_debugfs_status_fops); 1698 } 1699 1700 void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe) 1701 { 1702 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); 1703 u32 tmp = 0, int_vector; 1704 1705 if (DISPLAY_VER(display) >= 20) { 1706 tmp = intel_de_read(display, PIPEDMC_INTERRUPT(pipe)); 1707 intel_de_write(display, PIPEDMC_INTERRUPT(pipe), tmp); 1708 1709 if (tmp & PIPEDMC_FLIPQ_PROG_DONE) { 1710 spin_lock(&display->drm->event_lock); 1711 1712 if (crtc->flipq_event) { 1713 /* 1714 * Update vblank counter/timestamp in case it 1715 * hasn't been done yet for this frame. 1716 */ 1717 drm_crtc_accurate_vblank_count(&crtc->base); 1718 1719 drm_crtc_send_vblank_event(&crtc->base, crtc->flipq_event); 1720 crtc->flipq_event = NULL; 1721 } 1722 1723 spin_unlock(&display->drm->event_lock); 1724 } 1725 1726 if (tmp & PIPEDMC_ATS_FAULT) 1727 drm_err_ratelimited(display->drm, "[CRTC:%d:%s] PIPEDMC ATS fault\n", 1728 crtc->base.base.id, crtc->base.name); 1729 if (tmp & PIPEDMC_GTT_FAULT) 1730 drm_err_ratelimited(display->drm, "[CRTC:%d:%s] PIPEDMC GTT fault\n", 1731 crtc->base.base.id, crtc->base.name); 1732 if (tmp & PIPEDMC_ERROR) 1733 drm_err(display->drm, "[CRTC:%d:%s] PIPEDMC error\n", 1734 crtc->base.base.id, crtc->base.name); 1735 } 1736 1737 int_vector = intel_de_read(display, PIPEDMC_STATUS(pipe)) & PIPEDMC_INT_VECTOR_MASK; 1738 if (tmp == 0 && int_vector != 0) 1739 drm_err(display->drm, "[CRTC:%d:%s] PIPEDMC interrupt vector 0x%x\n", 1740 crtc->base.base.id, crtc->base.name, int_vector); 1741 } 1742 1743 void intel_pipedmc_enable_event(struct intel_crtc *crtc, 1744 enum pipedmc_event_id event) 1745 { 1746 struct intel_display *display = to_intel_display(crtc); 1747 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe); 1748 1749 dmc_configure_event(display, dmc_id, event, true); 1750 } 1751 1752 void intel_pipedmc_disable_event(struct intel_crtc *crtc, 1753 enum pipedmc_event_id event) 1754 { 1755 struct intel_display *display = to_intel_display(crtc); 1756 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe); 1757 1758 dmc_configure_event(display, dmc_id, event, false); 1759 } 1760 1761 u32 intel_pipedmc_start_mmioaddr(struct intel_crtc *crtc) 1762 { 1763 struct intel_display *display = to_intel_display(crtc); 1764 struct intel_dmc *dmc = display_to_dmc(display); 1765 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe); 1766 1767 return dmc ? dmc->dmc_info[dmc_id].start_mmioaddr : 0; 1768 } 1769 1770 void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc) 1771 { 1772 struct intel_display *display = to_intel_display(crtc); 1773 enum pipe pipe = crtc->pipe; 1774 1775 intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe), 1776 PIPEDMC_ADAPTIVE_DCB_ENABLE); 1777 } 1778 1779 void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc) 1780 { 1781 struct intel_display *display = to_intel_display(crtc); 1782 enum pipe pipe = crtc->pipe; 1783 1784 intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe), 0); 1785 } 1786