xref: /linux/drivers/gpu/drm/arm/hdlcd_drv.h (revision 7ae9fb1b7ecbb5d85d07857943f677fd1a559b18)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  *  ARM HDLCD Controller register definition
4  */
5 
6 #ifndef __HDLCD_DRV_H__
7 #define __HDLCD_DRV_H__
8 
9 struct hdlcd_drm_private {
10 	struct drm_device		base;
11 	void __iomem			*mmio;
12 	struct clk			*clk;
13 	struct drm_crtc			crtc;
14 	struct drm_plane		*plane;
15 	unsigned int			irq;
16 #ifdef CONFIG_DEBUG_FS
17 	atomic_t buffer_underrun_count;
18 	atomic_t bus_error_count;
19 	atomic_t vsync_count;
20 	atomic_t dma_end_count;
21 #endif
22 };
23 
24 #define drm_to_hdlcd_priv(x)	container_of(x, struct hdlcd_drm_private, base)
25 #define crtc_to_hdlcd_priv(x)	container_of(x, struct hdlcd_drm_private, crtc)
26 
hdlcd_write(struct hdlcd_drm_private * hdlcd,unsigned int reg,u32 value)27 static inline void hdlcd_write(struct hdlcd_drm_private *hdlcd,
28 			       unsigned int reg, u32 value)
29 {
30 	writel(value, hdlcd->mmio + reg);
31 }
32 
hdlcd_read(struct hdlcd_drm_private * hdlcd,unsigned int reg)33 static inline u32 hdlcd_read(struct hdlcd_drm_private *hdlcd, unsigned int reg)
34 {
35 	return readl(hdlcd->mmio + reg);
36 }
37 
38 int hdlcd_setup_crtc(struct drm_device *dev);
39 void hdlcd_set_scanout(struct hdlcd_drm_private *hdlcd);
40 
41 #endif /* __HDLCD_DRV_H__ */
42