1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Memory Encryption Support Common Code
4 *
5 * Copyright (C) 2016 Advanced Micro Devices, Inc.
6 *
7 * Author: Tom Lendacky <thomas.lendacky@amd.com>
8 */
9
10 #include <linux/dma-direct.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/swiotlb.h>
13 #include <linux/cc_platform.h>
14 #include <linux/mem_encrypt.h>
15 #include <linux/virtio_anchor.h>
16 #include <linux/iommu-dma.h>
17
18 #include <asm/sev.h>
19
20 /* Override for DMA direct allocation check - ARCH_HAS_FORCE_DMA_UNENCRYPTED */
force_dma_unencrypted(struct device * dev)21 bool force_dma_unencrypted(struct device *dev)
22 {
23 /*
24 * For SEV, all DMA must be to unencrypted addresses.
25 */
26 if (cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT))
27 return true;
28
29 /*
30 * For SME, all DMA must be to unencrypted addresses if the
31 * device does not support DMA to addresses that include the
32 * encryption mask.
33 */
34 if (cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT) && !use_dma_iommu(dev)) {
35 u64 dma_enc_mask = DMA_BIT_MASK(__ffs64(sme_me_mask));
36 u64 dma_dev_mask = min_not_zero(dev->coherent_dma_mask,
37 dev->bus_dma_limit);
38
39 if (dma_dev_mask <= dma_enc_mask)
40 return true;
41 }
42
43 return false;
44 }
45
print_mem_encrypt_feature_info(void)46 static void print_mem_encrypt_feature_info(void)
47 {
48 pr_info("Memory Encryption Features active: ");
49
50 switch (cc_vendor) {
51 case CC_VENDOR_INTEL:
52 pr_cont("Intel TDX\n");
53 break;
54 case CC_VENDOR_AMD:
55 pr_cont("AMD");
56
57 /* Secure Memory Encryption */
58 if (cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT)) {
59 /*
60 * SME is mutually exclusive with any of the SEV
61 * features below.
62 */
63 pr_cont(" SME\n");
64 return;
65 }
66
67 /* Secure Encrypted Virtualization */
68 if (cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT))
69 pr_cont(" SEV");
70
71 /* Encrypted Register State */
72 if (cc_platform_has(CC_ATTR_GUEST_STATE_ENCRYPT))
73 pr_cont(" SEV-ES");
74
75 /* Secure Nested Paging */
76 if (cc_platform_has(CC_ATTR_GUEST_SEV_SNP))
77 pr_cont(" SEV-SNP");
78
79 pr_cont("\n");
80
81 sev_show_status();
82
83 break;
84 default:
85 pr_cont("Unknown\n");
86 }
87 }
88
89 /* Architecture __weak replacement functions */
mem_encrypt_init(void)90 void __init mem_encrypt_init(void)
91 {
92 if (!cc_platform_has(CC_ATTR_MEM_ENCRYPT))
93 return;
94
95 /* Call into SWIOTLB to update the SWIOTLB DMA buffers */
96 swiotlb_update_mem_attributes();
97
98 snp_secure_tsc_prepare();
99
100 print_mem_encrypt_feature_info();
101 }
102
mem_encrypt_setup_arch(void)103 void __init mem_encrypt_setup_arch(void)
104 {
105 phys_addr_t total_mem = memblock_phys_mem_size();
106 unsigned long size;
107
108 /*
109 * Do RMP table fixups after the e820 tables have been setup by
110 * e820__memory_setup().
111 */
112 if (cc_platform_has(CC_ATTR_HOST_SEV_SNP))
113 snp_fixup_e820_tables();
114
115 if (!cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT))
116 return;
117
118 /*
119 * For SEV and TDX, all DMA has to occur via shared/unencrypted pages.
120 * Kernel uses SWIOTLB to make this happen without changing device
121 * drivers. However, depending on the workload being run, the
122 * default 64MB of SWIOTLB may not be enough and SWIOTLB may
123 * run out of buffers for DMA, resulting in I/O errors and/or
124 * performance degradation especially with high I/O workloads.
125 *
126 * Adjust the default size of SWIOTLB using a percentage of guest
127 * memory for SWIOTLB buffers. Also, as the SWIOTLB bounce buffer
128 * memory is allocated from low memory, ensure that the adjusted size
129 * is within the limits of low available memory.
130 *
131 * The percentage of guest memory used here for SWIOTLB buffers
132 * is more of an approximation of the static adjustment which
133 * 64MB for <1G, and ~128M to 256M for 1G-to-4G, i.e., the 6%
134 */
135 size = total_mem * 6 / 100;
136 size = clamp_val(size, IO_TLB_DEFAULT_SIZE, SZ_1G);
137 swiotlb_adjust_size(size);
138
139 /* Set restricted memory access for virtio. */
140 virtio_set_mem_acc_cb(virtio_require_restricted_mem_acc);
141 }
142