1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * ST stm32 Chrom-Art - 2D Graphics Accelerator Driver
4 *
5 * Copyright (c) 2021 Dillon Min
6 * Dillon Min, <dillon.minfei@gmail.com>
7 *
8 * based on s5p-g2d
9 *
10 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
11 * Kamil Debski, <k.debski@samsung.com>
12 */
13
14 #include <linux/io.h>
15
16 #include "dma2d.h"
17 #include "dma2d-regs.h"
18
reg_read(void __iomem * base,u32 reg)19 static inline u32 reg_read(void __iomem *base, u32 reg)
20 {
21 return readl_relaxed(base + reg);
22 }
23
reg_write(void __iomem * base,u32 reg,u32 val)24 static inline void reg_write(void __iomem *base, u32 reg, u32 val)
25 {
26 writel_relaxed(val, base + reg);
27 }
28
reg_update_bits(void __iomem * base,u32 reg,u32 mask,u32 val)29 static inline void reg_update_bits(void __iomem *base, u32 reg, u32 mask,
30 u32 val)
31 {
32 reg_write(base, reg, (reg_read(base, reg) & ~mask) | val);
33 }
34
dma2d_start(struct dma2d_dev * d)35 void dma2d_start(struct dma2d_dev *d)
36 {
37 reg_update_bits(d->regs, DMA2D_CR_REG, CR_START, CR_START);
38 }
39
dma2d_get_int(struct dma2d_dev * d)40 u32 dma2d_get_int(struct dma2d_dev *d)
41 {
42 return reg_read(d->regs, DMA2D_ISR_REG);
43 }
44
dma2d_clear_int(struct dma2d_dev * d)45 void dma2d_clear_int(struct dma2d_dev *d)
46 {
47 u32 isr_val = reg_read(d->regs, DMA2D_ISR_REG);
48
49 reg_write(d->regs, DMA2D_IFCR_REG, isr_val & 0x003f);
50 }
51
dma2d_config_common(struct dma2d_dev * d,enum dma2d_op_mode op_mode,u16 width,u16 height)52 void dma2d_config_common(struct dma2d_dev *d, enum dma2d_op_mode op_mode,
53 u16 width, u16 height)
54 {
55 reg_update_bits(d->regs, DMA2D_CR_REG, CR_MODE_MASK,
56 op_mode << CR_MODE_SHIFT);
57
58 reg_write(d->regs, DMA2D_NLR_REG, (width << 16) | height);
59 }
60
dma2d_config_out(struct dma2d_dev * d,struct dma2d_frame * frm,dma_addr_t o_addr)61 void dma2d_config_out(struct dma2d_dev *d, struct dma2d_frame *frm,
62 dma_addr_t o_addr)
63 {
64 reg_update_bits(d->regs, DMA2D_CR_REG, CR_CEIE, CR_CEIE);
65 reg_update_bits(d->regs, DMA2D_CR_REG, CR_CTCIE, CR_CTCIE);
66 reg_update_bits(d->regs, DMA2D_CR_REG, CR_CAEIE, CR_CAEIE);
67 reg_update_bits(d->regs, DMA2D_CR_REG, CR_TCIE, CR_TCIE);
68 reg_update_bits(d->regs, DMA2D_CR_REG, CR_TEIE, CR_TEIE);
69
70 if (frm->fmt->cmode >= CM_MODE_ARGB8888 &&
71 frm->fmt->cmode <= CM_MODE_ARGB4444)
72 reg_update_bits(d->regs, DMA2D_OPFCCR_REG, OPFCCR_CM_MASK,
73 frm->fmt->cmode);
74
75 reg_write(d->regs, DMA2D_OMAR_REG, o_addr);
76
77 reg_write(d->regs, DMA2D_OCOLR_REG,
78 (frm->a_rgb[3] << 24) |
79 (frm->a_rgb[2] << 16) |
80 (frm->a_rgb[1] << 8) |
81 frm->a_rgb[0]);
82
83 reg_update_bits(d->regs, DMA2D_OOR_REG, OOR_LO_MASK,
84 frm->line_offset & 0x3fff);
85 }
86
dma2d_config_fg(struct dma2d_dev * d,struct dma2d_frame * frm,dma_addr_t f_addr)87 void dma2d_config_fg(struct dma2d_dev *d, struct dma2d_frame *frm,
88 dma_addr_t f_addr)
89 {
90 reg_write(d->regs, DMA2D_FGMAR_REG, f_addr);
91 reg_update_bits(d->regs, DMA2D_FGOR_REG, FGOR_LO_MASK,
92 frm->line_offset);
93
94 if (frm->fmt->cmode >= CM_MODE_ARGB8888 &&
95 frm->fmt->cmode <= CM_MODE_A4)
96 reg_update_bits(d->regs, DMA2D_FGPFCCR_REG, FGPFCCR_CM_MASK,
97 frm->fmt->cmode);
98
99 reg_update_bits(d->regs, DMA2D_FGPFCCR_REG, FGPFCCR_AM_MASK,
100 (frm->a_mode << 16) & 0x03);
101
102 reg_update_bits(d->regs, DMA2D_FGPFCCR_REG, FGPFCCR_ALPHA_MASK,
103 frm->a_rgb[3] << 24);
104
105 reg_write(d->regs, DMA2D_FGCOLR_REG,
106 (frm->a_rgb[2] << 16) |
107 (frm->a_rgb[1] << 8) |
108 frm->a_rgb[0]);
109 }
110
dma2d_config_bg(struct dma2d_dev * d,struct dma2d_frame * frm,dma_addr_t b_addr)111 void dma2d_config_bg(struct dma2d_dev *d, struct dma2d_frame *frm,
112 dma_addr_t b_addr)
113 {
114 reg_write(d->regs, DMA2D_BGMAR_REG, b_addr);
115 reg_update_bits(d->regs, DMA2D_BGOR_REG, BGOR_LO_MASK,
116 frm->line_offset);
117
118 if (frm->fmt->cmode >= CM_MODE_ARGB8888 &&
119 frm->fmt->cmode <= CM_MODE_A4)
120 reg_update_bits(d->regs, DMA2D_BGPFCCR_REG, BGPFCCR_CM_MASK,
121 frm->fmt->cmode);
122
123 reg_update_bits(d->regs, DMA2D_BGPFCCR_REG, BGPFCCR_AM_MASK,
124 (frm->a_mode << 16) & 0x03);
125
126 reg_update_bits(d->regs, DMA2D_BGPFCCR_REG, BGPFCCR_ALPHA_MASK,
127 frm->a_rgb[3] << 24);
128
129 reg_write(d->regs, DMA2D_BGCOLR_REG,
130 (frm->a_rgb[2] << 16) |
131 (frm->a_rgb[1] << 8) |
132 frm->a_rgb[0]);
133 }
134