1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include <linux/vmalloc.h>
28 #include <drm/display/drm_dp_helper.h>
29 #include <drm/display/drm_dp_mst_helper.h>
30 #include <drm/drm_atomic.h>
31 #include <drm/drm_atomic_helper.h>
32 #include <drm/drm_fixed.h>
33 #include <drm/drm_edid.h>
34 #include "dm_services.h"
35 #include "amdgpu.h"
36 #include "amdgpu_dm.h"
37 #include "dmub_cmd.h"
38 #include "amdgpu_dm_mst_types.h"
39 #include "amdgpu_dm_hdcp.h"
40
41 #include "dc.h"
42 #include "dm_helpers.h"
43
44 #include "ddc_service_types.h"
45 #include "dpcd_defs.h"
46
47 #if defined(CONFIG_DEBUG_FS)
48 #include "amdgpu_dm_debugfs.h"
49 #endif
50
51 #include "dc/resource/dcn20/dcn20_resource.h"
52
53 #define PEAK_FACTOR_X1000 1006
54
55 /*
56 * Translate a failed AUX transaction's operation result into an errno-style
57 * return value. @result is returned unchanged for AUX_RET_SUCCESS.
58 */
dm_dp_aux_transfer_result(ssize_t result,enum aux_return_code_type operation_result)59 STATIC_IFN_KUNIT ssize_t dm_dp_aux_transfer_result(ssize_t result,
60 enum aux_return_code_type operation_result)
61 {
62 switch (operation_result) {
63 case AUX_RET_SUCCESS:
64 break;
65 case AUX_RET_ERROR_HPD_DISCON:
66 case AUX_RET_ERROR_UNKNOWN:
67 case AUX_RET_ERROR_INVALID_OPERATION:
68 case AUX_RET_ERROR_PROTOCOL_ERROR:
69 result = -EIO;
70 break;
71 case AUX_RET_ERROR_INVALID_REPLY:
72 case AUX_RET_ERROR_ENGINE_ACQUIRE:
73 result = -EBUSY;
74 break;
75 case AUX_RET_ERROR_TIMEOUT:
76 result = -ETIMEDOUT;
77 break;
78 }
79
80 return result;
81 }
82 EXPORT_IF_KUNIT(dm_dp_aux_transfer_result);
83
84 /*
85 * Derive the AUX payload transaction flags from a DP AUX request field.
86 */
dm_dp_aux_fill_payload_flags(u8 request,struct aux_payload * payload)87 STATIC_IFN_KUNIT void dm_dp_aux_fill_payload_flags(u8 request,
88 struct aux_payload *payload)
89 {
90 payload->i2c_over_aux = (request & DP_AUX_NATIVE_WRITE) == 0;
91 payload->write = (request & DP_AUX_I2C_READ) == 0;
92 payload->mot = (request & DP_AUX_I2C_MOT) != 0;
93 payload->write_status_update =
94 (request & DP_AUX_I2C_WRITE_STATUS_UPDATE) != 0;
95 }
96 EXPORT_IF_KUNIT(dm_dp_aux_fill_payload_flags);
97
98 /*
99 * This function handles both native AUX and I2C-Over-AUX transactions.
100 */
dm_dp_aux_transfer(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)101 STATIC_IFN_KUNIT ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
102 struct drm_dp_aux_msg *msg)
103 {
104 ssize_t result = 0;
105 struct aux_payload payload;
106 enum aux_return_code_type operation_result;
107 struct amdgpu_device *adev;
108 struct ddc_service *ddc;
109 uint8_t copy[16];
110
111 if (WARN_ON(msg->size > 16))
112 return -E2BIG;
113
114 payload.address = msg->address;
115 payload.data = msg->buffer;
116 payload.length = msg->size;
117 payload.reply = &msg->reply;
118 dm_dp_aux_fill_payload_flags(msg->request, &payload);
119 payload.defer_delay = 0;
120
121 if (payload.write) {
122 memcpy(copy, msg->buffer, msg->size);
123 payload.data = copy;
124 }
125
126 result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload,
127 &operation_result);
128
129 /*
130 * w/a on certain intel platform where hpd is unexpected to pull low during
131 * 1st sideband message transaction by return AUX_RET_ERROR_HPD_DISCON
132 * aux transaction is succuess in such case, therefore bypass the error
133 */
134 ddc = TO_DM_AUX(aux)->ddc_service;
135 adev = ddc->ctx->driver_context;
136 if (adev->dm.aux_hpd_discon_quirk) {
137 if (msg->address == DP_SIDEBAND_MSG_DOWN_REQ_BASE &&
138 operation_result == AUX_RET_ERROR_HPD_DISCON) {
139 result = msg->size;
140 operation_result = AUX_RET_SUCCESS;
141 }
142 }
143
144 /*
145 * result equals to 0 includes the cases of AUX_DEFER/I2C_DEFER
146 */
147 if (payload.write && result >= 0) {
148 if (result) {
149 /*one byte indicating partially written bytes*/
150 drm_dbg_dp(adev_to_drm(adev), "AUX partially written\n");
151 result = payload.data[0];
152 } else if (!payload.reply[0])
153 /*I2C_ACK|AUX_ACK*/
154 result = msg->size;
155 }
156
157 if (result < 0) {
158 result = dm_dp_aux_transfer_result(result, operation_result);
159
160 drm_dbg_dp(adev_to_drm(adev), "DP AUX transfer fail:%d\n", operation_result);
161 }
162
163 if (payload.reply[0])
164 drm_dbg_dp(adev_to_drm(adev), "AUX reply command not ACK: 0x%02x.",
165 payload.reply[0]);
166
167 return result;
168 }
169 EXPORT_IF_KUNIT(dm_dp_aux_transfer);
170
171 static void
dm_dp_mst_connector_destroy(struct drm_connector * connector)172 dm_dp_mst_connector_destroy(struct drm_connector *connector)
173 {
174 struct amdgpu_dm_connector *aconnector =
175 to_amdgpu_dm_connector(connector);
176
177 if (aconnector->dc_sink) {
178 dc_link_remove_remote_sink(aconnector->dc_link,
179 aconnector->dc_sink);
180 dc_sink_release(aconnector->dc_sink);
181 }
182
183 drm_edid_free(aconnector->drm_edid);
184
185 drm_connector_cleanup(connector);
186 drm_dp_mst_put_port_malloc(aconnector->mst_output_port);
187 kfree(aconnector);
188 }
189
190 static int
amdgpu_dm_mst_connector_late_register(struct drm_connector * connector)191 amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
192 {
193 struct amdgpu_dm_connector *amdgpu_dm_connector =
194 to_amdgpu_dm_connector(connector);
195 int r;
196
197 r = drm_dp_mst_connector_late_register(connector,
198 amdgpu_dm_connector->mst_output_port);
199 if (r < 0)
200 return r;
201
202 #if defined(CONFIG_DEBUG_FS)
203 connector_debugfs_init(amdgpu_dm_connector);
204 #endif
205
206 return 0;
207 }
208
209
210 STATIC_IFN_KUNIT void
amdgpu_dm_mst_reset_mst_connector_setting(struct amdgpu_dm_connector * aconnector)211 amdgpu_dm_mst_reset_mst_connector_setting(struct amdgpu_dm_connector *aconnector)
212 {
213 aconnector->drm_edid = NULL;
214 aconnector->dsc_aux = NULL;
215 aconnector->mst_output_port->passthrough_aux = NULL;
216 aconnector->mst_local_bw = 0;
217 aconnector->vc_full_pbn = 0;
218 }
219 EXPORT_IF_KUNIT(amdgpu_dm_mst_reset_mst_connector_setting);
220
221 static void
amdgpu_dm_mst_connector_early_unregister(struct drm_connector * connector)222 amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
223 {
224 struct amdgpu_dm_connector *aconnector =
225 to_amdgpu_dm_connector(connector);
226 struct drm_dp_mst_port *port = aconnector->mst_output_port;
227 struct amdgpu_dm_connector *root = aconnector->mst_root;
228 struct dc_link *dc_link = aconnector->dc_link;
229 struct dc_sink *dc_sink = aconnector->dc_sink;
230
231 drm_dp_mst_connector_early_unregister(connector, port);
232
233 /*
234 * Release dc_sink for connector which its attached port is
235 * no longer in the mst topology
236 */
237 drm_modeset_lock(&root->mst_mgr.base.lock, NULL);
238 if (dc_sink) {
239 if (dc_link->sink_count)
240 dc_link_remove_remote_sink(dc_link, dc_sink);
241
242 drm_dbg_dp(connector->dev,
243 "DM_MST: remove remote sink 0x%p, %d remaining\n",
244 dc_sink, dc_link->sink_count);
245
246 dc_sink_release(dc_sink);
247 aconnector->dc_sink = NULL;
248 amdgpu_dm_mst_reset_mst_connector_setting(aconnector);
249 }
250
251 aconnector->mst_status = MST_STATUS_DEFAULT;
252 drm_modeset_unlock(&root->mst_mgr.base.lock);
253 }
254
255 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
256 .fill_modes = drm_helper_probe_single_connector_modes,
257 .destroy = dm_dp_mst_connector_destroy,
258 .reset = amdgpu_dm_connector_funcs_reset,
259 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
260 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
261 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
262 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
263 .late_register = amdgpu_dm_mst_connector_late_register,
264 .early_unregister = amdgpu_dm_mst_connector_early_unregister,
265 };
266
needs_dsc_aux_workaround(struct dc_link * link)267 bool needs_dsc_aux_workaround(struct dc_link *link)
268 {
269 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
270 (link->dpcd_caps.dpcd_rev.raw == DPCD_REV_14 || link->dpcd_caps.dpcd_rev.raw == DPCD_REV_12) &&
271 link->dpcd_caps.sink_count.bits.SINK_COUNT >= 2)
272 return true;
273
274 return false;
275 }
276 EXPORT_IF_KUNIT(needs_dsc_aux_workaround);
277
278 #if defined(CONFIG_DRM_AMD_DC_FP)
is_synaptics_cascaded_panamera(struct dc_link * link,struct drm_dp_mst_port * port)279 static bool is_synaptics_cascaded_panamera(struct dc_link *link, struct drm_dp_mst_port *port)
280 {
281 u8 branch_vendor_data[4] = { 0 }; // Vendor data 0x50C ~ 0x50F
282
283 if (drm_dp_dpcd_read(port->mgr->aux, DP_BRANCH_VENDOR_SPECIFIC_START, &branch_vendor_data, 4) == 4) {
284 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
285 IS_SYNAPTICS_CASCADED_PANAMERA(link->dpcd_caps.branch_dev_name, branch_vendor_data)) {
286 DRM_INFO("Synaptics Cascaded MST hub\n");
287 return true;
288 }
289 }
290
291 return false;
292 }
293
validate_dsc_caps_on_connector(struct amdgpu_dm_connector * aconnector)294 static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector)
295 {
296 struct dc_sink *dc_sink = aconnector->dc_sink;
297 struct drm_dp_mst_port *port = aconnector->mst_output_port;
298 u8 dsc_caps[16] = { 0 };
299 u8 dsc_branch_dec_caps_raw[3] = { 0 }; // DSC branch decoder caps 0xA0 ~ 0xA2
300 u8 *dsc_branch_dec_caps = NULL;
301
302 aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);
303
304 /*
305 * drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs
306 * because it only check the dsc/fec caps of the "port variable" and not the dock
307 *
308 * This case will return NULL: DSC capabe MST dock connected to a non fec/dsc capable display
309 *
310 * Workaround: explicitly check the use case above and use the mst dock's aux as dsc_aux
311 *
312 */
313 if (!aconnector->dsc_aux && !port->parent->port_parent &&
314 needs_dsc_aux_workaround(aconnector->dc_link))
315 aconnector->dsc_aux = &aconnector->mst_root->dm_dp_aux.aux;
316
317 /* synaptics cascaded MST hub case */
318 if (is_synaptics_cascaded_panamera(aconnector->dc_link, port))
319 aconnector->dsc_aux = port->mgr->aux;
320
321 if (!aconnector->dsc_aux)
322 return false;
323
324 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0)
325 return false;
326
327 if (drm_dp_dpcd_read(aconnector->dsc_aux,
328 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, dsc_branch_dec_caps_raw, 3) == 3)
329 dsc_branch_dec_caps = dsc_branch_dec_caps_raw;
330
331 if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
332 dsc_caps, dsc_branch_dec_caps,
333 &dc_sink->dsc_caps.dsc_dec_caps))
334 return false;
335
336 return true;
337 }
338 #endif
339
retrieve_downstream_port_device(struct amdgpu_dm_connector * aconnector)340 STATIC_IFN_KUNIT bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnector)
341 {
342 union dp_downstream_port_present ds_port_present;
343
344 if (!aconnector->dsc_aux)
345 return false;
346
347 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DOWNSTREAMPORT_PRESENT, &ds_port_present, 1) < 0) {
348 DRM_INFO("Failed to read downstream_port_present 0x05 from DFP of branch device\n");
349 return false;
350 }
351
352 aconnector->mst_downstream_port_present = ds_port_present;
353 DRM_INFO("Downstream port present %d, type %d\n",
354 ds_port_present.fields.PORT_PRESENT, ds_port_present.fields.PORT_TYPE);
355
356 return true;
357 }
358 EXPORT_IF_KUNIT(retrieve_downstream_port_device);
359
retrieve_branch_specific_data(struct amdgpu_dm_connector * aconnector)360 STATIC_IFN_KUNIT bool retrieve_branch_specific_data(struct amdgpu_dm_connector *aconnector)
361 {
362 struct drm_connector *connector = &aconnector->base;
363 struct drm_dp_mst_port *port = aconnector->mst_output_port;
364 struct drm_dp_mst_port *port_parent;
365 struct drm_dp_aux *immediate_upstream_aux;
366 struct drm_dp_desc branch_desc;
367
368 if (!port->parent)
369 return false;
370
371 port_parent = port->parent->port_parent;
372
373 immediate_upstream_aux = port_parent ? &port_parent->aux : port->mgr->aux;
374
375 if (drm_dp_read_desc(immediate_upstream_aux, &branch_desc, true))
376 return false;
377
378 aconnector->branch_ieee_oui = (branch_desc.ident.oui[0] << 16) +
379 (branch_desc.ident.oui[1] << 8) +
380 (branch_desc.ident.oui[2]);
381
382 drm_dbg_dp(port->aux.drm_dev, "MST branch oui 0x%x detected at %s\n",
383 aconnector->branch_ieee_oui, connector->name);
384
385 return true;
386 }
387 EXPORT_IF_KUNIT(retrieve_branch_specific_data);
388
dm_dp_mst_get_modes(struct drm_connector * connector)389 static int dm_dp_mst_get_modes(struct drm_connector *connector)
390 {
391 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
392 int ret = 0;
393
394 if (!aconnector->drm_edid) {
395 const struct drm_edid *drm_edid;
396
397 drm_edid = drm_dp_mst_edid_read(connector,
398 &aconnector->mst_root->mst_mgr,
399 aconnector->mst_output_port);
400
401 if (!drm_edid) {
402 amdgpu_dm_set_mst_status(&aconnector->mst_status,
403 MST_REMOTE_EDID, false);
404
405 drm_edid_connector_update(
406 &aconnector->base,
407 NULL);
408
409 DRM_DEBUG_KMS("Can't get EDID of %s. Add default remote sink.", connector->name);
410 if (!aconnector->dc_sink) {
411 struct dc_sink *dc_sink;
412 struct dc_sink_init_data init_params = {
413 .link = aconnector->dc_link,
414 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
415
416 dc_sink = dc_link_add_remote_sink(
417 aconnector->dc_link,
418 NULL,
419 0,
420 &init_params);
421
422 if (!dc_sink) {
423 DRM_ERROR("Unable to add a remote sink\n");
424 return 0;
425 }
426
427 drm_dbg_dp(connector->dev,
428 "DM_MST: add remote sink 0x%p, %d remaining\n",
429 dc_sink,
430 aconnector->dc_link->sink_count);
431
432 dc_sink->priv = aconnector;
433 aconnector->dc_sink = dc_sink;
434 }
435
436 return ret;
437 }
438
439 aconnector->drm_edid = drm_edid;
440 amdgpu_dm_set_mst_status(&aconnector->mst_status,
441 MST_REMOTE_EDID, true);
442 }
443
444 if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) {
445 dc_sink_release(aconnector->dc_sink);
446 aconnector->dc_sink = NULL;
447 }
448
449 if (!aconnector->dc_sink) {
450 struct dc_sink *dc_sink;
451 struct dc_sink_init_data init_params = {
452 .link = aconnector->dc_link,
453 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
454 const struct edid *edid;
455
456 edid = drm_edid_raw(aconnector->drm_edid); // FIXME: Get rid of drm_edid_raw()
457 dc_sink = dc_link_add_remote_sink(
458 aconnector->dc_link,
459 (uint8_t *)edid,
460 (edid->extensions + 1) * EDID_LENGTH,
461 &init_params);
462
463 if (!dc_sink) {
464 DRM_ERROR("Unable to add a remote sink\n");
465 return 0;
466 }
467
468 drm_dbg_dp(connector->dev,
469 "DM_MST: add remote sink 0x%p, %d remaining\n",
470 dc_sink, aconnector->dc_link->sink_count);
471
472 dc_sink->priv = aconnector;
473 /* dc_link_add_remote_sink returns a new reference */
474 aconnector->dc_sink = dc_sink;
475
476 /* when display is unplugged from mst hub, connctor will be
477 * destroyed within dm_dp_mst_connector_destroy. connector
478 * hdcp perperties, like type, undesired, desired, enabled,
479 * will be lost. So, save hdcp properties into hdcp_work within
480 * amdgpu_dm_atomic_commit_tail. if the same display is
481 * plugged back with same display index, its hdcp properties
482 * will be retrieved from hdcp_work within dm_dp_mst_get_modes
483 */
484 if (connector->state) {
485 struct drm_device *dev = connector->dev;
486 struct amdgpu_device *adev = drm_to_adev(dev);
487
488 if (adev->dm.hdcp_workqueue &&
489 connector->index < AMDGPU_DM_MAX_DISPLAY_COUNT) {
490 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
491 struct hdcp_workqueue *hdcp_w =
492 &hdcp_work[aconnector->dc_link->link_index];
493
494 connector->state->hdcp_content_type =
495 hdcp_w->hdcp_content_type[connector->index];
496 connector->state->content_protection =
497 hdcp_w->content_protection[connector->index];
498 }
499 }
500
501 amdgpu_dm_update_freesync_caps(
502 connector, aconnector->drm_edid, true);
503
504 #if defined(CONFIG_DRM_AMD_DC_FP)
505 if (!validate_dsc_caps_on_connector(aconnector))
506 memset(&aconnector->dc_sink->dsc_caps,
507 0, sizeof(aconnector->dc_sink->dsc_caps));
508 #endif
509
510 if (!retrieve_downstream_port_device(aconnector))
511 memset(&aconnector->mst_downstream_port_present,
512 0, sizeof(aconnector->mst_downstream_port_present));
513 }
514
515 drm_edid_connector_update(&aconnector->base, aconnector->drm_edid);
516
517 ret = drm_edid_connector_add_modes(connector);
518
519 return ret;
520 }
521
522 STATIC_IFN_KUNIT struct drm_encoder *
dm_mst_atomic_best_encoder(struct drm_connector * connector,struct drm_atomic_commit * state)523 dm_mst_atomic_best_encoder(struct drm_connector *connector,
524 struct drm_atomic_commit *state)
525 {
526 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,
527 connector);
528 struct amdgpu_device *adev = drm_to_adev(connector->dev);
529 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(connector_state->crtc);
530
531 return &adev->dm.mst_encoders[acrtc->crtc_id].base;
532 }
533 EXPORT_IF_KUNIT(dm_mst_atomic_best_encoder);
534
535 STATIC_IFN_KUNIT int
dm_dp_mst_detect(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx,bool force)536 dm_dp_mst_detect(struct drm_connector *connector,
537 struct drm_modeset_acquire_ctx *ctx, bool force)
538 {
539 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
540 struct amdgpu_dm_connector *master = aconnector->mst_root;
541 struct drm_dp_mst_port *port = aconnector->mst_output_port;
542 int connection_status;
543
544 if (drm_connector_is_unregistered(connector))
545 return connector_status_disconnected;
546
547 connection_status = drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
548 aconnector->mst_output_port);
549
550 if (port->pdt != DP_PEER_DEVICE_NONE && !port->dpcd_rev) {
551 uint8_t dpcd_rev;
552 int ret;
553
554 ret = drm_dp_dpcd_readb(&port->aux, DP_DP13_DPCD_REV, &dpcd_rev);
555
556 if (ret == 1) {
557 port->dpcd_rev = dpcd_rev;
558
559 /* Could be DP1.2 DP Rx case*/
560 if (!dpcd_rev) {
561 ret = drm_dp_dpcd_readb(&port->aux, DP_DPCD_REV, &dpcd_rev);
562
563 if (ret == 1)
564 port->dpcd_rev = dpcd_rev;
565 }
566
567 if (!dpcd_rev)
568 DRM_DEBUG_KMS("Can't decide DPCD revision number!");
569 }
570
571 /*
572 * Could be legacy sink, logical port etc on DP1.2.
573 * Will get Nack under these cases when issue remote
574 * DPCD read.
575 */
576 if (ret != 1)
577 DRM_DEBUG_KMS("Can't access DPCD");
578 } else if (port->pdt == DP_PEER_DEVICE_NONE) {
579 port->dpcd_rev = 0;
580 }
581
582 /*
583 * Release dc_sink for connector which unplug event is notified by CSN msg
584 */
585 if (connection_status == connector_status_disconnected && aconnector->dc_sink) {
586 if (aconnector->dc_link->sink_count)
587 dc_link_remove_remote_sink(aconnector->dc_link, aconnector->dc_sink);
588
589 drm_dbg_dp(connector->dev,
590 "DM_MST: remove remote sink 0x%p, %d remaining\n",
591 aconnector->dc_link,
592 aconnector->dc_link->sink_count);
593
594 dc_sink_release(aconnector->dc_sink);
595 aconnector->dc_sink = NULL;
596 amdgpu_dm_mst_reset_mst_connector_setting(aconnector);
597
598 amdgpu_dm_set_mst_status(&aconnector->mst_status,
599 MST_REMOTE_EDID | MST_ALLOCATE_NEW_PAYLOAD | MST_CLEAR_ALLOCATED_PAYLOAD,
600 false);
601 }
602
603 return connection_status;
604 }
605 EXPORT_IF_KUNIT(dm_dp_mst_detect);
606
dm_dp_mst_atomic_check(struct drm_connector * connector,struct drm_atomic_commit * state)607 STATIC_IFN_KUNIT int dm_dp_mst_atomic_check(struct drm_connector *connector,
608 struct drm_atomic_commit *state)
609 {
610 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
611 struct drm_dp_mst_topology_mgr *mst_mgr = &aconnector->mst_root->mst_mgr;
612 struct drm_dp_mst_port *mst_port = aconnector->mst_output_port;
613
614 return drm_dp_atomic_release_time_slots(state, mst_mgr, mst_port);
615 }
616 EXPORT_IF_KUNIT(dm_dp_mst_atomic_check);
617
618 static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = {
619 .get_modes = dm_dp_mst_get_modes,
620 .mode_valid = amdgpu_dm_connector_mode_valid,
621 .atomic_best_encoder = dm_mst_atomic_best_encoder,
622 .detect_ctx = dm_dp_mst_detect,
623 .atomic_check = dm_dp_mst_atomic_check,
624 };
625
amdgpu_dm_encoder_destroy(struct drm_encoder * encoder)626 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
627 {
628 drm_encoder_cleanup(encoder);
629 }
630
631 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
632 .destroy = amdgpu_dm_encoder_destroy,
633 };
634
635 void
dm_dp_create_fake_mst_encoders(struct amdgpu_device * adev)636 dm_dp_create_fake_mst_encoders(struct amdgpu_device *adev)
637 {
638 struct drm_device *dev = adev_to_drm(adev);
639 int i;
640
641 for (i = 0; i < adev->dm.display_indexes_num; i++) {
642 struct amdgpu_encoder *amdgpu_encoder = &adev->dm.mst_encoders[i];
643 struct drm_encoder *encoder = &amdgpu_encoder->base;
644
645 encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
646
647 drm_encoder_init(
648 dev,
649 &amdgpu_encoder->base,
650 &amdgpu_dm_encoder_funcs,
651 DRM_MODE_ENCODER_DPMST,
652 NULL);
653
654 drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs);
655 }
656 }
657 EXPORT_IF_KUNIT(dm_dp_create_fake_mst_encoders);
658
659 static struct drm_connector *
dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr * mgr,struct drm_dp_mst_port * port,const char * pathprop)660 dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
661 struct drm_dp_mst_port *port,
662 const char *pathprop)
663 {
664 struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
665 struct drm_device *dev = master->base.dev;
666 struct amdgpu_device *adev = drm_to_adev(dev);
667 struct amdgpu_dm_connector *aconnector;
668 struct drm_connector *connector;
669 int i;
670
671 aconnector = kzalloc_obj(*aconnector);
672 if (!aconnector)
673 return NULL;
674
675 DRM_DEBUG_DRIVER("%s: Create aconnector 0x%p for port 0x%p\n", __func__, aconnector, port);
676
677 connector = &aconnector->base;
678 aconnector->mst_output_port = port;
679 aconnector->mst_root = master;
680 amdgpu_dm_set_mst_status(&aconnector->mst_status,
681 MST_PROBE, true);
682
683 if (drm_connector_dynamic_init(
684 dev,
685 connector,
686 &dm_dp_mst_connector_funcs,
687 DRM_MODE_CONNECTOR_DisplayPort,
688 NULL)) {
689 kfree(aconnector);
690 return NULL;
691 }
692 drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs);
693
694 amdgpu_dm_connector_init_helper(
695 &adev->dm,
696 aconnector,
697 DRM_MODE_CONNECTOR_DisplayPort,
698 master->dc_link,
699 master->connector_id);
700
701 for (i = 0; i < adev->dm.display_indexes_num; i++) {
702 drm_connector_attach_encoder(&aconnector->base,
703 &adev->dm.mst_encoders[i].base);
704 }
705
706 connector->max_bpc_property = master->base.max_bpc_property;
707 if (connector->max_bpc_property)
708 drm_connector_attach_max_bpc_property(connector, 8, 16);
709
710 connector->vrr_capable_property = master->base.vrr_capable_property;
711 if (connector->vrr_capable_property)
712 drm_connector_attach_vrr_capable_property(connector);
713
714 drm_object_attach_property(
715 &connector->base,
716 dev->mode_config.path_property,
717 0);
718 drm_object_attach_property(
719 &connector->base,
720 dev->mode_config.tile_property,
721 0);
722 connector->colorspace_property = master->base.colorspace_property;
723 if (connector->colorspace_property)
724 drm_connector_attach_colorspace_property(connector);
725
726 drm_connector_set_path_property(connector, pathprop);
727
728 if (!retrieve_branch_specific_data(aconnector))
729 aconnector->branch_ieee_oui = 0;
730
731 /*
732 * Initialize connector state before adding the connectror to drm and
733 * framebuffer lists
734 */
735 amdgpu_dm_connector_funcs_reset(connector);
736
737 drm_dp_mst_get_port_malloc(port);
738
739 return connector;
740 }
741
742 /*
743 * Select the ESI[1] mask used to filter the MST sideband ready bits for a
744 * given message-ready event type.
745 */
dm_mst_msg_ready_mask(enum mst_msg_ready_type msg_rdy_type)746 STATIC_IFN_KUNIT u8 dm_mst_msg_ready_mask(enum mst_msg_ready_type msg_rdy_type)
747 {
748 switch (msg_rdy_type) {
749 case DOWN_REP_MSG_RDY_EVENT:
750 /* Only handle DOWN_REP_MSG_RDY case*/
751 return DP_DOWN_REP_MSG_RDY;
752 case UP_REQ_MSG_RDY_EVENT:
753 /* Only handle UP_REQ_MSG_RDY case*/
754 return DP_UP_REQ_MSG_RDY;
755 default:
756 /* Handle both cases*/
757 return DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY;
758 }
759 }
760 EXPORT_IF_KUNIT(dm_mst_msg_ready_mask);
761
762 /*
763 * Select the DPCD ESI address and read length based on the DPCD revision.
764 */
dm_mst_select_esi_dpcd(u8 dpcd_rev,int * dpcd_addr,u8 * dpcd_bytes_to_read)765 STATIC_IFN_KUNIT void dm_mst_select_esi_dpcd(u8 dpcd_rev, int *dpcd_addr,
766 u8 *dpcd_bytes_to_read)
767 {
768 if (dpcd_rev < 0x12) {
769 *dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
770 /* DPCD 0x200 - 0x201 for downstream IRQ */
771 *dpcd_addr = DP_SINK_COUNT;
772 } else {
773 *dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
774 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
775 *dpcd_addr = DP_SINK_COUNT_ESI;
776 }
777 }
778 EXPORT_IF_KUNIT(dm_mst_select_esi_dpcd);
779
dm_handle_mst_sideband_msg_ready_event(struct drm_dp_mst_topology_mgr * mgr,enum mst_msg_ready_type msg_rdy_type)780 void dm_handle_mst_sideband_msg_ready_event(
781 struct drm_dp_mst_topology_mgr *mgr,
782 enum mst_msg_ready_type msg_rdy_type)
783 {
784 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
785 uint8_t dret;
786 bool new_irq_handled = false;
787 int dpcd_addr;
788 uint8_t dpcd_bytes_to_read;
789 const uint8_t max_process_count = 30;
790 uint8_t process_count = 0;
791 u8 retry;
792 struct amdgpu_dm_connector *aconnector =
793 container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
794
795
796 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
797
798 dm_mst_select_esi_dpcd(link_status->dpcd_caps->dpcd_rev.raw, &dpcd_addr,
799 &dpcd_bytes_to_read);
800
801 mutex_lock(&aconnector->handle_mst_msg_ready);
802
803 while (process_count < max_process_count) {
804 u8 ack[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = {};
805
806 process_count++;
807
808 dret = drm_dp_dpcd_read(
809 &aconnector->dm_dp_aux.aux,
810 dpcd_addr,
811 esi,
812 dpcd_bytes_to_read);
813
814 if (dret != dpcd_bytes_to_read) {
815 DRM_DEBUG_KMS("DPCD read and acked number is not as expected!");
816 break;
817 }
818
819 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
820
821 esi[1] &= dm_mst_msg_ready_mask(msg_rdy_type);
822
823 if (!esi[1])
824 break;
825
826 /* handle MST irq */
827 if (aconnector->mst_mgr.mst_state)
828 drm_dp_mst_hpd_irq_handle_event(&aconnector->mst_mgr,
829 esi,
830 ack,
831 &new_irq_handled);
832
833 if (new_irq_handled) {
834 /* ACK at DPCD to notify down stream */
835 for (retry = 0; retry < 3; retry++) {
836 ssize_t wret;
837
838 wret = drm_dp_dpcd_writeb(&aconnector->dm_dp_aux.aux,
839 dpcd_addr + 1,
840 ack[1]);
841 if (wret == 1)
842 break;
843 }
844
845 if (retry == 3) {
846 DRM_ERROR("Failed to ack MST event.\n");
847 break;
848 }
849
850 drm_dp_mst_hpd_irq_send_new_request(&aconnector->mst_mgr);
851
852 new_irq_handled = false;
853 } else {
854 break;
855 }
856 }
857
858 mutex_unlock(&aconnector->handle_mst_msg_ready);
859
860 if (process_count == max_process_count)
861 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
862 }
863 EXPORT_IF_KUNIT(dm_handle_mst_sideband_msg_ready_event);
864
dm_handle_mst_down_rep_msg_ready(struct drm_dp_mst_topology_mgr * mgr)865 STATIC_IFN_KUNIT void dm_handle_mst_down_rep_msg_ready(struct drm_dp_mst_topology_mgr *mgr)
866 {
867 dm_handle_mst_sideband_msg_ready_event(mgr, DOWN_REP_MSG_RDY_EVENT);
868 }
869 EXPORT_IF_KUNIT(dm_handle_mst_down_rep_msg_ready);
870
871 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
872 .add_connector = dm_dp_add_mst_connector,
873 .poll_hpd_irq = dm_handle_mst_down_rep_msg_ready,
874 };
875
amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager * dm,struct amdgpu_dm_connector * aconnector,int link_index)876 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
877 struct amdgpu_dm_connector *aconnector,
878 int link_index)
879 {
880 struct dc_link_settings max_link_enc_cap = {0};
881
882 aconnector->dm_dp_aux.aux.name =
883 kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d",
884 link_index);
885 aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
886 aconnector->dm_dp_aux.aux.drm_dev = dm->ddev;
887 aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
888
889 drm_dp_aux_init(&aconnector->dm_dp_aux.aux);
890 drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux,
891 &aconnector->base);
892 drm_dp_dpcd_set_probe(&aconnector->dm_dp_aux.aux, false);
893
894 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
895 return;
896
897 dc_link_dp_get_max_link_enc_cap(aconnector->dc_link, &max_link_enc_cap);
898 aconnector->mst_mgr.cbs = &dm_mst_cbs;
899 drm_dp_mst_topology_mgr_init(&aconnector->mst_mgr, adev_to_drm(dm->adev),
900 &aconnector->dm_dp_aux.aux, 16, 4, aconnector->connector_id);
901
902 drm_connector_attach_dp_subconnector_property(&aconnector->base);
903 }
904 EXPORT_IF_KUNIT(amdgpu_dm_initialize_dp_connector);
905
dm_mst_get_pbn_divider(struct dc_link * link)906 uint32_t dm_mst_get_pbn_divider(struct dc_link *link)
907 {
908 uint32_t pbn_div_x100;
909 uint64_t dividend, divisor;
910
911 if (!link)
912 return 0;
913
914 dividend = (uint64_t)dc_link_bandwidth_kbps(link, dc_link_get_link_cap(link)) * 100;
915 divisor = 8 * 1000 * 54;
916
917 pbn_div_x100 = div64_u64(dividend, divisor);
918
919 return dfixed_const(pbn_div_x100) / 100;
920 }
921 EXPORT_IF_KUNIT(dm_mst_get_pbn_divider);
922
923 struct dsc_mst_fairness_params {
924 struct dc_crtc_timing *timing;
925 struct dc_sink *sink;
926 struct dc_dsc_bw_range bw_range;
927 bool compression_possible;
928 struct drm_dp_mst_port *port;
929 enum dsc_clock_force_state clock_force_enable;
930 uint32_t num_slices_h;
931 uint32_t num_slices_v;
932 uint32_t bpp_overwrite;
933 struct amdgpu_dm_connector *aconnector;
934 };
935
936 #if defined(CONFIG_DRM_AMD_DC_FP)
get_fec_overhead_multiplier(struct dc_link * dc_link)937 static uint16_t get_fec_overhead_multiplier(struct dc_link *dc_link)
938 {
939 u8 link_coding_cap;
940 uint16_t fec_overhead_multiplier_x1000 = PBN_FEC_OVERHEAD_MULTIPLIER_8B_10B;
941
942 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(dc_link);
943 if (link_coding_cap == DP_128b_132b_ENCODING)
944 fec_overhead_multiplier_x1000 = PBN_FEC_OVERHEAD_MULTIPLIER_128B_132B;
945
946 return fec_overhead_multiplier_x1000;
947 }
948
kbps_to_peak_pbn(int kbps,uint16_t fec_overhead_multiplier_x1000)949 static int kbps_to_peak_pbn(int kbps, uint16_t fec_overhead_multiplier_x1000)
950 {
951 u64 peak_kbps = kbps;
952
953 peak_kbps *= 1006;
954 peak_kbps *= fec_overhead_multiplier_x1000;
955 peak_kbps = div_u64(peak_kbps, 1000 * 1000);
956 return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000));
957 }
958
set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params * params,struct dsc_mst_fairness_vars * vars,int count,int k)959 static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params,
960 struct dsc_mst_fairness_vars *vars,
961 int count,
962 int k)
963 {
964 struct drm_connector *drm_connector;
965 int i;
966 struct dc_dsc_config_options dsc_options = {0};
967
968 for (i = 0; i < count; i++) {
969 drm_connector = ¶ms[i].aconnector->base;
970
971 dc_dsc_get_default_config_option(params[i].sink->ctx->dc, &dsc_options);
972 dsc_options.max_target_bpp_limit_override_x16 = drm_connector->display_info.max_dsc_bpp * 16;
973
974 memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
975 if (vars[i + k].dsc_enabled && dc_dsc_compute_config(
976 params[i].sink->ctx->dc->res_pool->dscs[0],
977 ¶ms[i].sink->dsc_caps.dsc_dec_caps,
978 &dsc_options,
979 0,
980 params[i].timing,
981 dc_link_get_highest_encoding_format(params[i].aconnector->dc_link),
982 ¶ms[i].timing->dsc_cfg)) {
983 params[i].timing->flags.DSC = 1;
984
985 if (params[i].bpp_overwrite)
986 params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite;
987 else
988 params[i].timing->dsc_cfg.bits_per_pixel = vars[i + k].bpp_x16;
989
990 if (params[i].num_slices_h)
991 params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h;
992
993 if (params[i].num_slices_v)
994 params[i].timing->dsc_cfg.num_slices_v = params[i].num_slices_v;
995 } else {
996 params[i].timing->flags.DSC = 0;
997 }
998 params[i].timing->dsc_cfg.mst_pbn = vars[i + k].pbn;
999 }
1000
1001 for (i = 0; i < count; i++) {
1002 if (params[i].sink) {
1003 if (params[i].sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
1004 params[i].sink->sink_signal != SIGNAL_TYPE_NONE)
1005 DRM_DEBUG_DRIVER("MST_DSC %s i=%d dispname=%s\n", __func__, i,
1006 params[i].sink->edid_caps.display_name);
1007 }
1008
1009 DRM_DEBUG_DRIVER("MST_DSC dsc=%d bits_per_pixel=%d pbn=%d\n",
1010 params[i].timing->flags.DSC,
1011 params[i].timing->dsc_cfg.bits_per_pixel,
1012 vars[i + k].pbn);
1013 }
1014 }
1015
bpp_x16_from_pbn(struct dsc_mst_fairness_params param,int pbn)1016 static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
1017 {
1018 struct dc_dsc_config dsc_config;
1019 u64 kbps;
1020
1021 struct drm_connector *drm_connector = ¶m.aconnector->base;
1022 struct dc_dsc_config_options dsc_options = {0};
1023
1024 dc_dsc_get_default_config_option(param.sink->ctx->dc, &dsc_options);
1025 dsc_options.max_target_bpp_limit_override_x16 = drm_connector->display_info.max_dsc_bpp * 16;
1026
1027 kbps = div_u64((u64)pbn * 994 * 8 * 54, 64);
1028 dc_dsc_compute_config(
1029 param.sink->ctx->dc->res_pool->dscs[0],
1030 ¶m.sink->dsc_caps.dsc_dec_caps,
1031 &dsc_options,
1032 (int) kbps, param.timing,
1033 dc_link_get_highest_encoding_format(param.aconnector->dc_link),
1034 &dsc_config);
1035
1036 return dsc_config.bits_per_pixel;
1037 }
1038
increase_dsc_bpp(struct drm_atomic_commit * state,struct drm_dp_mst_topology_state * mst_state,struct dc_link * dc_link,struct dsc_mst_fairness_params * params,struct dsc_mst_fairness_vars * vars,int count,int k)1039 static int increase_dsc_bpp(struct drm_atomic_commit *state,
1040 struct drm_dp_mst_topology_state *mst_state,
1041 struct dc_link *dc_link,
1042 struct dsc_mst_fairness_params *params,
1043 struct dsc_mst_fairness_vars *vars,
1044 int count,
1045 int k)
1046 {
1047 int i;
1048 bool bpp_increased[MAX_PIPES];
1049 int initial_slack[MAX_PIPES];
1050 int min_initial_slack;
1051 int next_index;
1052 int remaining_to_increase = 0;
1053 int link_timeslots_used;
1054 int fair_pbn_alloc;
1055 int ret = 0;
1056 uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link);
1057
1058 for (i = 0; i < count; i++) {
1059 if (vars[i + k].dsc_enabled) {
1060 initial_slack[i] =
1061 kbps_to_peak_pbn(params[i].bw_range.max_kbps, fec_overhead_multiplier_x1000) - vars[i + k].pbn;
1062 bpp_increased[i] = false;
1063 remaining_to_increase += 1;
1064 } else {
1065 initial_slack[i] = 0;
1066 bpp_increased[i] = true;
1067 }
1068 }
1069
1070 while (remaining_to_increase) {
1071 next_index = -1;
1072 min_initial_slack = -1;
1073 for (i = 0; i < count; i++) {
1074 if (!bpp_increased[i]) {
1075 if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) {
1076 min_initial_slack = initial_slack[i];
1077 next_index = i;
1078 }
1079 }
1080 }
1081
1082 if (next_index == -1)
1083 break;
1084
1085 link_timeslots_used = 0;
1086
1087 for (i = 0; i < count; i++)
1088 link_timeslots_used += DIV_ROUND_UP(vars[i + k].pbn, dfixed_trunc(mst_state->pbn_div));
1089
1090 fair_pbn_alloc =
1091 (63 - link_timeslots_used) / remaining_to_increase * dfixed_trunc(mst_state->pbn_div);
1092
1093 if (initial_slack[next_index] > fair_pbn_alloc) {
1094 vars[next_index].pbn += fair_pbn_alloc;
1095 ret = drm_dp_atomic_find_time_slots(state,
1096 params[next_index].port->mgr,
1097 params[next_index].port,
1098 vars[next_index].pbn);
1099 if (ret < 0)
1100 return ret;
1101
1102 ret = drm_dp_mst_atomic_check(state);
1103 if (ret == 0) {
1104 vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn);
1105 } else {
1106 vars[next_index].pbn -= fair_pbn_alloc;
1107 ret = drm_dp_atomic_find_time_slots(state,
1108 params[next_index].port->mgr,
1109 params[next_index].port,
1110 vars[next_index].pbn);
1111 if (ret < 0)
1112 return ret;
1113 }
1114 } else {
1115 vars[next_index].pbn += initial_slack[next_index];
1116 ret = drm_dp_atomic_find_time_slots(state,
1117 params[next_index].port->mgr,
1118 params[next_index].port,
1119 vars[next_index].pbn);
1120 if (ret < 0)
1121 return ret;
1122
1123 ret = drm_dp_mst_atomic_check(state);
1124 if (ret == 0) {
1125 vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16;
1126 } else {
1127 vars[next_index].pbn -= initial_slack[next_index];
1128 ret = drm_dp_atomic_find_time_slots(state,
1129 params[next_index].port->mgr,
1130 params[next_index].port,
1131 vars[next_index].pbn);
1132 if (ret < 0)
1133 return ret;
1134 }
1135 }
1136
1137 bpp_increased[next_index] = true;
1138 remaining_to_increase--;
1139 }
1140 return 0;
1141 }
1142
try_disable_dsc(struct drm_atomic_commit * state,struct dc_link * dc_link,struct dsc_mst_fairness_params * params,struct dsc_mst_fairness_vars * vars,int count,int k)1143 static int try_disable_dsc(struct drm_atomic_commit *state,
1144 struct dc_link *dc_link,
1145 struct dsc_mst_fairness_params *params,
1146 struct dsc_mst_fairness_vars *vars,
1147 int count,
1148 int k)
1149 {
1150 int i;
1151 bool tried[MAX_PIPES];
1152 int kbps_increase[MAX_PIPES];
1153 int max_kbps_increase;
1154 int next_index;
1155 int remaining_to_try = 0;
1156 int ret;
1157 uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link);
1158 int var_pbn;
1159
1160 for (i = 0; i < count; i++) {
1161 if (vars[i + k].dsc_enabled
1162 && vars[i + k].bpp_x16 == params[i].bw_range.max_target_bpp_x16
1163 && params[i].clock_force_enable == DSC_CLK_FORCE_DEFAULT) {
1164 kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps;
1165 tried[i] = false;
1166 remaining_to_try += 1;
1167 } else {
1168 kbps_increase[i] = 0;
1169 tried[i] = true;
1170 }
1171 }
1172
1173 while (remaining_to_try) {
1174 next_index = -1;
1175 max_kbps_increase = -1;
1176 for (i = 0; i < count; i++) {
1177 if (!tried[i]) {
1178 if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) {
1179 max_kbps_increase = kbps_increase[i];
1180 next_index = i;
1181 }
1182 }
1183 }
1184
1185 if (next_index == -1)
1186 break;
1187
1188 DRM_DEBUG_DRIVER("MST_DSC index #%d, try no compression\n", next_index);
1189 var_pbn = vars[next_index].pbn;
1190 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps, fec_overhead_multiplier_x1000);
1191 ret = drm_dp_atomic_find_time_slots(state,
1192 params[next_index].port->mgr,
1193 params[next_index].port,
1194 vars[next_index].pbn);
1195 if (ret < 0) {
1196 DRM_DEBUG_DRIVER("%s:%d MST_DSC index #%d, failed to set pbn to the state, %d\n",
1197 __func__, __LINE__, next_index, ret);
1198 vars[next_index].pbn = var_pbn;
1199 return ret;
1200 }
1201
1202 ret = drm_dp_mst_atomic_check(state);
1203 if (ret == 0) {
1204 DRM_DEBUG_DRIVER("MST_DSC index #%d, greedily disable dsc\n", next_index);
1205 vars[next_index].dsc_enabled = false;
1206 vars[next_index].bpp_x16 = 0;
1207 } else {
1208 DRM_DEBUG_DRIVER("MST_DSC index #%d, restore optimized pbn value\n", next_index);
1209 vars[next_index].pbn = var_pbn;
1210 ret = drm_dp_atomic_find_time_slots(state,
1211 params[next_index].port->mgr,
1212 params[next_index].port,
1213 vars[next_index].pbn);
1214 if (ret < 0) {
1215 DRM_DEBUG_DRIVER("%s:%d MST_DSC index #%d, failed to set pbn to the state, %d\n",
1216 __func__, __LINE__, next_index, ret);
1217 return ret;
1218 }
1219 }
1220
1221 tried[next_index] = true;
1222 remaining_to_try--;
1223 }
1224 return 0;
1225 }
1226
get_conv_frl_bw(struct amdgpu_dm_connector * aconnector,uint32_t * bw_in_kbps,uint32_t * dsc_bw_in_kbps)1227 static bool get_conv_frl_bw(struct amdgpu_dm_connector *aconnector,
1228 uint32_t *bw_in_kbps, uint32_t *dsc_bw_in_kbps)
1229 {
1230 unsigned int max_conv_bw_in_kbps = 0;
1231 unsigned int max_sink_bw_in_kbps = 0;
1232 unsigned int dsc_max_sink_bw_in_kbps = 0;
1233
1234 if (aconnector->dc_sink &&
1235 aconnector->dc_link->dc->caps.dp_hdmi21_pcon_support &&
1236 aconnector->mst_downstream_port_caps.bytes.byte0.bits.DWN_STRM_PORTX_TYPE == DOWN_STREAM_DETAILED_HDMI) {
1237 max_conv_bw_in_kbps = dc_link_bw_kbps_from_raw_frl_link_rate_data(
1238 aconnector->dc_link->dc,
1239 aconnector->mst_downstream_port_caps.bytes.byte2.bits.MAX_ENCODED_LINK_BW_SUPPORT);
1240 if (aconnector->dc_sink->edid_caps.max_frl_rate && max_conv_bw_in_kbps) {
1241 max_sink_bw_in_kbps = dc_link_bw_kbps_from_raw_frl_link_rate_data(
1242 aconnector->dc_link->dc,
1243 aconnector->dc_sink->edid_caps.max_frl_rate);
1244 dsc_max_sink_bw_in_kbps = dc_link_bw_kbps_from_raw_frl_link_rate_data(
1245 aconnector->dc_link->dc,
1246 aconnector->dc_sink->edid_caps.frl_dsc_max_frl_rate);
1247
1248 *bw_in_kbps = min(max_conv_bw_in_kbps, max_sink_bw_in_kbps);
1249 *dsc_bw_in_kbps = min(*bw_in_kbps, dsc_max_sink_bw_in_kbps);
1250 }
1251 }
1252
1253 return *bw_in_kbps > 0; // Frl endpoint is detected
1254 }
1255
build_frl_mst_dsc_params(struct amdgpu_dm_connector * aconnector,struct dc_stream_state * stream,struct dc_dsc_policy * dsc_policy,struct dsc_mst_fairness_params * params,uint32_t frl_conv_dsc_bw_in_kbps)1256 static void build_frl_mst_dsc_params(struct amdgpu_dm_connector *aconnector,
1257 struct dc_stream_state *stream,
1258 struct dc_dsc_policy *dsc_policy,
1259 struct dsc_mst_fairness_params *params,
1260 uint32_t frl_conv_dsc_bw_in_kbps)
1261 {
1262 uint32_t min_bpp_x16, max_bpp_x16;
1263 struct dc_dsc_config_options dsc_options = {0};
1264
1265 min_bpp_x16 = dsc_policy->min_target_bpp * 16;
1266 max_bpp_x16 = dsc_policy->max_target_bpp * 16;
1267
1268 dc_dsc_get_default_config_option(stream->sink->ctx->dc, &dsc_options);
1269 dsc_options.max_target_bpp_limit_override_x16 =
1270 stream->sink->edid_caps.panel_patch.max_dsc_target_bpp_limit * 16;
1271
1272 if (dc_dsc_compute_config(
1273 stream->sink->ctx->dc->res_pool->dscs[0],
1274 &stream->sink->dsc_caps.dsc_dec_caps,
1275 &dsc_options,
1276 frl_conv_dsc_bw_in_kbps,
1277 &stream->timing,
1278 dc_link_get_highest_encoding_format(aconnector->dc_link),
1279 &stream->timing.dsc_cfg)) {
1280 // The timing can enable dsc
1281 if (stream->sink->dsc_caps.dsc_dec_caps.is_vic_all_bpp && min_bpp_x16 <= stream->timing.dsc_cfg.bits_per_pixel) {
1282 // with all supported bpp within the range limit
1283 params->bw_range.max_target_bpp_x16 = min(stream->timing.dsc_cfg.bits_per_pixel, dsc_policy->max_target_bpp * 16);
1284 params->bw_range.min_target_bpp_x16 = min_bpp_x16;
1285 params->bw_range.max_kbps = (params->bw_range.max_target_bpp_x16 * stream->timing.pix_clk_100hz + 159) / 160;
1286 params->bw_range.min_kbps = (params->bw_range.min_target_bpp_x16 * stream->timing.pix_clk_100hz + 159) / 160;
1287 } else if (!stream->sink->dsc_caps.dsc_dec_caps.is_vic_all_bpp &&
1288 min_bpp_x16 <= stream->timing.dsc_cfg.bits_per_pixel &&
1289 max_bpp_x16 >= stream->timing.dsc_cfg.bits_per_pixel) {
1290 // with selected bpp only within the range limit
1291 params->bw_range.max_target_bpp_x16 = stream->timing.dsc_cfg.bits_per_pixel;
1292 params->bw_range.max_kbps = (params->bw_range.max_target_bpp_x16 * stream->timing.pix_clk_100hz + 159) / 160;
1293 params->bw_range.min_target_bpp_x16 = params->bw_range.max_target_bpp_x16;
1294 params->bw_range.min_kbps = params->bw_range.max_kbps;
1295 }
1296 }
1297 }
1298
log_dsc_params(int count,struct dsc_mst_fairness_vars * vars,int k)1299 static void log_dsc_params(int count, struct dsc_mst_fairness_vars *vars, int k)
1300 {
1301 int i;
1302
1303 for (i = 0; i < count; i++)
1304 DRM_DEBUG_DRIVER("MST_DSC DSC params: stream #%d --- dsc_enabled = %d, bpp_x16 = %d, pbn = %d\n",
1305 i, vars[i + k].dsc_enabled, vars[i + k].bpp_x16, vars[i + k].pbn);
1306 }
1307
compute_mst_dsc_configs_for_link(struct drm_atomic_commit * state,struct dc_state * dc_state,struct dc_link * dc_link,struct dsc_mst_fairness_vars * vars,struct drm_dp_mst_topology_mgr * mgr,int * link_vars_start_index)1308 static int compute_mst_dsc_configs_for_link(struct drm_atomic_commit *state,
1309 struct dc_state *dc_state,
1310 struct dc_link *dc_link,
1311 struct dsc_mst_fairness_vars *vars,
1312 struct drm_dp_mst_topology_mgr *mgr,
1313 int *link_vars_start_index)
1314 {
1315 struct dc_stream_state *stream;
1316 struct dsc_mst_fairness_params params[MAX_PIPES];
1317 struct amdgpu_dm_connector *aconnector;
1318 struct drm_dp_mst_topology_state *mst_state = drm_atomic_get_mst_topology_state(state, mgr);
1319 int count = 0;
1320 int i, k, ret;
1321 bool debugfs_overwrite = false;
1322 uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link);
1323 struct drm_connector_state *new_conn_state;
1324 bool is_frl_endpoint_present;
1325 uint32_t frl_conv_bw_in_kbps, frl_conv_dsc_bw_in_kbps;
1326
1327 memset(params, 0, sizeof(params));
1328
1329 if (IS_ERR(mst_state))
1330 return PTR_ERR(mst_state);
1331
1332 /* Set up params */
1333 DRM_DEBUG_DRIVER("%s: MST_DSC Try to set up params from %d streams\n", __func__, dc_state->stream_count);
1334 for (i = 0; i < dc_state->stream_count; i++) {
1335 struct dc_dsc_policy dsc_policy = {0};
1336
1337 stream = dc_state->streams[i];
1338
1339 if (stream->link != dc_link)
1340 continue;
1341
1342 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1343 if (!aconnector)
1344 continue;
1345
1346 if (!aconnector->mst_output_port)
1347 continue;
1348
1349 new_conn_state = drm_atomic_get_new_connector_state(state, &aconnector->base);
1350
1351 if (!new_conn_state) {
1352 DRM_DEBUG_DRIVER("%s:%d MST_DSC Skip the stream 0x%p with invalid new_conn_state\n",
1353 __func__, __LINE__, stream);
1354 continue;
1355 }
1356
1357 stream->timing.flags.DSC = 0;
1358
1359 params[count].timing = &stream->timing;
1360 params[count].sink = stream->sink;
1361 params[count].aconnector = aconnector;
1362 params[count].port = aconnector->mst_output_port;
1363 params[count].clock_force_enable = aconnector->dsc_settings.dsc_force_enable;
1364 if (params[count].clock_force_enable == DSC_CLK_FORCE_ENABLE)
1365 debugfs_overwrite = true;
1366 params[count].num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
1367 params[count].num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
1368 params[count].bpp_overwrite = aconnector->dsc_settings.dsc_bits_per_pixel;
1369 params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported;
1370 dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy, dc_link_get_highest_encoding_format(stream->link));
1371 is_frl_endpoint_present = get_conv_frl_bw(aconnector, &frl_conv_bw_in_kbps, &frl_conv_dsc_bw_in_kbps);
1372 if (stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported &&
1373 is_frl_endpoint_present &&
1374 frl_conv_dsc_bw_in_kbps &&
1375 stream->sink->dsc_caps.dsc_dec_caps.is_frl)
1376 build_frl_mst_dsc_params(aconnector, stream, &dsc_policy, ¶ms[count], frl_conv_dsc_bw_in_kbps);
1377 if (!dc_dsc_compute_bandwidth_range(
1378 stream->sink->ctx->dc->res_pool->dscs[0],
1379 stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
1380 dsc_policy.min_target_bpp * 16,
1381 dsc_policy.max_target_bpp * 16,
1382 &stream->sink->dsc_caps.dsc_dec_caps,
1383 &stream->timing,
1384 dc_link_get_highest_encoding_format(dc_link),
1385 ¶ms[count].bw_range))
1386 params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing,
1387 dc_link_get_highest_encoding_format(dc_link));
1388
1389 DRM_DEBUG_DRIVER("MST_DSC #%d stream 0x%p - max_kbps = %u, min_kbps = %u, uncompressed_kbps = %u\n",
1390 count, stream, params[count].bw_range.max_kbps, params[count].bw_range.min_kbps,
1391 params[count].bw_range.stream_kbps);
1392 count++;
1393 }
1394
1395 DRM_DEBUG_DRIVER("%s: MST_DSC Params set up for %d streams\n", __func__, count);
1396
1397 if (count == 0) {
1398 ASSERT(0);
1399 return 0;
1400 }
1401
1402 /* k is start index of vars for current phy link used by mst hub */
1403 k = *link_vars_start_index;
1404 /* set vars start index for next mst hub phy link */
1405 *link_vars_start_index += count;
1406
1407 /* Try no compression */
1408 DRM_DEBUG_DRIVER("MST_DSC Try no compression\n");
1409 for (i = 0; i < count; i++) {
1410 vars[i + k].aconnector = params[i].aconnector;
1411 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps, fec_overhead_multiplier_x1000);
1412 vars[i + k].dsc_enabled = false;
1413 vars[i + k].bpp_x16 = 0;
1414 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, params[i].port,
1415 vars[i + k].pbn);
1416 if (ret < 0)
1417 return ret;
1418 }
1419 ret = drm_dp_mst_atomic_check(state);
1420 if (ret == 0 && !debugfs_overwrite) {
1421 set_dsc_configs_from_fairness_vars(params, vars, count, k);
1422 return 0;
1423 } else if (ret != -ENOSPC) {
1424 return ret;
1425 }
1426
1427 log_dsc_params(count, vars, k);
1428
1429 /* Try max compression */
1430 DRM_DEBUG_DRIVER("MST_DSC Try max compression\n");
1431 for (i = 0; i < count; i++) {
1432 if (params[i].compression_possible && params[i].clock_force_enable != DSC_CLK_FORCE_DISABLE) {
1433 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps, fec_overhead_multiplier_x1000);
1434 vars[i + k].dsc_enabled = true;
1435 vars[i + k].bpp_x16 = params[i].bw_range.min_target_bpp_x16;
1436 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr,
1437 params[i].port, vars[i + k].pbn);
1438 if (ret < 0)
1439 return ret;
1440 } else {
1441 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps, fec_overhead_multiplier_x1000);
1442 vars[i + k].dsc_enabled = false;
1443 vars[i + k].bpp_x16 = 0;
1444 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr,
1445 params[i].port, vars[i + k].pbn);
1446 if (ret < 0)
1447 return ret;
1448 }
1449 }
1450 ret = drm_dp_mst_atomic_check(state);
1451 if (ret != 0)
1452 return ret;
1453
1454 log_dsc_params(count, vars, k);
1455
1456 /* Optimize degree of compression */
1457 DRM_DEBUG_DRIVER("MST_DSC Try optimize compression\n");
1458 ret = increase_dsc_bpp(state, mst_state, dc_link, params, vars, count, k);
1459 if (ret < 0) {
1460 DRM_DEBUG_DRIVER("MST_DSC Failed to optimize compression\n");
1461 return ret;
1462 }
1463
1464 log_dsc_params(count, vars, k);
1465
1466 DRM_DEBUG_DRIVER("MST_DSC Try disable compression\n");
1467 ret = try_disable_dsc(state, dc_link, params, vars, count, k);
1468 if (ret < 0) {
1469 DRM_DEBUG_DRIVER("MST_DSC Failed to disable compression\n");
1470 return ret;
1471 }
1472
1473 log_dsc_params(count, vars, k);
1474
1475 set_dsc_configs_from_fairness_vars(params, vars, count, k);
1476
1477 return 0;
1478 }
1479
is_dsc_need_re_compute(struct drm_atomic_commit * state,struct dc_state * dc_state,struct dc_link * dc_link)1480 static bool is_dsc_need_re_compute(
1481 struct drm_atomic_commit *state,
1482 struct dc_state *dc_state,
1483 struct dc_link *dc_link)
1484 {
1485 int i, j;
1486 bool is_dsc_need_re_compute = false;
1487 struct amdgpu_dm_connector *stream_on_link[MAX_PIPES];
1488 int new_stream_on_link_num = 0;
1489 struct amdgpu_dm_connector *aconnector;
1490 struct dc_stream_state *stream;
1491 const struct dc *dc = dc_link->dc;
1492
1493 /* only check phy used by dsc mst branch */
1494 if (dc_link->type != dc_connection_mst_branch)
1495 goto out;
1496
1497 /* add a check for older MST DSC with no virtual DPCDs */
1498 if (needs_dsc_aux_workaround(dc_link) &&
1499 (!(dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT ||
1500 dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT)))
1501 goto out;
1502
1503 for (i = 0; i < MAX_PIPES; i++)
1504 stream_on_link[i] = NULL;
1505
1506 DRM_DEBUG_DRIVER("%s: MST_DSC check on %d streams in new dc_state\n", __func__, dc_state->stream_count);
1507
1508 /* check if there is mode change in new request */
1509 for (i = 0; i < dc_state->stream_count; i++) {
1510 struct drm_crtc_state *new_crtc_state;
1511 struct drm_connector_state *new_conn_state;
1512
1513 stream = dc_state->streams[i];
1514 if (!stream)
1515 continue;
1516
1517 DRM_DEBUG_DRIVER("%s:%d MST_DSC checking #%d stream 0x%p\n", __func__, __LINE__, i, stream);
1518
1519 /* check if stream using the same link for mst */
1520 if (stream->link != dc_link)
1521 continue;
1522
1523 aconnector = (struct amdgpu_dm_connector *) stream->dm_stream_context;
1524 if (!aconnector)
1525 continue;
1526
1527 stream_on_link[new_stream_on_link_num] = aconnector;
1528 new_stream_on_link_num++;
1529
1530 new_conn_state = drm_atomic_get_new_connector_state(state, &aconnector->base);
1531 if (!new_conn_state) {
1532 DRM_DEBUG_DRIVER("%s:%d MST_DSC no new_conn_state for stream 0x%p, aconnector 0x%p\n",
1533 __func__, __LINE__, stream, aconnector);
1534 continue;
1535 }
1536
1537 if (IS_ERR(new_conn_state))
1538 continue;
1539
1540 if (!new_conn_state->crtc)
1541 continue;
1542
1543 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
1544 if (!new_crtc_state) {
1545 DRM_DEBUG_DRIVER("%s:%d MST_DSC no new_crtc_state for crtc of stream 0x%p, aconnector 0x%p\n",
1546 __func__, __LINE__, stream, aconnector);
1547 continue;
1548 }
1549
1550 if (IS_ERR(new_crtc_state))
1551 continue;
1552
1553 if (new_crtc_state->enable && new_crtc_state->active) {
1554 if (new_crtc_state->mode_changed || new_crtc_state->active_changed ||
1555 new_crtc_state->connectors_changed) {
1556 DRM_DEBUG_DRIVER("%s:%d MST_DSC dsc recompute required."
1557 "stream 0x%p in new dc_state\n",
1558 __func__, __LINE__, stream);
1559 is_dsc_need_re_compute = true;
1560 goto out;
1561 }
1562 }
1563 }
1564
1565 if (new_stream_on_link_num == 0) {
1566 DRM_DEBUG_DRIVER("%s:%d MST_DSC no mode change request for streams in new dc_state\n",
1567 __func__, __LINE__);
1568 is_dsc_need_re_compute = false;
1569 goto out;
1570 }
1571
1572 DRM_DEBUG_DRIVER("%s: MST_DSC check on %d streams in current dc_state\n",
1573 __func__, dc->current_state->stream_count);
1574
1575 /* check current_state if there stream on link but it is not in
1576 * new request state
1577 */
1578 for (i = 0; i < dc->current_state->stream_count; i++) {
1579 stream = dc->current_state->streams[i];
1580 /* only check stream on the mst hub */
1581 if (stream->link != dc_link)
1582 continue;
1583
1584 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1585 if (!aconnector)
1586 continue;
1587
1588 for (j = 0; j < new_stream_on_link_num; j++) {
1589 if (stream_on_link[j]) {
1590 if (aconnector == stream_on_link[j])
1591 break;
1592 }
1593 }
1594
1595 if (j == new_stream_on_link_num) {
1596 /* not in new state */
1597 DRM_DEBUG_DRIVER("%s:%d MST_DSC dsc recompute required."
1598 "stream 0x%p in current dc_state but not in new dc_state\n",
1599 __func__, __LINE__, stream);
1600 is_dsc_need_re_compute = true;
1601 break;
1602 }
1603 }
1604
1605 out:
1606 DRM_DEBUG_DRIVER("%s: MST_DSC dsc recompute %s\n",
1607 __func__, is_dsc_need_re_compute ? "required" : "not required");
1608
1609 return is_dsc_need_re_compute;
1610 }
1611
compute_mst_dsc_configs_for_state(struct drm_atomic_commit * state,struct dc_state * dc_state,struct dsc_mst_fairness_vars * vars)1612 int compute_mst_dsc_configs_for_state(struct drm_atomic_commit *state,
1613 struct dc_state *dc_state,
1614 struct dsc_mst_fairness_vars *vars)
1615 {
1616 int i, j;
1617 struct dc_stream_state *stream;
1618 bool computed_streams[MAX_PIPES];
1619 struct amdgpu_dm_connector *aconnector;
1620 struct drm_dp_mst_topology_mgr *mst_mgr;
1621 struct resource_pool *res_pool;
1622 int link_vars_start_index = 0;
1623 int ret = 0;
1624
1625 for (i = 0; i < dc_state->stream_count; i++)
1626 computed_streams[i] = false;
1627
1628 for (i = 0; i < dc_state->stream_count; i++) {
1629 stream = dc_state->streams[i];
1630 res_pool = stream->ctx->dc->res_pool;
1631
1632 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
1633 continue;
1634
1635 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1636
1637 DRM_DEBUG_DRIVER("%s: MST_DSC compute mst dsc configs for stream 0x%p, aconnector 0x%p\n",
1638 __func__, stream, aconnector);
1639
1640 if (!aconnector || !aconnector->dc_sink || !aconnector->mst_output_port)
1641 continue;
1642
1643 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
1644 continue;
1645
1646 if (computed_streams[i])
1647 continue;
1648
1649 if (res_pool->funcs->remove_stream_from_ctx &&
1650 res_pool->funcs->remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK)
1651 return -EINVAL;
1652
1653 if (!is_dsc_need_re_compute(state, dc_state, stream->link))
1654 continue;
1655
1656 mst_mgr = aconnector->mst_output_port->mgr;
1657 ret = compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars, mst_mgr,
1658 &link_vars_start_index);
1659 if (ret != 0)
1660 return ret;
1661
1662 for (j = 0; j < dc_state->stream_count; j++) {
1663 if (dc_state->streams[j]->link == stream->link)
1664 computed_streams[j] = true;
1665 }
1666 }
1667
1668 for (i = 0; i < dc_state->stream_count; i++) {
1669 stream = dc_state->streams[i];
1670
1671 if (stream->timing.flags.DSC == 1)
1672 if (dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream) != DC_OK) {
1673 DRM_DEBUG_DRIVER("%s:%d MST_DSC Failed to request dsc hw resource for stream 0x%p\n",
1674 __func__, __LINE__, stream);
1675 return -EINVAL;
1676 }
1677 }
1678
1679 return ret;
1680 }
1681
pre_compute_mst_dsc_configs_for_state(struct drm_atomic_commit * state,struct dc_state * dc_state,struct dsc_mst_fairness_vars * vars)1682 static int pre_compute_mst_dsc_configs_for_state(struct drm_atomic_commit *state,
1683 struct dc_state *dc_state,
1684 struct dsc_mst_fairness_vars *vars)
1685 {
1686 int i, j;
1687 struct dc_stream_state *stream;
1688 bool computed_streams[MAX_PIPES];
1689 struct amdgpu_dm_connector *aconnector;
1690 struct drm_dp_mst_topology_mgr *mst_mgr;
1691 int link_vars_start_index = 0;
1692 int ret = 0;
1693
1694 for (i = 0; i < dc_state->stream_count; i++)
1695 computed_streams[i] = false;
1696
1697 for (i = 0; i < dc_state->stream_count; i++) {
1698 stream = dc_state->streams[i];
1699
1700 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
1701 continue;
1702
1703 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1704
1705 DRM_DEBUG_DRIVER("MST_DSC pre compute mst dsc configs for #%d stream 0x%p, aconnector 0x%p\n",
1706 i, stream, aconnector);
1707
1708 if (!aconnector || !aconnector->dc_sink || !aconnector->mst_output_port)
1709 continue;
1710
1711 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
1712 continue;
1713
1714 if (computed_streams[i])
1715 continue;
1716
1717 if (!is_dsc_need_re_compute(state, dc_state, stream->link))
1718 continue;
1719
1720 mst_mgr = aconnector->mst_output_port->mgr;
1721 ret = compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars, mst_mgr,
1722 &link_vars_start_index);
1723 if (ret != 0)
1724 return ret;
1725
1726 for (j = 0; j < dc_state->stream_count; j++) {
1727 if (dc_state->streams[j]->link == stream->link)
1728 computed_streams[j] = true;
1729 }
1730 }
1731
1732 return ret;
1733 }
1734
find_crtc_index_in_state_by_stream(struct drm_atomic_commit * state,struct dc_stream_state * stream)1735 static int find_crtc_index_in_state_by_stream(struct drm_atomic_commit *state,
1736 struct dc_stream_state *stream)
1737 {
1738 int i;
1739 struct drm_crtc *crtc;
1740 struct drm_crtc_state *new_state, *old_state;
1741
1742 for_each_oldnew_crtc_in_state(state, crtc, old_state, new_state, i) {
1743 struct dm_crtc_state *dm_state = to_dm_crtc_state(new_state);
1744
1745 if (dm_state->stream == stream)
1746 return i;
1747 }
1748 return -1;
1749 }
1750
is_link_to_dschub(struct dc_link * dc_link)1751 static bool is_link_to_dschub(struct dc_link *dc_link)
1752 {
1753 union dpcd_dsc_basic_capabilities *dsc_caps =
1754 &dc_link->dpcd_caps.dsc_caps.dsc_basic_caps;
1755
1756 /* only check phy used by dsc mst branch */
1757 if (dc_link->type != dc_connection_mst_branch)
1758 return false;
1759
1760 if (!(dsc_caps->fields.dsc_support.DSC_SUPPORT ||
1761 dsc_caps->fields.dsc_support.DSC_PASSTHROUGH_SUPPORT))
1762 return false;
1763 return true;
1764 }
1765
is_dsc_precompute_needed(struct drm_atomic_commit * state)1766 static bool is_dsc_precompute_needed(struct drm_atomic_commit *state)
1767 {
1768 int i;
1769 struct drm_crtc *crtc;
1770 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
1771 bool ret = false;
1772
1773 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1774 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(new_crtc_state);
1775
1776 if (!amdgpu_dm_find_first_crtc_matching_connector(state, crtc)) {
1777 ret = false;
1778 break;
1779 }
1780 if (dm_crtc_state->stream && dm_crtc_state->stream->link)
1781 if (is_link_to_dschub(dm_crtc_state->stream->link))
1782 ret = true;
1783 }
1784 return ret;
1785 }
1786
pre_validate_dsc(struct drm_atomic_commit * state,struct dm_atomic_state ** dm_state_ptr,struct dsc_mst_fairness_vars * vars)1787 int pre_validate_dsc(struct drm_atomic_commit *state,
1788 struct dm_atomic_state **dm_state_ptr,
1789 struct dsc_mst_fairness_vars *vars)
1790 {
1791 int i;
1792 struct dm_atomic_state *dm_state;
1793 struct dc_state *local_dc_state = NULL;
1794 int ret = 0;
1795
1796 if (!is_dsc_precompute_needed(state)) {
1797 DRM_INFO_ONCE("%s:%d MST_DSC dsc precompute is not needed\n", __func__, __LINE__);
1798 return 0;
1799 }
1800 ret = dm_atomic_get_state(state, dm_state_ptr);
1801 if (ret != 0) {
1802 DRM_INFO_ONCE("%s:%d MST_DSC dm_atomic_get_state() failed\n", __func__, __LINE__);
1803 return ret;
1804 }
1805 dm_state = *dm_state_ptr;
1806
1807 /*
1808 * create local vailable for dc_state. copy content of streams of dm_state->context
1809 * to local variable. make sure stream pointer of local variable not the same as stream
1810 * from dm_state->context.
1811 */
1812
1813 local_dc_state = vmalloc(sizeof(struct dc_state));
1814 if (!local_dc_state)
1815 return -ENOMEM;
1816 memcpy(local_dc_state, dm_state->context, sizeof(struct dc_state));
1817
1818 for (i = 0; i < local_dc_state->stream_count; i++) {
1819 struct dc_stream_state *stream = dm_state->context->streams[i];
1820 int ind = find_crtc_index_in_state_by_stream(state, stream);
1821
1822 if (ind >= 0) {
1823 struct drm_connector *connector;
1824 struct drm_connector_state *drm_new_conn_state;
1825 struct dm_connector_state *dm_new_conn_state;
1826 struct dm_crtc_state *dm_old_crtc_state;
1827
1828 connector =
1829 amdgpu_dm_find_first_crtc_matching_connector(state,
1830 state->crtcs[ind].ptr);
1831 if (!connector)
1832 continue;
1833
1834 drm_new_conn_state =
1835 drm_atomic_get_new_connector_state(state,
1836 connector);
1837 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
1838 dm_old_crtc_state = to_dm_crtc_state(state->crtcs[ind].old_state);
1839
1840 local_dc_state->streams[i] =
1841 amdgpu_dm_create_validate_stream_for_sink(connector,
1842 &state->crtcs[ind].new_state->mode,
1843 dm_new_conn_state,
1844 dm_old_crtc_state->stream);
1845 if (local_dc_state->streams[i] == NULL) {
1846 ret = -EINVAL;
1847 break;
1848 }
1849 }
1850 }
1851
1852 if (ret != 0)
1853 goto clean_exit;
1854
1855 ret = pre_compute_mst_dsc_configs_for_state(state, local_dc_state, vars);
1856 if (ret != 0) {
1857 DRM_INFO_ONCE("%s:%d MST_DSC dsc pre_compute_mst_dsc_configs_for_state() failed\n",
1858 __func__, __LINE__);
1859 ret = -EINVAL;
1860 goto clean_exit;
1861 }
1862
1863 /*
1864 * compare local_streams -> timing with dm_state->context,
1865 * if the same set crtc_state->mode-change = 0;
1866 */
1867 for (i = 0; i < local_dc_state->stream_count; i++) {
1868 struct dc_stream_state *stream = dm_state->context->streams[i];
1869
1870 if (local_dc_state->streams[i] &&
1871 dc_is_timing_changed(stream, local_dc_state->streams[i])) {
1872 DRM_INFO_ONCE("%s:%d MST_DSC crtc[%d] needs mode_change\n", __func__, __LINE__, i);
1873 } else {
1874 int ind = find_crtc_index_in_state_by_stream(state, stream);
1875
1876 if (ind >= 0) {
1877 struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(state->crtcs[ind].new_state);
1878
1879 DRM_INFO_ONCE("%s:%d MST_DSC no mode changed for stream 0x%p\n",
1880 __func__, __LINE__, stream);
1881 dm_new_crtc_state->base.mode_changed = dm_new_crtc_state->mode_changed_independent_from_dsc;
1882 }
1883 }
1884 }
1885 clean_exit:
1886 for (i = 0; i < local_dc_state->stream_count; i++) {
1887 struct dc_stream_state *stream = dm_state->context->streams[i];
1888
1889 if (local_dc_state->streams[i] != stream)
1890 dc_stream_release(local_dc_state->streams[i]);
1891 }
1892
1893 vfree(local_dc_state);
1894
1895 return ret;
1896 }
1897
kbps_from_pbn(unsigned int pbn)1898 static uint32_t kbps_from_pbn(unsigned int pbn)
1899 {
1900 uint64_t kbps = (uint64_t)pbn;
1901
1902 kbps *= (1000000 / PEAK_FACTOR_X1000);
1903 kbps *= 8;
1904 kbps *= 54;
1905 kbps /= 64;
1906
1907 return (uint32_t)kbps;
1908 }
1909
is_dsc_common_config_possible(struct dc_stream_state * stream,struct dc_dsc_bw_range * bw_range)1910 static bool is_dsc_common_config_possible(struct dc_stream_state *stream,
1911 struct dc_dsc_bw_range *bw_range)
1912 {
1913 struct dc_dsc_policy dsc_policy = {0};
1914 bool is_dsc_possible;
1915
1916 dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy, dc_link_get_highest_encoding_format(stream->link));
1917 is_dsc_possible = dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc->res_pool->dscs[0],
1918 stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
1919 dsc_policy.min_target_bpp * 16,
1920 dsc_policy.max_target_bpp * 16,
1921 &stream->sink->dsc_caps.dsc_dec_caps,
1922 &stream->timing, dc_link_get_highest_encoding_format(stream->link), bw_range);
1923
1924 return is_dsc_possible;
1925 }
1926 #endif
1927
1928 #if defined(CONFIG_DRM_AMD_DC_FP)
dp_get_link_current_set_bw(struct drm_dp_aux * aux,uint32_t * cur_link_bw)1929 static bool dp_get_link_current_set_bw(struct drm_dp_aux *aux, uint32_t *cur_link_bw)
1930 {
1931 uint32_t total_data_bw_efficiency_x10000 = 0;
1932 uint32_t link_rate_per_lane_kbps = 0;
1933 enum dc_link_rate link_rate;
1934 union lane_count_set lane_count;
1935 u8 dp_link_encoding;
1936 u8 link_bw_set = 0;
1937 u8 data[16] = {0};
1938
1939 *cur_link_bw = 0;
1940
1941 if (drm_dp_dpcd_read(aux, DP_LINK_BW_SET, data, 16) != 16)
1942 return false;
1943
1944 dp_link_encoding = data[DP_MAIN_LINK_CHANNEL_CODING_SET - DP_LINK_BW_SET];
1945 link_bw_set = data[DP_LINK_BW_SET - DP_LINK_BW_SET];
1946 lane_count.raw = data[DP_LANE_COUNT_SET - DP_LINK_BW_SET];
1947
1948 drm_dbg_dp(aux->drm_dev, "MST_DSC downlink setting: %d, 0x%x x %d\n",
1949 dp_link_encoding, link_bw_set, lane_count.bits.LANE_COUNT_SET);
1950
1951 switch (dp_link_encoding) {
1952 case DP_8b_10b_ENCODING:
1953 link_rate = link_bw_set;
1954 link_rate_per_lane_kbps = link_rate * LINK_RATE_REF_FREQ_IN_KHZ * BITS_PER_DP_BYTE;
1955 total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_8b_10b_x10000;
1956 total_data_bw_efficiency_x10000 /= 100;
1957 total_data_bw_efficiency_x10000 *= DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100;
1958 break;
1959 case DP_128b_132b_ENCODING:
1960 switch (link_bw_set) {
1961 case DP_LINK_BW_10:
1962 link_rate = LINK_RATE_UHBR10;
1963 break;
1964 case DP_LINK_BW_13_5:
1965 link_rate = LINK_RATE_UHBR13_5;
1966 break;
1967 case DP_LINK_BW_20:
1968 link_rate = LINK_RATE_UHBR20;
1969 break;
1970 default:
1971 return false;
1972 }
1973
1974 link_rate_per_lane_kbps = link_rate * 10000;
1975 total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_128b_132b_x10000;
1976 break;
1977 default:
1978 return false;
1979 }
1980
1981 *cur_link_bw = link_rate_per_lane_kbps * lane_count.bits.LANE_COUNT_SET / 10000 * total_data_bw_efficiency_x10000;
1982 return true;
1983 }
1984 #endif
1985
dm_dp_mst_is_port_support_mode(struct amdgpu_dm_connector * aconnector,struct dc_stream_state * stream)1986 enum dc_status dm_dp_mst_is_port_support_mode(
1987 struct amdgpu_dm_connector *aconnector,
1988 struct dc_stream_state *stream)
1989 {
1990 #if defined(CONFIG_DRM_AMD_DC_FP)
1991 int branch_max_throughput_mps = 0;
1992 struct dc_link_settings cur_link_settings;
1993 uint32_t end_to_end_bw_in_kbps = 0;
1994 uint32_t root_link_bw_in_kbps = 0;
1995 uint32_t virtual_channel_bw_in_kbps = 0;
1996 struct dc_dsc_bw_range bw_range = {0};
1997 struct dc_dsc_config_options dsc_options = {0};
1998 uint32_t stream_kbps;
1999
2000 if (!aconnector->dc_sink)
2001 return DC_FAIL_BANDWIDTH_VALIDATE;
2002
2003 /* DSC unnecessary case
2004 * Check if timing could be supported within end-to-end BW
2005 */
2006 stream_kbps =
2007 dc_bandwidth_in_kbps_from_timing(&stream->timing,
2008 dc_link_get_highest_encoding_format(stream->link));
2009 cur_link_settings = stream->link->verified_link_cap;
2010 root_link_bw_in_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, &cur_link_settings);
2011 virtual_channel_bw_in_kbps = kbps_from_pbn(aconnector->mst_output_port->full_pbn);
2012
2013 /* pick the end to end bw bottleneck */
2014 end_to_end_bw_in_kbps = min(root_link_bw_in_kbps, virtual_channel_bw_in_kbps);
2015
2016 if (stream_kbps <= end_to_end_bw_in_kbps) {
2017 DRM_DEBUG_DRIVER("MST_DSC no dsc required. End-to-end bw sufficient\n");
2018 return DC_OK;
2019 }
2020
2021 /*DSC necessary case*/
2022 if (!aconnector->dsc_aux)
2023 return DC_FAIL_BANDWIDTH_VALIDATE;
2024
2025 if (is_dsc_common_config_possible(stream, &bw_range)) {
2026
2027 /*capable of dsc passthough. dsc bitstream along the entire path*/
2028 if (aconnector->mst_output_port->passthrough_aux) {
2029 if (bw_range.min_kbps > end_to_end_bw_in_kbps) {
2030 DRM_DEBUG_DRIVER("MST_DSC dsc passthrough and decode at endpoint"
2031 "Max dsc compression bw can't fit into end-to-end bw\n");
2032 return DC_FAIL_BANDWIDTH_VALIDATE;
2033 }
2034 } else {
2035 /*dsc bitstream decoded at the dp last link*/
2036 struct drm_dp_mst_port *immediate_upstream_port = NULL;
2037 uint32_t end_link_bw = 0;
2038
2039 /*Get last DP link BW capability. Mode shall be supported by Legacy peer*/
2040 if (aconnector->mst_output_port->pdt != DP_PEER_DEVICE_DP_LEGACY_CONV &&
2041 aconnector->mst_output_port->pdt != DP_PEER_DEVICE_NONE) {
2042 if (aconnector->vc_full_pbn != aconnector->mst_output_port->full_pbn) {
2043 dp_get_link_current_set_bw(&aconnector->mst_output_port->aux, &end_link_bw);
2044 aconnector->vc_full_pbn = aconnector->mst_output_port->full_pbn;
2045 aconnector->mst_local_bw = end_link_bw;
2046 } else {
2047 end_link_bw = aconnector->mst_local_bw;
2048 }
2049
2050 if (end_link_bw > 0 &&
2051 stream_kbps > end_link_bw &&
2052 aconnector->branch_ieee_oui != DP_BRANCH_DEVICE_ID_90CC24) {
2053 DRM_DEBUG_DRIVER("MST_DSC dsc decode at last link. "
2054 "Mode required bw can't fit into last link\n");
2055 return DC_FAIL_BANDWIDTH_VALIDATE;
2056 }
2057 }
2058
2059 /*Get virtual channel bandwidth between source and the link before the last link*/
2060 if (aconnector->mst_output_port->parent->port_parent)
2061 immediate_upstream_port = aconnector->mst_output_port->parent->port_parent;
2062
2063 if (immediate_upstream_port) {
2064 virtual_channel_bw_in_kbps = kbps_from_pbn(immediate_upstream_port->full_pbn);
2065 virtual_channel_bw_in_kbps = min(root_link_bw_in_kbps, virtual_channel_bw_in_kbps);
2066 } else {
2067 /* For topology LCT 1 case - only one mstb*/
2068 virtual_channel_bw_in_kbps = root_link_bw_in_kbps;
2069 }
2070
2071 if (bw_range.min_kbps > virtual_channel_bw_in_kbps) {
2072 DRM_DEBUG_DRIVER("MST_DSC dsc decode at last link."
2073 "Max dsc compression can't fit into MST available bw\n");
2074 return DC_FAIL_BANDWIDTH_VALIDATE;
2075 }
2076 }
2077
2078 /*Confirm if we can obtain dsc config*/
2079 dc_dsc_get_default_config_option(stream->link->dc, &dsc_options);
2080 dsc_options.max_target_bpp_limit_override_x16 = aconnector->base.display_info.max_dsc_bpp * 16;
2081 if (dc_dsc_compute_config(stream->sink->ctx->dc->res_pool->dscs[0],
2082 &stream->sink->dsc_caps.dsc_dec_caps,
2083 &dsc_options,
2084 end_to_end_bw_in_kbps,
2085 &stream->timing,
2086 dc_link_get_highest_encoding_format(stream->link),
2087 &stream->timing.dsc_cfg)) {
2088 stream->timing.flags.DSC = 1;
2089 DRM_DEBUG_DRIVER("MST_DSC require dsc and dsc config found\n");
2090 } else {
2091 DRM_DEBUG_DRIVER("MST_DSC require dsc but can't find appropriate dsc config\n");
2092 return DC_FAIL_BANDWIDTH_VALIDATE;
2093 }
2094
2095 /* check is mst dsc output bandwidth branch_overall_throughput_0_mps */
2096 switch (stream->timing.pixel_encoding) {
2097 case PIXEL_ENCODING_RGB:
2098 case PIXEL_ENCODING_YCBCR444:
2099 branch_max_throughput_mps =
2100 aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_0_mps;
2101 break;
2102 case PIXEL_ENCODING_YCBCR422:
2103 case PIXEL_ENCODING_YCBCR420:
2104 branch_max_throughput_mps =
2105 aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_1_mps;
2106 break;
2107 default:
2108 break;
2109 }
2110
2111 if (branch_max_throughput_mps != 0 &&
2112 ((stream->timing.pix_clk_100hz / 10) > branch_max_throughput_mps * 1000)) {
2113 DRM_DEBUG_DRIVER("MST_DSC require dsc but max throughput mps fails\n");
2114 return DC_FAIL_BANDWIDTH_VALIDATE;
2115 }
2116 } else {
2117 DRM_DEBUG_DRIVER("MST_DSC require dsc but can't find common dsc config\n");
2118 return DC_FAIL_BANDWIDTH_VALIDATE;
2119 }
2120 #endif
2121 return DC_OK;
2122 }
2123 EXPORT_IF_KUNIT(dm_dp_mst_is_port_support_mode);
2124