1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/vmalloc.h>
27 #include <drm/display/drm_dp_helper.h>
28 #include <drm/display/drm_dp_mst_helper.h>
29 #include <drm/drm_atomic.h>
30 #include <drm/drm_atomic_helper.h>
31 #include <drm/drm_fixed.h>
32 #include <drm/drm_edid.h>
33 #include "dm_services.h"
34 #include "amdgpu.h"
35 #include "amdgpu_dm.h"
36 #include "amdgpu_dm_mst_types.h"
37 #include "amdgpu_dm_hdcp.h"
38
39 #include "dc.h"
40 #include "dm_helpers.h"
41
42 #include "ddc_service_types.h"
43 #include "dpcd_defs.h"
44
45 #include "dmub_cmd.h"
46 #if defined(CONFIG_DEBUG_FS)
47 #include "amdgpu_dm_debugfs.h"
48 #endif
49
50 #include "dc/resource/dcn20/dcn20_resource.h"
51
52 #define PEAK_FACTOR_X1000 1006
53
dm_dp_aux_transfer(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)54 static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
55 struct drm_dp_aux_msg *msg)
56 {
57 ssize_t result = 0;
58 struct aux_payload payload;
59 enum aux_return_code_type operation_result;
60 struct amdgpu_device *adev;
61 struct ddc_service *ddc;
62
63 if (WARN_ON(msg->size > 16))
64 return -E2BIG;
65
66 payload.address = msg->address;
67 payload.data = msg->buffer;
68 payload.length = msg->size;
69 payload.reply = &msg->reply;
70 payload.i2c_over_aux = (msg->request & DP_AUX_NATIVE_WRITE) == 0;
71 payload.write = (msg->request & DP_AUX_I2C_READ) == 0;
72 payload.mot = (msg->request & DP_AUX_I2C_MOT) != 0;
73 payload.write_status_update =
74 (msg->request & DP_AUX_I2C_WRITE_STATUS_UPDATE) != 0;
75 payload.defer_delay = 0;
76
77 result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload,
78 &operation_result);
79
80 /*
81 * w/a on certain intel platform where hpd is unexpected to pull low during
82 * 1st sideband message transaction by return AUX_RET_ERROR_HPD_DISCON
83 * aux transaction is succuess in such case, therefore bypass the error
84 */
85 ddc = TO_DM_AUX(aux)->ddc_service;
86 adev = ddc->ctx->driver_context;
87 if (adev->dm.aux_hpd_discon_quirk) {
88 if (msg->address == DP_SIDEBAND_MSG_DOWN_REQ_BASE &&
89 operation_result == AUX_RET_ERROR_HPD_DISCON) {
90 result = 0;
91 operation_result = AUX_RET_SUCCESS;
92 }
93 }
94
95 if (payload.write && result >= 0)
96 result = msg->size;
97
98 if (result < 0)
99 switch (operation_result) {
100 case AUX_RET_SUCCESS:
101 break;
102 case AUX_RET_ERROR_HPD_DISCON:
103 case AUX_RET_ERROR_UNKNOWN:
104 case AUX_RET_ERROR_INVALID_OPERATION:
105 case AUX_RET_ERROR_PROTOCOL_ERROR:
106 result = -EIO;
107 break;
108 case AUX_RET_ERROR_INVALID_REPLY:
109 case AUX_RET_ERROR_ENGINE_ACQUIRE:
110 result = -EBUSY;
111 break;
112 case AUX_RET_ERROR_TIMEOUT:
113 result = -ETIMEDOUT;
114 break;
115 }
116
117 return result;
118 }
119
120 static void
dm_dp_mst_connector_destroy(struct drm_connector * connector)121 dm_dp_mst_connector_destroy(struct drm_connector *connector)
122 {
123 struct amdgpu_dm_connector *aconnector =
124 to_amdgpu_dm_connector(connector);
125
126 if (aconnector->dc_sink) {
127 dc_link_remove_remote_sink(aconnector->dc_link,
128 aconnector->dc_sink);
129 dc_sink_release(aconnector->dc_sink);
130 }
131
132 drm_edid_free(aconnector->drm_edid);
133
134 drm_connector_cleanup(connector);
135 drm_dp_mst_put_port_malloc(aconnector->mst_output_port);
136 kfree(aconnector);
137 }
138
139 static int
amdgpu_dm_mst_connector_late_register(struct drm_connector * connector)140 amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
141 {
142 struct amdgpu_dm_connector *amdgpu_dm_connector =
143 to_amdgpu_dm_connector(connector);
144 int r;
145
146 r = drm_dp_mst_connector_late_register(connector,
147 amdgpu_dm_connector->mst_output_port);
148 if (r < 0)
149 return r;
150
151 #if defined(CONFIG_DEBUG_FS)
152 connector_debugfs_init(amdgpu_dm_connector);
153 #endif
154
155 return 0;
156 }
157
158 static void
amdgpu_dm_mst_connector_early_unregister(struct drm_connector * connector)159 amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
160 {
161 struct amdgpu_dm_connector *aconnector =
162 to_amdgpu_dm_connector(connector);
163 struct drm_dp_mst_port *port = aconnector->mst_output_port;
164 struct amdgpu_dm_connector *root = aconnector->mst_root;
165 struct dc_link *dc_link = aconnector->dc_link;
166 struct dc_sink *dc_sink = aconnector->dc_sink;
167
168 drm_dp_mst_connector_early_unregister(connector, port);
169
170 /*
171 * Release dc_sink for connector which its attached port is
172 * no longer in the mst topology
173 */
174 drm_modeset_lock(&root->mst_mgr.base.lock, NULL);
175 if (dc_sink) {
176 if (dc_link->sink_count)
177 dc_link_remove_remote_sink(dc_link, dc_sink);
178
179 drm_dbg_dp(connector->dev,
180 "DM_MST: remove remote sink 0x%p, %d remaining\n",
181 dc_sink, dc_link->sink_count);
182
183 dc_sink_release(dc_sink);
184 aconnector->dc_sink = NULL;
185 aconnector->drm_edid = NULL;
186 aconnector->dsc_aux = NULL;
187 port->passthrough_aux = NULL;
188 }
189
190 aconnector->mst_status = MST_STATUS_DEFAULT;
191 drm_modeset_unlock(&root->mst_mgr.base.lock);
192 }
193
194 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
195 .fill_modes = drm_helper_probe_single_connector_modes,
196 .destroy = dm_dp_mst_connector_destroy,
197 .reset = amdgpu_dm_connector_funcs_reset,
198 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
199 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
200 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
201 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
202 .late_register = amdgpu_dm_mst_connector_late_register,
203 .early_unregister = amdgpu_dm_mst_connector_early_unregister,
204 };
205
needs_dsc_aux_workaround(struct dc_link * link)206 bool needs_dsc_aux_workaround(struct dc_link *link)
207 {
208 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
209 (link->dpcd_caps.dpcd_rev.raw == DPCD_REV_14 || link->dpcd_caps.dpcd_rev.raw == DPCD_REV_12) &&
210 link->dpcd_caps.sink_count.bits.SINK_COUNT >= 2)
211 return true;
212
213 return false;
214 }
215
216 #if defined(CONFIG_DRM_AMD_DC_FP)
is_synaptics_cascaded_panamera(struct dc_link * link,struct drm_dp_mst_port * port)217 static bool is_synaptics_cascaded_panamera(struct dc_link *link, struct drm_dp_mst_port *port)
218 {
219 u8 branch_vendor_data[4] = { 0 }; // Vendor data 0x50C ~ 0x50F
220
221 if (drm_dp_dpcd_read(port->mgr->aux, DP_BRANCH_VENDOR_SPECIFIC_START, &branch_vendor_data, 4) == 4) {
222 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
223 IS_SYNAPTICS_CASCADED_PANAMERA(link->dpcd_caps.branch_dev_name, branch_vendor_data)) {
224 DRM_INFO("Synaptics Cascaded MST hub\n");
225 return true;
226 }
227 }
228
229 return false;
230 }
231
validate_dsc_caps_on_connector(struct amdgpu_dm_connector * aconnector)232 static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector)
233 {
234 struct dc_sink *dc_sink = aconnector->dc_sink;
235 struct drm_dp_mst_port *port = aconnector->mst_output_port;
236 u8 dsc_caps[16] = { 0 };
237 u8 dsc_branch_dec_caps_raw[3] = { 0 }; // DSC branch decoder caps 0xA0 ~ 0xA2
238 u8 *dsc_branch_dec_caps = NULL;
239
240 aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);
241
242 /*
243 * drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs
244 * because it only check the dsc/fec caps of the "port variable" and not the dock
245 *
246 * This case will return NULL: DSC capabe MST dock connected to a non fec/dsc capable display
247 *
248 * Workaround: explicitly check the use case above and use the mst dock's aux as dsc_aux
249 *
250 */
251 if (!aconnector->dsc_aux && !port->parent->port_parent &&
252 needs_dsc_aux_workaround(aconnector->dc_link))
253 aconnector->dsc_aux = &aconnector->mst_root->dm_dp_aux.aux;
254
255 /* synaptics cascaded MST hub case */
256 if (is_synaptics_cascaded_panamera(aconnector->dc_link, port))
257 aconnector->dsc_aux = port->mgr->aux;
258
259 if (!aconnector->dsc_aux)
260 return false;
261
262 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0)
263 return false;
264
265 if (drm_dp_dpcd_read(aconnector->dsc_aux,
266 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, dsc_branch_dec_caps_raw, 3) == 3)
267 dsc_branch_dec_caps = dsc_branch_dec_caps_raw;
268
269 if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
270 dsc_caps, dsc_branch_dec_caps,
271 &dc_sink->dsc_caps.dsc_dec_caps))
272 return false;
273
274 return true;
275 }
276 #endif
277
retrieve_downstream_port_device(struct amdgpu_dm_connector * aconnector)278 static bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnector)
279 {
280 union dp_downstream_port_present ds_port_present;
281
282 if (!aconnector->dsc_aux)
283 return false;
284
285 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DOWNSTREAMPORT_PRESENT, &ds_port_present, 1) < 0) {
286 DRM_INFO("Failed to read downstream_port_present 0x05 from DFP of branch device\n");
287 return false;
288 }
289
290 aconnector->mst_downstream_port_present = ds_port_present;
291 DRM_INFO("Downstream port present %d, type %d\n",
292 ds_port_present.fields.PORT_PRESENT, ds_port_present.fields.PORT_TYPE);
293
294 return true;
295 }
296
dm_dp_mst_get_modes(struct drm_connector * connector)297 static int dm_dp_mst_get_modes(struct drm_connector *connector)
298 {
299 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
300 int ret = 0;
301
302 if (!aconnector)
303 return drm_add_edid_modes(connector, NULL);
304
305 if (!aconnector->drm_edid) {
306 const struct drm_edid *drm_edid;
307
308 drm_edid = drm_dp_mst_edid_read(connector,
309 &aconnector->mst_root->mst_mgr,
310 aconnector->mst_output_port);
311
312 if (!drm_edid) {
313 amdgpu_dm_set_mst_status(&aconnector->mst_status,
314 MST_REMOTE_EDID, false);
315
316 drm_edid_connector_update(
317 &aconnector->base,
318 NULL);
319
320 DRM_DEBUG_KMS("Can't get EDID of %s. Add default remote sink.", connector->name);
321 if (!aconnector->dc_sink) {
322 struct dc_sink *dc_sink;
323 struct dc_sink_init_data init_params = {
324 .link = aconnector->dc_link,
325 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
326
327 dc_sink = dc_link_add_remote_sink(
328 aconnector->dc_link,
329 NULL,
330 0,
331 &init_params);
332
333 if (!dc_sink) {
334 DRM_ERROR("Unable to add a remote sink\n");
335 return 0;
336 }
337
338 drm_dbg_dp(connector->dev,
339 "DM_MST: add remote sink 0x%p, %d remaining\n",
340 dc_sink,
341 aconnector->dc_link->sink_count);
342
343 dc_sink->priv = aconnector;
344 aconnector->dc_sink = dc_sink;
345 }
346
347 return ret;
348 }
349
350 aconnector->drm_edid = drm_edid;
351 amdgpu_dm_set_mst_status(&aconnector->mst_status,
352 MST_REMOTE_EDID, true);
353 }
354
355 if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) {
356 dc_sink_release(aconnector->dc_sink);
357 aconnector->dc_sink = NULL;
358 }
359
360 if (!aconnector->dc_sink) {
361 struct dc_sink *dc_sink;
362 struct dc_sink_init_data init_params = {
363 .link = aconnector->dc_link,
364 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
365 const struct edid *edid;
366
367 edid = drm_edid_raw(aconnector->drm_edid); // FIXME: Get rid of drm_edid_raw()
368 dc_sink = dc_link_add_remote_sink(
369 aconnector->dc_link,
370 (uint8_t *)edid,
371 (edid->extensions + 1) * EDID_LENGTH,
372 &init_params);
373
374 if (!dc_sink) {
375 DRM_ERROR("Unable to add a remote sink\n");
376 return 0;
377 }
378
379 drm_dbg_dp(connector->dev,
380 "DM_MST: add remote sink 0x%p, %d remaining\n",
381 dc_sink, aconnector->dc_link->sink_count);
382
383 dc_sink->priv = aconnector;
384 /* dc_link_add_remote_sink returns a new reference */
385 aconnector->dc_sink = dc_sink;
386
387 /* when display is unplugged from mst hub, connctor will be
388 * destroyed within dm_dp_mst_connector_destroy. connector
389 * hdcp perperties, like type, undesired, desired, enabled,
390 * will be lost. So, save hdcp properties into hdcp_work within
391 * amdgpu_dm_atomic_commit_tail. if the same display is
392 * plugged back with same display index, its hdcp properties
393 * will be retrieved from hdcp_work within dm_dp_mst_get_modes
394 */
395 if (aconnector->dc_sink && connector->state) {
396 struct drm_device *dev = connector->dev;
397 struct amdgpu_device *adev = drm_to_adev(dev);
398
399 if (adev->dm.hdcp_workqueue) {
400 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
401 struct hdcp_workqueue *hdcp_w =
402 &hdcp_work[aconnector->dc_link->link_index];
403
404 connector->state->hdcp_content_type =
405 hdcp_w->hdcp_content_type[connector->index];
406 connector->state->content_protection =
407 hdcp_w->content_protection[connector->index];
408 }
409 }
410
411 if (aconnector->dc_sink) {
412 amdgpu_dm_update_freesync_caps(
413 connector, aconnector->drm_edid);
414
415 #if defined(CONFIG_DRM_AMD_DC_FP)
416 if (!validate_dsc_caps_on_connector(aconnector))
417 memset(&aconnector->dc_sink->dsc_caps,
418 0, sizeof(aconnector->dc_sink->dsc_caps));
419 #endif
420
421 if (!retrieve_downstream_port_device(aconnector))
422 memset(&aconnector->mst_downstream_port_present,
423 0, sizeof(aconnector->mst_downstream_port_present));
424 }
425 }
426
427 drm_edid_connector_update(&aconnector->base, aconnector->drm_edid);
428
429 ret = drm_edid_connector_add_modes(connector);
430
431 return ret;
432 }
433
434 static struct drm_encoder *
dm_mst_atomic_best_encoder(struct drm_connector * connector,struct drm_atomic_state * state)435 dm_mst_atomic_best_encoder(struct drm_connector *connector,
436 struct drm_atomic_state *state)
437 {
438 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,
439 connector);
440 struct amdgpu_device *adev = drm_to_adev(connector->dev);
441 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(connector_state->crtc);
442
443 return &adev->dm.mst_encoders[acrtc->crtc_id].base;
444 }
445
446 static int
dm_dp_mst_detect(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx,bool force)447 dm_dp_mst_detect(struct drm_connector *connector,
448 struct drm_modeset_acquire_ctx *ctx, bool force)
449 {
450 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
451 struct amdgpu_dm_connector *master = aconnector->mst_root;
452 struct drm_dp_mst_port *port = aconnector->mst_output_port;
453 int connection_status;
454
455 if (drm_connector_is_unregistered(connector))
456 return connector_status_disconnected;
457
458 connection_status = drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
459 aconnector->mst_output_port);
460
461 if (port->pdt != DP_PEER_DEVICE_NONE && !port->dpcd_rev) {
462 uint8_t dpcd_rev;
463 int ret;
464
465 ret = drm_dp_dpcd_readb(&port->aux, DP_DP13_DPCD_REV, &dpcd_rev);
466
467 if (ret == 1) {
468 port->dpcd_rev = dpcd_rev;
469
470 /* Could be DP1.2 DP Rx case*/
471 if (!dpcd_rev) {
472 ret = drm_dp_dpcd_readb(&port->aux, DP_DPCD_REV, &dpcd_rev);
473
474 if (ret == 1)
475 port->dpcd_rev = dpcd_rev;
476 }
477
478 if (!dpcd_rev)
479 DRM_DEBUG_KMS("Can't decide DPCD revision number!");
480 }
481
482 /*
483 * Could be legacy sink, logical port etc on DP1.2.
484 * Will get Nack under these cases when issue remote
485 * DPCD read.
486 */
487 if (ret != 1)
488 DRM_DEBUG_KMS("Can't access DPCD");
489 } else if (port->pdt == DP_PEER_DEVICE_NONE) {
490 port->dpcd_rev = 0;
491 }
492
493 /*
494 * Release dc_sink for connector which unplug event is notified by CSN msg
495 */
496 if (connection_status == connector_status_disconnected && aconnector->dc_sink) {
497 if (aconnector->dc_link->sink_count)
498 dc_link_remove_remote_sink(aconnector->dc_link, aconnector->dc_sink);
499
500 drm_dbg_dp(connector->dev,
501 "DM_MST: remove remote sink 0x%p, %d remaining\n",
502 aconnector->dc_link,
503 aconnector->dc_link->sink_count);
504
505 dc_sink_release(aconnector->dc_sink);
506 aconnector->dc_sink = NULL;
507 aconnector->drm_edid = NULL;
508 aconnector->dsc_aux = NULL;
509 port->passthrough_aux = NULL;
510
511 amdgpu_dm_set_mst_status(&aconnector->mst_status,
512 MST_REMOTE_EDID | MST_ALLOCATE_NEW_PAYLOAD | MST_CLEAR_ALLOCATED_PAYLOAD,
513 false);
514 }
515
516 return connection_status;
517 }
518
dm_dp_mst_atomic_check(struct drm_connector * connector,struct drm_atomic_state * state)519 static int dm_dp_mst_atomic_check(struct drm_connector *connector,
520 struct drm_atomic_state *state)
521 {
522 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
523 struct drm_dp_mst_topology_mgr *mst_mgr = &aconnector->mst_root->mst_mgr;
524 struct drm_dp_mst_port *mst_port = aconnector->mst_output_port;
525
526 return drm_dp_atomic_release_time_slots(state, mst_mgr, mst_port);
527 }
528
529 static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = {
530 .get_modes = dm_dp_mst_get_modes,
531 .mode_valid = amdgpu_dm_connector_mode_valid,
532 .atomic_best_encoder = dm_mst_atomic_best_encoder,
533 .detect_ctx = dm_dp_mst_detect,
534 .atomic_check = dm_dp_mst_atomic_check,
535 };
536
amdgpu_dm_encoder_destroy(struct drm_encoder * encoder)537 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
538 {
539 drm_encoder_cleanup(encoder);
540 }
541
542 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
543 .destroy = amdgpu_dm_encoder_destroy,
544 };
545
546 void
dm_dp_create_fake_mst_encoders(struct amdgpu_device * adev)547 dm_dp_create_fake_mst_encoders(struct amdgpu_device *adev)
548 {
549 struct drm_device *dev = adev_to_drm(adev);
550 int i;
551
552 for (i = 0; i < adev->dm.display_indexes_num; i++) {
553 struct amdgpu_encoder *amdgpu_encoder = &adev->dm.mst_encoders[i];
554 struct drm_encoder *encoder = &amdgpu_encoder->base;
555
556 encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
557
558 drm_encoder_init(
559 dev,
560 &amdgpu_encoder->base,
561 &amdgpu_dm_encoder_funcs,
562 DRM_MODE_ENCODER_DPMST,
563 NULL);
564
565 drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs);
566 }
567 }
568
569 static struct drm_connector *
dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr * mgr,struct drm_dp_mst_port * port,const char * pathprop)570 dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
571 struct drm_dp_mst_port *port,
572 const char *pathprop)
573 {
574 struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
575 struct drm_device *dev = master->base.dev;
576 struct amdgpu_device *adev = drm_to_adev(dev);
577 struct amdgpu_dm_connector *aconnector;
578 struct drm_connector *connector;
579 int i;
580
581 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
582 if (!aconnector)
583 return NULL;
584
585 DRM_DEBUG_DRIVER("%s: Create aconnector 0x%p for port 0x%p\n", __func__, aconnector, port);
586
587 connector = &aconnector->base;
588 aconnector->mst_output_port = port;
589 aconnector->mst_root = master;
590 amdgpu_dm_set_mst_status(&aconnector->mst_status,
591 MST_PROBE, true);
592
593 if (drm_connector_init(
594 dev,
595 connector,
596 &dm_dp_mst_connector_funcs,
597 DRM_MODE_CONNECTOR_DisplayPort)) {
598 kfree(aconnector);
599 return NULL;
600 }
601 drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs);
602
603 amdgpu_dm_connector_init_helper(
604 &adev->dm,
605 aconnector,
606 DRM_MODE_CONNECTOR_DisplayPort,
607 master->dc_link,
608 master->connector_id);
609
610 for (i = 0; i < adev->dm.display_indexes_num; i++) {
611 drm_connector_attach_encoder(&aconnector->base,
612 &adev->dm.mst_encoders[i].base);
613 }
614
615 connector->max_bpc_property = master->base.max_bpc_property;
616 if (connector->max_bpc_property)
617 drm_connector_attach_max_bpc_property(connector, 8, 16);
618
619 connector->vrr_capable_property = master->base.vrr_capable_property;
620 if (connector->vrr_capable_property)
621 drm_connector_attach_vrr_capable_property(connector);
622
623 drm_object_attach_property(
624 &connector->base,
625 dev->mode_config.path_property,
626 0);
627 drm_object_attach_property(
628 &connector->base,
629 dev->mode_config.tile_property,
630 0);
631 connector->colorspace_property = master->base.colorspace_property;
632 if (connector->colorspace_property)
633 drm_connector_attach_colorspace_property(connector);
634
635 drm_connector_set_path_property(connector, pathprop);
636
637 /*
638 * Initialize connector state before adding the connectror to drm and
639 * framebuffer lists
640 */
641 amdgpu_dm_connector_funcs_reset(connector);
642
643 drm_dp_mst_get_port_malloc(port);
644
645 return connector;
646 }
647
dm_handle_mst_sideband_msg_ready_event(struct drm_dp_mst_topology_mgr * mgr,enum mst_msg_ready_type msg_rdy_type)648 void dm_handle_mst_sideband_msg_ready_event(
649 struct drm_dp_mst_topology_mgr *mgr,
650 enum mst_msg_ready_type msg_rdy_type)
651 {
652 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
653 uint8_t dret;
654 bool new_irq_handled = false;
655 int dpcd_addr;
656 uint8_t dpcd_bytes_to_read;
657 const uint8_t max_process_count = 30;
658 uint8_t process_count = 0;
659 u8 retry;
660 struct amdgpu_dm_connector *aconnector =
661 container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
662
663
664 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
665
666 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
667 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
668 /* DPCD 0x200 - 0x201 for downstream IRQ */
669 dpcd_addr = DP_SINK_COUNT;
670 } else {
671 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
672 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
673 dpcd_addr = DP_SINK_COUNT_ESI;
674 }
675
676 mutex_lock(&aconnector->handle_mst_msg_ready);
677
678 while (process_count < max_process_count) {
679 u8 ack[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = {};
680
681 process_count++;
682
683 dret = drm_dp_dpcd_read(
684 &aconnector->dm_dp_aux.aux,
685 dpcd_addr,
686 esi,
687 dpcd_bytes_to_read);
688
689 if (dret != dpcd_bytes_to_read) {
690 DRM_DEBUG_KMS("DPCD read and acked number is not as expected!");
691 break;
692 }
693
694 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
695
696 switch (msg_rdy_type) {
697 case DOWN_REP_MSG_RDY_EVENT:
698 /* Only handle DOWN_REP_MSG_RDY case*/
699 esi[1] &= DP_DOWN_REP_MSG_RDY;
700 break;
701 case UP_REQ_MSG_RDY_EVENT:
702 /* Only handle UP_REQ_MSG_RDY case*/
703 esi[1] &= DP_UP_REQ_MSG_RDY;
704 break;
705 default:
706 /* Handle both cases*/
707 esi[1] &= (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY);
708 break;
709 }
710
711 if (!esi[1])
712 break;
713
714 /* handle MST irq */
715 if (aconnector->mst_mgr.mst_state)
716 drm_dp_mst_hpd_irq_handle_event(&aconnector->mst_mgr,
717 esi,
718 ack,
719 &new_irq_handled);
720
721 if (new_irq_handled) {
722 /* ACK at DPCD to notify down stream */
723 for (retry = 0; retry < 3; retry++) {
724 ssize_t wret;
725
726 wret = drm_dp_dpcd_writeb(&aconnector->dm_dp_aux.aux,
727 dpcd_addr + 1,
728 ack[1]);
729 if (wret == 1)
730 break;
731 }
732
733 if (retry == 3) {
734 DRM_ERROR("Failed to ack MST event.\n");
735 break;
736 }
737
738 drm_dp_mst_hpd_irq_send_new_request(&aconnector->mst_mgr);
739
740 new_irq_handled = false;
741 } else {
742 break;
743 }
744 }
745
746 mutex_unlock(&aconnector->handle_mst_msg_ready);
747
748 if (process_count == max_process_count)
749 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
750 }
751
dm_handle_mst_down_rep_msg_ready(struct drm_dp_mst_topology_mgr * mgr)752 static void dm_handle_mst_down_rep_msg_ready(struct drm_dp_mst_topology_mgr *mgr)
753 {
754 dm_handle_mst_sideband_msg_ready_event(mgr, DOWN_REP_MSG_RDY_EVENT);
755 }
756
757 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
758 .add_connector = dm_dp_add_mst_connector,
759 .poll_hpd_irq = dm_handle_mst_down_rep_msg_ready,
760 };
761
amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager * dm,struct amdgpu_dm_connector * aconnector,int link_index)762 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
763 struct amdgpu_dm_connector *aconnector,
764 int link_index)
765 {
766 struct dc_link_settings max_link_enc_cap = {0};
767
768 aconnector->dm_dp_aux.aux.name =
769 kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d",
770 link_index);
771 aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
772 aconnector->dm_dp_aux.aux.drm_dev = dm->ddev;
773 aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
774
775 drm_dp_aux_init(&aconnector->dm_dp_aux.aux);
776 drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux,
777 &aconnector->base);
778
779 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
780 return;
781
782 dc_link_dp_get_max_link_enc_cap(aconnector->dc_link, &max_link_enc_cap);
783 aconnector->mst_mgr.cbs = &dm_mst_cbs;
784 drm_dp_mst_topology_mgr_init(&aconnector->mst_mgr, adev_to_drm(dm->adev),
785 &aconnector->dm_dp_aux.aux, 16, 4, aconnector->connector_id);
786
787 drm_connector_attach_dp_subconnector_property(&aconnector->base);
788 }
789
dm_mst_get_pbn_divider(struct dc_link * link)790 int dm_mst_get_pbn_divider(struct dc_link *link)
791 {
792 if (!link)
793 return 0;
794
795 return dc_link_bandwidth_kbps(link,
796 dc_link_get_link_cap(link)) / (8 * 1000 * 54);
797 }
798
799 struct dsc_mst_fairness_params {
800 struct dc_crtc_timing *timing;
801 struct dc_sink *sink;
802 struct dc_dsc_bw_range bw_range;
803 bool compression_possible;
804 struct drm_dp_mst_port *port;
805 enum dsc_clock_force_state clock_force_enable;
806 uint32_t num_slices_h;
807 uint32_t num_slices_v;
808 uint32_t bpp_overwrite;
809 struct amdgpu_dm_connector *aconnector;
810 };
811
812 #if defined(CONFIG_DRM_AMD_DC_FP)
get_fec_overhead_multiplier(struct dc_link * dc_link)813 static uint16_t get_fec_overhead_multiplier(struct dc_link *dc_link)
814 {
815 u8 link_coding_cap;
816 uint16_t fec_overhead_multiplier_x1000 = PBN_FEC_OVERHEAD_MULTIPLIER_8B_10B;
817
818 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(dc_link);
819 if (link_coding_cap == DP_128b_132b_ENCODING)
820 fec_overhead_multiplier_x1000 = PBN_FEC_OVERHEAD_MULTIPLIER_128B_132B;
821
822 return fec_overhead_multiplier_x1000;
823 }
824
kbps_to_peak_pbn(int kbps,uint16_t fec_overhead_multiplier_x1000)825 static int kbps_to_peak_pbn(int kbps, uint16_t fec_overhead_multiplier_x1000)
826 {
827 u64 peak_kbps = kbps;
828
829 peak_kbps *= 1006;
830 peak_kbps *= fec_overhead_multiplier_x1000;
831 peak_kbps = div_u64(peak_kbps, 1000 * 1000);
832 return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000));
833 }
834
set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params * params,struct dsc_mst_fairness_vars * vars,int count,int k)835 static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params,
836 struct dsc_mst_fairness_vars *vars,
837 int count,
838 int k)
839 {
840 struct drm_connector *drm_connector;
841 int i;
842 struct dc_dsc_config_options dsc_options = {0};
843
844 for (i = 0; i < count; i++) {
845 drm_connector = ¶ms[i].aconnector->base;
846
847 dc_dsc_get_default_config_option(params[i].sink->ctx->dc, &dsc_options);
848 dsc_options.max_target_bpp_limit_override_x16 = drm_connector->display_info.max_dsc_bpp * 16;
849
850 memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
851 if (vars[i + k].dsc_enabled && dc_dsc_compute_config(
852 params[i].sink->ctx->dc->res_pool->dscs[0],
853 ¶ms[i].sink->dsc_caps.dsc_dec_caps,
854 &dsc_options,
855 0,
856 params[i].timing,
857 dc_link_get_highest_encoding_format(params[i].aconnector->dc_link),
858 ¶ms[i].timing->dsc_cfg)) {
859 params[i].timing->flags.DSC = 1;
860
861 if (params[i].bpp_overwrite)
862 params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite;
863 else
864 params[i].timing->dsc_cfg.bits_per_pixel = vars[i + k].bpp_x16;
865
866 if (params[i].num_slices_h)
867 params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h;
868
869 if (params[i].num_slices_v)
870 params[i].timing->dsc_cfg.num_slices_v = params[i].num_slices_v;
871 } else {
872 params[i].timing->flags.DSC = 0;
873 }
874 params[i].timing->dsc_cfg.mst_pbn = vars[i + k].pbn;
875 }
876
877 for (i = 0; i < count; i++) {
878 if (params[i].sink) {
879 if (params[i].sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
880 params[i].sink->sink_signal != SIGNAL_TYPE_NONE)
881 DRM_DEBUG_DRIVER("MST_DSC %s i=%d dispname=%s\n", __func__, i,
882 params[i].sink->edid_caps.display_name);
883 }
884
885 DRM_DEBUG_DRIVER("MST_DSC dsc=%d bits_per_pixel=%d pbn=%d\n",
886 params[i].timing->flags.DSC,
887 params[i].timing->dsc_cfg.bits_per_pixel,
888 vars[i + k].pbn);
889 }
890 }
891
bpp_x16_from_pbn(struct dsc_mst_fairness_params param,int pbn)892 static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
893 {
894 struct dc_dsc_config dsc_config;
895 u64 kbps;
896
897 struct drm_connector *drm_connector = ¶m.aconnector->base;
898 struct dc_dsc_config_options dsc_options = {0};
899
900 dc_dsc_get_default_config_option(param.sink->ctx->dc, &dsc_options);
901 dsc_options.max_target_bpp_limit_override_x16 = drm_connector->display_info.max_dsc_bpp * 16;
902
903 kbps = div_u64((u64)pbn * 994 * 8 * 54, 64);
904 dc_dsc_compute_config(
905 param.sink->ctx->dc->res_pool->dscs[0],
906 ¶m.sink->dsc_caps.dsc_dec_caps,
907 &dsc_options,
908 (int) kbps, param.timing,
909 dc_link_get_highest_encoding_format(param.aconnector->dc_link),
910 &dsc_config);
911
912 return dsc_config.bits_per_pixel;
913 }
914
increase_dsc_bpp(struct drm_atomic_state * state,struct drm_dp_mst_topology_state * mst_state,struct dc_link * dc_link,struct dsc_mst_fairness_params * params,struct dsc_mst_fairness_vars * vars,int count,int k)915 static int increase_dsc_bpp(struct drm_atomic_state *state,
916 struct drm_dp_mst_topology_state *mst_state,
917 struct dc_link *dc_link,
918 struct dsc_mst_fairness_params *params,
919 struct dsc_mst_fairness_vars *vars,
920 int count,
921 int k)
922 {
923 int i;
924 bool bpp_increased[MAX_PIPES];
925 int initial_slack[MAX_PIPES];
926 int min_initial_slack;
927 int next_index;
928 int remaining_to_increase = 0;
929 int link_timeslots_used;
930 int fair_pbn_alloc;
931 int ret = 0;
932 uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link);
933
934 for (i = 0; i < count; i++) {
935 if (vars[i + k].dsc_enabled) {
936 initial_slack[i] =
937 kbps_to_peak_pbn(params[i].bw_range.max_kbps, fec_overhead_multiplier_x1000) - vars[i + k].pbn;
938 bpp_increased[i] = false;
939 remaining_to_increase += 1;
940 } else {
941 initial_slack[i] = 0;
942 bpp_increased[i] = true;
943 }
944 }
945
946 while (remaining_to_increase) {
947 next_index = -1;
948 min_initial_slack = -1;
949 for (i = 0; i < count; i++) {
950 if (!bpp_increased[i]) {
951 if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) {
952 min_initial_slack = initial_slack[i];
953 next_index = i;
954 }
955 }
956 }
957
958 if (next_index == -1)
959 break;
960
961 link_timeslots_used = 0;
962
963 for (i = 0; i < count; i++)
964 link_timeslots_used += DIV_ROUND_UP(vars[i + k].pbn, dfixed_trunc(mst_state->pbn_div));
965
966 fair_pbn_alloc =
967 (63 - link_timeslots_used) / remaining_to_increase * dfixed_trunc(mst_state->pbn_div);
968
969 if (initial_slack[next_index] > fair_pbn_alloc) {
970 vars[next_index].pbn += fair_pbn_alloc;
971 ret = drm_dp_atomic_find_time_slots(state,
972 params[next_index].port->mgr,
973 params[next_index].port,
974 vars[next_index].pbn);
975 if (ret < 0)
976 return ret;
977
978 ret = drm_dp_mst_atomic_check(state);
979 if (ret == 0) {
980 vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn);
981 } else {
982 vars[next_index].pbn -= fair_pbn_alloc;
983 ret = drm_dp_atomic_find_time_slots(state,
984 params[next_index].port->mgr,
985 params[next_index].port,
986 vars[next_index].pbn);
987 if (ret < 0)
988 return ret;
989 }
990 } else {
991 vars[next_index].pbn += initial_slack[next_index];
992 ret = drm_dp_atomic_find_time_slots(state,
993 params[next_index].port->mgr,
994 params[next_index].port,
995 vars[next_index].pbn);
996 if (ret < 0)
997 return ret;
998
999 ret = drm_dp_mst_atomic_check(state);
1000 if (ret == 0) {
1001 vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16;
1002 } else {
1003 vars[next_index].pbn -= initial_slack[next_index];
1004 ret = drm_dp_atomic_find_time_slots(state,
1005 params[next_index].port->mgr,
1006 params[next_index].port,
1007 vars[next_index].pbn);
1008 if (ret < 0)
1009 return ret;
1010 }
1011 }
1012
1013 bpp_increased[next_index] = true;
1014 remaining_to_increase--;
1015 }
1016 return 0;
1017 }
1018
try_disable_dsc(struct drm_atomic_state * state,struct dc_link * dc_link,struct dsc_mst_fairness_params * params,struct dsc_mst_fairness_vars * vars,int count,int k)1019 static int try_disable_dsc(struct drm_atomic_state *state,
1020 struct dc_link *dc_link,
1021 struct dsc_mst_fairness_params *params,
1022 struct dsc_mst_fairness_vars *vars,
1023 int count,
1024 int k)
1025 {
1026 int i;
1027 bool tried[MAX_PIPES];
1028 int kbps_increase[MAX_PIPES];
1029 int max_kbps_increase;
1030 int next_index;
1031 int remaining_to_try = 0;
1032 int ret;
1033 uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link);
1034 int var_pbn;
1035
1036 for (i = 0; i < count; i++) {
1037 if (vars[i + k].dsc_enabled
1038 && vars[i + k].bpp_x16 == params[i].bw_range.max_target_bpp_x16
1039 && params[i].clock_force_enable == DSC_CLK_FORCE_DEFAULT) {
1040 kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps;
1041 tried[i] = false;
1042 remaining_to_try += 1;
1043 } else {
1044 kbps_increase[i] = 0;
1045 tried[i] = true;
1046 }
1047 }
1048
1049 while (remaining_to_try) {
1050 next_index = -1;
1051 max_kbps_increase = -1;
1052 for (i = 0; i < count; i++) {
1053 if (!tried[i]) {
1054 if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) {
1055 max_kbps_increase = kbps_increase[i];
1056 next_index = i;
1057 }
1058 }
1059 }
1060
1061 if (next_index == -1)
1062 break;
1063
1064 DRM_DEBUG_DRIVER("MST_DSC index #%d, try no compression\n", next_index);
1065 var_pbn = vars[next_index].pbn;
1066 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps, fec_overhead_multiplier_x1000);
1067 ret = drm_dp_atomic_find_time_slots(state,
1068 params[next_index].port->mgr,
1069 params[next_index].port,
1070 vars[next_index].pbn);
1071 if (ret < 0) {
1072 DRM_DEBUG_DRIVER("%s:%d MST_DSC index #%d, failed to set pbn to the state, %d\n",
1073 __func__, __LINE__, next_index, ret);
1074 vars[next_index].pbn = var_pbn;
1075 return ret;
1076 }
1077
1078 ret = drm_dp_mst_atomic_check(state);
1079 if (ret == 0) {
1080 DRM_DEBUG_DRIVER("MST_DSC index #%d, greedily disable dsc\n", next_index);
1081 vars[next_index].dsc_enabled = false;
1082 vars[next_index].bpp_x16 = 0;
1083 } else {
1084 DRM_DEBUG_DRIVER("MST_DSC index #%d, restore optimized pbn value\n", next_index);
1085 vars[next_index].pbn = var_pbn;
1086 ret = drm_dp_atomic_find_time_slots(state,
1087 params[next_index].port->mgr,
1088 params[next_index].port,
1089 vars[next_index].pbn);
1090 if (ret < 0) {
1091 DRM_DEBUG_DRIVER("%s:%d MST_DSC index #%d, failed to set pbn to the state, %d\n",
1092 __func__, __LINE__, next_index, ret);
1093 return ret;
1094 }
1095 }
1096
1097 tried[next_index] = true;
1098 remaining_to_try--;
1099 }
1100 return 0;
1101 }
1102
log_dsc_params(int count,struct dsc_mst_fairness_vars * vars,int k)1103 static void log_dsc_params(int count, struct dsc_mst_fairness_vars *vars, int k)
1104 {
1105 int i;
1106
1107 for (i = 0; i < count; i++)
1108 DRM_DEBUG_DRIVER("MST_DSC DSC params: stream #%d --- dsc_enabled = %d, bpp_x16 = %d, pbn = %d\n",
1109 i, vars[i + k].dsc_enabled, vars[i + k].bpp_x16, vars[i + k].pbn);
1110 }
1111
compute_mst_dsc_configs_for_link(struct drm_atomic_state * state,struct dc_state * dc_state,struct dc_link * dc_link,struct dsc_mst_fairness_vars * vars,struct drm_dp_mst_topology_mgr * mgr,int * link_vars_start_index)1112 static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
1113 struct dc_state *dc_state,
1114 struct dc_link *dc_link,
1115 struct dsc_mst_fairness_vars *vars,
1116 struct drm_dp_mst_topology_mgr *mgr,
1117 int *link_vars_start_index)
1118 {
1119 struct dc_stream_state *stream;
1120 struct dsc_mst_fairness_params params[MAX_PIPES];
1121 struct amdgpu_dm_connector *aconnector;
1122 struct drm_dp_mst_topology_state *mst_state = drm_atomic_get_mst_topology_state(state, mgr);
1123 int count = 0;
1124 int i, k, ret;
1125 bool debugfs_overwrite = false;
1126 uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link);
1127 struct drm_connector_state *new_conn_state;
1128
1129 memset(params, 0, sizeof(params));
1130
1131 if (IS_ERR(mst_state))
1132 return PTR_ERR(mst_state);
1133
1134 /* Set up params */
1135 DRM_DEBUG_DRIVER("%s: MST_DSC Try to set up params from %d streams\n", __func__, dc_state->stream_count);
1136 for (i = 0; i < dc_state->stream_count; i++) {
1137 struct dc_dsc_policy dsc_policy = {0};
1138
1139 stream = dc_state->streams[i];
1140
1141 if (stream->link != dc_link)
1142 continue;
1143
1144 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1145 if (!aconnector)
1146 continue;
1147
1148 if (!aconnector->mst_output_port)
1149 continue;
1150
1151 new_conn_state = drm_atomic_get_new_connector_state(state, &aconnector->base);
1152
1153 if (!new_conn_state) {
1154 DRM_DEBUG_DRIVER("%s:%d MST_DSC Skip the stream 0x%p with invalid new_conn_state\n",
1155 __func__, __LINE__, stream);
1156 continue;
1157 }
1158
1159 stream->timing.flags.DSC = 0;
1160
1161 params[count].timing = &stream->timing;
1162 params[count].sink = stream->sink;
1163 params[count].aconnector = aconnector;
1164 params[count].port = aconnector->mst_output_port;
1165 params[count].clock_force_enable = aconnector->dsc_settings.dsc_force_enable;
1166 if (params[count].clock_force_enable == DSC_CLK_FORCE_ENABLE)
1167 debugfs_overwrite = true;
1168 params[count].num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
1169 params[count].num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
1170 params[count].bpp_overwrite = aconnector->dsc_settings.dsc_bits_per_pixel;
1171 params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported;
1172 dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy, dc_link_get_highest_encoding_format(stream->link));
1173 if (!dc_dsc_compute_bandwidth_range(
1174 stream->sink->ctx->dc->res_pool->dscs[0],
1175 stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
1176 dsc_policy.min_target_bpp * 16,
1177 dsc_policy.max_target_bpp * 16,
1178 &stream->sink->dsc_caps.dsc_dec_caps,
1179 &stream->timing,
1180 dc_link_get_highest_encoding_format(dc_link),
1181 ¶ms[count].bw_range))
1182 params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing,
1183 dc_link_get_highest_encoding_format(dc_link));
1184
1185 DRM_DEBUG_DRIVER("MST_DSC #%d stream 0x%p - max_kbps = %u, min_kbps = %u, uncompressed_kbps = %u\n",
1186 count, stream, params[count].bw_range.max_kbps, params[count].bw_range.min_kbps,
1187 params[count].bw_range.stream_kbps);
1188 count++;
1189 }
1190
1191 DRM_DEBUG_DRIVER("%s: MST_DSC Params set up for %d streams\n", __func__, count);
1192
1193 if (count == 0) {
1194 ASSERT(0);
1195 return 0;
1196 }
1197
1198 /* k is start index of vars for current phy link used by mst hub */
1199 k = *link_vars_start_index;
1200 /* set vars start index for next mst hub phy link */
1201 *link_vars_start_index += count;
1202
1203 /* Try no compression */
1204 DRM_DEBUG_DRIVER("MST_DSC Try no compression\n");
1205 for (i = 0; i < count; i++) {
1206 vars[i + k].aconnector = params[i].aconnector;
1207 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps, fec_overhead_multiplier_x1000);
1208 vars[i + k].dsc_enabled = false;
1209 vars[i + k].bpp_x16 = 0;
1210 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, params[i].port,
1211 vars[i + k].pbn);
1212 if (ret < 0)
1213 return ret;
1214 }
1215 ret = drm_dp_mst_atomic_check(state);
1216 if (ret == 0 && !debugfs_overwrite) {
1217 set_dsc_configs_from_fairness_vars(params, vars, count, k);
1218 return 0;
1219 } else if (ret != -ENOSPC) {
1220 return ret;
1221 }
1222
1223 log_dsc_params(count, vars, k);
1224
1225 /* Try max compression */
1226 DRM_DEBUG_DRIVER("MST_DSC Try max compression\n");
1227 for (i = 0; i < count; i++) {
1228 if (params[i].compression_possible && params[i].clock_force_enable != DSC_CLK_FORCE_DISABLE) {
1229 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps, fec_overhead_multiplier_x1000);
1230 vars[i + k].dsc_enabled = true;
1231 vars[i + k].bpp_x16 = params[i].bw_range.min_target_bpp_x16;
1232 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr,
1233 params[i].port, vars[i + k].pbn);
1234 if (ret < 0)
1235 return ret;
1236 } else {
1237 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps, fec_overhead_multiplier_x1000);
1238 vars[i + k].dsc_enabled = false;
1239 vars[i + k].bpp_x16 = 0;
1240 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr,
1241 params[i].port, vars[i + k].pbn);
1242 if (ret < 0)
1243 return ret;
1244 }
1245 }
1246 ret = drm_dp_mst_atomic_check(state);
1247 if (ret != 0)
1248 return ret;
1249
1250 log_dsc_params(count, vars, k);
1251
1252 /* Optimize degree of compression */
1253 DRM_DEBUG_DRIVER("MST_DSC Try optimize compression\n");
1254 ret = increase_dsc_bpp(state, mst_state, dc_link, params, vars, count, k);
1255 if (ret < 0) {
1256 DRM_DEBUG_DRIVER("MST_DSC Failed to optimize compression\n");
1257 return ret;
1258 }
1259
1260 log_dsc_params(count, vars, k);
1261
1262 DRM_DEBUG_DRIVER("MST_DSC Try disable compression\n");
1263 ret = try_disable_dsc(state, dc_link, params, vars, count, k);
1264 if (ret < 0) {
1265 DRM_DEBUG_DRIVER("MST_DSC Failed to disable compression\n");
1266 return ret;
1267 }
1268
1269 log_dsc_params(count, vars, k);
1270
1271 set_dsc_configs_from_fairness_vars(params, vars, count, k);
1272
1273 return 0;
1274 }
1275
is_dsc_need_re_compute(struct drm_atomic_state * state,struct dc_state * dc_state,struct dc_link * dc_link)1276 static bool is_dsc_need_re_compute(
1277 struct drm_atomic_state *state,
1278 struct dc_state *dc_state,
1279 struct dc_link *dc_link)
1280 {
1281 int i, j;
1282 bool is_dsc_need_re_compute = false;
1283 struct amdgpu_dm_connector *stream_on_link[MAX_PIPES];
1284 int new_stream_on_link_num = 0;
1285 struct amdgpu_dm_connector *aconnector;
1286 struct dc_stream_state *stream;
1287 const struct dc *dc = dc_link->dc;
1288
1289 /* only check phy used by dsc mst branch */
1290 if (dc_link->type != dc_connection_mst_branch)
1291 goto out;
1292
1293 /* add a check for older MST DSC with no virtual DPCDs */
1294 if (needs_dsc_aux_workaround(dc_link) &&
1295 (!(dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT ||
1296 dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT)))
1297 goto out;
1298
1299 for (i = 0; i < MAX_PIPES; i++)
1300 stream_on_link[i] = NULL;
1301
1302 DRM_DEBUG_DRIVER("%s: MST_DSC check on %d streams in new dc_state\n", __func__, dc_state->stream_count);
1303
1304 /* check if there is mode change in new request */
1305 for (i = 0; i < dc_state->stream_count; i++) {
1306 struct drm_crtc_state *new_crtc_state;
1307 struct drm_connector_state *new_conn_state;
1308
1309 stream = dc_state->streams[i];
1310 if (!stream)
1311 continue;
1312
1313 DRM_DEBUG_DRIVER("%s:%d MST_DSC checking #%d stream 0x%p\n", __func__, __LINE__, i, stream);
1314
1315 /* check if stream using the same link for mst */
1316 if (stream->link != dc_link)
1317 continue;
1318
1319 aconnector = (struct amdgpu_dm_connector *) stream->dm_stream_context;
1320 if (!aconnector)
1321 continue;
1322
1323 stream_on_link[new_stream_on_link_num] = aconnector;
1324 new_stream_on_link_num++;
1325
1326 new_conn_state = drm_atomic_get_new_connector_state(state, &aconnector->base);
1327 if (!new_conn_state) {
1328 DRM_DEBUG_DRIVER("%s:%d MST_DSC no new_conn_state for stream 0x%p, aconnector 0x%p\n",
1329 __func__, __LINE__, stream, aconnector);
1330 continue;
1331 }
1332
1333 if (IS_ERR(new_conn_state))
1334 continue;
1335
1336 if (!new_conn_state->crtc)
1337 continue;
1338
1339 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
1340 if (!new_crtc_state) {
1341 DRM_DEBUG_DRIVER("%s:%d MST_DSC no new_crtc_state for crtc of stream 0x%p, aconnector 0x%p\n",
1342 __func__, __LINE__, stream, aconnector);
1343 continue;
1344 }
1345
1346 if (IS_ERR(new_crtc_state))
1347 continue;
1348
1349 if (new_crtc_state->enable && new_crtc_state->active) {
1350 if (new_crtc_state->mode_changed || new_crtc_state->active_changed ||
1351 new_crtc_state->connectors_changed) {
1352 DRM_DEBUG_DRIVER("%s:%d MST_DSC dsc recompute required."
1353 "stream 0x%p in new dc_state\n",
1354 __func__, __LINE__, stream);
1355 is_dsc_need_re_compute = true;
1356 goto out;
1357 }
1358 }
1359 }
1360
1361 if (new_stream_on_link_num == 0) {
1362 DRM_DEBUG_DRIVER("%s:%d MST_DSC no mode change request for streams in new dc_state\n",
1363 __func__, __LINE__);
1364 is_dsc_need_re_compute = false;
1365 goto out;
1366 }
1367
1368 DRM_DEBUG_DRIVER("%s: MST_DSC check on %d streams in current dc_state\n",
1369 __func__, dc->current_state->stream_count);
1370
1371 /* check current_state if there stream on link but it is not in
1372 * new request state
1373 */
1374 for (i = 0; i < dc->current_state->stream_count; i++) {
1375 stream = dc->current_state->streams[i];
1376 /* only check stream on the mst hub */
1377 if (stream->link != dc_link)
1378 continue;
1379
1380 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1381 if (!aconnector)
1382 continue;
1383
1384 for (j = 0; j < new_stream_on_link_num; j++) {
1385 if (stream_on_link[j]) {
1386 if (aconnector == stream_on_link[j])
1387 break;
1388 }
1389 }
1390
1391 if (j == new_stream_on_link_num) {
1392 /* not in new state */
1393 DRM_DEBUG_DRIVER("%s:%d MST_DSC dsc recompute required."
1394 "stream 0x%p in current dc_state but not in new dc_state\n",
1395 __func__, __LINE__, stream);
1396 is_dsc_need_re_compute = true;
1397 break;
1398 }
1399 }
1400
1401 out:
1402 DRM_DEBUG_DRIVER("%s: MST_DSC dsc recompute %s\n",
1403 __func__, is_dsc_need_re_compute ? "required" : "not required");
1404
1405 return is_dsc_need_re_compute;
1406 }
1407
compute_mst_dsc_configs_for_state(struct drm_atomic_state * state,struct dc_state * dc_state,struct dsc_mst_fairness_vars * vars)1408 int compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
1409 struct dc_state *dc_state,
1410 struct dsc_mst_fairness_vars *vars)
1411 {
1412 int i, j;
1413 struct dc_stream_state *stream;
1414 bool computed_streams[MAX_PIPES];
1415 struct amdgpu_dm_connector *aconnector;
1416 struct drm_dp_mst_topology_mgr *mst_mgr;
1417 struct resource_pool *res_pool;
1418 int link_vars_start_index = 0;
1419 int ret = 0;
1420
1421 for (i = 0; i < dc_state->stream_count; i++)
1422 computed_streams[i] = false;
1423
1424 for (i = 0; i < dc_state->stream_count; i++) {
1425 stream = dc_state->streams[i];
1426 res_pool = stream->ctx->dc->res_pool;
1427
1428 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
1429 continue;
1430
1431 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1432
1433 DRM_DEBUG_DRIVER("%s: MST_DSC compute mst dsc configs for stream 0x%p, aconnector 0x%p\n",
1434 __func__, stream, aconnector);
1435
1436 if (!aconnector || !aconnector->dc_sink || !aconnector->mst_output_port)
1437 continue;
1438
1439 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
1440 continue;
1441
1442 if (computed_streams[i])
1443 continue;
1444
1445 if (res_pool->funcs->remove_stream_from_ctx &&
1446 res_pool->funcs->remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK)
1447 return -EINVAL;
1448
1449 if (!is_dsc_need_re_compute(state, dc_state, stream->link))
1450 continue;
1451
1452 mst_mgr = aconnector->mst_output_port->mgr;
1453 ret = compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars, mst_mgr,
1454 &link_vars_start_index);
1455 if (ret != 0)
1456 return ret;
1457
1458 for (j = 0; j < dc_state->stream_count; j++) {
1459 if (dc_state->streams[j]->link == stream->link)
1460 computed_streams[j] = true;
1461 }
1462 }
1463
1464 for (i = 0; i < dc_state->stream_count; i++) {
1465 stream = dc_state->streams[i];
1466
1467 if (stream->timing.flags.DSC == 1)
1468 if (dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream) != DC_OK) {
1469 DRM_DEBUG_DRIVER("%s:%d MST_DSC Failed to request dsc hw resource for stream 0x%p\n",
1470 __func__, __LINE__, stream);
1471 return -EINVAL;
1472 }
1473 }
1474
1475 return ret;
1476 }
1477
pre_compute_mst_dsc_configs_for_state(struct drm_atomic_state * state,struct dc_state * dc_state,struct dsc_mst_fairness_vars * vars)1478 static int pre_compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
1479 struct dc_state *dc_state,
1480 struct dsc_mst_fairness_vars *vars)
1481 {
1482 int i, j;
1483 struct dc_stream_state *stream;
1484 bool computed_streams[MAX_PIPES];
1485 struct amdgpu_dm_connector *aconnector;
1486 struct drm_dp_mst_topology_mgr *mst_mgr;
1487 int link_vars_start_index = 0;
1488 int ret = 0;
1489
1490 for (i = 0; i < dc_state->stream_count; i++)
1491 computed_streams[i] = false;
1492
1493 for (i = 0; i < dc_state->stream_count; i++) {
1494 stream = dc_state->streams[i];
1495
1496 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
1497 continue;
1498
1499 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1500
1501 DRM_DEBUG_DRIVER("MST_DSC pre compute mst dsc configs for #%d stream 0x%p, aconnector 0x%p\n",
1502 i, stream, aconnector);
1503
1504 if (!aconnector || !aconnector->dc_sink || !aconnector->mst_output_port)
1505 continue;
1506
1507 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
1508 continue;
1509
1510 if (computed_streams[i])
1511 continue;
1512
1513 if (!is_dsc_need_re_compute(state, dc_state, stream->link))
1514 continue;
1515
1516 mst_mgr = aconnector->mst_output_port->mgr;
1517 ret = compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars, mst_mgr,
1518 &link_vars_start_index);
1519 if (ret != 0)
1520 return ret;
1521
1522 for (j = 0; j < dc_state->stream_count; j++) {
1523 if (dc_state->streams[j]->link == stream->link)
1524 computed_streams[j] = true;
1525 }
1526 }
1527
1528 return ret;
1529 }
1530
find_crtc_index_in_state_by_stream(struct drm_atomic_state * state,struct dc_stream_state * stream)1531 static int find_crtc_index_in_state_by_stream(struct drm_atomic_state *state,
1532 struct dc_stream_state *stream)
1533 {
1534 int i;
1535 struct drm_crtc *crtc;
1536 struct drm_crtc_state *new_state, *old_state;
1537
1538 for_each_oldnew_crtc_in_state(state, crtc, old_state, new_state, i) {
1539 struct dm_crtc_state *dm_state = to_dm_crtc_state(new_state);
1540
1541 if (dm_state->stream == stream)
1542 return i;
1543 }
1544 return -1;
1545 }
1546
is_link_to_dschub(struct dc_link * dc_link)1547 static bool is_link_to_dschub(struct dc_link *dc_link)
1548 {
1549 union dpcd_dsc_basic_capabilities *dsc_caps =
1550 &dc_link->dpcd_caps.dsc_caps.dsc_basic_caps;
1551
1552 /* only check phy used by dsc mst branch */
1553 if (dc_link->type != dc_connection_mst_branch)
1554 return false;
1555
1556 if (!(dsc_caps->fields.dsc_support.DSC_SUPPORT ||
1557 dsc_caps->fields.dsc_support.DSC_PASSTHROUGH_SUPPORT))
1558 return false;
1559 return true;
1560 }
1561
is_dsc_precompute_needed(struct drm_atomic_state * state)1562 static bool is_dsc_precompute_needed(struct drm_atomic_state *state)
1563 {
1564 int i;
1565 struct drm_crtc *crtc;
1566 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
1567 bool ret = false;
1568
1569 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1570 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(new_crtc_state);
1571
1572 if (!amdgpu_dm_find_first_crtc_matching_connector(state, crtc)) {
1573 ret = false;
1574 break;
1575 }
1576 if (dm_crtc_state->stream && dm_crtc_state->stream->link)
1577 if (is_link_to_dschub(dm_crtc_state->stream->link))
1578 ret = true;
1579 }
1580 return ret;
1581 }
1582
pre_validate_dsc(struct drm_atomic_state * state,struct dm_atomic_state ** dm_state_ptr,struct dsc_mst_fairness_vars * vars)1583 int pre_validate_dsc(struct drm_atomic_state *state,
1584 struct dm_atomic_state **dm_state_ptr,
1585 struct dsc_mst_fairness_vars *vars)
1586 {
1587 int i;
1588 struct dm_atomic_state *dm_state;
1589 struct dc_state *local_dc_state = NULL;
1590 int ret = 0;
1591
1592 if (!is_dsc_precompute_needed(state)) {
1593 DRM_INFO_ONCE("%s:%d MST_DSC dsc precompute is not needed\n", __func__, __LINE__);
1594 return 0;
1595 }
1596 ret = dm_atomic_get_state(state, dm_state_ptr);
1597 if (ret != 0) {
1598 DRM_INFO_ONCE("%s:%d MST_DSC dm_atomic_get_state() failed\n", __func__, __LINE__);
1599 return ret;
1600 }
1601 dm_state = *dm_state_ptr;
1602
1603 /*
1604 * create local vailable for dc_state. copy content of streams of dm_state->context
1605 * to local variable. make sure stream pointer of local variable not the same as stream
1606 * from dm_state->context.
1607 */
1608
1609 local_dc_state = vmalloc(sizeof(struct dc_state));
1610 if (!local_dc_state)
1611 return -ENOMEM;
1612 memcpy(local_dc_state, dm_state->context, sizeof(struct dc_state));
1613
1614 for (i = 0; i < local_dc_state->stream_count; i++) {
1615 struct dc_stream_state *stream = dm_state->context->streams[i];
1616 int ind = find_crtc_index_in_state_by_stream(state, stream);
1617
1618 if (ind >= 0) {
1619 struct drm_connector *connector;
1620 struct amdgpu_dm_connector *aconnector;
1621 struct drm_connector_state *drm_new_conn_state;
1622 struct dm_connector_state *dm_new_conn_state;
1623 struct dm_crtc_state *dm_old_crtc_state;
1624
1625 connector =
1626 amdgpu_dm_find_first_crtc_matching_connector(state,
1627 state->crtcs[ind].ptr);
1628 aconnector = to_amdgpu_dm_connector(connector);
1629 drm_new_conn_state =
1630 drm_atomic_get_new_connector_state(state,
1631 &aconnector->base);
1632 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
1633 dm_old_crtc_state = to_dm_crtc_state(state->crtcs[ind].old_state);
1634
1635 local_dc_state->streams[i] =
1636 create_validate_stream_for_sink(aconnector,
1637 &state->crtcs[ind].new_state->mode,
1638 dm_new_conn_state,
1639 dm_old_crtc_state->stream);
1640 if (local_dc_state->streams[i] == NULL) {
1641 ret = -EINVAL;
1642 break;
1643 }
1644 }
1645 }
1646
1647 if (ret != 0)
1648 goto clean_exit;
1649
1650 ret = pre_compute_mst_dsc_configs_for_state(state, local_dc_state, vars);
1651 if (ret != 0) {
1652 DRM_INFO_ONCE("%s:%d MST_DSC dsc pre_compute_mst_dsc_configs_for_state() failed\n",
1653 __func__, __LINE__);
1654 ret = -EINVAL;
1655 goto clean_exit;
1656 }
1657
1658 /*
1659 * compare local_streams -> timing with dm_state->context,
1660 * if the same set crtc_state->mode-change = 0;
1661 */
1662 for (i = 0; i < local_dc_state->stream_count; i++) {
1663 struct dc_stream_state *stream = dm_state->context->streams[i];
1664
1665 if (local_dc_state->streams[i] &&
1666 dc_is_timing_changed(stream, local_dc_state->streams[i])) {
1667 DRM_INFO_ONCE("%s:%d MST_DSC crtc[%d] needs mode_change\n", __func__, __LINE__, i);
1668 } else {
1669 int ind = find_crtc_index_in_state_by_stream(state, stream);
1670
1671 if (ind >= 0) {
1672 DRM_INFO_ONCE("%s:%d MST_DSC no mode changed for stream 0x%p\n",
1673 __func__, __LINE__, stream);
1674 state->crtcs[ind].new_state->mode_changed = 0;
1675 }
1676 }
1677 }
1678 clean_exit:
1679 for (i = 0; i < local_dc_state->stream_count; i++) {
1680 struct dc_stream_state *stream = dm_state->context->streams[i];
1681
1682 if (local_dc_state->streams[i] != stream)
1683 dc_stream_release(local_dc_state->streams[i]);
1684 }
1685
1686 vfree(local_dc_state);
1687
1688 return ret;
1689 }
1690
kbps_from_pbn(unsigned int pbn)1691 static unsigned int kbps_from_pbn(unsigned int pbn)
1692 {
1693 unsigned int kbps = pbn;
1694
1695 kbps *= (1000000 / PEAK_FACTOR_X1000);
1696 kbps *= 8;
1697 kbps *= 54;
1698 kbps /= 64;
1699
1700 return kbps;
1701 }
1702
is_dsc_common_config_possible(struct dc_stream_state * stream,struct dc_dsc_bw_range * bw_range)1703 static bool is_dsc_common_config_possible(struct dc_stream_state *stream,
1704 struct dc_dsc_bw_range *bw_range)
1705 {
1706 struct dc_dsc_policy dsc_policy = {0};
1707
1708 dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy, dc_link_get_highest_encoding_format(stream->link));
1709 dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc->res_pool->dscs[0],
1710 stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
1711 dsc_policy.min_target_bpp * 16,
1712 dsc_policy.max_target_bpp * 16,
1713 &stream->sink->dsc_caps.dsc_dec_caps,
1714 &stream->timing, dc_link_get_highest_encoding_format(stream->link), bw_range);
1715
1716 return bw_range->max_target_bpp_x16 && bw_range->min_target_bpp_x16;
1717 }
1718 #endif
1719
1720 #if defined(CONFIG_DRM_AMD_DC_FP)
dp_get_link_current_set_bw(struct drm_dp_aux * aux,uint32_t * cur_link_bw)1721 static bool dp_get_link_current_set_bw(struct drm_dp_aux *aux, uint32_t *cur_link_bw)
1722 {
1723 uint32_t total_data_bw_efficiency_x10000 = 0;
1724 uint32_t link_rate_per_lane_kbps = 0;
1725 enum dc_link_rate link_rate;
1726 union lane_count_set lane_count;
1727 u8 dp_link_encoding;
1728 u8 link_bw_set = 0;
1729
1730 *cur_link_bw = 0;
1731
1732 if (drm_dp_dpcd_read(aux, DP_MAIN_LINK_CHANNEL_CODING_SET, &dp_link_encoding, 1) != 1 ||
1733 drm_dp_dpcd_read(aux, DP_LANE_COUNT_SET, &lane_count.raw, 1) != 1 ||
1734 drm_dp_dpcd_read(aux, DP_LINK_BW_SET, &link_bw_set, 1) != 1)
1735 return false;
1736
1737 switch (dp_link_encoding) {
1738 case DP_8b_10b_ENCODING:
1739 link_rate = link_bw_set;
1740 link_rate_per_lane_kbps = link_rate * LINK_RATE_REF_FREQ_IN_KHZ * BITS_PER_DP_BYTE;
1741 total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_8b_10b_x10000;
1742 total_data_bw_efficiency_x10000 /= 100;
1743 total_data_bw_efficiency_x10000 *= DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100;
1744 break;
1745 case DP_128b_132b_ENCODING:
1746 switch (link_bw_set) {
1747 case DP_LINK_BW_10:
1748 link_rate = LINK_RATE_UHBR10;
1749 break;
1750 case DP_LINK_BW_13_5:
1751 link_rate = LINK_RATE_UHBR13_5;
1752 break;
1753 case DP_LINK_BW_20:
1754 link_rate = LINK_RATE_UHBR20;
1755 break;
1756 default:
1757 return false;
1758 }
1759
1760 link_rate_per_lane_kbps = link_rate * 10000;
1761 total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_128b_132b_x10000;
1762 break;
1763 default:
1764 return false;
1765 }
1766
1767 *cur_link_bw = link_rate_per_lane_kbps * lane_count.bits.LANE_COUNT_SET / 10000 * total_data_bw_efficiency_x10000;
1768 return true;
1769 }
1770 #endif
1771
dm_dp_mst_is_port_support_mode(struct amdgpu_dm_connector * aconnector,struct dc_stream_state * stream)1772 enum dc_status dm_dp_mst_is_port_support_mode(
1773 struct amdgpu_dm_connector *aconnector,
1774 struct dc_stream_state *stream)
1775 {
1776 #if defined(CONFIG_DRM_AMD_DC_FP)
1777 int branch_max_throughput_mps = 0;
1778 struct dc_link_settings cur_link_settings;
1779 uint32_t end_to_end_bw_in_kbps = 0;
1780 uint32_t root_link_bw_in_kbps = 0;
1781 uint32_t virtual_channel_bw_in_kbps = 0;
1782 struct dc_dsc_bw_range bw_range = {0};
1783 struct dc_dsc_config_options dsc_options = {0};
1784 uint32_t stream_kbps;
1785
1786 /* DSC unnecessary case
1787 * Check if timing could be supported within end-to-end BW
1788 */
1789 stream_kbps =
1790 dc_bandwidth_in_kbps_from_timing(&stream->timing,
1791 dc_link_get_highest_encoding_format(stream->link));
1792 cur_link_settings = stream->link->verified_link_cap;
1793 root_link_bw_in_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, &cur_link_settings);
1794 virtual_channel_bw_in_kbps = kbps_from_pbn(aconnector->mst_output_port->full_pbn);
1795
1796 /* pick the end to end bw bottleneck */
1797 end_to_end_bw_in_kbps = min(root_link_bw_in_kbps, virtual_channel_bw_in_kbps);
1798
1799 if (stream_kbps <= end_to_end_bw_in_kbps) {
1800 DRM_DEBUG_DRIVER("MST_DSC no dsc required. End-to-end bw sufficient\n");
1801 return DC_OK;
1802 }
1803
1804 /*DSC necessary case*/
1805 if (!aconnector->dsc_aux)
1806 return DC_FAIL_BANDWIDTH_VALIDATE;
1807
1808 if (is_dsc_common_config_possible(stream, &bw_range)) {
1809
1810 /*capable of dsc passthough. dsc bitstream along the entire path*/
1811 if (aconnector->mst_output_port->passthrough_aux) {
1812 if (bw_range.min_kbps > end_to_end_bw_in_kbps) {
1813 DRM_DEBUG_DRIVER("MST_DSC dsc passthrough and decode at endpoint"
1814 "Max dsc compression bw can't fit into end-to-end bw\n");
1815 return DC_FAIL_BANDWIDTH_VALIDATE;
1816 }
1817 } else {
1818 /*dsc bitstream decoded at the dp last link*/
1819 struct drm_dp_mst_port *immediate_upstream_port = NULL;
1820 uint32_t end_link_bw = 0;
1821
1822 /*Get last DP link BW capability*/
1823 if (dp_get_link_current_set_bw(&aconnector->mst_output_port->aux, &end_link_bw)) {
1824 if (stream_kbps > end_link_bw) {
1825 DRM_DEBUG_DRIVER("MST_DSC dsc decode at last link."
1826 "Mode required bw can't fit into last link\n");
1827 return DC_FAIL_BANDWIDTH_VALIDATE;
1828 }
1829 }
1830
1831 /*Get virtual channel bandwidth between source and the link before the last link*/
1832 if (aconnector->mst_output_port->parent->port_parent)
1833 immediate_upstream_port = aconnector->mst_output_port->parent->port_parent;
1834
1835 if (immediate_upstream_port) {
1836 virtual_channel_bw_in_kbps = kbps_from_pbn(immediate_upstream_port->full_pbn);
1837 virtual_channel_bw_in_kbps = min(root_link_bw_in_kbps, virtual_channel_bw_in_kbps);
1838 if (bw_range.min_kbps > virtual_channel_bw_in_kbps) {
1839 DRM_DEBUG_DRIVER("MST_DSC dsc decode at last link."
1840 "Max dsc compression can't fit into MST available bw\n");
1841 return DC_FAIL_BANDWIDTH_VALIDATE;
1842 }
1843 }
1844 }
1845
1846 /*Confirm if we can obtain dsc config*/
1847 dc_dsc_get_default_config_option(stream->link->dc, &dsc_options);
1848 dsc_options.max_target_bpp_limit_override_x16 = aconnector->base.display_info.max_dsc_bpp * 16;
1849 if (dc_dsc_compute_config(stream->sink->ctx->dc->res_pool->dscs[0],
1850 &stream->sink->dsc_caps.dsc_dec_caps,
1851 &dsc_options,
1852 end_to_end_bw_in_kbps,
1853 &stream->timing,
1854 dc_link_get_highest_encoding_format(stream->link),
1855 &stream->timing.dsc_cfg)) {
1856 stream->timing.flags.DSC = 1;
1857 DRM_DEBUG_DRIVER("MST_DSC require dsc and dsc config found\n");
1858 } else {
1859 DRM_DEBUG_DRIVER("MST_DSC require dsc but can't find appropriate dsc config\n");
1860 return DC_FAIL_BANDWIDTH_VALIDATE;
1861 }
1862
1863 /* check is mst dsc output bandwidth branch_overall_throughput_0_mps */
1864 switch (stream->timing.pixel_encoding) {
1865 case PIXEL_ENCODING_RGB:
1866 case PIXEL_ENCODING_YCBCR444:
1867 branch_max_throughput_mps =
1868 aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_0_mps;
1869 break;
1870 case PIXEL_ENCODING_YCBCR422:
1871 case PIXEL_ENCODING_YCBCR420:
1872 branch_max_throughput_mps =
1873 aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_1_mps;
1874 break;
1875 default:
1876 break;
1877 }
1878
1879 if (branch_max_throughput_mps != 0 &&
1880 ((stream->timing.pix_clk_100hz / 10) > branch_max_throughput_mps * 1000)) {
1881 DRM_DEBUG_DRIVER("MST_DSC require dsc but max throughput mps fails\n");
1882 return DC_FAIL_BANDWIDTH_VALIDATE;
1883 }
1884 } else {
1885 DRM_DEBUG_DRIVER("MST_DSC require dsc but can't find common dsc config\n");
1886 return DC_FAIL_BANDWIDTH_VALIDATE;
1887 }
1888 #endif
1889 return DC_OK;
1890 }
1891