1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ADC driver for the Ingenic JZ47xx SoCs 4 * Copyright (c) 2019 Artur Rojek <contact@artur-rojek.eu> 5 * 6 * based on drivers/mfd/jz4740-adc.c 7 */ 8 9 #include <dt-bindings/iio/adc/ingenic,adc.h> 10 11 #include <linux/cleanup.h> 12 #include <linux/clk.h> 13 #include <linux/iio/buffer.h> 14 #include <linux/iio/iio.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/iopoll.h> 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/mod_devicetable.h> 21 #include <linux/mutex.h> 22 #include <linux/of.h> 23 #include <linux/platform_device.h> 24 #include <linux/property.h> 25 26 #define JZ_ADC_REG_ENABLE 0x00 27 #define JZ_ADC_REG_CFG 0x04 28 #define JZ_ADC_REG_CTRL 0x08 29 #define JZ_ADC_REG_STATUS 0x0c 30 #define JZ_ADC_REG_ADSAME 0x10 31 #define JZ_ADC_REG_ADWAIT 0x14 32 #define JZ_ADC_REG_ADTCH 0x18 33 #define JZ_ADC_REG_ADBDAT 0x1c 34 #define JZ_ADC_REG_ADSDAT 0x20 35 #define JZ_ADC_REG_ADCMD 0x24 36 #define JZ_ADC_REG_ADCLK 0x28 37 38 #define JZ_ADC_REG_ENABLE_PD BIT(7) 39 #define JZ_ADC_REG_CFG_AUX_MD (BIT(0) | BIT(1)) 40 #define JZ_ADC_REG_CFG_BAT_MD BIT(4) 41 #define JZ_ADC_REG_CFG_SAMPLE_NUM(n) ((n) << 10) 42 #define JZ_ADC_REG_CFG_PULL_UP(n) ((n) << 16) 43 #define JZ_ADC_REG_CFG_CMD_SEL BIT(22) 44 #define JZ_ADC_REG_CFG_VBAT_SEL BIT(30) 45 #define JZ_ADC_REG_CFG_TOUCH_OPS_MASK (BIT(31) | GENMASK(23, 10)) 46 #define JZ_ADC_REG_ADCLK_CLKDIV_LSB 0 47 #define JZ4725B_ADC_REG_ADCLK_CLKDIV10US_LSB 16 48 #define JZ4770_ADC_REG_ADCLK_CLKDIV10US_LSB 8 49 #define JZ4770_ADC_REG_ADCLK_CLKDIVMS_LSB 16 50 51 #define JZ_ADC_REG_ADCMD_YNADC BIT(7) 52 #define JZ_ADC_REG_ADCMD_YPADC BIT(8) 53 #define JZ_ADC_REG_ADCMD_XNADC BIT(9) 54 #define JZ_ADC_REG_ADCMD_XPADC BIT(10) 55 #define JZ_ADC_REG_ADCMD_VREFPYP BIT(11) 56 #define JZ_ADC_REG_ADCMD_VREFPXP BIT(12) 57 #define JZ_ADC_REG_ADCMD_VREFPXN BIT(13) 58 #define JZ_ADC_REG_ADCMD_VREFPAUX BIT(14) 59 #define JZ_ADC_REG_ADCMD_VREFPVDD33 BIT(15) 60 #define JZ_ADC_REG_ADCMD_VREFNYN BIT(16) 61 #define JZ_ADC_REG_ADCMD_VREFNXP BIT(17) 62 #define JZ_ADC_REG_ADCMD_VREFNXN BIT(18) 63 #define JZ_ADC_REG_ADCMD_VREFAUX BIT(19) 64 #define JZ_ADC_REG_ADCMD_YNGRU BIT(20) 65 #define JZ_ADC_REG_ADCMD_XNGRU BIT(21) 66 #define JZ_ADC_REG_ADCMD_XPGRU BIT(22) 67 #define JZ_ADC_REG_ADCMD_YPSUP BIT(23) 68 #define JZ_ADC_REG_ADCMD_XNSUP BIT(24) 69 #define JZ_ADC_REG_ADCMD_XPSUP BIT(25) 70 71 #define JZ_ADC_AUX_VREF 3300 72 #define JZ_ADC_AUX_VREF_BITS 12 73 #define JZ_ADC_BATTERY_LOW_VREF 2500 74 #define JZ_ADC_BATTERY_LOW_VREF_BITS 12 75 #define JZ4725B_ADC_BATTERY_HIGH_VREF 7500 76 #define JZ4725B_ADC_BATTERY_HIGH_VREF_BITS 10 77 #define JZ4740_ADC_BATTERY_HIGH_VREF (7500 * 0.986) 78 #define JZ4740_ADC_BATTERY_HIGH_VREF_BITS 12 79 #define JZ4760_ADC_BATTERY_VREF 2500 80 #define JZ4770_ADC_BATTERY_VREF 1200 81 #define JZ4770_ADC_BATTERY_VREF_BITS 12 82 83 #define JZ_ADC_IRQ_AUX BIT(0) 84 #define JZ_ADC_IRQ_BATTERY BIT(1) 85 #define JZ_ADC_IRQ_TOUCH BIT(2) 86 #define JZ_ADC_IRQ_PEN_DOWN BIT(3) 87 #define JZ_ADC_IRQ_PEN_UP BIT(4) 88 #define JZ_ADC_IRQ_PEN_DOWN_SLEEP BIT(5) 89 #define JZ_ADC_IRQ_SLEEP BIT(7) 90 91 struct ingenic_adc; 92 93 struct ingenic_adc_soc_data { 94 unsigned int battery_high_vref; 95 unsigned int battery_high_vref_bits; 96 const int *battery_raw_avail; 97 size_t battery_raw_avail_size; 98 const int *battery_scale_avail; 99 size_t battery_scale_avail_size; 100 unsigned int battery_vref_mode: 1; 101 unsigned int has_aux_md: 1; 102 const struct iio_chan_spec *channels; 103 unsigned int num_channels; 104 int (*init_clk_div)(struct device *dev, struct ingenic_adc *adc); 105 }; 106 107 struct ingenic_adc { 108 void __iomem *base; 109 struct clk *clk; 110 struct mutex lock; 111 struct mutex aux_lock; 112 const struct ingenic_adc_soc_data *soc_data; 113 bool low_vref_mode; 114 }; 115 116 static void ingenic_adc_set_adcmd(struct iio_dev *iio_dev, unsigned long mask) 117 { 118 struct ingenic_adc *adc = iio_priv(iio_dev); 119 120 guard(mutex)(&adc->lock); 121 122 /* Init ADCMD */ 123 readl(adc->base + JZ_ADC_REG_ADCMD); 124 125 if (mask & 0x3) { 126 /* Second channel (INGENIC_ADC_TOUCH_YP): sample YP vs. GND */ 127 writel(JZ_ADC_REG_ADCMD_XNGRU 128 | JZ_ADC_REG_ADCMD_VREFNXN | JZ_ADC_REG_ADCMD_VREFPVDD33 129 | JZ_ADC_REG_ADCMD_YPADC, 130 adc->base + JZ_ADC_REG_ADCMD); 131 132 /* First channel (INGENIC_ADC_TOUCH_XP): sample XP vs. GND */ 133 writel(JZ_ADC_REG_ADCMD_YNGRU 134 | JZ_ADC_REG_ADCMD_VREFNYN | JZ_ADC_REG_ADCMD_VREFPVDD33 135 | JZ_ADC_REG_ADCMD_XPADC, 136 adc->base + JZ_ADC_REG_ADCMD); 137 } 138 139 if (mask & 0xc) { 140 /* Fourth channel (INGENIC_ADC_TOUCH_YN): sample YN vs. GND */ 141 writel(JZ_ADC_REG_ADCMD_XNGRU 142 | JZ_ADC_REG_ADCMD_VREFNXN | JZ_ADC_REG_ADCMD_VREFPVDD33 143 | JZ_ADC_REG_ADCMD_YNADC, 144 adc->base + JZ_ADC_REG_ADCMD); 145 146 /* Third channel (INGENIC_ADC_TOUCH_XN): sample XN vs. GND */ 147 writel(JZ_ADC_REG_ADCMD_YNGRU 148 | JZ_ADC_REG_ADCMD_VREFNYN | JZ_ADC_REG_ADCMD_VREFPVDD33 149 | JZ_ADC_REG_ADCMD_XNADC, 150 adc->base + JZ_ADC_REG_ADCMD); 151 } 152 153 if (mask & 0x30) { 154 /* Sixth channel (INGENIC_ADC_TOUCH_YD): sample YP vs. YN */ 155 writel(JZ_ADC_REG_ADCMD_VREFNYN | JZ_ADC_REG_ADCMD_VREFPVDD33 156 | JZ_ADC_REG_ADCMD_YPADC, 157 adc->base + JZ_ADC_REG_ADCMD); 158 159 /* Fifth channel (INGENIC_ADC_TOUCH_XD): sample XP vs. XN */ 160 writel(JZ_ADC_REG_ADCMD_VREFNXN | JZ_ADC_REG_ADCMD_VREFPVDD33 161 | JZ_ADC_REG_ADCMD_XPADC, 162 adc->base + JZ_ADC_REG_ADCMD); 163 } 164 165 /* We're done */ 166 writel(0, adc->base + JZ_ADC_REG_ADCMD); 167 } 168 169 static void ingenic_adc_set_config(struct ingenic_adc *adc, 170 uint32_t mask, 171 uint32_t val) 172 { 173 uint32_t cfg; 174 175 guard(mutex)(&adc->lock); 176 177 cfg = readl(adc->base + JZ_ADC_REG_CFG) & ~mask; 178 cfg |= val; 179 writel(cfg, adc->base + JZ_ADC_REG_CFG); 180 } 181 182 static void __ingenic_adc_enable(struct ingenic_adc *adc, int engine, 183 bool enabled) 184 { 185 u8 val; 186 187 val = readb(adc->base + JZ_ADC_REG_ENABLE); 188 189 if (enabled) 190 val |= BIT(engine); 191 else 192 val &= ~BIT(engine); 193 194 writeb(val, adc->base + JZ_ADC_REG_ENABLE); 195 } 196 197 static void ingenic_adc_enable(struct ingenic_adc *adc, 198 int engine, 199 bool enabled) 200 { 201 guard(mutex)(&adc->lock); 202 __ingenic_adc_enable(adc, engine, enabled); 203 } 204 205 static int ingenic_adc_capture(struct ingenic_adc *adc, 206 int engine) 207 { 208 u32 cfg; 209 u8 val; 210 int ret; 211 212 /* 213 * Disable CMD_SEL temporarily, because it causes wrong VBAT readings, 214 * probably due to the switch of VREF. We must keep the lock here to 215 * avoid races with the buffer enable/disable functions. 216 */ 217 guard(mutex)(&adc->lock); 218 cfg = readl(adc->base + JZ_ADC_REG_CFG); 219 writel(cfg & ~JZ_ADC_REG_CFG_CMD_SEL, adc->base + JZ_ADC_REG_CFG); 220 221 __ingenic_adc_enable(adc, engine, true); 222 ret = readb_poll_timeout(adc->base + JZ_ADC_REG_ENABLE, val, 223 !(val & BIT(engine)), 250, 1000); 224 if (ret) 225 __ingenic_adc_enable(adc, engine, false); 226 227 writel(cfg, adc->base + JZ_ADC_REG_CFG); 228 229 return ret; 230 } 231 232 static int ingenic_adc_write_raw(struct iio_dev *iio_dev, 233 struct iio_chan_spec const *chan, 234 int val, 235 int val2, 236 long m) 237 { 238 struct ingenic_adc *adc = iio_priv(iio_dev); 239 struct device *dev = iio_dev->dev.parent; 240 int ret; 241 242 switch (m) { 243 case IIO_CHAN_INFO_SCALE: 244 switch (chan->channel) { 245 case INGENIC_ADC_BATTERY: 246 if (!adc->soc_data->battery_vref_mode) 247 return -EINVAL; 248 249 ret = clk_enable(adc->clk); 250 if (ret) { 251 dev_err(dev, "Failed to enable clock: %d\n", 252 ret); 253 return ret; 254 } 255 256 if (val > JZ_ADC_BATTERY_LOW_VREF) { 257 ingenic_adc_set_config(adc, 258 JZ_ADC_REG_CFG_BAT_MD, 259 0); 260 adc->low_vref_mode = false; 261 } else { 262 ingenic_adc_set_config(adc, 263 JZ_ADC_REG_CFG_BAT_MD, 264 JZ_ADC_REG_CFG_BAT_MD); 265 adc->low_vref_mode = true; 266 } 267 268 clk_disable(adc->clk); 269 270 return 0; 271 default: 272 return -EINVAL; 273 } 274 default: 275 return -EINVAL; 276 } 277 } 278 279 static const int jz4725b_adc_battery_raw_avail[] = { 280 0, 1, (1 << JZ_ADC_BATTERY_LOW_VREF_BITS) - 1, 281 }; 282 283 static const int jz4725b_adc_battery_scale_avail[] = { 284 JZ4725B_ADC_BATTERY_HIGH_VREF, JZ4725B_ADC_BATTERY_HIGH_VREF_BITS, 285 JZ_ADC_BATTERY_LOW_VREF, JZ_ADC_BATTERY_LOW_VREF_BITS, 286 }; 287 288 static const int jz4740_adc_battery_raw_avail[] = { 289 0, 1, (1 << JZ_ADC_BATTERY_LOW_VREF_BITS) - 1, 290 }; 291 292 static const int jz4740_adc_battery_scale_avail[] = { 293 JZ4740_ADC_BATTERY_HIGH_VREF, JZ4740_ADC_BATTERY_HIGH_VREF_BITS, 294 JZ_ADC_BATTERY_LOW_VREF, JZ_ADC_BATTERY_LOW_VREF_BITS, 295 }; 296 297 static const int jz4760_adc_battery_scale_avail[] = { 298 JZ4760_ADC_BATTERY_VREF, JZ4770_ADC_BATTERY_VREF_BITS, 299 }; 300 301 static const int jz4770_adc_battery_raw_avail[] = { 302 0, 1, (1 << JZ4770_ADC_BATTERY_VREF_BITS) - 1, 303 }; 304 305 static const int jz4770_adc_battery_scale_avail[] = { 306 JZ4770_ADC_BATTERY_VREF, JZ4770_ADC_BATTERY_VREF_BITS, 307 }; 308 309 static int jz4725b_adc_init_clk_div(struct device *dev, struct ingenic_adc *adc) 310 { 311 struct clk *parent_clk; 312 unsigned long parent_rate, rate; 313 unsigned int div_main, div_10us; 314 315 parent_clk = clk_get_parent(adc->clk); 316 if (!parent_clk) { 317 dev_err(dev, "ADC clock has no parent\n"); 318 return -ENODEV; 319 } 320 parent_rate = clk_get_rate(parent_clk); 321 322 /* 323 * The JZ4725B ADC works at 500 kHz to 8 MHz. 324 * We pick the highest rate possible. 325 * In practice we typically get 6 MHz, half of the 12 MHz EXT clock. 326 */ 327 div_main = DIV_ROUND_UP(parent_rate, 8000000); 328 div_main = clamp(div_main, 1u, 64u); 329 rate = parent_rate / div_main; 330 if (rate < 500000 || rate > 8000000) { 331 dev_err(dev, "No valid divider for ADC main clock\n"); 332 return -EINVAL; 333 } 334 335 /* We also need a divider that produces a 10us clock. */ 336 div_10us = DIV_ROUND_UP(rate, 100000); 337 338 writel(((div_10us - 1) << JZ4725B_ADC_REG_ADCLK_CLKDIV10US_LSB) | 339 (div_main - 1) << JZ_ADC_REG_ADCLK_CLKDIV_LSB, 340 adc->base + JZ_ADC_REG_ADCLK); 341 342 return 0; 343 } 344 345 static int jz4770_adc_init_clk_div(struct device *dev, struct ingenic_adc *adc) 346 { 347 struct clk *parent_clk; 348 unsigned long parent_rate, rate; 349 unsigned int div_main, div_ms, div_10us; 350 351 parent_clk = clk_get_parent(adc->clk); 352 if (!parent_clk) { 353 dev_err(dev, "ADC clock has no parent\n"); 354 return -ENODEV; 355 } 356 parent_rate = clk_get_rate(parent_clk); 357 358 /* 359 * The JZ4770 ADC works at 20 kHz to 200 kHz. 360 * We pick the highest rate possible. 361 */ 362 div_main = DIV_ROUND_UP(parent_rate, 200000); 363 div_main = clamp(div_main, 1u, 256u); 364 rate = parent_rate / div_main; 365 if (rate < 20000 || rate > 200000) { 366 dev_err(dev, "No valid divider for ADC main clock\n"); 367 return -EINVAL; 368 } 369 370 /* We also need a divider that produces a 10us clock. */ 371 div_10us = DIV_ROUND_UP(rate, 10000); 372 /* And another, which produces a 1ms clock. */ 373 div_ms = DIV_ROUND_UP(rate, 1000); 374 375 writel(((div_ms - 1) << JZ4770_ADC_REG_ADCLK_CLKDIVMS_LSB) | 376 ((div_10us - 1) << JZ4770_ADC_REG_ADCLK_CLKDIV10US_LSB) | 377 (div_main - 1) << JZ_ADC_REG_ADCLK_CLKDIV_LSB, 378 adc->base + JZ_ADC_REG_ADCLK); 379 380 return 0; 381 } 382 383 static const struct iio_chan_spec jz4740_channels[] = { 384 { 385 .extend_name = "aux", 386 .type = IIO_VOLTAGE, 387 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 388 BIT(IIO_CHAN_INFO_SCALE), 389 .indexed = 1, 390 .channel = INGENIC_ADC_AUX, 391 .scan_index = -1, 392 }, 393 { 394 .extend_name = "battery", 395 .type = IIO_VOLTAGE, 396 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 397 BIT(IIO_CHAN_INFO_SCALE), 398 .info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW) | 399 BIT(IIO_CHAN_INFO_SCALE), 400 .indexed = 1, 401 .channel = INGENIC_ADC_BATTERY, 402 .scan_index = -1, 403 }, 404 }; 405 406 static const struct iio_chan_spec jz4760_channels[] = { 407 { 408 .extend_name = "aux", 409 .type = IIO_VOLTAGE, 410 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 411 BIT(IIO_CHAN_INFO_SCALE), 412 .indexed = 1, 413 .channel = INGENIC_ADC_AUX0, 414 .scan_index = -1, 415 }, 416 { 417 .extend_name = "aux1", 418 .type = IIO_VOLTAGE, 419 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 420 BIT(IIO_CHAN_INFO_SCALE), 421 .indexed = 1, 422 .channel = INGENIC_ADC_AUX, 423 .scan_index = -1, 424 }, 425 { 426 .extend_name = "aux2", 427 .type = IIO_VOLTAGE, 428 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 429 BIT(IIO_CHAN_INFO_SCALE), 430 .indexed = 1, 431 .channel = INGENIC_ADC_AUX2, 432 .scan_index = -1, 433 }, 434 { 435 .extend_name = "battery", 436 .type = IIO_VOLTAGE, 437 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 438 BIT(IIO_CHAN_INFO_SCALE), 439 .info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW) | 440 BIT(IIO_CHAN_INFO_SCALE), 441 .indexed = 1, 442 .channel = INGENIC_ADC_BATTERY, 443 .scan_index = -1, 444 }, 445 }; 446 447 static const struct iio_chan_spec jz4770_channels[] = { 448 { 449 .type = IIO_VOLTAGE, 450 .indexed = 1, 451 .channel = INGENIC_ADC_TOUCH_XP, 452 .scan_index = 0, 453 .scan_type = { 454 .sign = 'u', 455 .realbits = 12, 456 .storagebits = 16, 457 }, 458 }, 459 { 460 .type = IIO_VOLTAGE, 461 .indexed = 1, 462 .channel = INGENIC_ADC_TOUCH_YP, 463 .scan_index = 1, 464 .scan_type = { 465 .sign = 'u', 466 .realbits = 12, 467 .storagebits = 16, 468 }, 469 }, 470 { 471 .type = IIO_VOLTAGE, 472 .indexed = 1, 473 .channel = INGENIC_ADC_TOUCH_XN, 474 .scan_index = 2, 475 .scan_type = { 476 .sign = 'u', 477 .realbits = 12, 478 .storagebits = 16, 479 }, 480 }, 481 { 482 .type = IIO_VOLTAGE, 483 .indexed = 1, 484 .channel = INGENIC_ADC_TOUCH_YN, 485 .scan_index = 3, 486 .scan_type = { 487 .sign = 'u', 488 .realbits = 12, 489 .storagebits = 16, 490 }, 491 }, 492 { 493 .type = IIO_VOLTAGE, 494 .indexed = 1, 495 .channel = INGENIC_ADC_TOUCH_XD, 496 .scan_index = 4, 497 .scan_type = { 498 .sign = 'u', 499 .realbits = 12, 500 .storagebits = 16, 501 }, 502 }, 503 { 504 .type = IIO_VOLTAGE, 505 .indexed = 1, 506 .channel = INGENIC_ADC_TOUCH_YD, 507 .scan_index = 5, 508 .scan_type = { 509 .sign = 'u', 510 .realbits = 12, 511 .storagebits = 16, 512 }, 513 }, 514 { 515 .extend_name = "aux", 516 .type = IIO_VOLTAGE, 517 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 518 BIT(IIO_CHAN_INFO_SCALE), 519 .indexed = 1, 520 .channel = INGENIC_ADC_AUX, 521 .scan_index = -1, 522 }, 523 { 524 .extend_name = "battery", 525 .type = IIO_VOLTAGE, 526 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 527 BIT(IIO_CHAN_INFO_SCALE), 528 .info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW) | 529 BIT(IIO_CHAN_INFO_SCALE), 530 .indexed = 1, 531 .channel = INGENIC_ADC_BATTERY, 532 .scan_index = -1, 533 }, 534 { 535 .extend_name = "aux2", 536 .type = IIO_VOLTAGE, 537 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 538 BIT(IIO_CHAN_INFO_SCALE), 539 .indexed = 1, 540 .channel = INGENIC_ADC_AUX2, 541 .scan_index = -1, 542 }, 543 }; 544 545 static const struct ingenic_adc_soc_data jz4725b_adc_soc_data = { 546 .battery_high_vref = JZ4725B_ADC_BATTERY_HIGH_VREF, 547 .battery_high_vref_bits = JZ4725B_ADC_BATTERY_HIGH_VREF_BITS, 548 .battery_raw_avail = jz4725b_adc_battery_raw_avail, 549 .battery_raw_avail_size = ARRAY_SIZE(jz4725b_adc_battery_raw_avail), 550 .battery_scale_avail = jz4725b_adc_battery_scale_avail, 551 .battery_scale_avail_size = ARRAY_SIZE(jz4725b_adc_battery_scale_avail), 552 .battery_vref_mode = true, 553 .has_aux_md = false, 554 .channels = jz4740_channels, 555 .num_channels = ARRAY_SIZE(jz4740_channels), 556 .init_clk_div = jz4725b_adc_init_clk_div, 557 }; 558 559 static const struct ingenic_adc_soc_data jz4740_adc_soc_data = { 560 .battery_high_vref = JZ4740_ADC_BATTERY_HIGH_VREF, 561 .battery_high_vref_bits = JZ4740_ADC_BATTERY_HIGH_VREF_BITS, 562 .battery_raw_avail = jz4740_adc_battery_raw_avail, 563 .battery_raw_avail_size = ARRAY_SIZE(jz4740_adc_battery_raw_avail), 564 .battery_scale_avail = jz4740_adc_battery_scale_avail, 565 .battery_scale_avail_size = ARRAY_SIZE(jz4740_adc_battery_scale_avail), 566 .battery_vref_mode = true, 567 .has_aux_md = false, 568 .channels = jz4740_channels, 569 .num_channels = ARRAY_SIZE(jz4740_channels), 570 .init_clk_div = NULL, /* no ADCLK register on JZ4740 */ 571 }; 572 573 static const struct ingenic_adc_soc_data jz4760_adc_soc_data = { 574 .battery_high_vref = JZ4760_ADC_BATTERY_VREF, 575 .battery_high_vref_bits = JZ4770_ADC_BATTERY_VREF_BITS, 576 .battery_raw_avail = jz4770_adc_battery_raw_avail, 577 .battery_raw_avail_size = ARRAY_SIZE(jz4770_adc_battery_raw_avail), 578 .battery_scale_avail = jz4760_adc_battery_scale_avail, 579 .battery_scale_avail_size = ARRAY_SIZE(jz4760_adc_battery_scale_avail), 580 .battery_vref_mode = false, 581 .has_aux_md = true, 582 .channels = jz4760_channels, 583 .num_channels = ARRAY_SIZE(jz4760_channels), 584 .init_clk_div = jz4770_adc_init_clk_div, 585 }; 586 587 static const struct ingenic_adc_soc_data jz4770_adc_soc_data = { 588 .battery_high_vref = JZ4770_ADC_BATTERY_VREF, 589 .battery_high_vref_bits = JZ4770_ADC_BATTERY_VREF_BITS, 590 .battery_raw_avail = jz4770_adc_battery_raw_avail, 591 .battery_raw_avail_size = ARRAY_SIZE(jz4770_adc_battery_raw_avail), 592 .battery_scale_avail = jz4770_adc_battery_scale_avail, 593 .battery_scale_avail_size = ARRAY_SIZE(jz4770_adc_battery_scale_avail), 594 .battery_vref_mode = false, 595 .has_aux_md = true, 596 .channels = jz4770_channels, 597 .num_channels = ARRAY_SIZE(jz4770_channels), 598 .init_clk_div = jz4770_adc_init_clk_div, 599 }; 600 601 static int ingenic_adc_read_avail(struct iio_dev *iio_dev, 602 struct iio_chan_spec const *chan, 603 const int **vals, 604 int *type, 605 int *length, 606 long m) 607 { 608 struct ingenic_adc *adc = iio_priv(iio_dev); 609 610 switch (m) { 611 case IIO_CHAN_INFO_RAW: 612 *type = IIO_VAL_INT; 613 *length = adc->soc_data->battery_raw_avail_size; 614 *vals = adc->soc_data->battery_raw_avail; 615 return IIO_AVAIL_RANGE; 616 case IIO_CHAN_INFO_SCALE: 617 *type = IIO_VAL_FRACTIONAL_LOG2; 618 *length = adc->soc_data->battery_scale_avail_size; 619 *vals = adc->soc_data->battery_scale_avail; 620 return IIO_AVAIL_LIST; 621 default: 622 return -EINVAL; 623 } 624 } 625 626 static int __ingenic_adc_read_chan(struct ingenic_adc *adc, 627 struct iio_chan_spec const *chan, 628 int *val) 629 { 630 int cmd, ret, engine = (chan->channel == INGENIC_ADC_BATTERY); 631 632 if (adc->soc_data->has_aux_md && engine == 0) { 633 switch (chan->channel) { 634 case INGENIC_ADC_AUX0: 635 cmd = 0; 636 break; 637 case INGENIC_ADC_AUX: 638 cmd = 1; 639 break; 640 case INGENIC_ADC_AUX2: 641 cmd = 2; 642 break; 643 } 644 645 ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_AUX_MD, cmd); 646 } 647 648 ret = ingenic_adc_capture(adc, engine); 649 if (ret) 650 return ret; 651 652 switch (chan->channel) { 653 case INGENIC_ADC_AUX0: 654 case INGENIC_ADC_AUX: 655 case INGENIC_ADC_AUX2: 656 *val = readw(adc->base + JZ_ADC_REG_ADSDAT); 657 break; 658 case INGENIC_ADC_BATTERY: 659 *val = readw(adc->base + JZ_ADC_REG_ADBDAT); 660 break; 661 } 662 663 return IIO_VAL_INT; 664 } 665 666 static int ingenic_adc_read_chan_info_raw(struct iio_dev *iio_dev, 667 struct iio_chan_spec const *chan, 668 int *val) 669 { 670 struct ingenic_adc *adc = iio_priv(iio_dev); 671 int ret; 672 673 ret = clk_enable(adc->clk); 674 if (ret) { 675 dev_err(iio_dev->dev.parent, "Failed to enable clock: %d\n", ret); 676 return ret; 677 } 678 679 /* We cannot sample the aux channels in parallel. */ 680 scoped_guard(mutex, &adc->aux_lock) 681 ret = __ingenic_adc_read_chan(adc, chan, val); 682 683 clk_disable(adc->clk); 684 685 return ret; 686 } 687 688 static int ingenic_adc_read_raw(struct iio_dev *iio_dev, 689 struct iio_chan_spec const *chan, 690 int *val, 691 int *val2, 692 long m) 693 { 694 struct ingenic_adc *adc = iio_priv(iio_dev); 695 696 switch (m) { 697 case IIO_CHAN_INFO_RAW: 698 return ingenic_adc_read_chan_info_raw(iio_dev, chan, val); 699 case IIO_CHAN_INFO_SCALE: 700 switch (chan->channel) { 701 case INGENIC_ADC_AUX0: 702 case INGENIC_ADC_AUX: 703 case INGENIC_ADC_AUX2: 704 *val = JZ_ADC_AUX_VREF; 705 *val2 = JZ_ADC_AUX_VREF_BITS; 706 break; 707 case INGENIC_ADC_BATTERY: 708 if (adc->low_vref_mode) { 709 *val = JZ_ADC_BATTERY_LOW_VREF; 710 *val2 = JZ_ADC_BATTERY_LOW_VREF_BITS; 711 } else { 712 *val = adc->soc_data->battery_high_vref; 713 *val2 = adc->soc_data->battery_high_vref_bits; 714 } 715 break; 716 } 717 718 return IIO_VAL_FRACTIONAL_LOG2; 719 default: 720 return -EINVAL; 721 } 722 } 723 724 static int ingenic_adc_fwnode_xlate(struct iio_dev *iio_dev, 725 const struct fwnode_reference_args *iiospec) 726 { 727 int i; 728 729 if (!iiospec->nargs) 730 return -EINVAL; 731 732 for (i = 0; i < iio_dev->num_channels; ++i) 733 if (iio_dev->channels[i].channel == iiospec->args[0]) 734 return i; 735 736 return -EINVAL; 737 } 738 739 static const struct iio_info ingenic_adc_info = { 740 .write_raw = ingenic_adc_write_raw, 741 .read_raw = ingenic_adc_read_raw, 742 .read_avail = ingenic_adc_read_avail, 743 .fwnode_xlate = ingenic_adc_fwnode_xlate, 744 }; 745 746 static int ingenic_adc_buffer_enable(struct iio_dev *iio_dev) 747 { 748 struct ingenic_adc *adc = iio_priv(iio_dev); 749 int ret; 750 751 ret = clk_enable(adc->clk); 752 if (ret) { 753 dev_err(iio_dev->dev.parent, "Failed to enable clock: %d\n", 754 ret); 755 return ret; 756 } 757 758 /* It takes significant time for the touchscreen hw to stabilize. */ 759 msleep(50); 760 ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_TOUCH_OPS_MASK, 761 JZ_ADC_REG_CFG_SAMPLE_NUM(4) | 762 JZ_ADC_REG_CFG_PULL_UP(4)); 763 764 writew(80, adc->base + JZ_ADC_REG_ADWAIT); 765 writew(2, adc->base + JZ_ADC_REG_ADSAME); 766 writeb((u8)~JZ_ADC_IRQ_TOUCH, adc->base + JZ_ADC_REG_CTRL); 767 writel(0, adc->base + JZ_ADC_REG_ADTCH); 768 769 ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_CMD_SEL, 770 JZ_ADC_REG_CFG_CMD_SEL); 771 ingenic_adc_set_adcmd(iio_dev, iio_dev->active_scan_mask[0]); 772 773 ingenic_adc_enable(adc, 2, true); 774 775 return 0; 776 } 777 778 static int ingenic_adc_buffer_disable(struct iio_dev *iio_dev) 779 { 780 struct ingenic_adc *adc = iio_priv(iio_dev); 781 782 ingenic_adc_enable(adc, 2, false); 783 784 ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_CMD_SEL, 0); 785 786 writeb(0xff, adc->base + JZ_ADC_REG_CTRL); 787 writeb(0xff, adc->base + JZ_ADC_REG_STATUS); 788 ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_TOUCH_OPS_MASK, 0); 789 writew(0, adc->base + JZ_ADC_REG_ADSAME); 790 writew(0, adc->base + JZ_ADC_REG_ADWAIT); 791 clk_disable(adc->clk); 792 793 return 0; 794 } 795 796 static const struct iio_buffer_setup_ops ingenic_buffer_setup_ops = { 797 .postenable = &ingenic_adc_buffer_enable, 798 .predisable = &ingenic_adc_buffer_disable 799 }; 800 801 static irqreturn_t ingenic_adc_irq(int irq, void *data) 802 { 803 struct iio_dev *iio_dev = data; 804 struct ingenic_adc *adc = iio_priv(iio_dev); 805 unsigned long mask = iio_dev->active_scan_mask[0]; 806 unsigned int i; 807 u32 tdat[3]; 808 809 for (i = 0; i < ARRAY_SIZE(tdat); mask >>= 2, i++) { 810 if (mask & 0x3) 811 tdat[i] = readl(adc->base + JZ_ADC_REG_ADTCH); 812 else 813 tdat[i] = 0; 814 } 815 816 iio_push_to_buffers(iio_dev, tdat); 817 writeb(JZ_ADC_IRQ_TOUCH, adc->base + JZ_ADC_REG_STATUS); 818 819 return IRQ_HANDLED; 820 } 821 822 static int ingenic_adc_probe(struct platform_device *pdev) 823 { 824 struct device *dev = &pdev->dev; 825 struct iio_dev *iio_dev; 826 struct ingenic_adc *adc; 827 const struct ingenic_adc_soc_data *soc_data; 828 int irq, ret; 829 830 soc_data = device_get_match_data(dev); 831 if (!soc_data) 832 return -EINVAL; 833 834 iio_dev = devm_iio_device_alloc(dev, sizeof(*adc)); 835 if (!iio_dev) 836 return -ENOMEM; 837 838 adc = iio_priv(iio_dev); 839 mutex_init(&adc->lock); 840 mutex_init(&adc->aux_lock); 841 adc->soc_data = soc_data; 842 843 irq = platform_get_irq(pdev, 0); 844 if (irq < 0) 845 return irq; 846 847 ret = devm_request_irq(dev, irq, ingenic_adc_irq, 0, 848 dev_name(dev), iio_dev); 849 if (ret < 0) { 850 dev_err(dev, "Failed to request irq: %d\n", ret); 851 return ret; 852 } 853 854 adc->base = devm_platform_ioremap_resource(pdev, 0); 855 if (IS_ERR(adc->base)) 856 return PTR_ERR(adc->base); 857 858 adc->clk = devm_clk_get_prepared(dev, "adc"); 859 if (IS_ERR(adc->clk)) { 860 dev_err(dev, "Unable to get clock\n"); 861 return PTR_ERR(adc->clk); 862 } 863 864 ret = clk_enable(adc->clk); 865 if (ret) { 866 dev_err(dev, "Failed to enable clock\n"); 867 return ret; 868 } 869 870 /* Set clock dividers. */ 871 if (soc_data->init_clk_div) { 872 ret = soc_data->init_clk_div(dev, adc); 873 if (ret) { 874 clk_disable_unprepare(adc->clk); 875 return ret; 876 } 877 } 878 879 /* Put hardware in a known passive state. */ 880 writeb(0x00, adc->base + JZ_ADC_REG_ENABLE); 881 writeb(0xff, adc->base + JZ_ADC_REG_CTRL); 882 883 /* JZ4760B specific */ 884 if (device_property_present(dev, "ingenic,use-internal-divider")) 885 ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_VBAT_SEL, 886 JZ_ADC_REG_CFG_VBAT_SEL); 887 else 888 ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_VBAT_SEL, 0); 889 890 usleep_range(2000, 3000); /* Must wait at least 2ms. */ 891 clk_disable(adc->clk); 892 893 iio_dev->name = "jz-adc"; 894 iio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE; 895 iio_dev->setup_ops = &ingenic_buffer_setup_ops; 896 iio_dev->channels = soc_data->channels; 897 iio_dev->num_channels = soc_data->num_channels; 898 iio_dev->info = &ingenic_adc_info; 899 900 ret = devm_iio_device_register(dev, iio_dev); 901 if (ret) 902 dev_err(dev, "Unable to register IIO device\n"); 903 904 return ret; 905 } 906 907 static const struct of_device_id ingenic_adc_of_match[] = { 908 { .compatible = "ingenic,jz4725b-adc", .data = &jz4725b_adc_soc_data, }, 909 { .compatible = "ingenic,jz4740-adc", .data = &jz4740_adc_soc_data, }, 910 { .compatible = "ingenic,jz4760-adc", .data = &jz4760_adc_soc_data, }, 911 { .compatible = "ingenic,jz4760b-adc", .data = &jz4760_adc_soc_data, }, 912 { .compatible = "ingenic,jz4770-adc", .data = &jz4770_adc_soc_data, }, 913 { } 914 }; 915 MODULE_DEVICE_TABLE(of, ingenic_adc_of_match); 916 917 static struct platform_driver ingenic_adc_driver = { 918 .driver = { 919 .name = "ingenic-adc", 920 .of_match_table = ingenic_adc_of_match, 921 }, 922 .probe = ingenic_adc_probe, 923 }; 924 module_platform_driver(ingenic_adc_driver); 925 MODULE_DESCRIPTION("ADC driver for the Ingenic JZ47xx SoCs"); 926 MODULE_LICENSE("GPL v2"); 927