1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2014 Broadcom Corporation
3
4 #include <linux/kernel.h>
5 #include <linux/err.h>
6 #include <linux/clk-provider.h>
7 #include <linux/io.h>
8 #include <linux/of.h>
9 #include <linux/clkdev.h>
10 #include <linux/of_address.h>
11 #include <linux/delay.h>
12
13 #include "clk-iproc.h"
14
15 struct iproc_asiu;
16
17 struct iproc_asiu_clk {
18 struct clk_hw hw;
19 const char *name;
20 struct iproc_asiu *asiu;
21 unsigned long rate;
22 struct iproc_asiu_div div;
23 struct iproc_asiu_gate gate;
24 };
25
26 struct iproc_asiu {
27 void __iomem *div_base;
28 void __iomem *gate_base;
29
30 struct iproc_asiu_clk clks[];
31 };
32
33 #define to_asiu_clk(hw) container_of(hw, struct iproc_asiu_clk, hw)
34
iproc_asiu_clk_enable(struct clk_hw * hw)35 static int iproc_asiu_clk_enable(struct clk_hw *hw)
36 {
37 struct iproc_asiu_clk *clk = to_asiu_clk(hw);
38 struct iproc_asiu *asiu = clk->asiu;
39 u32 val;
40
41 /* some clocks at the ASIU level are always enabled */
42 if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET)
43 return 0;
44
45 val = readl(asiu->gate_base + clk->gate.offset);
46 val |= (1 << clk->gate.en_shift);
47 writel(val, asiu->gate_base + clk->gate.offset);
48
49 return 0;
50 }
51
iproc_asiu_clk_disable(struct clk_hw * hw)52 static void iproc_asiu_clk_disable(struct clk_hw *hw)
53 {
54 struct iproc_asiu_clk *clk = to_asiu_clk(hw);
55 struct iproc_asiu *asiu = clk->asiu;
56 u32 val;
57
58 /* some clocks at the ASIU level are always enabled */
59 if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET)
60 return;
61
62 val = readl(asiu->gate_base + clk->gate.offset);
63 val &= ~(1 << clk->gate.en_shift);
64 writel(val, asiu->gate_base + clk->gate.offset);
65 }
66
iproc_asiu_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)67 static unsigned long iproc_asiu_clk_recalc_rate(struct clk_hw *hw,
68 unsigned long parent_rate)
69 {
70 struct iproc_asiu_clk *clk = to_asiu_clk(hw);
71 struct iproc_asiu *asiu = clk->asiu;
72 u32 val;
73 unsigned int div_h, div_l;
74
75 if (parent_rate == 0) {
76 clk->rate = 0;
77 return 0;
78 }
79
80 /* if clock divisor is not enabled, simply return parent rate */
81 val = readl(asiu->div_base + clk->div.offset);
82 if ((val & (1 << clk->div.en_shift)) == 0) {
83 clk->rate = parent_rate;
84 return parent_rate;
85 }
86
87 /* clock rate = parent rate / (high_div + 1) + (low_div + 1) */
88 div_h = (val >> clk->div.high_shift) & bit_mask(clk->div.high_width);
89 div_h++;
90 div_l = (val >> clk->div.low_shift) & bit_mask(clk->div.low_width);
91 div_l++;
92
93 clk->rate = parent_rate / (div_h + div_l);
94 pr_debug("%s: rate: %lu. parent rate: %lu div_h: %u div_l: %u\n",
95 __func__, clk->rate, parent_rate, div_h, div_l);
96
97 return clk->rate;
98 }
99
iproc_asiu_clk_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)100 static int iproc_asiu_clk_determine_rate(struct clk_hw *hw,
101 struct clk_rate_request *req)
102 {
103 unsigned int div;
104
105 if (req->rate == 0 || req->best_parent_rate == 0)
106 return -EINVAL;
107
108 if (req->rate == req->best_parent_rate)
109 return 0;
110
111 div = DIV_ROUND_CLOSEST(req->best_parent_rate, req->rate);
112 if (div < 2) {
113 req->rate = req->best_parent_rate;
114
115 return 0;
116 }
117
118 req->rate = req->best_parent_rate / div;
119
120 return 0;
121 }
122
iproc_asiu_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)123 static int iproc_asiu_clk_set_rate(struct clk_hw *hw, unsigned long rate,
124 unsigned long parent_rate)
125 {
126 struct iproc_asiu_clk *clk = to_asiu_clk(hw);
127 struct iproc_asiu *asiu = clk->asiu;
128 unsigned int div, div_h, div_l;
129 u32 val;
130
131 if (rate == 0 || parent_rate == 0)
132 return -EINVAL;
133
134 /* simply disable the divisor if one wants the same rate as parent */
135 if (rate == parent_rate) {
136 val = readl(asiu->div_base + clk->div.offset);
137 val &= ~(1 << clk->div.en_shift);
138 writel(val, asiu->div_base + clk->div.offset);
139 return 0;
140 }
141
142 div = DIV_ROUND_CLOSEST(parent_rate, rate);
143 if (div < 2)
144 return -EINVAL;
145
146 div_h = div_l = div >> 1;
147 div_h--;
148 div_l--;
149
150 val = readl(asiu->div_base + clk->div.offset);
151 val |= 1 << clk->div.en_shift;
152 if (div_h) {
153 val &= ~(bit_mask(clk->div.high_width)
154 << clk->div.high_shift);
155 val |= div_h << clk->div.high_shift;
156 } else {
157 val &= ~(bit_mask(clk->div.high_width)
158 << clk->div.high_shift);
159 }
160 if (div_l) {
161 val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift);
162 val |= div_l << clk->div.low_shift;
163 } else {
164 val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift);
165 }
166 writel(val, asiu->div_base + clk->div.offset);
167
168 return 0;
169 }
170
171 static const struct clk_ops iproc_asiu_ops = {
172 .enable = iproc_asiu_clk_enable,
173 .disable = iproc_asiu_clk_disable,
174 .recalc_rate = iproc_asiu_clk_recalc_rate,
175 .determine_rate = iproc_asiu_clk_determine_rate,
176 .set_rate = iproc_asiu_clk_set_rate,
177 };
178
iproc_asiu_setup(struct device_node * node,const struct iproc_asiu_div * div,const struct iproc_asiu_gate * gate,unsigned int num_clks)179 void __init iproc_asiu_setup(struct device_node *node,
180 const struct iproc_asiu_div *div,
181 const struct iproc_asiu_gate *gate,
182 unsigned int num_clks)
183 {
184 int i, ret;
185 struct iproc_asiu *asiu;
186 struct clk_hw_onecell_data *clk_data;
187
188 if (WARN_ON(!gate || !div))
189 return;
190
191 asiu = kzalloc_flex(*asiu, clks, num_clks);
192 if (WARN_ON(!asiu))
193 return;
194
195 clk_data = kzalloc_flex(*clk_data, hws, num_clks);
196 if (WARN_ON(!clk_data))
197 goto err_clks;
198 clk_data->num = num_clks;
199
200 asiu->div_base = of_iomap(node, 0);
201 if (WARN_ON(!asiu->div_base))
202 goto err_iomap_div;
203
204 asiu->gate_base = of_iomap(node, 1);
205 if (WARN_ON(!asiu->gate_base))
206 goto err_iomap_gate;
207
208 for (i = 0; i < num_clks; i++) {
209 struct clk_init_data init;
210 const char *parent_name;
211 struct iproc_asiu_clk *asiu_clk;
212 const char *clk_name;
213
214 ret = of_property_read_string_index(node, "clock-output-names",
215 i, &clk_name);
216 if (WARN_ON(ret))
217 goto err_clk_register;
218
219 asiu_clk = &asiu->clks[i];
220 asiu_clk->name = clk_name;
221 asiu_clk->asiu = asiu;
222 asiu_clk->div = div[i];
223 asiu_clk->gate = gate[i];
224 init.name = clk_name;
225 init.ops = &iproc_asiu_ops;
226 init.flags = 0;
227 parent_name = of_clk_get_parent_name(node, 0);
228 init.parent_names = (parent_name ? &parent_name : NULL);
229 init.num_parents = (parent_name ? 1 : 0);
230 asiu_clk->hw.init = &init;
231
232 ret = clk_hw_register(NULL, &asiu_clk->hw);
233 if (WARN_ON(ret))
234 goto err_clk_register;
235 clk_data->hws[i] = &asiu_clk->hw;
236 }
237
238 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
239 clk_data);
240 if (WARN_ON(ret))
241 goto err_clk_register;
242
243 return;
244
245 err_clk_register:
246 while (--i >= 0)
247 clk_hw_unregister(clk_data->hws[i]);
248 iounmap(asiu->gate_base);
249
250 err_iomap_gate:
251 iounmap(asiu->div_base);
252
253 err_iomap_div:
254 kfree(clk_data);
255
256 err_clks:
257 kfree(asiu);
258 }
259