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/linux/drivers/clk/baikal-t1/
H A Dccu-div.c61 unsigned long div) in ccu_div_lock_delay_ns()
71 unsigned long div) in ccu_div_calc_freq()
76 static int ccu_div_var_update_clkdiv(struct ccu_div *div, in ccu_div_var_update_clkdiv()
113 struct ccu_div *div = to_ccu_div(hw); in ccu_div_var_enable() local
142 struct ccu_div *div = to_ccu_div(hw); in ccu_div_gate_enable() local
155 struct ccu_div *div = to_ccu_div(hw); in ccu_div_gate_disable() local
165 struct ccu_div *div = to_ccu_div(hw); in ccu_div_gate_is_enabled() local
175 struct ccu_div *div = to_ccu_div(hw); in ccu_div_buf_enable() local
188 struct ccu_div *div = to_ccu_div(hw); in ccu_div_buf_disable() local
199 struct ccu_div *div = to_ccu_div(hw); in ccu_div_buf_is_enabled() local
[all …]
/linux/drivers/clk/ti/
H A Ddivider.c72 unsigned int div) in _get_table_val()
82 static unsigned int _get_val(struct clk_omap_divider *divider, u8 div) in _get_val()
97 unsigned int div, val; in ti_clk_divider_recalc_rate() local
120 unsigned int div) in _is_valid_table_div()
130 static bool _is_valid_div(struct clk_omap_divider *divider, unsigned int div) in _is_valid_div()
144 int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); in _div_round_up() local
229 int div; in ti_clk_divider_round_rate() local
239 unsigned int div, value; in ti_clk_divider_set_rate() local
310 struct clk_omap_divider *div) in _register_divider()
384 struct clk_omap_divider *div) in ti_clk_get_div_table()
[all …]
/linux/drivers/clk/imx/
H A Dclk-divider-gate.c21 struct clk_divider *div = to_clk_divider(hw); in to_clk_divider_gate() local
29 struct clk_divider *div = to_clk_divider(hw); in clk_divider_gate_recalc_rate_ro() local
45 struct clk_divider *div = to_clk_divider(hw); in clk_divider_gate_recalc_rate() local
77 struct clk_divider *div = to_clk_divider(hw); in clk_divider_gate_set_rate() local
106 struct clk_divider *div = to_clk_divider(hw); in clk_divider_enable() local
129 struct clk_divider *div = to_clk_divider(hw); in clk_divider_disable() local
146 struct clk_divider *div = to_clk_divider(hw); in clk_divider_is_enabled() local
H A Dclk-pllv3.c115 u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask; in clk_pllv3_recalc_rate() local
133 u32 val, div; in clk_pllv3_set_rate() local
163 u32 div = readl_relaxed(pll->base) & pll->div_mask; in clk_pllv3_sys_recalc_rate() local
174 u32 div; in clk_pllv3_sys_round_rate() local
191 u32 val, div; in clk_pllv3_sys_set_rate() local
220 u32 div = readl_relaxed(pll->base) & pll->div_mask; in clk_pllv3_av_recalc_rate() local
235 u32 div; in clk_pllv3_av_round_rate() local
267 u32 val, div; in clk_pllv3_av_set_rate() local
/linux/drivers/clk/berlin/
H A Dberlin2-div.c67 struct berlin2_div *div = to_berlin2_div(hw); in berlin2_div_is_enabled() local
85 struct berlin2_div *div = to_berlin2_div(hw); in berlin2_div_enable() local
104 struct berlin2_div *div = to_berlin2_div(hw); in berlin2_div_disable() local
121 struct berlin2_div *div = to_berlin2_div(hw); in berlin2_div_set_parent() local
152 struct berlin2_div *div = to_berlin2_div(hw); in berlin2_div_get_parent() local
179 struct berlin2_div *div = to_berlin2_div(hw); in berlin2_div_recalc_rate() local
237 struct berlin2_div *div; in berlin2_div_register() local
/linux/drivers/clk/sophgo/
H A Dclk-cv18xx-ip.c88 struct cv1800_clk_div *div = hw_to_cv1800_clk_div(hw); in div_enable() local
95 struct cv1800_clk_div *div = hw_to_cv1800_clk_div(hw); in div_disable() local
102 struct cv1800_clk_div *div = hw_to_cv1800_clk_div(hw); in div_is_enabled() local
108 struct cv1800_clk_regfield *div, in div_helper_set_rate()
132 struct cv1800_clk_regfield *div) in div_helper_get_clockdiv()
153 static u32 div_helper_round_rate(struct cv1800_clk_regfield *div, in div_helper_round_rate()
171 struct cv1800_clk_div *div = data; in div_round_rate() local
252 struct cv1800_clk_div *div = hw_to_cv1800_clk_div(hw); in div_determine_rate() local
261 struct cv1800_clk_div *div = hw_to_cv1800_clk_div(hw); in div_recalc_rate() local
275 struct cv1800_clk_div *div = hw_to_cv1800_clk_div(hw); in div_set_rate() local
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/linux/drivers/clk/
H A Dclk-divider.c106 unsigned int div) in _get_table_val()
117 unsigned int div, unsigned long flags, u8 width) in _get_val()
135 unsigned int div; in divider_recalc_rate() local
163 unsigned int div) in _is_valid_table_div()
173 static bool _is_valid_div(const struct clk_div_table *table, unsigned int div, in _is_valid_div()
183 static int _round_up_table(const struct clk_div_table *table, int div) in _round_up_table()
201 static int _round_down_table(const struct clk_div_table *table, int div) in _round_down_table()
223 int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); in _div_round_up() local
276 static int _next_div(const struct clk_div_table *table, int div, in _next_div()
350 int div; in divider_determine_rate() local
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H A Dclk-highbank.c196 u32 div = (readl(hbclk->reg) & HB_A9_PCLK_DIV) ? 8 : 4; in clk_cpu_periphclk_recalc_rate() local
208 u32 div = (readl(hbclk->reg) & HB_A9_BCLK_DIV_MASK) >> HB_A9_BCLK_DIV_SHIFT; in clk_cpu_a9bclk_recalc_rate() local
221 u32 div; in clk_periclk_recalc_rate() local
233 u32 div; in clk_periclk_round_rate() local
246 u32 div; in clk_periclk_set_rate() local
H A Dclk-cdce706.c29 #define CDCE706_DIVIDER(div) (13 + (div)) argument
50 #define CDCE706_DIVIDER_PLL(div) (9 + (div) - ((div) > 2) - ((div) > 4)) argument
51 #define CDCE706_DIVIDER_PLL_SHIFT(div) ((div) < 2 ? 5 : 3 * ((div) & 1)) argument
52 #define CDCE706_DIVIDER_PLL_MASK(div) (0x7 << CDCE706_DIVIDER_PLL_SHIFT(div)) argument
72 unsigned div; member
190 unsigned long mul, div; in cdce706_pll_round_rate() local
216 unsigned long mul = hwd->mul, div = hwd->div; in cdce706_pll_set_rate() local
297 unsigned long mul, div; in cdce706_divider_determine_rate() local
/linux/drivers/clk/bcm/
H A Dclk-kona.c50 static inline u64 scaled_div_value(struct bcm_clk_div *div, u32 reg_div) in scaled_div_value()
60 u64 scaled_div_build(struct bcm_clk_div *div, u32 div_value, u32 billionths) in scaled_div_build()
75 scaled_div_min(struct bcm_clk_div *div) in scaled_div_min()
84 u64 scaled_div_max(struct bcm_clk_div *div) in scaled_div_max()
101 divider(struct bcm_clk_div *div, u64 scaled_div) in divider()
111 scale_rate(struct bcm_clk_div *div, u32 rate) in scale_rate()
556 static u64 divider_read_scaled(struct ccu_data *ccu, struct bcm_clk_div *div) in divider_read_scaled()
584 struct bcm_clk_div *div, struct bcm_clk_trig *trig) in __div_commit()
640 struct bcm_clk_div *div, struct bcm_clk_trig *trig) in div_init()
648 struct bcm_clk_div *div, struct bcm_clk_trig *trig, in divider_write()
[all …]
H A Dclk-iproc-asiu.c22 struct iproc_asiu_div div; member
104 unsigned int div; in iproc_asiu_clk_round_rate() local
124 unsigned int div, div_h, div_l; in iproc_asiu_clk_set_rate() local
176 const struct iproc_asiu_div *div, in iproc_asiu_setup()
/linux/drivers/clk/mxs/
H A Dclk-div.c38 struct clk_div *div = to_clk_div(hw); in clk_div_recalc_rate() local
46 struct clk_div *div = to_clk_div(hw); in clk_div_round_rate() local
54 struct clk_div *div = to_clk_div(hw); in clk_div_set_rate() local
73 struct clk_div *div; in mxs_clk_div() local
H A Dclk-frac.c37 u32 div; in clk_frac_recalc_rate() local
52 u32 div; in clk_frac_round_rate() local
78 u32 div, val; in clk_frac_set_rate() local
/linux/drivers/clk/qcom/
H A Dclk-regmap-mux-div.c23 int mux_div_set_src_div(struct clk_regmap_mux_div *md, u32 src, u32 div) in mux_div_set_src_div()
60 u32 *div) in mux_div_get_src_div()
92 unsigned int i, div, max_div; in mux_div_determine_rate() local
129 u32 div, max_div, best_src = 0, best_div = 0; in __mux_div_set_rate_and_parent() local
167 u32 i, div, src = 0; in mux_div_get_parent() local
206 u32 div, src; in mux_div_recalc_rate() local
/linux/drivers/clk/sunxi/
H A Dclk-sunxi.c35 u8 div; in sun4i_get_pll1_factors() local
159 u8 div; in sun8i_a23_get_pll1_factors() local
203 u8 div; in sun4i_get_pll5_factors() local
230 u8 div; in sun6i_a31_get_pll6_factors() local
251 u32 div; in sun5i_a13_get_ahb_factors() local
290 u8 div, calcp, calcm = 1; in sun6i_get_ahb1_factors() local
348 int div; in sun4i_get_apb1_factors() local
386 u8 div, calcm, calcp; in sun7i_a20_get_out_factors() local
879 } div[SUNXI_DIVS_MAX_QTY]; member
H A Dclk-sun9i-cpus.c33 #define SUN9I_CPUS_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_DIV_MASK) | \ argument
39 #define SUN9I_CPUS_PLL4_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_PLL4_DIV_MASK) | \ argument
72 u8 div, pre_div = 1; in sun9i_a80_cpus_clk_round() local
154 u8 div, pre_div, parent; in sun9i_a80_cpus_clk_set_rate() local
/linux/drivers/gpu/drm/mcde/
H A Dmcde_clk_div.c47 int best_div = 1, div; in mcde_clk_div_choose_div() local
77 int div = mcde_clk_div_choose_div(hw, rate, prate, true); in mcde_clk_div_round_rate() local
88 int div; in mcde_clk_div_recalc_rate() local
113 int div = mcde_clk_div_choose_div(hw, rate, &prate, false); in mcde_clk_div_set_rate() local
/linux/drivers/clk/tegra/
H A Dclk-tegra20-emc.c58 u32 val, div; in emc_recalc_rate() local
76 u32 val, div; in emc_set_parent() local
106 u32 val, div; in emc_set_rate() local
139 u32 val, div; in emc_set_rate_and_parent() local
176 int div; in emc_determine_rate() local
H A Dclk-divider.c24 int div; in get_div() local
40 int div, mul; in clk_frac_div_recalc_rate() local
65 int div, mul; in clk_frac_div_round_rate() local
84 int div; in clk_frac_div_set_rate() local
/linux/drivers/clk/actions/
H A Dowl-divider.c29 struct owl_divider *div = hw_to_owl_divider(hw); in owl_divider_round_rate() local
55 struct owl_divider *div = hw_to_owl_divider(hw); in owl_divider_recalc_rate() local
84 struct owl_divider *div = hw_to_owl_divider(hw); in owl_divider_set_rate() local
/linux/drivers/clk/at91/
H A Dclk-master.c39 u8 div; member
87 u8 div; in clk_master_div_recalc_rate() local
118 unsigned int mckr, div; in clk_master_div_save_context() local
139 u8 div; in clk_master_div_restore_context() local
163 unsigned long parent_rate, int div) in clk_master_div_set()
255 unsigned int mckr, div, new_div = 0; in clk_master_div_notifier_fn() local
358 u32 div) in clk_sama7g5_master_best_diff()
593 unsigned int div, i; in clk_sama7g5_master_determine_rate() local
695 unsigned int div = master->div << MASTER_DIV_SHIFT; in clk_sama7g5_master_set() local
763 unsigned long div, flags; in clk_sama7g5_master_set_rate() local
/linux/drivers/clk/mvebu/
H A Dorion.c60 int *mult, int *div) in mv88f5181_get_clk_ratio()
128 int *mult, int *div) in mv88f5182_get_clk_ratio()
185 int *mult, int *div) in mv88f5281_get_clk_ratio()
251 int *mult, int *div) in mv88f6183_get_clk_ratio()
/linux/drivers/clk/socfpga/
H A Dclk-gate.c92 u32 div = 1, val; in socfpga_clk_get_div() local
113 u32 div = socfpga_clk_get_div(socfpgaclk); in socfpga_clk_recalc_rate() local
123 u32 div = socfpga_clk_get_div(socfpgaclk); in socfpga_clk_determine_rate() local
/linux/drivers/gpu/drm/pl111/
H A Dpl111_display.c449 int best_div = 1, div; in pl111_clk_div_choose_div() local
479 int div = pl111_clk_div_choose_div(hw, rate, prate, true); in pl111_clk_div_round_rate() local
490 int div; in pl111_clk_div_recalc_rate() local
508 int div = pl111_clk_div_choose_div(hw, rate, &prate, false); in pl111_clk_div_set_rate() local
540 struct clk_hw *div = &priv->clk_div; in pl111_init_clock_divider() local
/linux/drivers/media/pci/ttpci/
H A Dbudget.c204 u32 div = (c->frequency + 479500) / 125; in alps_bsrv2_tuner_set_params() local
244 u32 div; in alps_tdbe2_tuner_set_params() local
274 u32 div; in grundig_29504_401_tuner_set_params() local
332 u32 div; in grundig_29504_451_tuner_set_params() local
357 u32 div; in s5h1420_tuner_set_params() local

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