1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * libahci.c - Common AHCI SATA low-level routines
4 *
5 * Maintained by: Tejun Heo <tj@kernel.org>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2004-2005 Red Hat, Inc.
10 *
11 * libata documentation is available via 'make {ps|pdf}docs',
12 * as Documentation/driver-api/libata.rst
13 *
14 * AHCI hardware documentation:
15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
17 */
18
19 #include <linux/bitops.h>
20 #include <linux/kernel.h>
21 #include <linux/gfp.h>
22 #include <linux/module.h>
23 #include <linux/nospec.h>
24 #include <linux/blkdev.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/device.h>
29 #include <scsi/scsi_host.h>
30 #include <scsi/scsi_cmnd.h>
31 #include <linux/libata.h>
32 #include <linux/pci.h>
33 #include "ahci.h"
34 #include "libata.h"
35
36 static int ahci_skip_host_reset;
37 int ahci_ignore_sss;
38 EXPORT_SYMBOL_GPL(ahci_ignore_sss);
39
40 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
41 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
42
43 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
44 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
45
46 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
47 unsigned hints);
48 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
49 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
50 size_t size);
51 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
52 ssize_t size);
53
54
55
56 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
57 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
58 static void ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
59 static void ahci_qc_ncq_fill_rtf(struct ata_port *ap, u64 done_mask);
60 static int ahci_port_start(struct ata_port *ap);
61 static void ahci_port_stop(struct ata_port *ap);
62 static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc);
63 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
64 static void ahci_freeze(struct ata_port *ap);
65 static void ahci_thaw(struct ata_port *ap);
66 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
67 static void ahci_enable_fbs(struct ata_port *ap);
68 static void ahci_disable_fbs(struct ata_port *ap);
69 static void ahci_pmp_attach(struct ata_port *ap);
70 static void ahci_pmp_detach(struct ata_port *ap);
71 static int ahci_softreset(struct ata_link *link, unsigned int *class,
72 unsigned long deadline);
73 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
74 unsigned long deadline);
75 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
76 unsigned long deadline);
77 static void ahci_postreset(struct ata_link *link, unsigned int *class);
78 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
79 static void ahci_dev_config(struct ata_device *dev);
80 #ifdef CONFIG_PM
81 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
82 #endif
83 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
84 static ssize_t ahci_activity_store(struct ata_device *dev,
85 enum sw_activity val);
86 static void ahci_init_sw_activity(struct ata_link *link);
87
88 static ssize_t ahci_show_host_caps(struct device *dev,
89 struct device_attribute *attr, char *buf);
90 static ssize_t ahci_show_host_cap2(struct device *dev,
91 struct device_attribute *attr, char *buf);
92 static ssize_t ahci_show_host_version(struct device *dev,
93 struct device_attribute *attr, char *buf);
94 static ssize_t ahci_show_port_cmd(struct device *dev,
95 struct device_attribute *attr, char *buf);
96 static ssize_t ahci_read_em_buffer(struct device *dev,
97 struct device_attribute *attr, char *buf);
98 static ssize_t ahci_store_em_buffer(struct device *dev,
99 struct device_attribute *attr,
100 const char *buf, size_t size);
101 static ssize_t ahci_show_em_supported(struct device *dev,
102 struct device_attribute *attr, char *buf);
103 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance);
104
105 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
106 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
107 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
108 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
109 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
110 ahci_read_em_buffer, ahci_store_em_buffer);
111 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
112
113 static struct attribute *ahci_shost_attrs[] = {
114 &dev_attr_link_power_management_policy.attr,
115 &dev_attr_em_message_type.attr,
116 &dev_attr_em_message.attr,
117 &dev_attr_ahci_host_caps.attr,
118 &dev_attr_ahci_host_cap2.attr,
119 &dev_attr_ahci_host_version.attr,
120 &dev_attr_ahci_port_cmd.attr,
121 &dev_attr_em_buffer.attr,
122 &dev_attr_em_message_supported.attr,
123 NULL
124 };
125
126 static const struct attribute_group ahci_shost_attr_group = {
127 .attrs = ahci_shost_attrs
128 };
129
130 const struct attribute_group *ahci_shost_groups[] = {
131 &ahci_shost_attr_group,
132 NULL
133 };
134 EXPORT_SYMBOL_GPL(ahci_shost_groups);
135
136 static struct attribute *ahci_sdev_attrs[] = {
137 &dev_attr_sw_activity.attr,
138 &dev_attr_unload_heads.attr,
139 &dev_attr_ncq_prio_supported.attr,
140 &dev_attr_ncq_prio_enable.attr,
141 NULL
142 };
143
144 static const struct attribute_group ahci_sdev_attr_group = {
145 .attrs = ahci_sdev_attrs
146 };
147
148 const struct attribute_group *ahci_sdev_groups[] = {
149 &ahci_sdev_attr_group,
150 NULL
151 };
152 EXPORT_SYMBOL_GPL(ahci_sdev_groups);
153
154 struct ata_port_operations ahci_ops = {
155 .inherits = &sata_pmp_port_ops,
156
157 .qc_defer = ahci_pmp_qc_defer,
158 .qc_prep = ahci_qc_prep,
159 .qc_issue = ahci_qc_issue,
160 .qc_fill_rtf = ahci_qc_fill_rtf,
161 .qc_ncq_fill_rtf = ahci_qc_ncq_fill_rtf,
162
163 .freeze = ahci_freeze,
164 .thaw = ahci_thaw,
165 .softreset = ahci_softreset,
166 .hardreset = ahci_hardreset,
167 .postreset = ahci_postreset,
168 .pmp_softreset = ahci_softreset,
169 .error_handler = ahci_error_handler,
170 .post_internal_cmd = ahci_post_internal_cmd,
171 .dev_config = ahci_dev_config,
172
173 .scr_read = ahci_scr_read,
174 .scr_write = ahci_scr_write,
175 .pmp_attach = ahci_pmp_attach,
176 .pmp_detach = ahci_pmp_detach,
177
178 .set_lpm = ahci_set_lpm,
179 .em_show = ahci_led_show,
180 .em_store = ahci_led_store,
181 .sw_activity_show = ahci_activity_show,
182 .sw_activity_store = ahci_activity_store,
183 .transmit_led_message = ahci_transmit_led_message,
184 #ifdef CONFIG_PM
185 .port_suspend = ahci_port_suspend,
186 .port_resume = ahci_port_resume,
187 #endif
188 .port_start = ahci_port_start,
189 .port_stop = ahci_port_stop,
190 };
191 EXPORT_SYMBOL_GPL(ahci_ops);
192
193 struct ata_port_operations ahci_pmp_retry_srst_ops = {
194 .inherits = &ahci_ops,
195 .softreset = ahci_pmp_retry_softreset,
196 };
197 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
198
199 static bool ahci_em_messages __read_mostly = true;
200 module_param(ahci_em_messages, bool, 0444);
201 /* add other LED protocol types when they become supported */
202 MODULE_PARM_DESC(ahci_em_messages,
203 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
204
205 /* device sleep idle timeout in ms */
206 static int devslp_idle_timeout __read_mostly = 1000;
207 module_param(devslp_idle_timeout, int, 0644);
208 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
209
ahci_enable_ahci(void __iomem * mmio)210 static void ahci_enable_ahci(void __iomem *mmio)
211 {
212 int i;
213 u32 tmp;
214
215 /* turn on AHCI_EN */
216 tmp = readl(mmio + HOST_CTL);
217 if (tmp & HOST_AHCI_EN)
218 return;
219
220 /* Some controllers need AHCI_EN to be written multiple times.
221 * Try a few times before giving up.
222 */
223 for (i = 0; i < 5; i++) {
224 tmp |= HOST_AHCI_EN;
225 writel(tmp, mmio + HOST_CTL);
226 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
227 if (tmp & HOST_AHCI_EN)
228 return;
229 msleep(10);
230 }
231
232 WARN_ON(1);
233 }
234
235 /**
236 * ahci_rpm_get_port - Make sure the port is powered on
237 * @ap: Port to power on
238 *
239 * Whenever there is need to access the AHCI host registers outside of
240 * normal execution paths, call this function to make sure the host is
241 * actually powered on.
242 */
ahci_rpm_get_port(struct ata_port * ap)243 static int ahci_rpm_get_port(struct ata_port *ap)
244 {
245 return pm_runtime_get_sync(ap->dev);
246 }
247
248 /**
249 * ahci_rpm_put_port - Undoes ahci_rpm_get_port()
250 * @ap: Port to power down
251 *
252 * Undoes ahci_rpm_get_port() and possibly powers down the AHCI host
253 * if it has no more active users.
254 */
ahci_rpm_put_port(struct ata_port * ap)255 static void ahci_rpm_put_port(struct ata_port *ap)
256 {
257 pm_runtime_put(ap->dev);
258 }
259
ahci_show_host_caps(struct device * dev,struct device_attribute * attr,char * buf)260 static ssize_t ahci_show_host_caps(struct device *dev,
261 struct device_attribute *attr, char *buf)
262 {
263 struct Scsi_Host *shost = class_to_shost(dev);
264 struct ata_port *ap = ata_shost_to_port(shost);
265 struct ahci_host_priv *hpriv = ap->host->private_data;
266
267 return sprintf(buf, "%x\n", hpriv->cap);
268 }
269
ahci_show_host_cap2(struct device * dev,struct device_attribute * attr,char * buf)270 static ssize_t ahci_show_host_cap2(struct device *dev,
271 struct device_attribute *attr, char *buf)
272 {
273 struct Scsi_Host *shost = class_to_shost(dev);
274 struct ata_port *ap = ata_shost_to_port(shost);
275 struct ahci_host_priv *hpriv = ap->host->private_data;
276
277 return sprintf(buf, "%x\n", hpriv->cap2);
278 }
279
ahci_show_host_version(struct device * dev,struct device_attribute * attr,char * buf)280 static ssize_t ahci_show_host_version(struct device *dev,
281 struct device_attribute *attr, char *buf)
282 {
283 struct Scsi_Host *shost = class_to_shost(dev);
284 struct ata_port *ap = ata_shost_to_port(shost);
285 struct ahci_host_priv *hpriv = ap->host->private_data;
286
287 return sprintf(buf, "%x\n", hpriv->version);
288 }
289
ahci_show_port_cmd(struct device * dev,struct device_attribute * attr,char * buf)290 static ssize_t ahci_show_port_cmd(struct device *dev,
291 struct device_attribute *attr, char *buf)
292 {
293 struct Scsi_Host *shost = class_to_shost(dev);
294 struct ata_port *ap = ata_shost_to_port(shost);
295 void __iomem *port_mmio = ahci_port_base(ap);
296 ssize_t ret;
297
298 ahci_rpm_get_port(ap);
299 ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
300 ahci_rpm_put_port(ap);
301
302 return ret;
303 }
304
ahci_read_em_buffer(struct device * dev,struct device_attribute * attr,char * buf)305 static ssize_t ahci_read_em_buffer(struct device *dev,
306 struct device_attribute *attr, char *buf)
307 {
308 struct Scsi_Host *shost = class_to_shost(dev);
309 struct ata_port *ap = ata_shost_to_port(shost);
310 struct ahci_host_priv *hpriv = ap->host->private_data;
311 void __iomem *mmio = hpriv->mmio;
312 void __iomem *em_mmio = mmio + hpriv->em_loc;
313 u32 em_ctl, msg;
314 unsigned long flags;
315 size_t count;
316 int i;
317
318 ahci_rpm_get_port(ap);
319 spin_lock_irqsave(ap->lock, flags);
320
321 em_ctl = readl(mmio + HOST_EM_CTL);
322 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
323 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
324 spin_unlock_irqrestore(ap->lock, flags);
325 ahci_rpm_put_port(ap);
326 return -EINVAL;
327 }
328
329 if (!(em_ctl & EM_CTL_MR)) {
330 spin_unlock_irqrestore(ap->lock, flags);
331 ahci_rpm_put_port(ap);
332 return -EAGAIN;
333 }
334
335 if (!(em_ctl & EM_CTL_SMB))
336 em_mmio += hpriv->em_buf_sz;
337
338 count = hpriv->em_buf_sz;
339
340 /* the count should not be larger than PAGE_SIZE */
341 if (count > PAGE_SIZE) {
342 if (printk_ratelimit())
343 ata_port_warn(ap,
344 "EM read buffer size too large: "
345 "buffer size %u, page size %lu\n",
346 hpriv->em_buf_sz, PAGE_SIZE);
347 count = PAGE_SIZE;
348 }
349
350 for (i = 0; i < count; i += 4) {
351 msg = readl(em_mmio + i);
352 buf[i] = msg & 0xff;
353 buf[i + 1] = (msg >> 8) & 0xff;
354 buf[i + 2] = (msg >> 16) & 0xff;
355 buf[i + 3] = (msg >> 24) & 0xff;
356 }
357
358 spin_unlock_irqrestore(ap->lock, flags);
359 ahci_rpm_put_port(ap);
360
361 return i;
362 }
363
ahci_store_em_buffer(struct device * dev,struct device_attribute * attr,const char * buf,size_t size)364 static ssize_t ahci_store_em_buffer(struct device *dev,
365 struct device_attribute *attr,
366 const char *buf, size_t size)
367 {
368 struct Scsi_Host *shost = class_to_shost(dev);
369 struct ata_port *ap = ata_shost_to_port(shost);
370 struct ahci_host_priv *hpriv = ap->host->private_data;
371 void __iomem *mmio = hpriv->mmio;
372 void __iomem *em_mmio = mmio + hpriv->em_loc;
373 const unsigned char *msg_buf = buf;
374 u32 em_ctl, msg;
375 unsigned long flags;
376 int i;
377
378 /* check size validity */
379 if (!(ap->flags & ATA_FLAG_EM) ||
380 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
381 size % 4 || size > hpriv->em_buf_sz)
382 return -EINVAL;
383
384 ahci_rpm_get_port(ap);
385 spin_lock_irqsave(ap->lock, flags);
386
387 em_ctl = readl(mmio + HOST_EM_CTL);
388 if (em_ctl & EM_CTL_TM) {
389 spin_unlock_irqrestore(ap->lock, flags);
390 ahci_rpm_put_port(ap);
391 return -EBUSY;
392 }
393
394 for (i = 0; i < size; i += 4) {
395 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
396 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
397 writel(msg, em_mmio + i);
398 }
399
400 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
401
402 spin_unlock_irqrestore(ap->lock, flags);
403 ahci_rpm_put_port(ap);
404
405 return size;
406 }
407
ahci_show_em_supported(struct device * dev,struct device_attribute * attr,char * buf)408 static ssize_t ahci_show_em_supported(struct device *dev,
409 struct device_attribute *attr, char *buf)
410 {
411 struct Scsi_Host *shost = class_to_shost(dev);
412 struct ata_port *ap = ata_shost_to_port(shost);
413 struct ahci_host_priv *hpriv = ap->host->private_data;
414 void __iomem *mmio = hpriv->mmio;
415 u32 em_ctl;
416
417 ahci_rpm_get_port(ap);
418 em_ctl = readl(mmio + HOST_EM_CTL);
419 ahci_rpm_put_port(ap);
420
421 return sprintf(buf, "%s%s%s%s\n",
422 em_ctl & EM_CTL_LED ? "led " : "",
423 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
424 em_ctl & EM_CTL_SES ? "ses-2 " : "",
425 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
426 }
427
428 /**
429 * ahci_save_initial_config - Save and fixup initial config values
430 * @dev: target AHCI device
431 * @hpriv: host private area to store config values
432 *
433 * Some registers containing configuration info might be setup by
434 * BIOS and might be cleared on reset. This function saves the
435 * initial values of those registers into @hpriv such that they
436 * can be restored after controller reset.
437 *
438 * If inconsistent, config values are fixed up by this function.
439 *
440 * If it is not set already this function sets hpriv->start_engine to
441 * ahci_start_engine.
442 *
443 * LOCKING:
444 * None.
445 */
ahci_save_initial_config(struct device * dev,struct ahci_host_priv * hpriv)446 void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
447 {
448 void __iomem *mmio = hpriv->mmio;
449 void __iomem *port_mmio;
450 unsigned long port_map;
451 u32 cap, cap2, vers;
452 int i;
453
454 /* make sure AHCI mode is enabled before accessing CAP */
455 ahci_enable_ahci(mmio);
456
457 /*
458 * Values prefixed with saved_ are written back to the HBA and ports
459 * registers after reset. Values without are used for driver operation.
460 */
461
462 /*
463 * Override HW-init HBA capability fields with the platform-specific
464 * values. The rest of the HBA capabilities are defined as Read-only
465 * and can't be modified in CSR anyway.
466 */
467 cap = readl(mmio + HOST_CAP);
468 if (hpriv->saved_cap)
469 cap = (cap & ~(HOST_CAP_SSS | HOST_CAP_MPS)) | hpriv->saved_cap;
470 hpriv->saved_cap = cap;
471
472 /* CAP2 register is only defined for AHCI 1.2 and later */
473 vers = readl(mmio + HOST_VERSION);
474 if ((vers >> 16) > 1 ||
475 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
476 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
477 else
478 hpriv->saved_cap2 = cap2 = 0;
479
480 /* some chips have errata preventing 64bit use */
481 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
482 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
483 cap &= ~HOST_CAP_64;
484 }
485
486 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
487 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
488 cap &= ~HOST_CAP_NCQ;
489 }
490
491 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
492 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
493 cap |= HOST_CAP_NCQ;
494 }
495
496 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
497 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
498 cap &= ~HOST_CAP_PMP;
499 }
500
501 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
502 dev_info(dev,
503 "controller can't do SNTF, turning off CAP_SNTF\n");
504 cap &= ~HOST_CAP_SNTF;
505 }
506
507 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
508 dev_info(dev,
509 "controller can't do DEVSLP, turning off\n");
510 cap2 &= ~HOST_CAP2_SDS;
511 cap2 &= ~HOST_CAP2_SADM;
512 }
513
514 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
515 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
516 cap |= HOST_CAP_FBS;
517 }
518
519 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
520 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
521 cap &= ~HOST_CAP_FBS;
522 }
523
524 if (!(cap & HOST_CAP_ALPM) && (hpriv->flags & AHCI_HFLAG_YES_ALPM)) {
525 dev_info(dev, "controller can do ALPM, turning on CAP_ALPM\n");
526 cap |= HOST_CAP_ALPM;
527 }
528
529 if ((cap & HOST_CAP_SXS) && (hpriv->flags & AHCI_HFLAG_NO_SXS)) {
530 dev_info(dev, "controller does not support SXS, disabling CAP_SXS\n");
531 cap &= ~HOST_CAP_SXS;
532 }
533
534 /* Override the HBA ports mapping if the platform needs it */
535 port_map = readl(mmio + HOST_PORTS_IMPL);
536 if (hpriv->saved_port_map && port_map != hpriv->saved_port_map) {
537 dev_info(dev, "forcing port_map 0x%lx -> 0x%x\n",
538 port_map, hpriv->saved_port_map);
539 port_map = hpriv->saved_port_map;
540 } else {
541 hpriv->saved_port_map = port_map;
542 }
543
544 /* mask_port_map not set means that all ports are available */
545 if (hpriv->mask_port_map) {
546 dev_warn(dev, "masking port_map 0x%lx -> 0x%lx\n",
547 port_map,
548 port_map & hpriv->mask_port_map);
549 port_map &= hpriv->mask_port_map;
550 }
551
552 /* cross check port_map and cap.n_ports */
553 if (port_map) {
554 int map_ports = 0;
555
556 for (i = 0; i < AHCI_MAX_PORTS; i++)
557 if (port_map & (1 << i))
558 map_ports++;
559
560 /* If PI has more ports than n_ports, whine, clear
561 * port_map and let it be generated from n_ports.
562 */
563 if (map_ports > ahci_nr_ports(cap)) {
564 dev_warn(dev,
565 "implemented port map (0x%lx) contains more ports than nr_ports (%u), using nr_ports\n",
566 port_map, ahci_nr_ports(cap));
567 port_map = 0;
568 }
569 }
570
571 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
572 if (!port_map && vers < 0x10300) {
573 port_map = (1 << ahci_nr_ports(cap)) - 1;
574 dev_warn(dev, "forcing PORTS_IMPL to 0x%lx\n", port_map);
575
576 /* write the fixed up value to the PI register */
577 hpriv->saved_port_map = port_map;
578 }
579
580 /*
581 * Preserve the ports capabilities defined by the platform. Note there
582 * is no need in storing the rest of the P#.CMD fields since they are
583 * volatile.
584 */
585 for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) {
586 if (hpriv->saved_port_cap[i])
587 continue;
588
589 port_mmio = __ahci_port_base(hpriv, i);
590 hpriv->saved_port_cap[i] =
591 readl(port_mmio + PORT_CMD) & PORT_CMD_CAP;
592 }
593
594 /* record values to use during operation */
595 hpriv->cap = cap;
596 hpriv->cap2 = cap2;
597 hpriv->version = vers;
598 hpriv->port_map = port_map;
599
600 if (!hpriv->start_engine)
601 hpriv->start_engine = ahci_start_engine;
602
603 if (!hpriv->stop_engine)
604 hpriv->stop_engine = ahci_stop_engine;
605
606 if (!hpriv->irq_handler)
607 hpriv->irq_handler = ahci_single_level_irq_intr;
608 }
609 EXPORT_SYMBOL_GPL(ahci_save_initial_config);
610
611 /**
612 * ahci_restore_initial_config - Restore initial config
613 * @host: target ATA host
614 *
615 * Restore initial config stored by ahci_save_initial_config().
616 *
617 * LOCKING:
618 * None.
619 */
ahci_restore_initial_config(struct ata_host * host)620 static void ahci_restore_initial_config(struct ata_host *host)
621 {
622 struct ahci_host_priv *hpriv = host->private_data;
623 unsigned long port_map = hpriv->port_map;
624 void __iomem *mmio = hpriv->mmio;
625 void __iomem *port_mmio;
626 int i;
627
628 writel(hpriv->saved_cap, mmio + HOST_CAP);
629 if (hpriv->saved_cap2)
630 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
631 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
632 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
633
634 for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) {
635 port_mmio = __ahci_port_base(hpriv, i);
636 writel(hpriv->saved_port_cap[i], port_mmio + PORT_CMD);
637 }
638 }
639
ahci_scr_offset(struct ata_port * ap,unsigned int sc_reg)640 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
641 {
642 static const int offset[] = {
643 [SCR_STATUS] = PORT_SCR_STAT,
644 [SCR_CONTROL] = PORT_SCR_CTL,
645 [SCR_ERROR] = PORT_SCR_ERR,
646 [SCR_ACTIVE] = PORT_SCR_ACT,
647 [SCR_NOTIFICATION] = PORT_SCR_NTF,
648 };
649 struct ahci_host_priv *hpriv = ap->host->private_data;
650
651 if (sc_reg < ARRAY_SIZE(offset) &&
652 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
653 return offset[sc_reg];
654 return 0;
655 }
656
ahci_scr_read(struct ata_link * link,unsigned int sc_reg,u32 * val)657 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
658 {
659 void __iomem *port_mmio = ahci_port_base(link->ap);
660 int offset = ahci_scr_offset(link->ap, sc_reg);
661
662 if (offset) {
663 *val = readl(port_mmio + offset);
664 return 0;
665 }
666 return -EINVAL;
667 }
668
ahci_scr_write(struct ata_link * link,unsigned int sc_reg,u32 val)669 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
670 {
671 void __iomem *port_mmio = ahci_port_base(link->ap);
672 int offset = ahci_scr_offset(link->ap, sc_reg);
673
674 if (offset) {
675 writel(val, port_mmio + offset);
676 return 0;
677 }
678 return -EINVAL;
679 }
680
ahci_start_engine(struct ata_port * ap)681 void ahci_start_engine(struct ata_port *ap)
682 {
683 void __iomem *port_mmio = ahci_port_base(ap);
684 u32 tmp;
685
686 /* start DMA */
687 tmp = readl(port_mmio + PORT_CMD);
688 tmp |= PORT_CMD_START;
689 writel(tmp, port_mmio + PORT_CMD);
690 readl(port_mmio + PORT_CMD); /* flush */
691 }
692 EXPORT_SYMBOL_GPL(ahci_start_engine);
693
ahci_stop_engine(struct ata_port * ap)694 int ahci_stop_engine(struct ata_port *ap)
695 {
696 void __iomem *port_mmio = ahci_port_base(ap);
697 struct ahci_host_priv *hpriv = ap->host->private_data;
698 u32 tmp;
699
700 /*
701 * On some controllers, stopping a port's DMA engine while the port
702 * is in ALPM state (partial or slumber) results in failures on
703 * subsequent DMA engine starts. For those controllers, put the
704 * port back in active state before stopping its DMA engine.
705 */
706 if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) &&
707 (ap->link.lpm_policy > ATA_LPM_MAX_POWER) &&
708 ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) {
709 dev_err(ap->host->dev, "Failed to wake up port before engine stop\n");
710 return -EIO;
711 }
712
713 tmp = readl(port_mmio + PORT_CMD);
714
715 /* check if the HBA is idle */
716 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
717 return 0;
718
719 /*
720 * Don't try to issue commands but return with ENODEV if the
721 * AHCI controller not available anymore (e.g. due to PCIe hot
722 * unplugging). Otherwise a 500ms delay for each port is added.
723 */
724 if (tmp == 0xffffffff) {
725 dev_err(ap->host->dev, "AHCI controller unavailable!\n");
726 return -ENODEV;
727 }
728
729 /* setting HBA to idle */
730 tmp &= ~PORT_CMD_START;
731 writel(tmp, port_mmio + PORT_CMD);
732
733 /* wait for engine to stop. This could be as long as 500 msec */
734 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
735 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
736 if (tmp & PORT_CMD_LIST_ON)
737 return -EIO;
738
739 return 0;
740 }
741 EXPORT_SYMBOL_GPL(ahci_stop_engine);
742
ahci_start_fis_rx(struct ata_port * ap)743 void ahci_start_fis_rx(struct ata_port *ap)
744 {
745 void __iomem *port_mmio = ahci_port_base(ap);
746 struct ahci_host_priv *hpriv = ap->host->private_data;
747 struct ahci_port_priv *pp = ap->private_data;
748 u32 tmp;
749
750 /* set FIS registers */
751 if (hpriv->cap & HOST_CAP_64)
752 writel((pp->cmd_slot_dma >> 16) >> 16,
753 port_mmio + PORT_LST_ADDR_HI);
754 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
755
756 if (hpriv->cap & HOST_CAP_64)
757 writel((pp->rx_fis_dma >> 16) >> 16,
758 port_mmio + PORT_FIS_ADDR_HI);
759 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
760
761 /* enable FIS reception */
762 tmp = readl(port_mmio + PORT_CMD);
763 tmp |= PORT_CMD_FIS_RX;
764 writel(tmp, port_mmio + PORT_CMD);
765
766 /* flush */
767 readl(port_mmio + PORT_CMD);
768 }
769 EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
770
ahci_stop_fis_rx(struct ata_port * ap)771 static int ahci_stop_fis_rx(struct ata_port *ap)
772 {
773 void __iomem *port_mmio = ahci_port_base(ap);
774 u32 tmp;
775
776 /* disable FIS reception */
777 tmp = readl(port_mmio + PORT_CMD);
778 tmp &= ~PORT_CMD_FIS_RX;
779 writel(tmp, port_mmio + PORT_CMD);
780
781 /* wait for completion, spec says 500ms, give it 1000 */
782 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
783 PORT_CMD_FIS_ON, 10, 1000);
784 if (tmp & PORT_CMD_FIS_ON)
785 return -EBUSY;
786
787 return 0;
788 }
789
ahci_power_up(struct ata_port * ap)790 static void ahci_power_up(struct ata_port *ap)
791 {
792 struct ahci_host_priv *hpriv = ap->host->private_data;
793 void __iomem *port_mmio = ahci_port_base(ap);
794 u32 cmd;
795
796 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
797
798 /* spin up device */
799 if (hpriv->cap & HOST_CAP_SSS) {
800 cmd |= PORT_CMD_SPIN_UP;
801 writel(cmd, port_mmio + PORT_CMD);
802 }
803
804 /* wake up link */
805 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
806 }
807
ahci_set_lpm(struct ata_link * link,enum ata_lpm_policy policy,unsigned int hints)808 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
809 unsigned int hints)
810 {
811 struct ata_port *ap = link->ap;
812 struct ahci_host_priv *hpriv = ap->host->private_data;
813 struct ahci_port_priv *pp = ap->private_data;
814 void __iomem *port_mmio = ahci_port_base(ap);
815
816 if (policy != ATA_LPM_MAX_POWER) {
817 /* wakeup flag only applies to the max power policy */
818 hints &= ~ATA_LPM_WAKE_ONLY;
819
820 /*
821 * Disable interrupts on Phy Ready. This keeps us from
822 * getting woken up due to spurious phy ready
823 * interrupts.
824 */
825 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
826 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
827
828 sata_link_scr_lpm(link, policy, false);
829 }
830
831 if (hpriv->cap & HOST_CAP_ALPM) {
832 u32 cmd = readl(port_mmio + PORT_CMD);
833
834 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
835 if (!(hints & ATA_LPM_WAKE_ONLY))
836 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
837 cmd |= PORT_CMD_ICC_ACTIVE;
838
839 writel(cmd, port_mmio + PORT_CMD);
840 readl(port_mmio + PORT_CMD);
841
842 /* wait 10ms to be sure we've come out of LPM state */
843 ata_msleep(ap, 10);
844
845 if (hints & ATA_LPM_WAKE_ONLY)
846 return 0;
847 } else {
848 cmd |= PORT_CMD_ALPE;
849 if (policy == ATA_LPM_MIN_POWER)
850 cmd |= PORT_CMD_ASP;
851 else if (policy == ATA_LPM_MIN_POWER_WITH_PARTIAL)
852 cmd &= ~PORT_CMD_ASP;
853
854 /* write out new cmd value */
855 writel(cmd, port_mmio + PORT_CMD);
856 }
857 }
858
859 /* set aggressive device sleep */
860 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
861 (hpriv->cap2 & HOST_CAP2_SADM) &&
862 (link->device->flags & ATA_DFLAG_DEVSLP)) {
863 if (policy == ATA_LPM_MIN_POWER ||
864 policy == ATA_LPM_MIN_POWER_WITH_PARTIAL)
865 ahci_set_aggressive_devslp(ap, true);
866 else
867 ahci_set_aggressive_devslp(ap, false);
868 }
869
870 if (policy == ATA_LPM_MAX_POWER) {
871 sata_link_scr_lpm(link, policy, false);
872
873 /* turn PHYRDY IRQ back on */
874 pp->intr_mask |= PORT_IRQ_PHYRDY;
875 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
876 }
877
878 return 0;
879 }
880
881 #ifdef CONFIG_PM
ahci_power_down(struct ata_port * ap)882 static void ahci_power_down(struct ata_port *ap)
883 {
884 struct ahci_host_priv *hpriv = ap->host->private_data;
885 void __iomem *port_mmio = ahci_port_base(ap);
886 u32 cmd, scontrol;
887
888 if (!(hpriv->cap & HOST_CAP_SSS))
889 return;
890
891 /* put device into listen mode, first set PxSCTL.DET to 0 */
892 scontrol = readl(port_mmio + PORT_SCR_CTL);
893 scontrol &= ~0xf;
894 writel(scontrol, port_mmio + PORT_SCR_CTL);
895
896 /* then set PxCMD.SUD to 0 */
897 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
898 cmd &= ~PORT_CMD_SPIN_UP;
899 writel(cmd, port_mmio + PORT_CMD);
900 }
901 #endif
902
ahci_start_port(struct ata_port * ap)903 static void ahci_start_port(struct ata_port *ap)
904 {
905 struct ahci_host_priv *hpriv = ap->host->private_data;
906 struct ahci_port_priv *pp = ap->private_data;
907 struct ata_link *link;
908 struct ahci_em_priv *emp;
909 ssize_t rc;
910 int i;
911
912 /* enable FIS reception */
913 ahci_start_fis_rx(ap);
914
915 /* enable DMA */
916 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
917 hpriv->start_engine(ap);
918
919 /* turn on LEDs */
920 if (ap->flags & ATA_FLAG_EM) {
921 ata_for_each_link(link, ap, EDGE) {
922 emp = &pp->em_priv[link->pmp];
923
924 /* EM Transmit bit maybe busy during init */
925 for (i = 0; i < EM_MAX_RETRY; i++) {
926 rc = ap->ops->transmit_led_message(ap,
927 emp->led_state,
928 4);
929 /*
930 * If busy, give a breather but do not
931 * release EH ownership by using msleep()
932 * instead of ata_msleep(). EM Transmit
933 * bit is busy for the whole host and
934 * releasing ownership will cause other
935 * ports to fail the same way.
936 */
937 if (rc == -EBUSY)
938 msleep(1);
939 else
940 break;
941 }
942 }
943 }
944
945 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
946 ata_for_each_link(link, ap, EDGE)
947 ahci_init_sw_activity(link);
948
949 }
950
ahci_deinit_port(struct ata_port * ap,const char ** emsg)951 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
952 {
953 int rc;
954 struct ahci_host_priv *hpriv = ap->host->private_data;
955
956 /* disable DMA */
957 rc = hpriv->stop_engine(ap);
958 if (rc) {
959 *emsg = "failed to stop engine";
960 return rc;
961 }
962
963 /* disable FIS reception */
964 rc = ahci_stop_fis_rx(ap);
965 if (rc) {
966 *emsg = "failed stop FIS RX";
967 return rc;
968 }
969
970 return 0;
971 }
972
ahci_reset_controller(struct ata_host * host)973 int ahci_reset_controller(struct ata_host *host)
974 {
975 struct ahci_host_priv *hpriv = host->private_data;
976 void __iomem *mmio = hpriv->mmio;
977 u32 tmp;
978
979 /*
980 * We must be in AHCI mode, before using anything AHCI-specific, such
981 * as HOST_RESET.
982 */
983 ahci_enable_ahci(mmio);
984
985 /* Global controller reset */
986 if (ahci_skip_host_reset) {
987 dev_info(host->dev, "Skipping global host reset\n");
988 return 0;
989 }
990
991 tmp = readl(mmio + HOST_CTL);
992 if (!(tmp & HOST_RESET)) {
993 writel(tmp | HOST_RESET, mmio + HOST_CTL);
994 readl(mmio + HOST_CTL); /* flush */
995 }
996
997 /*
998 * To perform host reset, OS should set HOST_RESET and poll until this
999 * bit is read to be "0". Reset must complete within 1 second, or the
1000 * hardware should be considered fried.
1001 */
1002 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
1003 HOST_RESET, 10, 1000);
1004 if (tmp & HOST_RESET) {
1005 dev_err(host->dev, "Controller reset failed (0x%x)\n",
1006 tmp);
1007 return -EIO;
1008 }
1009
1010 /* Turn on AHCI mode */
1011 ahci_enable_ahci(mmio);
1012
1013 /* Some registers might be cleared on reset. Restore initial values. */
1014 if (!(hpriv->flags & AHCI_HFLAG_NO_WRITE_TO_RO))
1015 ahci_restore_initial_config(host);
1016
1017 return 0;
1018 }
1019 EXPORT_SYMBOL_GPL(ahci_reset_controller);
1020
ahci_sw_activity(struct ata_link * link)1021 static void ahci_sw_activity(struct ata_link *link)
1022 {
1023 struct ata_port *ap = link->ap;
1024 struct ahci_port_priv *pp = ap->private_data;
1025 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1026
1027 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
1028 return;
1029
1030 emp->activity++;
1031 if (!timer_pending(&emp->timer))
1032 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
1033 }
1034
ahci_sw_activity_blink(struct timer_list * t)1035 static void ahci_sw_activity_blink(struct timer_list *t)
1036 {
1037 struct ahci_em_priv *emp = from_timer(emp, t, timer);
1038 struct ata_link *link = emp->link;
1039 struct ata_port *ap = link->ap;
1040
1041 unsigned long led_message = emp->led_state;
1042 u32 activity_led_state;
1043 unsigned long flags;
1044
1045 led_message &= EM_MSG_LED_VALUE;
1046 led_message |= ap->port_no | (link->pmp << 8);
1047
1048 /* check to see if we've had activity. If so,
1049 * toggle state of LED and reset timer. If not,
1050 * turn LED to desired idle state.
1051 */
1052 spin_lock_irqsave(ap->lock, flags);
1053 if (emp->saved_activity != emp->activity) {
1054 emp->saved_activity = emp->activity;
1055 /* get the current LED state */
1056 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
1057
1058 if (activity_led_state)
1059 activity_led_state = 0;
1060 else
1061 activity_led_state = 1;
1062
1063 /* clear old state */
1064 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1065
1066 /* toggle state */
1067 led_message |= (activity_led_state << 16);
1068 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1069 } else {
1070 /* switch to idle */
1071 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1072 if (emp->blink_policy == BLINK_OFF)
1073 led_message |= (1 << 16);
1074 }
1075 spin_unlock_irqrestore(ap->lock, flags);
1076 ap->ops->transmit_led_message(ap, led_message, 4);
1077 }
1078
ahci_init_sw_activity(struct ata_link * link)1079 static void ahci_init_sw_activity(struct ata_link *link)
1080 {
1081 struct ata_port *ap = link->ap;
1082 struct ahci_port_priv *pp = ap->private_data;
1083 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1084
1085 /* init activity stats, setup timer */
1086 emp->saved_activity = emp->activity = 0;
1087 emp->link = link;
1088 timer_setup(&emp->timer, ahci_sw_activity_blink, 0);
1089
1090 /* check our blink policy and set flag for link if it's enabled */
1091 if (emp->blink_policy)
1092 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1093 }
1094
ahci_reset_em(struct ata_host * host)1095 int ahci_reset_em(struct ata_host *host)
1096 {
1097 struct ahci_host_priv *hpriv = host->private_data;
1098 void __iomem *mmio = hpriv->mmio;
1099 u32 em_ctl;
1100
1101 em_ctl = readl(mmio + HOST_EM_CTL);
1102 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1103 return -EINVAL;
1104
1105 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1106 return 0;
1107 }
1108 EXPORT_SYMBOL_GPL(ahci_reset_em);
1109
ahci_transmit_led_message(struct ata_port * ap,u32 state,ssize_t size)1110 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1111 ssize_t size)
1112 {
1113 struct ahci_host_priv *hpriv = ap->host->private_data;
1114 struct ahci_port_priv *pp = ap->private_data;
1115 void __iomem *mmio = hpriv->mmio;
1116 u32 em_ctl;
1117 u32 message[] = {0, 0};
1118 unsigned long flags;
1119 int pmp;
1120 struct ahci_em_priv *emp;
1121
1122 /* get the slot number from the message */
1123 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1124 if (pmp < EM_MAX_SLOTS)
1125 emp = &pp->em_priv[pmp];
1126 else
1127 return -EINVAL;
1128
1129 ahci_rpm_get_port(ap);
1130 spin_lock_irqsave(ap->lock, flags);
1131
1132 /*
1133 * if we are still busy transmitting a previous message,
1134 * do not allow
1135 */
1136 em_ctl = readl(mmio + HOST_EM_CTL);
1137 if (em_ctl & EM_CTL_TM) {
1138 spin_unlock_irqrestore(ap->lock, flags);
1139 ahci_rpm_put_port(ap);
1140 return -EBUSY;
1141 }
1142
1143 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1144 /*
1145 * create message header - this is all zero except for
1146 * the message size, which is 4 bytes.
1147 */
1148 message[0] |= (4 << 8);
1149
1150 /* ignore 0:4 of byte zero, fill in port info yourself */
1151 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1152
1153 /* write message to EM_LOC */
1154 writel(message[0], mmio + hpriv->em_loc);
1155 writel(message[1], mmio + hpriv->em_loc+4);
1156
1157 /*
1158 * tell hardware to transmit the message
1159 */
1160 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1161 }
1162
1163 /* save off new led state for port/slot */
1164 emp->led_state = state;
1165
1166 spin_unlock_irqrestore(ap->lock, flags);
1167 ahci_rpm_put_port(ap);
1168
1169 return size;
1170 }
1171
ahci_led_show(struct ata_port * ap,char * buf)1172 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1173 {
1174 struct ahci_port_priv *pp = ap->private_data;
1175 struct ata_link *link;
1176 struct ahci_em_priv *emp;
1177 int rc = 0;
1178
1179 ata_for_each_link(link, ap, EDGE) {
1180 emp = &pp->em_priv[link->pmp];
1181 rc += sprintf(buf, "%lx\n", emp->led_state);
1182 }
1183 return rc;
1184 }
1185
ahci_led_store(struct ata_port * ap,const char * buf,size_t size)1186 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1187 size_t size)
1188 {
1189 unsigned int state;
1190 int pmp;
1191 struct ahci_port_priv *pp = ap->private_data;
1192 struct ahci_em_priv *emp;
1193
1194 if (kstrtouint(buf, 0, &state) < 0)
1195 return -EINVAL;
1196
1197 /* get the slot number from the message */
1198 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1199 if (pmp < EM_MAX_SLOTS) {
1200 pmp = array_index_nospec(pmp, EM_MAX_SLOTS);
1201 emp = &pp->em_priv[pmp];
1202 } else {
1203 return -EINVAL;
1204 }
1205
1206 /* mask off the activity bits if we are in sw_activity
1207 * mode, user should turn off sw_activity before setting
1208 * activity led through em_message
1209 */
1210 if (emp->blink_policy)
1211 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1212
1213 return ap->ops->transmit_led_message(ap, state, size);
1214 }
1215
ahci_activity_store(struct ata_device * dev,enum sw_activity val)1216 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1217 {
1218 struct ata_link *link = dev->link;
1219 struct ata_port *ap = link->ap;
1220 struct ahci_port_priv *pp = ap->private_data;
1221 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1222 u32 port_led_state = emp->led_state;
1223
1224 /* save the desired Activity LED behavior */
1225 if (val == OFF) {
1226 /* clear LFLAG */
1227 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1228
1229 /* set the LED to OFF */
1230 port_led_state &= EM_MSG_LED_VALUE_OFF;
1231 port_led_state |= (ap->port_no | (link->pmp << 8));
1232 ap->ops->transmit_led_message(ap, port_led_state, 4);
1233 } else {
1234 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1235 if (val == BLINK_OFF) {
1236 /* set LED to ON for idle */
1237 port_led_state &= EM_MSG_LED_VALUE_OFF;
1238 port_led_state |= (ap->port_no | (link->pmp << 8));
1239 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1240 ap->ops->transmit_led_message(ap, port_led_state, 4);
1241 }
1242 }
1243 emp->blink_policy = val;
1244 return 0;
1245 }
1246
ahci_activity_show(struct ata_device * dev,char * buf)1247 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1248 {
1249 struct ata_link *link = dev->link;
1250 struct ata_port *ap = link->ap;
1251 struct ahci_port_priv *pp = ap->private_data;
1252 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1253
1254 /* display the saved value of activity behavior for this
1255 * disk.
1256 */
1257 return sprintf(buf, "%d\n", emp->blink_policy);
1258 }
1259
ahci_port_clear_pending_irq(struct ata_port * ap)1260 static void ahci_port_clear_pending_irq(struct ata_port *ap)
1261 {
1262 struct ahci_host_priv *hpriv = ap->host->private_data;
1263 void __iomem *port_mmio = ahci_port_base(ap);
1264 u32 tmp;
1265
1266 /* clear SError */
1267 tmp = readl(port_mmio + PORT_SCR_ERR);
1268 dev_dbg(ap->host->dev, "PORT_SCR_ERR 0x%x\n", tmp);
1269 writel(tmp, port_mmio + PORT_SCR_ERR);
1270
1271 /* clear port IRQ */
1272 tmp = readl(port_mmio + PORT_IRQ_STAT);
1273 dev_dbg(ap->host->dev, "PORT_IRQ_STAT 0x%x\n", tmp);
1274 if (tmp)
1275 writel(tmp, port_mmio + PORT_IRQ_STAT);
1276
1277 writel(1 << ap->port_no, hpriv->mmio + HOST_IRQ_STAT);
1278 }
1279
ahci_port_init(struct device * dev,struct ata_port * ap,int port_no,void __iomem * mmio,void __iomem * port_mmio)1280 static void ahci_port_init(struct device *dev, struct ata_port *ap,
1281 int port_no, void __iomem *mmio,
1282 void __iomem *port_mmio)
1283 {
1284 const char *emsg = NULL;
1285 int rc;
1286
1287 /* make sure port is not active */
1288 rc = ahci_deinit_port(ap, &emsg);
1289 if (rc)
1290 dev_warn(dev, "%s (%d)\n", emsg, rc);
1291
1292 ahci_port_clear_pending_irq(ap);
1293 }
1294
ahci_init_controller(struct ata_host * host)1295 void ahci_init_controller(struct ata_host *host)
1296 {
1297 struct ahci_host_priv *hpriv = host->private_data;
1298 void __iomem *mmio = hpriv->mmio;
1299 int i;
1300 void __iomem *port_mmio;
1301 u32 tmp;
1302
1303 for (i = 0; i < host->n_ports; i++) {
1304 struct ata_port *ap = host->ports[i];
1305
1306 port_mmio = ahci_port_base(ap);
1307 if (ata_port_is_dummy(ap))
1308 continue;
1309
1310 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1311 }
1312
1313 tmp = readl(mmio + HOST_CTL);
1314 dev_dbg(host->dev, "HOST_CTL 0x%x\n", tmp);
1315 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1316 tmp = readl(mmio + HOST_CTL);
1317 dev_dbg(host->dev, "HOST_CTL 0x%x\n", tmp);
1318 }
1319 EXPORT_SYMBOL_GPL(ahci_init_controller);
1320
ahci_dev_config(struct ata_device * dev)1321 static void ahci_dev_config(struct ata_device *dev)
1322 {
1323 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1324
1325 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1326 dev->max_sectors = 255;
1327 ata_dev_info(dev,
1328 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1329 }
1330 }
1331
ahci_dev_classify(struct ata_port * ap)1332 unsigned int ahci_dev_classify(struct ata_port *ap)
1333 {
1334 void __iomem *port_mmio = ahci_port_base(ap);
1335 struct ata_taskfile tf;
1336 u32 tmp;
1337
1338 tmp = readl(port_mmio + PORT_SIG);
1339 tf.lbah = (tmp >> 24) & 0xff;
1340 tf.lbam = (tmp >> 16) & 0xff;
1341 tf.lbal = (tmp >> 8) & 0xff;
1342 tf.nsect = (tmp) & 0xff;
1343
1344 return ata_port_classify(ap, &tf);
1345 }
1346 EXPORT_SYMBOL_GPL(ahci_dev_classify);
1347
ahci_fill_cmd_slot(struct ahci_port_priv * pp,unsigned int tag,u32 opts)1348 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1349 u32 opts)
1350 {
1351 dma_addr_t cmd_tbl_dma;
1352
1353 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1354
1355 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1356 pp->cmd_slot[tag].status = 0;
1357 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1358 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1359 }
1360 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
1361
ahci_kick_engine(struct ata_port * ap)1362 int ahci_kick_engine(struct ata_port *ap)
1363 {
1364 void __iomem *port_mmio = ahci_port_base(ap);
1365 struct ahci_host_priv *hpriv = ap->host->private_data;
1366 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1367 u32 tmp;
1368 int busy, rc;
1369
1370 /* stop engine */
1371 rc = hpriv->stop_engine(ap);
1372 if (rc)
1373 goto out_restart;
1374
1375 /* need to do CLO?
1376 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1377 */
1378 busy = status & (ATA_BUSY | ATA_DRQ);
1379 if (!busy && !sata_pmp_attached(ap)) {
1380 rc = 0;
1381 goto out_restart;
1382 }
1383
1384 if (!(hpriv->cap & HOST_CAP_CLO)) {
1385 rc = -EOPNOTSUPP;
1386 goto out_restart;
1387 }
1388
1389 /* perform CLO */
1390 tmp = readl(port_mmio + PORT_CMD);
1391 tmp |= PORT_CMD_CLO;
1392 writel(tmp, port_mmio + PORT_CMD);
1393
1394 rc = 0;
1395 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
1396 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1397 if (tmp & PORT_CMD_CLO)
1398 rc = -EIO;
1399
1400 /* restart engine */
1401 out_restart:
1402 hpriv->start_engine(ap);
1403 return rc;
1404 }
1405 EXPORT_SYMBOL_GPL(ahci_kick_engine);
1406
ahci_exec_polled_cmd(struct ata_port * ap,int pmp,struct ata_taskfile * tf,int is_cmd,u16 flags,unsigned int timeout_msec)1407 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1408 struct ata_taskfile *tf, int is_cmd, u16 flags,
1409 unsigned int timeout_msec)
1410 {
1411 const u32 cmd_fis_len = 5; /* five dwords */
1412 struct ahci_port_priv *pp = ap->private_data;
1413 void __iomem *port_mmio = ahci_port_base(ap);
1414 u8 *fis = pp->cmd_tbl;
1415 u32 tmp;
1416
1417 /* prep the command */
1418 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1419 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1420
1421 /* set port value for softreset of Port Multiplier */
1422 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) {
1423 tmp = readl(port_mmio + PORT_FBS);
1424 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1425 tmp |= pmp << PORT_FBS_DEV_OFFSET;
1426 writel(tmp, port_mmio + PORT_FBS);
1427 pp->fbs_last_dev = pmp;
1428 }
1429
1430 /* issue & wait */
1431 writel(1, port_mmio + PORT_CMD_ISSUE);
1432
1433 if (timeout_msec) {
1434 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1435 0x1, 0x1, 1, timeout_msec);
1436 if (tmp & 0x1) {
1437 ahci_kick_engine(ap);
1438 return -EBUSY;
1439 }
1440 } else
1441 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1442
1443 return 0;
1444 }
1445
ahci_do_softreset(struct ata_link * link,unsigned int * class,int pmp,unsigned long deadline,int (* check_ready)(struct ata_link * link))1446 int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1447 int pmp, unsigned long deadline,
1448 int (*check_ready)(struct ata_link *link))
1449 {
1450 struct ata_port *ap = link->ap;
1451 struct ahci_host_priv *hpriv = ap->host->private_data;
1452 struct ahci_port_priv *pp = ap->private_data;
1453 const char *reason = NULL;
1454 unsigned long now;
1455 unsigned int msecs;
1456 struct ata_taskfile tf;
1457 bool fbs_disabled = false;
1458 int rc;
1459
1460 /* prepare for SRST (AHCI-1.1 10.4.1) */
1461 rc = ahci_kick_engine(ap);
1462 if (rc && rc != -EOPNOTSUPP)
1463 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
1464
1465 /*
1466 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1467 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1468 * that is attached to port multiplier.
1469 */
1470 if (!ata_is_host_link(link) && pp->fbs_enabled) {
1471 ahci_disable_fbs(ap);
1472 fbs_disabled = true;
1473 }
1474
1475 ata_tf_init(link->device, &tf);
1476
1477 /* issue the first H2D Register FIS */
1478 msecs = 0;
1479 now = jiffies;
1480 if (time_after(deadline, now))
1481 msecs = jiffies_to_msecs(deadline - now);
1482
1483 tf.ctl |= ATA_SRST;
1484 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1485 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1486 rc = -EIO;
1487 reason = "1st FIS failed";
1488 goto fail;
1489 }
1490
1491 /* spec says at least 5us, but be generous and sleep for 1ms */
1492 ata_msleep(ap, 1);
1493
1494 /* issue the second H2D Register FIS */
1495 tf.ctl &= ~ATA_SRST;
1496 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1497
1498 /* wait for link to become ready */
1499 rc = ata_wait_after_reset(link, deadline, check_ready);
1500 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1501 /*
1502 * Workaround for cases where link online status can't
1503 * be trusted. Treat device readiness timeout as link
1504 * offline.
1505 */
1506 ata_link_info(link, "device not ready, treating as offline\n");
1507 *class = ATA_DEV_NONE;
1508 } else if (rc) {
1509 /* link occupied, -ENODEV too is an error */
1510 reason = "device not ready";
1511 goto fail;
1512 } else
1513 *class = ahci_dev_classify(ap);
1514
1515 /* re-enable FBS if disabled before */
1516 if (fbs_disabled)
1517 ahci_enable_fbs(ap);
1518
1519 return 0;
1520
1521 fail:
1522 ata_link_err(link, "softreset failed (%s)\n", reason);
1523 return rc;
1524 }
1525
ahci_check_ready(struct ata_link * link)1526 int ahci_check_ready(struct ata_link *link)
1527 {
1528 void __iomem *port_mmio = ahci_port_base(link->ap);
1529 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1530
1531 return ata_check_ready(status);
1532 }
1533 EXPORT_SYMBOL_GPL(ahci_check_ready);
1534
ahci_softreset(struct ata_link * link,unsigned int * class,unsigned long deadline)1535 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1536 unsigned long deadline)
1537 {
1538 int pmp = sata_srst_pmp(link);
1539
1540 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1541 }
1542 EXPORT_SYMBOL_GPL(ahci_do_softreset);
1543
ahci_bad_pmp_check_ready(struct ata_link * link)1544 static int ahci_bad_pmp_check_ready(struct ata_link *link)
1545 {
1546 void __iomem *port_mmio = ahci_port_base(link->ap);
1547 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1548 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1549
1550 /*
1551 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1552 * which can save timeout delay.
1553 */
1554 if (irq_status & PORT_IRQ_BAD_PMP)
1555 return -EIO;
1556
1557 return ata_check_ready(status);
1558 }
1559
ahci_pmp_retry_softreset(struct ata_link * link,unsigned int * class,unsigned long deadline)1560 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1561 unsigned long deadline)
1562 {
1563 struct ata_port *ap = link->ap;
1564 void __iomem *port_mmio = ahci_port_base(ap);
1565 int pmp = sata_srst_pmp(link);
1566 int rc;
1567 u32 irq_sts;
1568
1569 rc = ahci_do_softreset(link, class, pmp, deadline,
1570 ahci_bad_pmp_check_ready);
1571
1572 /*
1573 * Soft reset fails with IPMS set when PMP is enabled but
1574 * SATA HDD/ODD is connected to SATA port, do soft reset
1575 * again to port 0.
1576 */
1577 if (rc == -EIO) {
1578 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1579 if (irq_sts & PORT_IRQ_BAD_PMP) {
1580 ata_link_warn(link,
1581 "applying PMP SRST workaround "
1582 "and retrying\n");
1583 rc = ahci_do_softreset(link, class, 0, deadline,
1584 ahci_check_ready);
1585 }
1586 }
1587
1588 return rc;
1589 }
1590
ahci_do_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline,bool * online)1591 int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
1592 unsigned long deadline, bool *online)
1593 {
1594 const unsigned int *timing = sata_ehc_deb_timing(&link->eh_context);
1595 struct ata_port *ap = link->ap;
1596 struct ahci_port_priv *pp = ap->private_data;
1597 struct ahci_host_priv *hpriv = ap->host->private_data;
1598 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1599 struct ata_taskfile tf;
1600 int rc;
1601
1602 hpriv->stop_engine(ap);
1603
1604 /* clear D2H reception area to properly wait for D2H FIS */
1605 ata_tf_init(link->device, &tf);
1606 tf.status = ATA_BUSY;
1607 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1608
1609 ahci_port_clear_pending_irq(ap);
1610
1611 rc = sata_link_hardreset(link, timing, deadline, online,
1612 ahci_check_ready);
1613
1614 hpriv->start_engine(ap);
1615
1616 if (*online)
1617 *class = ahci_dev_classify(ap);
1618
1619 return rc;
1620 }
1621 EXPORT_SYMBOL_GPL(ahci_do_hardreset);
1622
ahci_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)1623 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1624 unsigned long deadline)
1625 {
1626 bool online;
1627
1628 return ahci_do_hardreset(link, class, deadline, &online);
1629 }
1630
ahci_postreset(struct ata_link * link,unsigned int * class)1631 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1632 {
1633 struct ata_port *ap = link->ap;
1634 void __iomem *port_mmio = ahci_port_base(ap);
1635 u32 new_tmp, tmp;
1636
1637 ata_std_postreset(link, class);
1638
1639 /* Make sure port's ATAPI bit is set appropriately */
1640 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1641 if (*class == ATA_DEV_ATAPI)
1642 new_tmp |= PORT_CMD_ATAPI;
1643 else
1644 new_tmp &= ~PORT_CMD_ATAPI;
1645 if (new_tmp != tmp) {
1646 writel(new_tmp, port_mmio + PORT_CMD);
1647 readl(port_mmio + PORT_CMD); /* flush */
1648 }
1649 }
1650
ahci_fill_sg(struct ata_queued_cmd * qc,void * cmd_tbl)1651 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1652 {
1653 struct scatterlist *sg;
1654 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1655 unsigned int si;
1656
1657 /*
1658 * Next, the S/G list.
1659 */
1660 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1661 dma_addr_t addr = sg_dma_address(sg);
1662 u32 sg_len = sg_dma_len(sg);
1663
1664 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1665 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1666 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1667 }
1668
1669 return si;
1670 }
1671
ahci_pmp_qc_defer(struct ata_queued_cmd * qc)1672 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1673 {
1674 struct ata_port *ap = qc->ap;
1675 struct ahci_port_priv *pp = ap->private_data;
1676
1677 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1678 return ata_std_qc_defer(qc);
1679 else
1680 return sata_pmp_qc_defer_cmd_switch(qc);
1681 }
1682
ahci_qc_prep(struct ata_queued_cmd * qc)1683 static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc)
1684 {
1685 struct ata_port *ap = qc->ap;
1686 struct ahci_port_priv *pp = ap->private_data;
1687 int is_atapi = ata_is_atapi(qc->tf.protocol);
1688 void *cmd_tbl;
1689 u32 opts;
1690 const u32 cmd_fis_len = 5; /* five dwords */
1691 unsigned int n_elem;
1692
1693 /*
1694 * Fill in command table information. First, the header,
1695 * a SATA Register - Host to Device command FIS.
1696 */
1697 cmd_tbl = pp->cmd_tbl + qc->hw_tag * AHCI_CMD_TBL_SZ;
1698
1699 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1700 if (is_atapi) {
1701 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1702 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1703 }
1704
1705 n_elem = 0;
1706 if (qc->flags & ATA_QCFLAG_DMAMAP)
1707 n_elem = ahci_fill_sg(qc, cmd_tbl);
1708
1709 /*
1710 * Fill in command slot information.
1711 */
1712 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1713 if (qc->tf.flags & ATA_TFLAG_WRITE)
1714 opts |= AHCI_CMD_WRITE;
1715 if (is_atapi)
1716 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1717
1718 ahci_fill_cmd_slot(pp, qc->hw_tag, opts);
1719
1720 return AC_ERR_OK;
1721 }
1722
ahci_fbs_dec_intr(struct ata_port * ap)1723 static void ahci_fbs_dec_intr(struct ata_port *ap)
1724 {
1725 struct ahci_port_priv *pp = ap->private_data;
1726 void __iomem *port_mmio = ahci_port_base(ap);
1727 u32 fbs = readl(port_mmio + PORT_FBS);
1728 int retries = 3;
1729
1730 BUG_ON(!pp->fbs_enabled);
1731
1732 /* time to wait for DEC is not specified by AHCI spec,
1733 * add a retry loop for safety.
1734 */
1735 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1736 fbs = readl(port_mmio + PORT_FBS);
1737 while ((fbs & PORT_FBS_DEC) && retries--) {
1738 udelay(1);
1739 fbs = readl(port_mmio + PORT_FBS);
1740 }
1741
1742 if (fbs & PORT_FBS_DEC)
1743 dev_err(ap->host->dev, "failed to clear device error\n");
1744 }
1745
ahci_error_intr(struct ata_port * ap,u32 irq_stat)1746 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1747 {
1748 struct ahci_host_priv *hpriv = ap->host->private_data;
1749 struct ahci_port_priv *pp = ap->private_data;
1750 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1751 struct ata_link *link = NULL;
1752 struct ata_queued_cmd *active_qc;
1753 struct ata_eh_info *active_ehi;
1754 bool fbs_need_dec = false;
1755 u32 serror;
1756
1757 /* determine active link with error */
1758 if (pp->fbs_enabled) {
1759 void __iomem *port_mmio = ahci_port_base(ap);
1760 u32 fbs = readl(port_mmio + PORT_FBS);
1761 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1762
1763 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
1764 link = &ap->pmp_link[pmp];
1765 fbs_need_dec = true;
1766 }
1767
1768 } else
1769 ata_for_each_link(link, ap, EDGE)
1770 if (ata_link_active(link))
1771 break;
1772
1773 if (!link)
1774 link = &ap->link;
1775
1776 active_qc = ata_qc_from_tag(ap, link->active_tag);
1777 active_ehi = &link->eh_info;
1778
1779 /* record irq stat */
1780 ata_ehi_clear_desc(host_ehi);
1781 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1782
1783 /* AHCI needs SError cleared; otherwise, it might lock up */
1784 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1785 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1786 host_ehi->serror |= serror;
1787
1788 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1789 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1790 irq_stat &= ~PORT_IRQ_IF_ERR;
1791
1792 if (irq_stat & PORT_IRQ_TF_ERR) {
1793 /* If qc is active, charge it; otherwise, the active
1794 * link. There's no active qc on NCQ errors. It will
1795 * be determined by EH by reading log page 10h.
1796 */
1797 if (active_qc)
1798 active_qc->err_mask |= AC_ERR_DEV;
1799 else
1800 active_ehi->err_mask |= AC_ERR_DEV;
1801
1802 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1803 host_ehi->serror &= ~SERR_INTERNAL;
1804 }
1805
1806 if (irq_stat & PORT_IRQ_UNK_FIS) {
1807 u32 *unk = pp->rx_fis + RX_FIS_UNK;
1808
1809 active_ehi->err_mask |= AC_ERR_HSM;
1810 active_ehi->action |= ATA_EH_RESET;
1811 ata_ehi_push_desc(active_ehi,
1812 "unknown FIS %08x %08x %08x %08x" ,
1813 unk[0], unk[1], unk[2], unk[3]);
1814 }
1815
1816 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1817 active_ehi->err_mask |= AC_ERR_HSM;
1818 active_ehi->action |= ATA_EH_RESET;
1819 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1820 }
1821
1822 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1823 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1824 host_ehi->action |= ATA_EH_RESET;
1825 ata_ehi_push_desc(host_ehi, "host bus error");
1826 }
1827
1828 if (irq_stat & PORT_IRQ_IF_ERR) {
1829 if (fbs_need_dec)
1830 active_ehi->err_mask |= AC_ERR_DEV;
1831 else {
1832 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1833 host_ehi->action |= ATA_EH_RESET;
1834 }
1835
1836 ata_ehi_push_desc(host_ehi, "interface fatal error");
1837 }
1838
1839 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1840 ata_ehi_hotplugged(host_ehi);
1841 ata_ehi_push_desc(host_ehi, "%s",
1842 irq_stat & PORT_IRQ_CONNECT ?
1843 "connection status changed" : "PHY RDY changed");
1844 }
1845
1846 /* okay, let's hand over to EH */
1847
1848 if (irq_stat & PORT_IRQ_FREEZE)
1849 ata_port_freeze(ap);
1850 else if (fbs_need_dec) {
1851 ata_link_abort(link);
1852 ahci_fbs_dec_intr(ap);
1853 } else
1854 ata_port_abort(ap);
1855 }
1856
ahci_qc_complete(struct ata_port * ap,void __iomem * port_mmio)1857 static void ahci_qc_complete(struct ata_port *ap, void __iomem *port_mmio)
1858 {
1859 struct ata_eh_info *ehi = &ap->link.eh_info;
1860 struct ahci_port_priv *pp = ap->private_data;
1861 u32 qc_active = 0;
1862 int rc;
1863
1864 /*
1865 * pp->active_link is not reliable once FBS is enabled, both
1866 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1867 * NCQ and non-NCQ commands may be in flight at the same time.
1868 */
1869 if (pp->fbs_enabled) {
1870 if (ap->qc_active) {
1871 qc_active = readl(port_mmio + PORT_SCR_ACT);
1872 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1873 }
1874 } else {
1875 /* pp->active_link is valid iff any command is in flight */
1876 if (ap->qc_active && pp->active_link->sactive)
1877 qc_active = readl(port_mmio + PORT_SCR_ACT);
1878 else
1879 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1880 }
1881
1882 rc = ata_qc_complete_multiple(ap, qc_active);
1883 if (unlikely(rc < 0 && !(ap->pflags & ATA_PFLAG_RESETTING))) {
1884 ehi->err_mask |= AC_ERR_HSM;
1885 ehi->action |= ATA_EH_RESET;
1886 ata_port_freeze(ap);
1887 }
1888 }
1889
ahci_handle_port_interrupt(struct ata_port * ap,void __iomem * port_mmio,u32 status)1890 static void ahci_handle_port_interrupt(struct ata_port *ap,
1891 void __iomem *port_mmio, u32 status)
1892 {
1893 struct ahci_port_priv *pp = ap->private_data;
1894 struct ahci_host_priv *hpriv = ap->host->private_data;
1895
1896 /* ignore BAD_PMP while resetting */
1897 if (unlikely(ap->pflags & ATA_PFLAG_RESETTING))
1898 status &= ~PORT_IRQ_BAD_PMP;
1899
1900 if (sata_lpm_ignore_phy_events(&ap->link)) {
1901 status &= ~PORT_IRQ_PHYRDY;
1902 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
1903 }
1904
1905 if (unlikely(status & PORT_IRQ_ERROR)) {
1906 /*
1907 * Before getting the error notification, we may have
1908 * received SDB FISes notifying successful completions.
1909 * Handle these first and then handle the error.
1910 */
1911 ahci_qc_complete(ap, port_mmio);
1912 ahci_error_intr(ap, status);
1913 return;
1914 }
1915
1916 if (status & PORT_IRQ_SDB_FIS) {
1917 /* If SNotification is available, leave notification
1918 * handling to sata_async_notification(). If not,
1919 * emulate it by snooping SDB FIS RX area.
1920 *
1921 * Snooping FIS RX area is probably cheaper than
1922 * poking SNotification but some constrollers which
1923 * implement SNotification, ICH9 for example, don't
1924 * store AN SDB FIS into receive area.
1925 */
1926 if (hpriv->cap & HOST_CAP_SNTF)
1927 sata_async_notification(ap);
1928 else {
1929 /* If the 'N' bit in word 0 of the FIS is set,
1930 * we just received asynchronous notification.
1931 * Tell libata about it.
1932 *
1933 * Lack of SNotification should not appear in
1934 * ahci 1.2, so the workaround is unnecessary
1935 * when FBS is enabled.
1936 */
1937 if (pp->fbs_enabled)
1938 WARN_ON_ONCE(1);
1939 else {
1940 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1941 u32 f0 = le32_to_cpu(f[0]);
1942 if (f0 & (1 << 15))
1943 sata_async_notification(ap);
1944 }
1945 }
1946 }
1947
1948 /* Handle completed commands */
1949 ahci_qc_complete(ap, port_mmio);
1950 }
1951
ahci_port_intr(struct ata_port * ap)1952 static void ahci_port_intr(struct ata_port *ap)
1953 {
1954 void __iomem *port_mmio = ahci_port_base(ap);
1955 u32 status;
1956
1957 status = readl(port_mmio + PORT_IRQ_STAT);
1958 writel(status, port_mmio + PORT_IRQ_STAT);
1959
1960 ahci_handle_port_interrupt(ap, port_mmio, status);
1961 }
1962
ahci_multi_irqs_intr_hard(int irq,void * dev_instance)1963 static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)
1964 {
1965 struct ata_port *ap = dev_instance;
1966 void __iomem *port_mmio = ahci_port_base(ap);
1967 u32 status;
1968
1969 status = readl(port_mmio + PORT_IRQ_STAT);
1970 writel(status, port_mmio + PORT_IRQ_STAT);
1971
1972 spin_lock(ap->lock);
1973 ahci_handle_port_interrupt(ap, port_mmio, status);
1974 spin_unlock(ap->lock);
1975
1976 return IRQ_HANDLED;
1977 }
1978
ahci_handle_port_intr(struct ata_host * host,u32 irq_masked)1979 u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
1980 {
1981 unsigned int i, handled = 0;
1982
1983 for (i = 0; i < host->n_ports; i++) {
1984 struct ata_port *ap;
1985
1986 if (!(irq_masked & (1 << i)))
1987 continue;
1988
1989 ap = host->ports[i];
1990 if (ap) {
1991 ahci_port_intr(ap);
1992 } else {
1993 if (ata_ratelimit())
1994 dev_warn(host->dev,
1995 "interrupt on disabled port %u\n", i);
1996 }
1997
1998 handled = 1;
1999 }
2000
2001 return handled;
2002 }
2003 EXPORT_SYMBOL_GPL(ahci_handle_port_intr);
2004
ahci_single_level_irq_intr(int irq,void * dev_instance)2005 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
2006 {
2007 struct ata_host *host = dev_instance;
2008 struct ahci_host_priv *hpriv;
2009 unsigned int rc = 0;
2010 void __iomem *mmio;
2011 u32 irq_stat, irq_masked;
2012
2013 hpriv = host->private_data;
2014 mmio = hpriv->mmio;
2015
2016 /* sigh. 0xffffffff is a valid return from h/w */
2017 irq_stat = readl(mmio + HOST_IRQ_STAT);
2018 if (!irq_stat)
2019 return IRQ_NONE;
2020
2021 irq_masked = irq_stat & hpriv->port_map;
2022
2023 spin_lock(&host->lock);
2024
2025 rc = ahci_handle_port_intr(host, irq_masked);
2026
2027 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
2028 * it should be cleared after all the port events are cleared;
2029 * otherwise, it will raise a spurious interrupt after each
2030 * valid one. Please read section 10.6.2 of ahci 1.1 for more
2031 * information.
2032 *
2033 * Also, use the unmasked value to clear interrupt as spurious
2034 * pending event on a dummy port might cause screaming IRQ.
2035 */
2036 writel(irq_stat, mmio + HOST_IRQ_STAT);
2037
2038 spin_unlock(&host->lock);
2039
2040 return IRQ_RETVAL(rc);
2041 }
2042
ahci_qc_issue(struct ata_queued_cmd * qc)2043 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
2044 {
2045 struct ata_port *ap = qc->ap;
2046 void __iomem *port_mmio = ahci_port_base(ap);
2047 struct ahci_port_priv *pp = ap->private_data;
2048
2049 /* Keep track of the currently active link. It will be used
2050 * in completion path to determine whether NCQ phase is in
2051 * progress.
2052 */
2053 pp->active_link = qc->dev->link;
2054
2055 if (ata_is_ncq(qc->tf.protocol))
2056 writel(1 << qc->hw_tag, port_mmio + PORT_SCR_ACT);
2057
2058 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
2059 u32 fbs = readl(port_mmio + PORT_FBS);
2060 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
2061 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
2062 writel(fbs, port_mmio + PORT_FBS);
2063 pp->fbs_last_dev = qc->dev->link->pmp;
2064 }
2065
2066 writel(1 << qc->hw_tag, port_mmio + PORT_CMD_ISSUE);
2067
2068 ahci_sw_activity(qc->dev->link);
2069
2070 return 0;
2071 }
2072 EXPORT_SYMBOL_GPL(ahci_qc_issue);
2073
ahci_qc_fill_rtf(struct ata_queued_cmd * qc)2074 static void ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2075 {
2076 struct ahci_port_priv *pp = qc->ap->private_data;
2077 u8 *rx_fis = pp->rx_fis;
2078
2079 if (pp->fbs_enabled)
2080 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
2081
2082 /*
2083 * After a successful execution of an ATA PIO data-in command,
2084 * the device doesn't send D2H Reg FIS to update the TF and
2085 * the host should take TF and E_Status from the preceding PIO
2086 * Setup FIS.
2087 */
2088 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
2089 !(qc->flags & ATA_QCFLAG_EH)) {
2090 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
2091 qc->result_tf.status = (rx_fis + RX_FIS_PIO_SETUP)[15];
2092 return;
2093 }
2094
2095 /*
2096 * For NCQ commands, we never get a D2H FIS, so reading the D2H Register
2097 * FIS area of the Received FIS Structure (which contains a copy of the
2098 * last D2H FIS received) will contain an outdated status code.
2099 * For NCQ commands, we instead get a SDB FIS, so read the SDB FIS area
2100 * instead. However, the SDB FIS does not contain the LBA, so we can't
2101 * use the ata_tf_from_fis() helper.
2102 */
2103 if (ata_is_ncq(qc->tf.protocol)) {
2104 const u8 *fis = rx_fis + RX_FIS_SDB;
2105
2106 /*
2107 * Successful NCQ commands have been filled already.
2108 * A failed NCQ command will read the status here.
2109 * (Note that a failed NCQ command will get a more specific
2110 * error when reading the NCQ Command Error log.)
2111 */
2112 qc->result_tf.status = fis[2];
2113 qc->result_tf.error = fis[3];
2114 return;
2115 }
2116
2117 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
2118 }
2119
ahci_qc_ncq_fill_rtf(struct ata_port * ap,u64 done_mask)2120 static void ahci_qc_ncq_fill_rtf(struct ata_port *ap, u64 done_mask)
2121 {
2122 struct ahci_port_priv *pp = ap->private_data;
2123 const u8 *fis;
2124
2125 /* No outstanding commands. */
2126 if (!ap->qc_active)
2127 return;
2128
2129 /*
2130 * FBS not enabled, so read status and error once, since they are shared
2131 * for all QCs.
2132 */
2133 if (!pp->fbs_enabled) {
2134 u8 status, error;
2135
2136 /* No outstanding NCQ commands. */
2137 if (!pp->active_link->sactive)
2138 return;
2139
2140 fis = pp->rx_fis + RX_FIS_SDB;
2141 status = fis[2];
2142 error = fis[3];
2143
2144 while (done_mask) {
2145 struct ata_queued_cmd *qc;
2146 unsigned int tag = __ffs64(done_mask);
2147
2148 qc = ata_qc_from_tag(ap, tag);
2149 if (qc && ata_is_ncq(qc->tf.protocol)) {
2150 qc->result_tf.status = status;
2151 qc->result_tf.error = error;
2152 qc->result_tf.flags = qc->tf.flags;
2153 qc->flags |= ATA_QCFLAG_RTF_FILLED;
2154 }
2155 done_mask &= ~(1ULL << tag);
2156 }
2157
2158 return;
2159 }
2160
2161 /*
2162 * FBS enabled, so read the status and error for each QC, since the QCs
2163 * can belong to different PMP links. (Each PMP link has its own FIS
2164 * Receive Area.)
2165 */
2166 while (done_mask) {
2167 struct ata_queued_cmd *qc;
2168 unsigned int tag = __ffs64(done_mask);
2169
2170 qc = ata_qc_from_tag(ap, tag);
2171 if (qc && ata_is_ncq(qc->tf.protocol)) {
2172 fis = pp->rx_fis;
2173 fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
2174 fis += RX_FIS_SDB;
2175 qc->result_tf.status = fis[2];
2176 qc->result_tf.error = fis[3];
2177 qc->result_tf.flags = qc->tf.flags;
2178 qc->flags |= ATA_QCFLAG_RTF_FILLED;
2179 }
2180 done_mask &= ~(1ULL << tag);
2181 }
2182 }
2183
ahci_freeze(struct ata_port * ap)2184 static void ahci_freeze(struct ata_port *ap)
2185 {
2186 void __iomem *port_mmio = ahci_port_base(ap);
2187
2188 /* turn IRQ off */
2189 writel(0, port_mmio + PORT_IRQ_MASK);
2190 }
2191
ahci_thaw(struct ata_port * ap)2192 static void ahci_thaw(struct ata_port *ap)
2193 {
2194 struct ahci_host_priv *hpriv = ap->host->private_data;
2195 void __iomem *mmio = hpriv->mmio;
2196 void __iomem *port_mmio = ahci_port_base(ap);
2197 u32 tmp;
2198 struct ahci_port_priv *pp = ap->private_data;
2199
2200 /* clear IRQ */
2201 tmp = readl(port_mmio + PORT_IRQ_STAT);
2202 writel(tmp, port_mmio + PORT_IRQ_STAT);
2203 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2204
2205 /* turn IRQ back on */
2206 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2207 }
2208
ahci_error_handler(struct ata_port * ap)2209 void ahci_error_handler(struct ata_port *ap)
2210 {
2211 struct ahci_host_priv *hpriv = ap->host->private_data;
2212
2213 if (!ata_port_is_frozen(ap)) {
2214 /* restart engine */
2215 hpriv->stop_engine(ap);
2216 hpriv->start_engine(ap);
2217 }
2218
2219 sata_pmp_error_handler(ap);
2220
2221 if (!ata_dev_enabled(ap->link.device))
2222 hpriv->stop_engine(ap);
2223 }
2224 EXPORT_SYMBOL_GPL(ahci_error_handler);
2225
ahci_post_internal_cmd(struct ata_queued_cmd * qc)2226 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2227 {
2228 struct ata_port *ap = qc->ap;
2229
2230 /* make DMA engine forget about the failed command */
2231 if (qc->flags & ATA_QCFLAG_EH)
2232 ahci_kick_engine(ap);
2233 }
2234
ahci_set_aggressive_devslp(struct ata_port * ap,bool sleep)2235 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2236 {
2237 struct ahci_host_priv *hpriv = ap->host->private_data;
2238 void __iomem *port_mmio = ahci_port_base(ap);
2239 struct ata_device *dev = ap->link.device;
2240 u32 devslp, dm, dito, mdat, deto, dito_conf;
2241 int rc;
2242 unsigned int err_mask;
2243
2244 devslp = readl(port_mmio + PORT_DEVSLP);
2245 if (!(devslp & PORT_DEVSLP_DSP)) {
2246 dev_info(ap->host->dev, "port does not support device sleep\n");
2247 return;
2248 }
2249
2250 /* disable device sleep */
2251 if (!sleep) {
2252 if (devslp & PORT_DEVSLP_ADSE) {
2253 writel(devslp & ~PORT_DEVSLP_ADSE,
2254 port_mmio + PORT_DEVSLP);
2255 err_mask = ata_dev_set_feature(dev,
2256 SETFEATURES_SATA_DISABLE,
2257 SATA_DEVSLP);
2258 if (err_mask && err_mask != AC_ERR_DEV)
2259 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2260 }
2261 return;
2262 }
2263
2264 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2265 dito = devslp_idle_timeout / (dm + 1);
2266 if (dito > 0x3ff)
2267 dito = 0x3ff;
2268
2269 dito_conf = (devslp >> PORT_DEVSLP_DITO_OFFSET) & 0x3FF;
2270
2271 /* device sleep was already enabled and same dito */
2272 if ((devslp & PORT_DEVSLP_ADSE) && (dito_conf == dito))
2273 return;
2274
2275 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2276 rc = hpriv->stop_engine(ap);
2277 if (rc)
2278 return;
2279
2280 /* Use the nominal value 10 ms if the read MDAT is zero,
2281 * the nominal value of DETO is 20 ms.
2282 */
2283 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
2284 ATA_LOG_DEVSLP_VALID_MASK) {
2285 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
2286 ATA_LOG_DEVSLP_MDAT_MASK;
2287 if (!mdat)
2288 mdat = 10;
2289 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
2290 if (!deto)
2291 deto = 20;
2292 } else {
2293 mdat = 10;
2294 deto = 20;
2295 }
2296
2297 /* Make dito, mdat, deto bits to 0s */
2298 devslp &= ~GENMASK_ULL(24, 2);
2299 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2300 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2301 (deto << PORT_DEVSLP_DETO_OFFSET) |
2302 PORT_DEVSLP_ADSE);
2303 writel(devslp, port_mmio + PORT_DEVSLP);
2304
2305 hpriv->start_engine(ap);
2306
2307 /* enable device sleep feature for the drive */
2308 err_mask = ata_dev_set_feature(dev,
2309 SETFEATURES_SATA_ENABLE,
2310 SATA_DEVSLP);
2311 if (err_mask && err_mask != AC_ERR_DEV)
2312 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2313 }
2314
ahci_enable_fbs(struct ata_port * ap)2315 static void ahci_enable_fbs(struct ata_port *ap)
2316 {
2317 struct ahci_host_priv *hpriv = ap->host->private_data;
2318 struct ahci_port_priv *pp = ap->private_data;
2319 void __iomem *port_mmio = ahci_port_base(ap);
2320 u32 fbs;
2321 int rc;
2322
2323 if (!pp->fbs_supported)
2324 return;
2325
2326 fbs = readl(port_mmio + PORT_FBS);
2327 if (fbs & PORT_FBS_EN) {
2328 pp->fbs_enabled = true;
2329 pp->fbs_last_dev = -1; /* initialization */
2330 return;
2331 }
2332
2333 rc = hpriv->stop_engine(ap);
2334 if (rc)
2335 return;
2336
2337 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2338 fbs = readl(port_mmio + PORT_FBS);
2339 if (fbs & PORT_FBS_EN) {
2340 dev_info(ap->host->dev, "FBS is enabled\n");
2341 pp->fbs_enabled = true;
2342 pp->fbs_last_dev = -1; /* initialization */
2343 } else
2344 dev_err(ap->host->dev, "Failed to enable FBS\n");
2345
2346 hpriv->start_engine(ap);
2347 }
2348
ahci_disable_fbs(struct ata_port * ap)2349 static void ahci_disable_fbs(struct ata_port *ap)
2350 {
2351 struct ahci_host_priv *hpriv = ap->host->private_data;
2352 struct ahci_port_priv *pp = ap->private_data;
2353 void __iomem *port_mmio = ahci_port_base(ap);
2354 u32 fbs;
2355 int rc;
2356
2357 if (!pp->fbs_supported)
2358 return;
2359
2360 fbs = readl(port_mmio + PORT_FBS);
2361 if ((fbs & PORT_FBS_EN) == 0) {
2362 pp->fbs_enabled = false;
2363 return;
2364 }
2365
2366 rc = hpriv->stop_engine(ap);
2367 if (rc)
2368 return;
2369
2370 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2371 fbs = readl(port_mmio + PORT_FBS);
2372 if (fbs & PORT_FBS_EN)
2373 dev_err(ap->host->dev, "Failed to disable FBS\n");
2374 else {
2375 dev_info(ap->host->dev, "FBS is disabled\n");
2376 pp->fbs_enabled = false;
2377 }
2378
2379 hpriv->start_engine(ap);
2380 }
2381
ahci_pmp_attach(struct ata_port * ap)2382 static void ahci_pmp_attach(struct ata_port *ap)
2383 {
2384 void __iomem *port_mmio = ahci_port_base(ap);
2385 struct ahci_port_priv *pp = ap->private_data;
2386 u32 cmd;
2387
2388 cmd = readl(port_mmio + PORT_CMD);
2389 cmd |= PORT_CMD_PMP;
2390 writel(cmd, port_mmio + PORT_CMD);
2391
2392 ahci_enable_fbs(ap);
2393
2394 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2395
2396 /*
2397 * We must not change the port interrupt mask register if the
2398 * port is marked frozen, the value in pp->intr_mask will be
2399 * restored later when the port is thawed.
2400 *
2401 * Note that during initialization, the port is marked as
2402 * frozen since the irq handler is not yet registered.
2403 */
2404 if (!ata_port_is_frozen(ap))
2405 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2406 }
2407
ahci_pmp_detach(struct ata_port * ap)2408 static void ahci_pmp_detach(struct ata_port *ap)
2409 {
2410 void __iomem *port_mmio = ahci_port_base(ap);
2411 struct ahci_port_priv *pp = ap->private_data;
2412 u32 cmd;
2413
2414 ahci_disable_fbs(ap);
2415
2416 cmd = readl(port_mmio + PORT_CMD);
2417 cmd &= ~PORT_CMD_PMP;
2418 writel(cmd, port_mmio + PORT_CMD);
2419
2420 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2421
2422 /* see comment above in ahci_pmp_attach() */
2423 if (!ata_port_is_frozen(ap))
2424 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2425 }
2426
ahci_port_resume(struct ata_port * ap)2427 int ahci_port_resume(struct ata_port *ap)
2428 {
2429 ahci_rpm_get_port(ap);
2430
2431 ahci_power_up(ap);
2432 ahci_start_port(ap);
2433
2434 if (sata_pmp_attached(ap))
2435 ahci_pmp_attach(ap);
2436 else
2437 ahci_pmp_detach(ap);
2438
2439 return 0;
2440 }
2441 EXPORT_SYMBOL_GPL(ahci_port_resume);
2442
2443 #ifdef CONFIG_PM
ahci_handle_s2idle(struct ata_port * ap)2444 static void ahci_handle_s2idle(struct ata_port *ap)
2445 {
2446 void __iomem *port_mmio = ahci_port_base(ap);
2447 u32 devslp;
2448
2449 if (pm_suspend_via_firmware())
2450 return;
2451 devslp = readl(port_mmio + PORT_DEVSLP);
2452 if ((devslp & PORT_DEVSLP_ADSE))
2453 ata_msleep(ap, devslp_idle_timeout);
2454 }
2455
ahci_port_suspend(struct ata_port * ap,pm_message_t mesg)2456 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2457 {
2458 const char *emsg = NULL;
2459 int rc;
2460
2461 rc = ahci_deinit_port(ap, &emsg);
2462 if (rc == 0)
2463 ahci_power_down(ap);
2464 else {
2465 ata_port_err(ap, "%s (%d)\n", emsg, rc);
2466 ata_port_freeze(ap);
2467 }
2468
2469 if (acpi_storage_d3(ap->host->dev))
2470 ahci_handle_s2idle(ap);
2471
2472 ahci_rpm_put_port(ap);
2473 return rc;
2474 }
2475 #endif
2476
ahci_port_start(struct ata_port * ap)2477 static int ahci_port_start(struct ata_port *ap)
2478 {
2479 struct ahci_host_priv *hpriv = ap->host->private_data;
2480 struct device *dev = ap->host->dev;
2481 struct ahci_port_priv *pp;
2482 void *mem;
2483 dma_addr_t mem_dma;
2484 size_t dma_sz, rx_fis_sz;
2485
2486 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2487 if (!pp)
2488 return -ENOMEM;
2489
2490 if (ap->host->n_ports > 1) {
2491 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2492 if (!pp->irq_desc) {
2493 devm_kfree(dev, pp);
2494 return -ENOMEM;
2495 }
2496 snprintf(pp->irq_desc, 8,
2497 "%s%d", dev_driver_string(dev), ap->port_no);
2498 }
2499
2500 /* check FBS capability */
2501 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2502 void __iomem *port_mmio = ahci_port_base(ap);
2503 u32 cmd = readl(port_mmio + PORT_CMD);
2504 if (cmd & PORT_CMD_FBSCP)
2505 pp->fbs_supported = true;
2506 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
2507 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2508 ap->port_no);
2509 pp->fbs_supported = true;
2510 } else
2511 dev_warn(dev, "port %d is not capable of FBS\n",
2512 ap->port_no);
2513 }
2514
2515 if (pp->fbs_supported) {
2516 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2517 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2518 } else {
2519 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2520 rx_fis_sz = AHCI_RX_FIS_SZ;
2521 }
2522
2523 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2524 if (!mem)
2525 return -ENOMEM;
2526
2527 /*
2528 * First item in chunk of DMA memory: 32-slot command table,
2529 * 32 bytes each in size
2530 */
2531 pp->cmd_slot = mem;
2532 pp->cmd_slot_dma = mem_dma;
2533
2534 mem += AHCI_CMD_SLOT_SZ;
2535 mem_dma += AHCI_CMD_SLOT_SZ;
2536
2537 /*
2538 * Second item: Received-FIS area
2539 */
2540 pp->rx_fis = mem;
2541 pp->rx_fis_dma = mem_dma;
2542
2543 mem += rx_fis_sz;
2544 mem_dma += rx_fis_sz;
2545
2546 /*
2547 * Third item: data area for storing a single command
2548 * and its scatter-gather table
2549 */
2550 pp->cmd_tbl = mem;
2551 pp->cmd_tbl_dma = mem_dma;
2552
2553 /*
2554 * Save off initial list of interrupts to be enabled.
2555 * This could be changed later
2556 */
2557 pp->intr_mask = DEF_PORT_IRQ;
2558
2559 /*
2560 * Switch to per-port locking in case each port has its own MSI vector.
2561 */
2562 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2563 spin_lock_init(&pp->lock);
2564 ap->lock = &pp->lock;
2565 }
2566
2567 ap->private_data = pp;
2568
2569 /* engage engines, captain */
2570 return ahci_port_resume(ap);
2571 }
2572
ahci_port_stop(struct ata_port * ap)2573 static void ahci_port_stop(struct ata_port *ap)
2574 {
2575 const char *emsg = NULL;
2576 struct ahci_host_priv *hpriv = ap->host->private_data;
2577 void __iomem *host_mmio = hpriv->mmio;
2578 int rc;
2579
2580 /* de-initialize port */
2581 rc = ahci_deinit_port(ap, &emsg);
2582 if (rc)
2583 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
2584
2585 /*
2586 * Clear GHC.IS to prevent stuck INTx after disabling MSI and
2587 * re-enabling INTx.
2588 */
2589 writel(1 << ap->port_no, host_mmio + HOST_IRQ_STAT);
2590
2591 ahci_rpm_put_port(ap);
2592 }
2593
ahci_print_info(struct ata_host * host,const char * scc_s)2594 void ahci_print_info(struct ata_host *host, const char *scc_s)
2595 {
2596 struct ahci_host_priv *hpriv = host->private_data;
2597 u32 vers, cap, cap2, impl, speed;
2598 const char *speed_s;
2599
2600 vers = hpriv->version;
2601 cap = hpriv->cap;
2602 cap2 = hpriv->cap2;
2603 impl = hpriv->port_map;
2604
2605 speed = (cap >> 20) & 0xf;
2606 if (speed == 1)
2607 speed_s = "1.5";
2608 else if (speed == 2)
2609 speed_s = "3";
2610 else if (speed == 3)
2611 speed_s = "6";
2612 else
2613 speed_s = "?";
2614
2615 dev_info(host->dev,
2616 "AHCI vers %02x%02x.%02x%02x, "
2617 "%u command slots, %s Gbps, %s mode\n"
2618 ,
2619
2620 (vers >> 24) & 0xff,
2621 (vers >> 16) & 0xff,
2622 (vers >> 8) & 0xff,
2623 vers & 0xff,
2624
2625 ((cap >> 8) & 0x1f) + 1,
2626 speed_s,
2627 scc_s);
2628
2629 dev_info(host->dev,
2630 "%u/%u ports implemented (port mask 0x%x)\n"
2631 ,
2632
2633 hweight32(impl),
2634 (cap & 0x1f) + 1,
2635 impl);
2636
2637 dev_info(host->dev,
2638 "flags: "
2639 "%s%s%s%s%s%s%s"
2640 "%s%s%s%s%s%s%s"
2641 "%s%s%s%s%s%s%s"
2642 "%s%s\n"
2643 ,
2644
2645 cap & HOST_CAP_64 ? "64bit " : "",
2646 cap & HOST_CAP_NCQ ? "ncq " : "",
2647 cap & HOST_CAP_SNTF ? "sntf " : "",
2648 cap & HOST_CAP_MPS ? "ilck " : "",
2649 cap & HOST_CAP_SSS ? "stag " : "",
2650 cap & HOST_CAP_ALPM ? "pm " : "",
2651 cap & HOST_CAP_LED ? "led " : "",
2652 cap & HOST_CAP_CLO ? "clo " : "",
2653 cap & HOST_CAP_ONLY ? "only " : "",
2654 cap & HOST_CAP_PMP ? "pmp " : "",
2655 cap & HOST_CAP_FBS ? "fbs " : "",
2656 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2657 cap & HOST_CAP_SSC ? "slum " : "",
2658 cap & HOST_CAP_PART ? "part " : "",
2659 cap & HOST_CAP_CCC ? "ccc " : "",
2660 cap & HOST_CAP_EMS ? "ems " : "",
2661 cap & HOST_CAP_SXS ? "sxs " : "",
2662 cap2 & HOST_CAP2_DESO ? "deso " : "",
2663 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2664 cap2 & HOST_CAP2_SDS ? "sds " : "",
2665 cap2 & HOST_CAP2_APST ? "apst " : "",
2666 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2667 cap2 & HOST_CAP2_BOH ? "boh " : ""
2668 );
2669 }
2670 EXPORT_SYMBOL_GPL(ahci_print_info);
2671
ahci_set_em_messages(struct ahci_host_priv * hpriv,struct ata_port_info * pi)2672 void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2673 struct ata_port_info *pi)
2674 {
2675 u8 messages;
2676 void __iomem *mmio = hpriv->mmio;
2677 u32 em_loc = readl(mmio + HOST_EM_LOC);
2678 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2679
2680 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2681 return;
2682
2683 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2684
2685 if (messages) {
2686 /* store em_loc */
2687 hpriv->em_loc = ((em_loc >> 16) * 4);
2688 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
2689 hpriv->em_msg_type = messages;
2690 pi->flags |= ATA_FLAG_EM;
2691 if (!(em_ctl & EM_CTL_ALHD))
2692 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2693 }
2694 }
2695 EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2696
ahci_host_activate_multi_irqs(struct ata_host * host,const struct scsi_host_template * sht)2697 static int ahci_host_activate_multi_irqs(struct ata_host *host,
2698 const struct scsi_host_template *sht)
2699 {
2700 struct ahci_host_priv *hpriv = host->private_data;
2701 int i, rc;
2702
2703 rc = ata_host_start(host);
2704 if (rc)
2705 return rc;
2706 /*
2707 * Requests IRQs according to AHCI-1.1 when multiple MSIs were
2708 * allocated. That is one MSI per port, starting from @irq.
2709 */
2710 for (i = 0; i < host->n_ports; i++) {
2711 struct ahci_port_priv *pp = host->ports[i]->private_data;
2712 int irq = hpriv->get_irq_vector(host, i);
2713
2714 /* Do not receive interrupts sent by dummy ports */
2715 if (!pp) {
2716 disable_irq(irq);
2717 continue;
2718 }
2719
2720 rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard,
2721 0, pp->irq_desc, host->ports[i]);
2722
2723 if (rc)
2724 return rc;
2725 ata_port_desc_misc(host->ports[i], irq);
2726 }
2727
2728 return ata_host_register(host, sht);
2729 }
2730
2731 /**
2732 * ahci_host_activate - start AHCI host, request IRQs and register it
2733 * @host: target ATA host
2734 * @sht: scsi_host_template to use when registering the host
2735 *
2736 * LOCKING:
2737 * Inherited from calling layer (may sleep).
2738 *
2739 * RETURNS:
2740 * 0 on success, -errno otherwise.
2741 */
ahci_host_activate(struct ata_host * host,const struct scsi_host_template * sht)2742 int ahci_host_activate(struct ata_host *host, const struct scsi_host_template *sht)
2743 {
2744 struct ahci_host_priv *hpriv = host->private_data;
2745 int irq = hpriv->irq;
2746 int rc;
2747
2748 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2749 if (hpriv->irq_handler &&
2750 hpriv->irq_handler != ahci_single_level_irq_intr)
2751 dev_warn(host->dev,
2752 "both AHCI_HFLAG_MULTI_MSI flag set and custom irq handler implemented\n");
2753 if (!hpriv->get_irq_vector) {
2754 dev_err(host->dev,
2755 "AHCI_HFLAG_MULTI_MSI requires ->get_irq_vector!\n");
2756 return -EIO;
2757 }
2758
2759 rc = ahci_host_activate_multi_irqs(host, sht);
2760 } else {
2761 rc = ata_host_activate(host, irq, hpriv->irq_handler,
2762 IRQF_SHARED, sht);
2763 }
2764
2765
2766 return rc;
2767 }
2768 EXPORT_SYMBOL_GPL(ahci_host_activate);
2769
2770 MODULE_AUTHOR("Jeff Garzik");
2771 MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2772 MODULE_LICENSE("GPL");
2773