1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 *
4 * hda_intel.c - Implementation of primary alsa driver code base
5 * for Intel HD Audio.
6 *
7 * Copyright(c) 2004 Intel Corporation
8 *
9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
10 * PeiSen Hou <pshou@realtek.com.tw>
11 *
12 * CONTACTS:
13 *
14 * Matt Jared matt.jared@intel.com
15 * Andy Kopp andy.kopp@intel.com
16 * Dan Kogan dan.d.kogan@intel.com
17 *
18 * CHANGES:
19 *
20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
21 */
22
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/moduleparam.h>
29 #include <linux/init.h>
30 #include <linux/slab.h>
31 #include <linux/pci.h>
32 #include <linux/mutex.h>
33 #include <linux/io.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/clocksource.h>
36 #include <linux/time.h>
37 #include <linux/completion.h>
38 #include <linux/acpi.h>
39 #include <linux/pgtable.h>
40 #include <linux/dmi.h>
41
42 #ifdef CONFIG_X86
43 /* for snoop control */
44 #include <asm/set_memory.h>
45 #include <asm/cpufeature.h>
46 #endif
47 #include <sound/core.h>
48 #include <sound/initval.h>
49 #include <sound/hdaudio.h>
50 #include <sound/hda_i915.h>
51 #include <sound/intel-dsp-config.h>
52 #include <linux/vgaarb.h>
53 #include <linux/vga_switcheroo.h>
54 #include <linux/apple-gmux.h>
55 #include <linux/firmware.h>
56 #include <sound/hda_codec.h>
57 #include "hda_controller.h"
58 #include "hda_intel.h"
59
60 #define CREATE_TRACE_POINTS
61 #include "hda_intel_trace.h"
62
63 /* position fix mode */
64 enum {
65 POS_FIX_AUTO,
66 POS_FIX_LPIB,
67 POS_FIX_POSBUF,
68 POS_FIX_VIACOMBO,
69 POS_FIX_COMBO,
70 POS_FIX_SKL,
71 POS_FIX_FIFO,
72 };
73
74 /* Defines for ATI HD Audio support in SB450 south bridge */
75 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
76 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
77
78 /* Defines for Nvidia HDA support */
79 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
80 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
81 #define NVIDIA_HDA_ISTRM_COH 0x4d
82 #define NVIDIA_HDA_OSTRM_COH 0x4c
83 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
84
85 /* Defines for Intel SCH HDA snoop control */
86 #define INTEL_HDA_CGCTL 0x48
87 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
88 #define INTEL_SCH_HDA_DEVC 0x78
89 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
90
91 /* max number of SDs */
92 /* ICH, ATI and VIA have 4 playback and 4 capture */
93 #define ICH6_NUM_CAPTURE 4
94 #define ICH6_NUM_PLAYBACK 4
95
96 /* ULI has 6 playback and 5 capture */
97 #define ULI_NUM_CAPTURE 5
98 #define ULI_NUM_PLAYBACK 6
99
100 /* ATI HDMI may have up to 8 playbacks and 0 capture */
101 #define ATIHDMI_NUM_CAPTURE 0
102 #define ATIHDMI_NUM_PLAYBACK 8
103
104
105 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
106 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
107 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
108 static char *model[SNDRV_CARDS];
109 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
110 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
111 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
112 static int probe_only[SNDRV_CARDS];
113 static int jackpoll_ms[SNDRV_CARDS];
114 static int single_cmd = -1;
115 static int enable_msi = -1;
116 #ifdef CONFIG_SND_HDA_PATCH_LOADER
117 static char *patch[SNDRV_CARDS];
118 #endif
119 #ifdef CONFIG_SND_HDA_INPUT_BEEP
120 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
121 CONFIG_SND_HDA_INPUT_BEEP_MODE};
122 #endif
123 static bool dmic_detect = 1;
124 static bool ctl_dev_id = IS_ENABLED(CONFIG_SND_HDA_CTL_DEV_ID) ? 1 : 0;
125
126 module_param_array(index, int, NULL, 0444);
127 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
128 module_param_array(id, charp, NULL, 0444);
129 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
130 module_param_array(enable, bool, NULL, 0444);
131 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
132 module_param_array(model, charp, NULL, 0444);
133 MODULE_PARM_DESC(model, "Use the given board model.");
134 module_param_array(position_fix, int, NULL, 0444);
135 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
136 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
137 module_param_array(bdl_pos_adj, int, NULL, 0644);
138 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
139 module_param_array(probe_mask, int, NULL, 0444);
140 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
141 module_param_array(probe_only, int, NULL, 0444);
142 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
143 module_param_array(jackpoll_ms, int, NULL, 0444);
144 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
145 module_param(single_cmd, bint, 0444);
146 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
147 "(for debugging only).");
148 module_param(enable_msi, bint, 0444);
149 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
150 #ifdef CONFIG_SND_HDA_PATCH_LOADER
151 module_param_array(patch, charp, NULL, 0444);
152 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
153 #endif
154 #ifdef CONFIG_SND_HDA_INPUT_BEEP
155 module_param_array(beep_mode, bool, NULL, 0444);
156 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
157 "(0=off, 1=on) (default=1).");
158 #endif
159 module_param(dmic_detect, bool, 0444);
160 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) "
161 "(0=off, 1=on) (default=1); "
162 "deprecated, use snd-intel-dspcfg.dsp_driver option instead");
163 module_param(ctl_dev_id, bool, 0444);
164 MODULE_PARM_DESC(ctl_dev_id, "Use control device identifier (based on codec address).");
165
166 #ifdef CONFIG_PM
167 static int param_set_xint(const char *val, const struct kernel_param *kp);
168 static const struct kernel_param_ops param_ops_xint = {
169 .set = param_set_xint,
170 .get = param_get_int,
171 };
172 #define param_check_xint param_check_int
173
174 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
175 module_param(power_save, xint, 0644);
176 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
177 "(in second, 0 = disable).");
178
179 static int pm_blacklist = -1;
180 module_param(pm_blacklist, bint, 0644);
181 MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist");
182
183 /* reset the HD-audio controller in power save mode.
184 * this may give more power-saving, but will take longer time to
185 * wake up.
186 */
187 static bool power_save_controller = 1;
188 module_param(power_save_controller, bool, 0644);
189 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
190 #else /* CONFIG_PM */
191 #define power_save 0
192 #define pm_blacklist 0
193 #define power_save_controller false
194 #endif /* CONFIG_PM */
195
196 static int align_buffer_size = -1;
197 module_param(align_buffer_size, bint, 0644);
198 MODULE_PARM_DESC(align_buffer_size,
199 "Force buffer and period sizes to be multiple of 128 bytes.");
200
201 #ifdef CONFIG_X86
202 static int hda_snoop = -1;
203 module_param_named(snoop, hda_snoop, bint, 0444);
204 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
205 #else
206 #define hda_snoop true
207 #endif
208
209
210 MODULE_LICENSE("GPL");
211 MODULE_DESCRIPTION("Intel HDA driver");
212
213 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
214 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
215 #define SUPPORT_VGA_SWITCHEROO
216 #endif
217 #endif
218
219
220 /*
221 */
222
223 /* driver types */
224 enum {
225 AZX_DRIVER_ICH,
226 AZX_DRIVER_PCH,
227 AZX_DRIVER_SCH,
228 AZX_DRIVER_SKL,
229 AZX_DRIVER_HDMI,
230 AZX_DRIVER_ATI,
231 AZX_DRIVER_ATIHDMI,
232 AZX_DRIVER_ATIHDMI_NS,
233 AZX_DRIVER_GFHDMI,
234 AZX_DRIVER_VIA,
235 AZX_DRIVER_SIS,
236 AZX_DRIVER_ULI,
237 AZX_DRIVER_NVIDIA,
238 AZX_DRIVER_TERA,
239 AZX_DRIVER_CTX,
240 AZX_DRIVER_CTHDA,
241 AZX_DRIVER_CMEDIA,
242 AZX_DRIVER_ZHAOXIN,
243 AZX_DRIVER_LOONGSON,
244 AZX_DRIVER_GENERIC,
245 AZX_NUM_DRIVERS, /* keep this as last entry */
246 };
247
248 #define azx_get_snoop_type(chip) \
249 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
250 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
251
252 /* quirks for old Intel chipsets */
253 #define AZX_DCAPS_INTEL_ICH \
254 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
255
256 /* quirks for Intel PCH */
257 #define AZX_DCAPS_INTEL_PCH_BASE \
258 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
259 AZX_DCAPS_SNOOP_TYPE(SCH))
260
261 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
262 #define AZX_DCAPS_INTEL_PCH_NOPM \
263 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
264
265 /* PCH for HSW/BDW; with runtime PM */
266 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
267 #define AZX_DCAPS_INTEL_PCH \
268 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
269
270 /* HSW HDMI */
271 #define AZX_DCAPS_INTEL_HASWELL \
272 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
273 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
274 AZX_DCAPS_SNOOP_TYPE(SCH))
275
276 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
277 #define AZX_DCAPS_INTEL_BROADWELL \
278 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
279 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
280 AZX_DCAPS_SNOOP_TYPE(SCH))
281
282 #define AZX_DCAPS_INTEL_BAYTRAIL \
283 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
284
285 #define AZX_DCAPS_INTEL_BRASWELL \
286 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
287 AZX_DCAPS_I915_COMPONENT)
288
289 #define AZX_DCAPS_INTEL_SKYLAKE \
290 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
291 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
292
293 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE
294
295 #define AZX_DCAPS_INTEL_LNL \
296 (AZX_DCAPS_INTEL_SKYLAKE | AZX_DCAPS_PIO_COMMANDS)
297
298 /* quirks for ATI SB / AMD Hudson */
299 #define AZX_DCAPS_PRESET_ATI_SB \
300 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\
301 AZX_DCAPS_SNOOP_TYPE(ATI))
302
303 /* quirks for ATI/AMD HDMI */
304 #define AZX_DCAPS_PRESET_ATI_HDMI \
305 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\
306 AZX_DCAPS_NO_MSI64)
307
308 /* quirks for ATI HDMI with snoop off */
309 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
310 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
311
312 /* quirks for AMD SB */
313 #define AZX_DCAPS_PRESET_AMD_SB \
314 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\
315 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME |\
316 AZX_DCAPS_RETRY_PROBE)
317
318 /* quirks for Nvidia */
319 #define AZX_DCAPS_PRESET_NVIDIA \
320 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
321 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
322
323 #define AZX_DCAPS_PRESET_CTHDA \
324 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
325 AZX_DCAPS_NO_64BIT |\
326 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
327
328 /*
329 * vga_switcheroo support
330 */
331 #ifdef SUPPORT_VGA_SWITCHEROO
332 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
333 #define needs_eld_notify_link(chip) ((chip)->bus.keep_power)
334 #else
335 #define use_vga_switcheroo(chip) 0
336 #define needs_eld_notify_link(chip) false
337 #endif
338
339 static const char * const driver_short_names[] = {
340 [AZX_DRIVER_ICH] = "HDA Intel",
341 [AZX_DRIVER_PCH] = "HDA Intel PCH",
342 [AZX_DRIVER_SCH] = "HDA Intel MID",
343 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
344 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
345 [AZX_DRIVER_ATI] = "HDA ATI SB",
346 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
347 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
348 [AZX_DRIVER_GFHDMI] = "HDA GF HDMI",
349 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
350 [AZX_DRIVER_SIS] = "HDA SIS966",
351 [AZX_DRIVER_ULI] = "HDA ULI M5461",
352 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
353 [AZX_DRIVER_TERA] = "HDA Teradici",
354 [AZX_DRIVER_CTX] = "HDA Creative",
355 [AZX_DRIVER_CTHDA] = "HDA Creative",
356 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
357 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
358 [AZX_DRIVER_LOONGSON] = "HDA Loongson",
359 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
360 };
361
362 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
363 static void set_default_power_save(struct azx *chip);
364
365 /*
366 * initialize the PCI registers
367 */
368 /* update bits in a PCI register byte */
update_pci_byte(struct pci_dev * pci,unsigned int reg,unsigned char mask,unsigned char val)369 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
370 unsigned char mask, unsigned char val)
371 {
372 unsigned char data;
373
374 pci_read_config_byte(pci, reg, &data);
375 data &= ~mask;
376 data |= (val & mask);
377 pci_write_config_byte(pci, reg, data);
378 }
379
azx_init_pci(struct azx * chip)380 static void azx_init_pci(struct azx *chip)
381 {
382 int snoop_type = azx_get_snoop_type(chip);
383
384 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
385 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
386 * Ensuring these bits are 0 clears playback static on some HD Audio
387 * codecs.
388 * The PCI register TCSEL is defined in the Intel manuals.
389 */
390 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
391 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
392 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
393 }
394
395 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
396 * we need to enable snoop.
397 */
398 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
399 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
400 azx_snoop(chip));
401 update_pci_byte(chip->pci,
402 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
403 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
404 }
405
406 /* For NVIDIA HDA, enable snoop */
407 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
408 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
409 azx_snoop(chip));
410 update_pci_byte(chip->pci,
411 NVIDIA_HDA_TRANSREG_ADDR,
412 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
413 update_pci_byte(chip->pci,
414 NVIDIA_HDA_ISTRM_COH,
415 0x01, NVIDIA_HDA_ENABLE_COHBIT);
416 update_pci_byte(chip->pci,
417 NVIDIA_HDA_OSTRM_COH,
418 0x01, NVIDIA_HDA_ENABLE_COHBIT);
419 }
420
421 /* Enable SCH/PCH snoop if needed */
422 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
423 unsigned short snoop;
424 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
425 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
426 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
427 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
428 if (!azx_snoop(chip))
429 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
430 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
431 pci_read_config_word(chip->pci,
432 INTEL_SCH_HDA_DEVC, &snoop);
433 }
434 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
435 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
436 "Disabled" : "Enabled");
437 }
438 }
439
440 /*
441 * In BXT-P A0, HD-Audio DMA requests is later than expected,
442 * and makes an audio stream sensitive to system latencies when
443 * 24/32 bits are playing.
444 * Adjusting threshold of DMA fifo to force the DMA request
445 * sooner to improve latency tolerance at the expense of power.
446 */
bxt_reduce_dma_latency(struct azx * chip)447 static void bxt_reduce_dma_latency(struct azx *chip)
448 {
449 u32 val;
450
451 val = azx_readl(chip, VS_EM4L);
452 val &= (0x3 << 20);
453 azx_writel(chip, VS_EM4L, val);
454 }
455
456 /*
457 * ML_LCAP bits:
458 * bit 0: 6 MHz Supported
459 * bit 1: 12 MHz Supported
460 * bit 2: 24 MHz Supported
461 * bit 3: 48 MHz Supported
462 * bit 4: 96 MHz Supported
463 * bit 5: 192 MHz Supported
464 */
intel_get_lctl_scf(struct azx * chip)465 static int intel_get_lctl_scf(struct azx *chip)
466 {
467 struct hdac_bus *bus = azx_bus(chip);
468 static const int preferred_bits[] = { 2, 3, 1, 4, 5 };
469 u32 val, t;
470 int i;
471
472 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
473
474 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
475 t = preferred_bits[i];
476 if (val & (1 << t))
477 return t;
478 }
479
480 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
481 return 0;
482 }
483
intel_ml_lctl_set_power(struct azx * chip,int state)484 static int intel_ml_lctl_set_power(struct azx *chip, int state)
485 {
486 struct hdac_bus *bus = azx_bus(chip);
487 u32 val;
488 int timeout;
489
490 /*
491 * Changes to LCTL.SCF are only needed for the first multi-link dealing
492 * with external codecs
493 */
494 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
495 val &= ~AZX_ML_LCTL_SPA;
496 val |= state << AZX_ML_LCTL_SPA_SHIFT;
497 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
498 /* wait for CPA */
499 timeout = 50;
500 while (timeout) {
501 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
502 AZX_ML_LCTL_CPA) == (state << AZX_ML_LCTL_CPA_SHIFT))
503 return 0;
504 timeout--;
505 udelay(10);
506 }
507
508 return -1;
509 }
510
intel_init_lctl(struct azx * chip)511 static void intel_init_lctl(struct azx *chip)
512 {
513 struct hdac_bus *bus = azx_bus(chip);
514 u32 val;
515 int ret;
516
517 /* 0. check lctl register value is correct or not */
518 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
519 /* only perform additional configurations if the SCF is initially based on 6MHz */
520 if ((val & AZX_ML_LCTL_SCF) != 0)
521 return;
522
523 /*
524 * Before operating on SPA, CPA must match SPA.
525 * Any deviation may result in undefined behavior.
526 */
527 if (((val & AZX_ML_LCTL_SPA) >> AZX_ML_LCTL_SPA_SHIFT) !=
528 ((val & AZX_ML_LCTL_CPA) >> AZX_ML_LCTL_CPA_SHIFT))
529 return;
530
531 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
532 ret = intel_ml_lctl_set_power(chip, 0);
533 udelay(100);
534 if (ret)
535 goto set_spa;
536
537 /* 2. update SCF to select an audio clock different from 6MHz */
538 val &= ~AZX_ML_LCTL_SCF;
539 val |= intel_get_lctl_scf(chip);
540 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
541
542 set_spa:
543 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
544 intel_ml_lctl_set_power(chip, 1);
545 udelay(100);
546 }
547
hda_intel_init_chip(struct azx * chip,bool full_reset)548 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
549 {
550 struct hdac_bus *bus = azx_bus(chip);
551 struct pci_dev *pci = chip->pci;
552 u32 val;
553
554 snd_hdac_set_codec_wakeup(bus, true);
555 if (chip->driver_type == AZX_DRIVER_SKL) {
556 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
557 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
558 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
559 }
560 azx_init_chip(chip, full_reset);
561 if (chip->driver_type == AZX_DRIVER_SKL) {
562 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
563 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
564 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
565 }
566
567 snd_hdac_set_codec_wakeup(bus, false);
568
569 /* reduce dma latency to avoid noise */
570 if (HDA_CONTROLLER_IS_APL(pci))
571 bxt_reduce_dma_latency(chip);
572
573 if (bus->mlcap != NULL)
574 intel_init_lctl(chip);
575 }
576
577 /* calculate runtime delay from LPIB */
azx_get_delay_from_lpib(struct azx * chip,struct azx_dev * azx_dev,unsigned int pos)578 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
579 unsigned int pos)
580 {
581 struct snd_pcm_substream *substream = azx_dev->core.substream;
582 int stream = substream->stream;
583 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
584 int delay;
585
586 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
587 delay = pos - lpib_pos;
588 else
589 delay = lpib_pos - pos;
590 if (delay < 0) {
591 if (delay >= azx_dev->core.delay_negative_threshold)
592 delay = 0;
593 else
594 delay += azx_dev->core.bufsize;
595 }
596
597 if (delay >= azx_dev->core.period_bytes) {
598 dev_info(chip->card->dev,
599 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
600 delay, azx_dev->core.period_bytes);
601 delay = 0;
602 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
603 chip->get_delay[stream] = NULL;
604 }
605
606 return bytes_to_frames(substream->runtime, delay);
607 }
608
609 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
610
611 /* called from IRQ */
azx_position_check(struct azx * chip,struct azx_dev * azx_dev)612 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
613 {
614 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
615 int ok;
616
617 ok = azx_position_ok(chip, azx_dev);
618 if (ok == 1) {
619 azx_dev->irq_pending = 0;
620 return ok;
621 } else if (ok == 0) {
622 /* bogus IRQ, process it later */
623 azx_dev->irq_pending = 1;
624 schedule_work(&hda->irq_pending_work);
625 }
626 return 0;
627 }
628
629 #define display_power(chip, enable) \
630 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
631
632 /*
633 * Check whether the current DMA position is acceptable for updating
634 * periods. Returns non-zero if it's OK.
635 *
636 * Many HD-audio controllers appear pretty inaccurate about
637 * the update-IRQ timing. The IRQ is issued before actually the
638 * data is processed. So, we need to process it afterwords in a
639 * workqueue.
640 *
641 * Returns 1 if OK to proceed, 0 for delay handling, -1 for skipping update
642 */
azx_position_ok(struct azx * chip,struct azx_dev * azx_dev)643 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
644 {
645 struct snd_pcm_substream *substream = azx_dev->core.substream;
646 struct snd_pcm_runtime *runtime = substream->runtime;
647 int stream = substream->stream;
648 u32 wallclk;
649 unsigned int pos;
650 snd_pcm_uframes_t hwptr, target;
651
652 /*
653 * The value of the WALLCLK register is always 0
654 * on the Loongson controller, so we return directly.
655 */
656 if (chip->driver_type == AZX_DRIVER_LOONGSON)
657 return 1;
658
659 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
660 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
661 return -1; /* bogus (too early) interrupt */
662
663 if (chip->get_position[stream])
664 pos = chip->get_position[stream](chip, azx_dev);
665 else { /* use the position buffer as default */
666 pos = azx_get_pos_posbuf(chip, azx_dev);
667 if (!pos || pos == (u32)-1) {
668 dev_info(chip->card->dev,
669 "Invalid position buffer, using LPIB read method instead.\n");
670 chip->get_position[stream] = azx_get_pos_lpib;
671 if (chip->get_position[0] == azx_get_pos_lpib &&
672 chip->get_position[1] == azx_get_pos_lpib)
673 azx_bus(chip)->use_posbuf = false;
674 pos = azx_get_pos_lpib(chip, azx_dev);
675 chip->get_delay[stream] = NULL;
676 } else {
677 chip->get_position[stream] = azx_get_pos_posbuf;
678 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
679 chip->get_delay[stream] = azx_get_delay_from_lpib;
680 }
681 }
682
683 if (pos >= azx_dev->core.bufsize)
684 pos = 0;
685
686 if (WARN_ONCE(!azx_dev->core.period_bytes,
687 "hda-intel: zero azx_dev->period_bytes"))
688 return -1; /* this shouldn't happen! */
689 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
690 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
691 /* NG - it's below the first next period boundary */
692 return chip->bdl_pos_adj ? 0 : -1;
693 azx_dev->core.start_wallclk += wallclk;
694
695 if (azx_dev->core.no_period_wakeup)
696 return 1; /* OK, no need to check period boundary */
697
698 if (runtime->hw_ptr_base != runtime->hw_ptr_interrupt)
699 return 1; /* OK, already in hwptr updating process */
700
701 /* check whether the period gets really elapsed */
702 pos = bytes_to_frames(runtime, pos);
703 hwptr = runtime->hw_ptr_base + pos;
704 if (hwptr < runtime->status->hw_ptr)
705 hwptr += runtime->buffer_size;
706 target = runtime->hw_ptr_interrupt + runtime->period_size;
707 if (hwptr < target) {
708 /* too early wakeup, process it later */
709 return chip->bdl_pos_adj ? 0 : -1;
710 }
711
712 return 1; /* OK, it's fine */
713 }
714
715 /*
716 * The work for pending PCM period updates.
717 */
azx_irq_pending_work(struct work_struct * work)718 static void azx_irq_pending_work(struct work_struct *work)
719 {
720 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
721 struct azx *chip = &hda->chip;
722 struct hdac_bus *bus = azx_bus(chip);
723 struct hdac_stream *s;
724 int pending, ok;
725
726 if (!hda->irq_pending_warned) {
727 dev_info(chip->card->dev,
728 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
729 chip->card->number);
730 hda->irq_pending_warned = 1;
731 }
732
733 for (;;) {
734 pending = 0;
735 spin_lock_irq(&bus->reg_lock);
736 list_for_each_entry(s, &bus->stream_list, list) {
737 struct azx_dev *azx_dev = stream_to_azx_dev(s);
738 if (!azx_dev->irq_pending ||
739 !s->substream ||
740 !s->running)
741 continue;
742 ok = azx_position_ok(chip, azx_dev);
743 if (ok > 0) {
744 azx_dev->irq_pending = 0;
745 spin_unlock(&bus->reg_lock);
746 snd_pcm_period_elapsed(s->substream);
747 spin_lock(&bus->reg_lock);
748 } else if (ok < 0) {
749 pending = 0; /* too early */
750 } else
751 pending++;
752 }
753 spin_unlock_irq(&bus->reg_lock);
754 if (!pending)
755 return;
756 msleep(1);
757 }
758 }
759
760 /* clear irq_pending flags and assure no on-going workq */
azx_clear_irq_pending(struct azx * chip)761 static void azx_clear_irq_pending(struct azx *chip)
762 {
763 struct hdac_bus *bus = azx_bus(chip);
764 struct hdac_stream *s;
765
766 spin_lock_irq(&bus->reg_lock);
767 list_for_each_entry(s, &bus->stream_list, list) {
768 struct azx_dev *azx_dev = stream_to_azx_dev(s);
769 azx_dev->irq_pending = 0;
770 }
771 spin_unlock_irq(&bus->reg_lock);
772 }
773
azx_acquire_irq(struct azx * chip,int do_disconnect)774 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
775 {
776 struct hdac_bus *bus = azx_bus(chip);
777 int ret;
778
779 if (!chip->msi || pci_alloc_irq_vectors(chip->pci, 1, 1, PCI_IRQ_MSI) < 0) {
780 ret = pci_alloc_irq_vectors(chip->pci, 1, 1, PCI_IRQ_INTX);
781 if (ret < 0)
782 return ret;
783 chip->msi = 0;
784 }
785
786 if (request_irq(chip->pci->irq, azx_interrupt,
787 chip->msi ? 0 : IRQF_SHARED,
788 chip->card->irq_descr, chip)) {
789 dev_err(chip->card->dev,
790 "unable to grab IRQ %d, disabling device\n",
791 chip->pci->irq);
792 if (do_disconnect)
793 snd_card_disconnect(chip->card);
794 return -1;
795 }
796 bus->irq = chip->pci->irq;
797 chip->card->sync_irq = bus->irq;
798 return 0;
799 }
800
801 /* get the current DMA position with correction on VIA chips */
azx_via_get_position(struct azx * chip,struct azx_dev * azx_dev)802 static unsigned int azx_via_get_position(struct azx *chip,
803 struct azx_dev *azx_dev)
804 {
805 unsigned int link_pos, mini_pos, bound_pos;
806 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
807 unsigned int fifo_size;
808
809 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
810 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
811 /* Playback, no problem using link position */
812 return link_pos;
813 }
814
815 /* Capture */
816 /* For new chipset,
817 * use mod to get the DMA position just like old chipset
818 */
819 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
820 mod_dma_pos %= azx_dev->core.period_bytes;
821
822 fifo_size = azx_stream(azx_dev)->fifo_size;
823
824 if (azx_dev->insufficient) {
825 /* Link position never gather than FIFO size */
826 if (link_pos <= fifo_size)
827 return 0;
828
829 azx_dev->insufficient = 0;
830 }
831
832 if (link_pos <= fifo_size)
833 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
834 else
835 mini_pos = link_pos - fifo_size;
836
837 /* Find nearest previous boudary */
838 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
839 mod_link_pos = link_pos % azx_dev->core.period_bytes;
840 if (mod_link_pos >= fifo_size)
841 bound_pos = link_pos - mod_link_pos;
842 else if (mod_dma_pos >= mod_mini_pos)
843 bound_pos = mini_pos - mod_mini_pos;
844 else {
845 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
846 if (bound_pos >= azx_dev->core.bufsize)
847 bound_pos = 0;
848 }
849
850 /* Calculate real DMA position we want */
851 return bound_pos + mod_dma_pos;
852 }
853
854 #define AMD_FIFO_SIZE 32
855
856 /* get the current DMA position with FIFO size correction */
azx_get_pos_fifo(struct azx * chip,struct azx_dev * azx_dev)857 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
858 {
859 struct snd_pcm_substream *substream = azx_dev->core.substream;
860 struct snd_pcm_runtime *runtime = substream->runtime;
861 unsigned int pos, delay;
862
863 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
864 if (!runtime)
865 return pos;
866
867 runtime->delay = AMD_FIFO_SIZE;
868 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
869 if (azx_dev->insufficient) {
870 if (pos < delay) {
871 delay = pos;
872 runtime->delay = bytes_to_frames(runtime, pos);
873 } else {
874 azx_dev->insufficient = 0;
875 }
876 }
877
878 /* correct the DMA position for capture stream */
879 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
880 if (pos < delay)
881 pos += azx_dev->core.bufsize;
882 pos -= delay;
883 }
884
885 return pos;
886 }
887
azx_get_delay_from_fifo(struct azx * chip,struct azx_dev * azx_dev,unsigned int pos)888 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
889 unsigned int pos)
890 {
891 struct snd_pcm_substream *substream = azx_dev->core.substream;
892
893 /* just read back the calculated value in the above */
894 return substream->runtime->delay;
895 }
896
__azx_shutdown_chip(struct azx * chip,bool skip_link_reset)897 static void __azx_shutdown_chip(struct azx *chip, bool skip_link_reset)
898 {
899 azx_stop_chip(chip);
900 if (!skip_link_reset)
901 azx_enter_link_reset(chip);
902 azx_clear_irq_pending(chip);
903 display_power(chip, false);
904 }
905
906 static DEFINE_MUTEX(card_list_lock);
907 static LIST_HEAD(card_list);
908
azx_shutdown_chip(struct azx * chip)909 static void azx_shutdown_chip(struct azx *chip)
910 {
911 __azx_shutdown_chip(chip, false);
912 }
913
azx_add_card_list(struct azx * chip)914 static void azx_add_card_list(struct azx *chip)
915 {
916 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
917 mutex_lock(&card_list_lock);
918 list_add(&hda->list, &card_list);
919 mutex_unlock(&card_list_lock);
920 }
921
azx_del_card_list(struct azx * chip)922 static void azx_del_card_list(struct azx *chip)
923 {
924 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
925 mutex_lock(&card_list_lock);
926 list_del_init(&hda->list);
927 mutex_unlock(&card_list_lock);
928 }
929
930 /* trigger power-save check at writing parameter */
param_set_xint(const char * val,const struct kernel_param * kp)931 static int __maybe_unused param_set_xint(const char *val, const struct kernel_param *kp)
932 {
933 struct hda_intel *hda;
934 struct azx *chip;
935 int prev = power_save;
936 int ret = param_set_int(val, kp);
937
938 if (ret || prev == power_save)
939 return ret;
940
941 if (pm_blacklist > 0)
942 return 0;
943
944 mutex_lock(&card_list_lock);
945 list_for_each_entry(hda, &card_list, list) {
946 chip = &hda->chip;
947 if (!hda->probe_continued || chip->disabled ||
948 hda->runtime_pm_disabled)
949 continue;
950 snd_hda_set_power_save(&chip->bus, power_save * 1000);
951 }
952 mutex_unlock(&card_list_lock);
953 return 0;
954 }
955
956 /*
957 * power management
958 */
azx_is_pm_ready(struct snd_card * card)959 static bool azx_is_pm_ready(struct snd_card *card)
960 {
961 struct azx *chip;
962 struct hda_intel *hda;
963
964 if (!card)
965 return false;
966 chip = card->private_data;
967 hda = container_of(chip, struct hda_intel, chip);
968 if (chip->disabled || hda->init_failed || !chip->running)
969 return false;
970 return true;
971 }
972
__azx_runtime_resume(struct azx * chip)973 static void __azx_runtime_resume(struct azx *chip)
974 {
975 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
976 struct hdac_bus *bus = azx_bus(chip);
977 struct hda_codec *codec;
978 int status;
979
980 display_power(chip, true);
981 if (hda->need_i915_power)
982 snd_hdac_i915_set_bclk(bus);
983
984 /* Read STATESTS before controller reset */
985 status = azx_readw(chip, STATESTS);
986
987 azx_init_pci(chip);
988 hda_intel_init_chip(chip, true);
989
990 /* Avoid codec resume if runtime resume is for system suspend */
991 if (!chip->pm_prepared) {
992 list_for_each_codec(codec, &chip->bus) {
993 if (codec->relaxed_resume)
994 continue;
995
996 if (codec->forced_resume || (status & (1 << codec->addr)))
997 pm_request_resume(hda_codec_dev(codec));
998 }
999 }
1000
1001 /* power down again for link-controlled chips */
1002 if (!hda->need_i915_power)
1003 display_power(chip, false);
1004 }
1005
azx_prepare(struct device * dev)1006 static int azx_prepare(struct device *dev)
1007 {
1008 struct snd_card *card = dev_get_drvdata(dev);
1009 struct azx *chip;
1010
1011 if (!azx_is_pm_ready(card))
1012 return 0;
1013
1014 chip = card->private_data;
1015 chip->pm_prepared = 1;
1016 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1017
1018 flush_work(&azx_bus(chip)->unsol_work);
1019
1020 /* HDA controller always requires different WAKEEN for runtime suspend
1021 * and system suspend, so don't use direct-complete here.
1022 */
1023 return 0;
1024 }
1025
azx_complete(struct device * dev)1026 static void azx_complete(struct device *dev)
1027 {
1028 struct snd_card *card = dev_get_drvdata(dev);
1029 struct azx *chip;
1030
1031 if (!azx_is_pm_ready(card))
1032 return;
1033
1034 chip = card->private_data;
1035 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1036 chip->pm_prepared = 0;
1037 }
1038
azx_suspend(struct device * dev)1039 static int azx_suspend(struct device *dev)
1040 {
1041 struct snd_card *card = dev_get_drvdata(dev);
1042 struct azx *chip;
1043
1044 if (!azx_is_pm_ready(card))
1045 return 0;
1046
1047 chip = card->private_data;
1048 azx_shutdown_chip(chip);
1049
1050 trace_azx_suspend(chip);
1051 return 0;
1052 }
1053
azx_resume(struct device * dev)1054 static int azx_resume(struct device *dev)
1055 {
1056 struct snd_card *card = dev_get_drvdata(dev);
1057 struct azx *chip;
1058
1059 if (!azx_is_pm_ready(card))
1060 return 0;
1061
1062 chip = card->private_data;
1063
1064 __azx_runtime_resume(chip);
1065
1066 trace_azx_resume(chip);
1067 return 0;
1068 }
1069
1070 /* put codec down to D3 at hibernation for Intel SKL+;
1071 * otherwise BIOS may still access the codec and screw up the driver
1072 */
azx_freeze_noirq(struct device * dev)1073 static int azx_freeze_noirq(struct device *dev)
1074 {
1075 struct snd_card *card = dev_get_drvdata(dev);
1076 struct azx *chip = card->private_data;
1077 struct pci_dev *pci = to_pci_dev(dev);
1078
1079 if (!azx_is_pm_ready(card))
1080 return 0;
1081 if (chip->driver_type == AZX_DRIVER_SKL)
1082 pci_set_power_state(pci, PCI_D3hot);
1083
1084 return 0;
1085 }
1086
azx_thaw_noirq(struct device * dev)1087 static int azx_thaw_noirq(struct device *dev)
1088 {
1089 struct snd_card *card = dev_get_drvdata(dev);
1090 struct azx *chip = card->private_data;
1091 struct pci_dev *pci = to_pci_dev(dev);
1092
1093 if (!azx_is_pm_ready(card))
1094 return 0;
1095 if (chip->driver_type == AZX_DRIVER_SKL)
1096 pci_set_power_state(pci, PCI_D0);
1097
1098 return 0;
1099 }
1100
azx_runtime_suspend(struct device * dev)1101 static int azx_runtime_suspend(struct device *dev)
1102 {
1103 struct snd_card *card = dev_get_drvdata(dev);
1104 struct azx *chip;
1105
1106 if (!azx_is_pm_ready(card))
1107 return 0;
1108 chip = card->private_data;
1109
1110 /* enable controller wake up event */
1111 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK);
1112
1113 azx_shutdown_chip(chip);
1114 trace_azx_runtime_suspend(chip);
1115 return 0;
1116 }
1117
azx_runtime_resume(struct device * dev)1118 static int azx_runtime_resume(struct device *dev)
1119 {
1120 struct snd_card *card = dev_get_drvdata(dev);
1121 struct azx *chip;
1122
1123 if (!azx_is_pm_ready(card))
1124 return 0;
1125 chip = card->private_data;
1126 __azx_runtime_resume(chip);
1127
1128 /* disable controller Wake Up event*/
1129 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK);
1130
1131 trace_azx_runtime_resume(chip);
1132 return 0;
1133 }
1134
azx_runtime_idle(struct device * dev)1135 static int azx_runtime_idle(struct device *dev)
1136 {
1137 struct snd_card *card = dev_get_drvdata(dev);
1138 struct azx *chip;
1139 struct hda_intel *hda;
1140
1141 if (!card)
1142 return 0;
1143
1144 chip = card->private_data;
1145 hda = container_of(chip, struct hda_intel, chip);
1146 if (chip->disabled || hda->init_failed)
1147 return 0;
1148
1149 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1150 azx_bus(chip)->codec_powered || !chip->running)
1151 return -EBUSY;
1152
1153 /* ELD notification gets broken when HD-audio bus is off */
1154 if (needs_eld_notify_link(chip))
1155 return -EBUSY;
1156
1157 return 0;
1158 }
1159
1160 static const struct dev_pm_ops azx_pm = {
1161 SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1162 .prepare = pm_sleep_ptr(azx_prepare),
1163 .complete = pm_sleep_ptr(azx_complete),
1164 .freeze_noirq = pm_sleep_ptr(azx_freeze_noirq),
1165 .thaw_noirq = pm_sleep_ptr(azx_thaw_noirq),
1166 RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1167 };
1168
1169
1170 static int azx_probe_continue(struct azx *chip);
1171
1172 #ifdef SUPPORT_VGA_SWITCHEROO
1173 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1174
azx_vs_set_state(struct pci_dev * pci,enum vga_switcheroo_state state)1175 static void azx_vs_set_state(struct pci_dev *pci,
1176 enum vga_switcheroo_state state)
1177 {
1178 struct snd_card *card = pci_get_drvdata(pci);
1179 struct azx *chip = card->private_data;
1180 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1181 struct hda_codec *codec;
1182 bool disabled;
1183
1184 wait_for_completion(&hda->probe_wait);
1185 if (hda->init_failed)
1186 return;
1187
1188 disabled = (state == VGA_SWITCHEROO_OFF);
1189 if (chip->disabled == disabled)
1190 return;
1191
1192 if (!hda->probe_continued) {
1193 chip->disabled = disabled;
1194 if (!disabled) {
1195 dev_info(chip->card->dev,
1196 "Start delayed initialization\n");
1197 if (azx_probe_continue(chip) < 0)
1198 dev_err(chip->card->dev, "initialization error\n");
1199 }
1200 } else {
1201 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1202 disabled ? "Disabling" : "Enabling");
1203 if (disabled) {
1204 list_for_each_codec(codec, &chip->bus) {
1205 pm_runtime_suspend(hda_codec_dev(codec));
1206 pm_runtime_disable(hda_codec_dev(codec));
1207 }
1208 pm_runtime_suspend(card->dev);
1209 pm_runtime_disable(card->dev);
1210 /* when we get suspended by vga_switcheroo we end up in D3cold,
1211 * however we have no ACPI handle, so pci/acpi can't put us there,
1212 * put ourselves there */
1213 pci->current_state = PCI_D3cold;
1214 chip->disabled = true;
1215 if (snd_hda_lock_devices(&chip->bus))
1216 dev_warn(chip->card->dev,
1217 "Cannot lock devices!\n");
1218 } else {
1219 snd_hda_unlock_devices(&chip->bus);
1220 chip->disabled = false;
1221 pm_runtime_enable(card->dev);
1222 list_for_each_codec(codec, &chip->bus) {
1223 pm_runtime_enable(hda_codec_dev(codec));
1224 pm_runtime_resume(hda_codec_dev(codec));
1225 }
1226 }
1227 }
1228 }
1229
azx_vs_can_switch(struct pci_dev * pci)1230 static bool azx_vs_can_switch(struct pci_dev *pci)
1231 {
1232 struct snd_card *card = pci_get_drvdata(pci);
1233 struct azx *chip = card->private_data;
1234 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1235
1236 wait_for_completion(&hda->probe_wait);
1237 if (hda->init_failed)
1238 return false;
1239 if (chip->disabled || !hda->probe_continued)
1240 return true;
1241 if (snd_hda_lock_devices(&chip->bus))
1242 return false;
1243 snd_hda_unlock_devices(&chip->bus);
1244 return true;
1245 }
1246
1247 /*
1248 * The discrete GPU cannot power down unless the HDA controller runtime
1249 * suspends, so activate runtime PM on codecs even if power_save == 0.
1250 */
setup_vga_switcheroo_runtime_pm(struct azx * chip)1251 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1252 {
1253 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1254 struct hda_codec *codec;
1255
1256 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
1257 list_for_each_codec(codec, &chip->bus)
1258 codec->auto_runtime_pm = 1;
1259 /* reset the power save setup */
1260 if (chip->running)
1261 set_default_power_save(chip);
1262 }
1263 }
1264
azx_vs_gpu_bound(struct pci_dev * pci,enum vga_switcheroo_client_id client_id)1265 static void azx_vs_gpu_bound(struct pci_dev *pci,
1266 enum vga_switcheroo_client_id client_id)
1267 {
1268 struct snd_card *card = pci_get_drvdata(pci);
1269 struct azx *chip = card->private_data;
1270
1271 if (client_id == VGA_SWITCHEROO_DIS)
1272 chip->bus.keep_power = 0;
1273 setup_vga_switcheroo_runtime_pm(chip);
1274 }
1275
init_vga_switcheroo(struct azx * chip)1276 static void init_vga_switcheroo(struct azx *chip)
1277 {
1278 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1279 struct pci_dev *p = get_bound_vga(chip->pci);
1280 struct pci_dev *parent;
1281 if (p) {
1282 dev_info(chip->card->dev,
1283 "Handle vga_switcheroo audio client\n");
1284 hda->use_vga_switcheroo = 1;
1285
1286 /* cleared in either gpu_bound op or codec probe, or when its
1287 * upstream port has _PR3 (i.e. dGPU).
1288 */
1289 parent = pci_upstream_bridge(p);
1290 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
1291 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1292 pci_dev_put(p);
1293 }
1294 }
1295
1296 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1297 .set_gpu_state = azx_vs_set_state,
1298 .can_switch = azx_vs_can_switch,
1299 .gpu_bound = azx_vs_gpu_bound,
1300 };
1301
register_vga_switcheroo(struct azx * chip)1302 static int register_vga_switcheroo(struct azx *chip)
1303 {
1304 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1305 struct pci_dev *p;
1306 int err;
1307
1308 if (!hda->use_vga_switcheroo)
1309 return 0;
1310
1311 p = get_bound_vga(chip->pci);
1312 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1313 pci_dev_put(p);
1314
1315 if (err < 0)
1316 return err;
1317 hda->vga_switcheroo_registered = 1;
1318
1319 return 0;
1320 }
1321 #else
1322 #define init_vga_switcheroo(chip) /* NOP */
1323 #define register_vga_switcheroo(chip) 0
1324 #define check_hdmi_disabled(pci) false
1325 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */
1326 #endif /* SUPPORT_VGA_SWITCHER */
1327
1328 /*
1329 * destructor
1330 */
azx_free(struct azx * chip)1331 static void azx_free(struct azx *chip)
1332 {
1333 struct pci_dev *pci = chip->pci;
1334 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1335 struct hdac_bus *bus = azx_bus(chip);
1336
1337 if (hda->freed)
1338 return;
1339
1340 if (azx_has_pm_runtime(chip) && chip->running) {
1341 pm_runtime_get_noresume(&pci->dev);
1342 pm_runtime_forbid(&pci->dev);
1343 pm_runtime_dont_use_autosuspend(&pci->dev);
1344 }
1345
1346 chip->running = 0;
1347
1348 azx_del_card_list(chip);
1349
1350 hda->init_failed = 1; /* to be sure */
1351 complete_all(&hda->probe_wait);
1352
1353 if (use_vga_switcheroo(hda)) {
1354 if (chip->disabled && hda->probe_continued)
1355 snd_hda_unlock_devices(&chip->bus);
1356 if (hda->vga_switcheroo_registered) {
1357 vga_switcheroo_unregister_client(chip->pci);
1358
1359 /* Some GPUs don't have sound, and azx_first_init fails,
1360 * leaving the device probed but non-functional. As long
1361 * as it's probed, the PCI subsystem keeps its runtime
1362 * PM status as active. Force it to suspended (as we
1363 * actually stop the chip) to allow GPU to suspend via
1364 * vga_switcheroo, and print a warning.
1365 */
1366 dev_warn(&pci->dev, "GPU sound probed, but not operational: please add a quirk to driver_denylist\n");
1367 pm_runtime_disable(&pci->dev);
1368 pm_runtime_set_suspended(&pci->dev);
1369 pm_runtime_enable(&pci->dev);
1370 }
1371 }
1372
1373 if (bus->chip_init) {
1374 azx_clear_irq_pending(chip);
1375 azx_stop_all_streams(chip);
1376 azx_stop_chip(chip);
1377 }
1378
1379 if (bus->irq >= 0)
1380 free_irq(bus->irq, (void*)chip);
1381
1382 azx_free_stream_pages(chip);
1383 azx_free_streams(chip);
1384 snd_hdac_bus_exit(bus);
1385
1386 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1387 release_firmware(chip->fw);
1388 #endif
1389 display_power(chip, false);
1390
1391 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1392 snd_hdac_i915_exit(bus);
1393
1394 hda->freed = 1;
1395 }
1396
azx_dev_disconnect(struct snd_device * device)1397 static int azx_dev_disconnect(struct snd_device *device)
1398 {
1399 struct azx *chip = device->device_data;
1400 struct hdac_bus *bus = azx_bus(chip);
1401
1402 chip->bus.shutdown = 1;
1403 cancel_work_sync(&bus->unsol_work);
1404
1405 return 0;
1406 }
1407
azx_dev_free(struct snd_device * device)1408 static int azx_dev_free(struct snd_device *device)
1409 {
1410 azx_free(device->device_data);
1411 return 0;
1412 }
1413
1414 #ifdef SUPPORT_VGA_SWITCHEROO
1415 #ifdef CONFIG_ACPI
1416 /* ATPX is in the integrated GPU's namespace */
atpx_present(void)1417 static bool atpx_present(void)
1418 {
1419 struct pci_dev *pdev = NULL;
1420 acpi_handle dhandle, atpx_handle;
1421 acpi_status status;
1422
1423 while ((pdev = pci_get_base_class(PCI_BASE_CLASS_DISPLAY, pdev))) {
1424 if ((pdev->class != PCI_CLASS_DISPLAY_VGA << 8) &&
1425 (pdev->class != PCI_CLASS_DISPLAY_OTHER << 8))
1426 continue;
1427
1428 dhandle = ACPI_HANDLE(&pdev->dev);
1429 if (dhandle) {
1430 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1431 if (ACPI_SUCCESS(status)) {
1432 pci_dev_put(pdev);
1433 return true;
1434 }
1435 }
1436 }
1437 return false;
1438 }
1439 #else
atpx_present(void)1440 static bool atpx_present(void)
1441 {
1442 return false;
1443 }
1444 #endif
1445
1446 /*
1447 * Check of disabled HDMI controller by vga_switcheroo
1448 */
get_bound_vga(struct pci_dev * pci)1449 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1450 {
1451 struct pci_dev *p;
1452
1453 /* check only discrete GPU */
1454 switch (pci->vendor) {
1455 case PCI_VENDOR_ID_ATI:
1456 case PCI_VENDOR_ID_AMD:
1457 if (pci->devfn == 1) {
1458 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1459 pci->bus->number, 0);
1460 if (p) {
1461 /* ATPX is in the integrated GPU's ACPI namespace
1462 * rather than the dGPU's namespace. However,
1463 * the dGPU is the one who is involved in
1464 * vgaswitcheroo.
1465 */
1466 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
1467 (atpx_present() || apple_gmux_detect(NULL, NULL)))
1468 return p;
1469 pci_dev_put(p);
1470 }
1471 }
1472 break;
1473 case PCI_VENDOR_ID_NVIDIA:
1474 if (pci->devfn == 1) {
1475 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1476 pci->bus->number, 0);
1477 if (p) {
1478 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1479 return p;
1480 pci_dev_put(p);
1481 }
1482 }
1483 break;
1484 }
1485 return NULL;
1486 }
1487
check_hdmi_disabled(struct pci_dev * pci)1488 static bool check_hdmi_disabled(struct pci_dev *pci)
1489 {
1490 bool vga_inactive = false;
1491 struct pci_dev *p = get_bound_vga(pci);
1492
1493 if (p) {
1494 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1495 vga_inactive = true;
1496 pci_dev_put(p);
1497 }
1498 return vga_inactive;
1499 }
1500 #endif /* SUPPORT_VGA_SWITCHEROO */
1501
1502 /*
1503 * allow/deny-listing for position_fix
1504 */
1505 static const struct snd_pci_quirk position_fix_list[] = {
1506 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1507 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1508 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1509 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1510 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1511 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1512 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1513 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1514 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1515 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1516 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1517 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1518 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1519 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1520 {}
1521 };
1522
check_position_fix(struct azx * chip,int fix)1523 static int check_position_fix(struct azx *chip, int fix)
1524 {
1525 const struct snd_pci_quirk *q;
1526
1527 switch (fix) {
1528 case POS_FIX_AUTO:
1529 case POS_FIX_LPIB:
1530 case POS_FIX_POSBUF:
1531 case POS_FIX_VIACOMBO:
1532 case POS_FIX_COMBO:
1533 case POS_FIX_SKL:
1534 case POS_FIX_FIFO:
1535 return fix;
1536 }
1537
1538 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1539 if (q) {
1540 dev_info(chip->card->dev,
1541 "position_fix set to %d for device %04x:%04x\n",
1542 q->value, q->subvendor, q->subdevice);
1543 return q->value;
1544 }
1545
1546 /* Check VIA/ATI HD Audio Controller exist */
1547 if (chip->driver_type == AZX_DRIVER_VIA) {
1548 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1549 return POS_FIX_VIACOMBO;
1550 }
1551 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1552 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1553 return POS_FIX_FIFO;
1554 }
1555 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1556 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1557 return POS_FIX_LPIB;
1558 }
1559 if (chip->driver_type == AZX_DRIVER_SKL) {
1560 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1561 return POS_FIX_SKL;
1562 }
1563 return POS_FIX_AUTO;
1564 }
1565
assign_position_fix(struct azx * chip,int fix)1566 static void assign_position_fix(struct azx *chip, int fix)
1567 {
1568 static const azx_get_pos_callback_t callbacks[] = {
1569 [POS_FIX_AUTO] = NULL,
1570 [POS_FIX_LPIB] = azx_get_pos_lpib,
1571 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1572 [POS_FIX_VIACOMBO] = azx_via_get_position,
1573 [POS_FIX_COMBO] = azx_get_pos_lpib,
1574 [POS_FIX_SKL] = azx_get_pos_posbuf,
1575 [POS_FIX_FIFO] = azx_get_pos_fifo,
1576 };
1577
1578 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1579
1580 /* combo mode uses LPIB only for playback */
1581 if (fix == POS_FIX_COMBO)
1582 chip->get_position[1] = NULL;
1583
1584 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1585 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1586 chip->get_delay[0] = chip->get_delay[1] =
1587 azx_get_delay_from_lpib;
1588 }
1589
1590 if (fix == POS_FIX_FIFO)
1591 chip->get_delay[0] = chip->get_delay[1] =
1592 azx_get_delay_from_fifo;
1593 }
1594
1595 /*
1596 * deny-lists for probe_mask
1597 */
1598 static const struct snd_pci_quirk probe_mask_list[] = {
1599 /* Thinkpad often breaks the controller communication when accessing
1600 * to the non-working (or non-existing) modem codec slot.
1601 */
1602 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1603 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1604 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1605 /* broken BIOS */
1606 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1607 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1608 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1609 /* forced codec slots */
1610 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1611 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1612 SND_PCI_QUIRK(0x1558, 0x0351, "Schenker Dock 15", 0x105),
1613 /* WinFast VP200 H (Teradici) user reported broken communication */
1614 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1615 {}
1616 };
1617
1618 #define AZX_FORCE_CODEC_MASK 0x100
1619
check_probe_mask(struct azx * chip,int dev)1620 static void check_probe_mask(struct azx *chip, int dev)
1621 {
1622 const struct snd_pci_quirk *q;
1623
1624 chip->codec_probe_mask = probe_mask[dev];
1625 if (chip->codec_probe_mask == -1) {
1626 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1627 if (q) {
1628 dev_info(chip->card->dev,
1629 "probe_mask set to 0x%x for device %04x:%04x\n",
1630 q->value, q->subvendor, q->subdevice);
1631 chip->codec_probe_mask = q->value;
1632 }
1633 }
1634
1635 /* check forced option */
1636 if (chip->codec_probe_mask != -1 &&
1637 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1638 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1639 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1640 (int)azx_bus(chip)->codec_mask);
1641 }
1642 }
1643
1644 /*
1645 * allow/deny-list for enable_msi
1646 */
1647 static const struct snd_pci_quirk msi_deny_list[] = {
1648 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1649 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1650 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1651 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1652 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1653 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1654 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1655 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1656 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1657 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1658 {}
1659 };
1660
check_msi(struct azx * chip)1661 static void check_msi(struct azx *chip)
1662 {
1663 const struct snd_pci_quirk *q;
1664
1665 if (enable_msi >= 0) {
1666 chip->msi = !!enable_msi;
1667 return;
1668 }
1669 chip->msi = 1; /* enable MSI as default */
1670 q = snd_pci_quirk_lookup(chip->pci, msi_deny_list);
1671 if (q) {
1672 dev_info(chip->card->dev,
1673 "msi for device %04x:%04x set to %d\n",
1674 q->subvendor, q->subdevice, q->value);
1675 chip->msi = q->value;
1676 return;
1677 }
1678
1679 /* NVidia chipsets seem to cause troubles with MSI */
1680 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1681 dev_info(chip->card->dev, "Disabling MSI\n");
1682 chip->msi = 0;
1683 }
1684 }
1685
1686 /* check the snoop mode availability */
azx_check_snoop_available(struct azx * chip)1687 static void azx_check_snoop_available(struct azx *chip)
1688 {
1689 int snoop = hda_snoop;
1690
1691 if (snoop >= 0) {
1692 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1693 snoop ? "snoop" : "non-snoop");
1694 chip->snoop = snoop;
1695 chip->uc_buffer = !snoop;
1696 return;
1697 }
1698
1699 snoop = true;
1700 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1701 chip->driver_type == AZX_DRIVER_VIA) {
1702 /* force to non-snoop mode for a new VIA controller
1703 * when BIOS is set
1704 */
1705 u8 val;
1706 pci_read_config_byte(chip->pci, 0x42, &val);
1707 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1708 chip->pci->revision == 0x20))
1709 snoop = false;
1710 }
1711
1712 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1713 snoop = false;
1714
1715 chip->snoop = snoop;
1716 if (!snoop) {
1717 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1718 /* C-Media requires non-cached pages only for CORB/RIRB */
1719 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1720 chip->uc_buffer = true;
1721 }
1722 }
1723
azx_probe_work(struct work_struct * work)1724 static void azx_probe_work(struct work_struct *work)
1725 {
1726 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work.work);
1727 azx_probe_continue(&hda->chip);
1728 }
1729
default_bdl_pos_adj(struct azx * chip)1730 static int default_bdl_pos_adj(struct azx *chip)
1731 {
1732 /* some exceptions: Atoms seem problematic with value 1 */
1733 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1734 switch (chip->pci->device) {
1735 case PCI_DEVICE_ID_INTEL_HDA_BYT:
1736 case PCI_DEVICE_ID_INTEL_HDA_BSW:
1737 return 32;
1738 case PCI_DEVICE_ID_INTEL_HDA_APL:
1739 return 64;
1740 }
1741 }
1742
1743 switch (chip->driver_type) {
1744 /*
1745 * increase the bdl size for Glenfly Gpus for hardware
1746 * limitation on hdac interrupt interval
1747 */
1748 case AZX_DRIVER_GFHDMI:
1749 return 128;
1750 case AZX_DRIVER_ICH:
1751 case AZX_DRIVER_PCH:
1752 return 1;
1753 default:
1754 return 32;
1755 }
1756 }
1757
1758 /*
1759 * constructor
1760 */
1761 static const struct hda_controller_ops pci_hda_ops;
1762
azx_create(struct snd_card * card,struct pci_dev * pci,int dev,unsigned int driver_caps,struct azx ** rchip)1763 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1764 int dev, unsigned int driver_caps,
1765 struct azx **rchip)
1766 {
1767 static const struct snd_device_ops ops = {
1768 .dev_disconnect = azx_dev_disconnect,
1769 .dev_free = azx_dev_free,
1770 };
1771 struct hda_intel *hda;
1772 struct azx *chip;
1773 int err;
1774
1775 *rchip = NULL;
1776
1777 err = pcim_enable_device(pci);
1778 if (err < 0)
1779 return err;
1780
1781 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL);
1782 if (!hda)
1783 return -ENOMEM;
1784
1785 chip = &hda->chip;
1786 mutex_init(&chip->open_mutex);
1787 chip->card = card;
1788 chip->pci = pci;
1789 chip->ops = &pci_hda_ops;
1790 chip->driver_caps = driver_caps;
1791 chip->driver_type = driver_caps & 0xff;
1792 check_msi(chip);
1793 chip->dev_index = dev;
1794 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1795 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1796 INIT_LIST_HEAD(&chip->pcm_list);
1797 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1798 INIT_LIST_HEAD(&hda->list);
1799 init_vga_switcheroo(chip);
1800 init_completion(&hda->probe_wait);
1801
1802 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1803
1804 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1805 chip->fallback_to_single_cmd = 1;
1806 else /* explicitly set to single_cmd or not */
1807 chip->single_cmd = single_cmd;
1808
1809 azx_check_snoop_available(chip);
1810
1811 if (bdl_pos_adj[dev] < 0)
1812 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1813 else
1814 chip->bdl_pos_adj = bdl_pos_adj[dev];
1815
1816 err = azx_bus_init(chip, model[dev]);
1817 if (err < 0)
1818 return err;
1819
1820 /* use the non-cached pages in non-snoop mode */
1821 if (!azx_snoop(chip))
1822 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_WC;
1823
1824 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1825 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1826 chip->bus.core.needs_damn_long_delay = 1;
1827 }
1828
1829 check_probe_mask(chip, dev);
1830
1831 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1832 if (err < 0) {
1833 dev_err(card->dev, "Error creating device [card]!\n");
1834 azx_free(chip);
1835 return err;
1836 }
1837
1838 /* continue probing in work context as may trigger request module */
1839 INIT_DELAYED_WORK(&hda->probe_work, azx_probe_work);
1840
1841 *rchip = chip;
1842
1843 return 0;
1844 }
1845
azx_first_init(struct azx * chip)1846 static int azx_first_init(struct azx *chip)
1847 {
1848 int dev = chip->dev_index;
1849 struct pci_dev *pci = chip->pci;
1850 struct snd_card *card = chip->card;
1851 struct hdac_bus *bus = azx_bus(chip);
1852 int err;
1853 unsigned short gcap;
1854 unsigned int dma_bits = 64;
1855
1856 #if BITS_PER_LONG != 64
1857 /* Fix up base address on ULI M5461 */
1858 if (chip->driver_type == AZX_DRIVER_ULI) {
1859 u16 tmp3;
1860 pci_read_config_word(pci, 0x40, &tmp3);
1861 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1862 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1863 }
1864 #endif
1865 /*
1866 * Fix response write request not synced to memory when handle
1867 * hdac interrupt on Glenfly Gpus
1868 */
1869 if (chip->driver_type == AZX_DRIVER_GFHDMI)
1870 bus->polling_mode = 1;
1871
1872 if (chip->driver_type == AZX_DRIVER_LOONGSON) {
1873 bus->polling_mode = 1;
1874 bus->not_use_interrupts = 1;
1875 bus->access_sdnctl_in_dword = 1;
1876 if (!chip->jackpoll_interval)
1877 chip->jackpoll_interval = msecs_to_jiffies(1500);
1878 }
1879
1880 err = pcim_iomap_regions(pci, 1 << 0, "ICH HD audio");
1881 if (err < 0)
1882 return err;
1883
1884 bus->addr = pci_resource_start(pci, 0);
1885 bus->remap_addr = pcim_iomap_table(pci)[0];
1886
1887 if (chip->driver_type == AZX_DRIVER_SKL)
1888 snd_hdac_bus_parse_capabilities(bus);
1889
1890 /*
1891 * Some Intel CPUs has always running timer (ART) feature and
1892 * controller may have Global time sync reporting capability, so
1893 * check both of these before declaring synchronized time reporting
1894 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1895 */
1896 chip->gts_present = false;
1897
1898 #ifdef CONFIG_X86
1899 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1900 chip->gts_present = true;
1901 #endif
1902
1903 if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1904 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1905 pci->no_64bit_msi = true;
1906 }
1907
1908 pci_set_master(pci);
1909
1910 gcap = azx_readw(chip, GCAP);
1911 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1912
1913 /* AMD devices support 40 or 48bit DMA, take the safe one */
1914 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1915 dma_bits = 40;
1916
1917 /* disable SB600 64bit support for safety */
1918 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1919 struct pci_dev *p_smbus;
1920 dma_bits = 40;
1921 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1922 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1923 NULL);
1924 if (p_smbus) {
1925 if (p_smbus->revision < 0x30)
1926 gcap &= ~AZX_GCAP_64OK;
1927 pci_dev_put(p_smbus);
1928 }
1929 }
1930
1931 /* NVidia hardware normally only supports up to 40 bits of DMA */
1932 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1933 dma_bits = 40;
1934
1935 /* disable 64bit DMA address on some devices */
1936 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1937 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1938 gcap &= ~AZX_GCAP_64OK;
1939 }
1940
1941 /* disable buffer size rounding to 128-byte multiples if supported */
1942 if (align_buffer_size >= 0)
1943 chip->align_buffer_size = !!align_buffer_size;
1944 else {
1945 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1946 chip->align_buffer_size = 0;
1947 else
1948 chip->align_buffer_size = 1;
1949 }
1950
1951 /* allow 64bit DMA address if supported by H/W */
1952 if (!(gcap & AZX_GCAP_64OK))
1953 dma_bits = 32;
1954 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits)))
1955 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32));
1956 dma_set_max_seg_size(&pci->dev, UINT_MAX);
1957
1958 /* read number of streams from GCAP register instead of using
1959 * hardcoded value
1960 */
1961 chip->capture_streams = (gcap >> 8) & 0x0f;
1962 chip->playback_streams = (gcap >> 12) & 0x0f;
1963 if (!chip->playback_streams && !chip->capture_streams) {
1964 /* gcap didn't give any info, switching to old method */
1965
1966 switch (chip->driver_type) {
1967 case AZX_DRIVER_ULI:
1968 chip->playback_streams = ULI_NUM_PLAYBACK;
1969 chip->capture_streams = ULI_NUM_CAPTURE;
1970 break;
1971 case AZX_DRIVER_ATIHDMI:
1972 case AZX_DRIVER_ATIHDMI_NS:
1973 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1974 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1975 break;
1976 case AZX_DRIVER_GFHDMI:
1977 case AZX_DRIVER_GENERIC:
1978 default:
1979 chip->playback_streams = ICH6_NUM_PLAYBACK;
1980 chip->capture_streams = ICH6_NUM_CAPTURE;
1981 break;
1982 }
1983 }
1984 chip->capture_index_offset = 0;
1985 chip->playback_index_offset = chip->capture_streams;
1986 chip->num_streams = chip->playback_streams + chip->capture_streams;
1987
1988 /* sanity check for the SDxCTL.STRM field overflow */
1989 if (chip->num_streams > 15 &&
1990 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1991 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1992 "forcing separate stream tags", chip->num_streams);
1993 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1994 }
1995
1996 /* initialize streams */
1997 err = azx_init_streams(chip);
1998 if (err < 0)
1999 return err;
2000
2001 err = azx_alloc_stream_pages(chip);
2002 if (err < 0)
2003 return err;
2004
2005 /* initialize chip */
2006 azx_init_pci(chip);
2007
2008 snd_hdac_i915_set_bclk(bus);
2009
2010 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
2011
2012 /* codec detection */
2013 if (!azx_bus(chip)->codec_mask) {
2014 dev_err(card->dev, "no codecs found!\n");
2015 /* keep running the rest for the runtime PM */
2016 }
2017
2018 if (azx_acquire_irq(chip, 0) < 0)
2019 return -EBUSY;
2020
2021 strcpy(card->driver, "HDA-Intel");
2022 strscpy(card->shortname, driver_short_names[chip->driver_type],
2023 sizeof(card->shortname));
2024 snprintf(card->longname, sizeof(card->longname),
2025 "%s at 0x%lx irq %i",
2026 card->shortname, bus->addr, bus->irq);
2027
2028 return 0;
2029 }
2030
2031 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2032 /* callback from request_firmware_nowait() */
azx_firmware_cb(const struct firmware * fw,void * context)2033 static void azx_firmware_cb(const struct firmware *fw, void *context)
2034 {
2035 struct snd_card *card = context;
2036 struct azx *chip = card->private_data;
2037
2038 if (fw)
2039 chip->fw = fw;
2040 else
2041 dev_err(card->dev, "Cannot load firmware, continue without patching\n");
2042 if (!chip->disabled) {
2043 /* continue probing */
2044 azx_probe_continue(chip);
2045 }
2046 }
2047 #endif
2048
disable_msi_reset_irq(struct azx * chip)2049 static int disable_msi_reset_irq(struct azx *chip)
2050 {
2051 struct hdac_bus *bus = azx_bus(chip);
2052 int err;
2053
2054 free_irq(bus->irq, chip);
2055 bus->irq = -1;
2056 chip->card->sync_irq = -1;
2057 pci_free_irq_vectors(chip->pci);
2058 chip->msi = 0;
2059 err = azx_acquire_irq(chip, 1);
2060 if (err < 0)
2061 return err;
2062
2063 return 0;
2064 }
2065
2066 /* Denylist for skipping the whole probe:
2067 * some HD-audio PCI entries are exposed without any codecs, and such devices
2068 * should be ignored from the beginning.
2069 */
2070 static const struct pci_device_id driver_denylist[] = {
2071 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */
2072 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */
2073 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */
2074 { PCI_DEVICE_SUB(0x1022, 0x15e3, 0x1022, 0xd601) }, /* ASRock X670E Taichi */
2075 {}
2076 };
2077
2078 static struct pci_device_id driver_denylist_ideapad_z570[] = {
2079 { PCI_DEVICE_SUB(0x10de, 0x0bea, 0x0000, 0x0000) }, /* NVIDIA GF108 HDA */
2080 {}
2081 };
2082
2083 /* DMI-based denylist, to be used when:
2084 * - PCI subsystem IDs are zero, impossible to distinguish from valid sound cards.
2085 * - Different modifications of the same laptop use different GPU models.
2086 */
2087 static const struct dmi_system_id driver_denylist_dmi[] = {
2088 {
2089 /* No HDA in NVIDIA DGPU. BIOS disables it, but quirk_nvidia_hda() reenables. */
2090 .matches = {
2091 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
2092 DMI_MATCH(DMI_PRODUCT_VERSION, "Ideapad Z570"),
2093 },
2094 .driver_data = &driver_denylist_ideapad_z570,
2095 },
2096 {}
2097 };
2098
2099 static const struct hda_controller_ops pci_hda_ops = {
2100 .disable_msi_reset_irq = disable_msi_reset_irq,
2101 .position_check = azx_position_check,
2102 };
2103
2104 static DECLARE_BITMAP(probed_devs, SNDRV_CARDS);
2105
azx_probe(struct pci_dev * pci,const struct pci_device_id * pci_id)2106 static int azx_probe(struct pci_dev *pci,
2107 const struct pci_device_id *pci_id)
2108 {
2109 const struct dmi_system_id *dmi;
2110 struct snd_card *card;
2111 struct hda_intel *hda;
2112 struct azx *chip;
2113 bool schedule_probe;
2114 int dev;
2115 int err;
2116
2117 if (pci_match_id(driver_denylist, pci)) {
2118 dev_info(&pci->dev, "Skipping the device on the denylist\n");
2119 return -ENODEV;
2120 }
2121
2122 dmi = dmi_first_match(driver_denylist_dmi);
2123 if (dmi && pci_match_id(dmi->driver_data, pci)) {
2124 dev_info(&pci->dev, "Skipping the device on the DMI denylist\n");
2125 return -ENODEV;
2126 }
2127
2128 dev = find_first_zero_bit(probed_devs, SNDRV_CARDS);
2129 if (dev >= SNDRV_CARDS)
2130 return -ENODEV;
2131 if (!enable[dev]) {
2132 set_bit(dev, probed_devs);
2133 return -ENOENT;
2134 }
2135
2136 /*
2137 * stop probe if another Intel's DSP driver should be activated
2138 */
2139 if (dmic_detect) {
2140 err = snd_intel_dsp_driver_probe(pci);
2141 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) {
2142 dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n");
2143 return -ENODEV;
2144 }
2145 } else {
2146 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n");
2147 }
2148
2149 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2150 0, &card);
2151 if (err < 0) {
2152 dev_err(&pci->dev, "Error creating card!\n");
2153 return err;
2154 }
2155
2156 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2157 if (err < 0)
2158 goto out_free;
2159 card->private_data = chip;
2160 hda = container_of(chip, struct hda_intel, chip);
2161
2162 pci_set_drvdata(pci, card);
2163
2164 #ifdef CONFIG_SND_HDA_I915
2165 /* bind with i915 if needed */
2166 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2167 err = snd_hdac_i915_init(azx_bus(chip));
2168 if (err < 0) {
2169 if (err == -EPROBE_DEFER)
2170 goto out_free;
2171
2172 /* if the controller is bound only with HDMI/DP
2173 * (for HSW and BDW), we need to abort the probe;
2174 * for other chips, still continue probing as other
2175 * codecs can be on the same link.
2176 */
2177 if (HDA_CONTROLLER_IN_GPU(pci)) {
2178 dev_err_probe(card->dev, err,
2179 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2180
2181 goto out_free;
2182 } else {
2183 /* don't bother any longer */
2184 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2185 }
2186 }
2187
2188 /* HSW/BDW controllers need this power */
2189 if (HDA_CONTROLLER_IN_GPU(pci))
2190 hda->need_i915_power = true;
2191 }
2192 #else
2193 if (HDA_CONTROLLER_IN_GPU(pci))
2194 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2195 #endif
2196
2197 err = register_vga_switcheroo(chip);
2198 if (err < 0) {
2199 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2200 goto out_free;
2201 }
2202
2203 if (check_hdmi_disabled(pci)) {
2204 dev_info(card->dev, "VGA controller is disabled\n");
2205 dev_info(card->dev, "Delaying initialization\n");
2206 chip->disabled = true;
2207 }
2208
2209 schedule_probe = !chip->disabled;
2210
2211 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2212 if (patch[dev] && *patch[dev]) {
2213 dev_info(card->dev, "Applying patch firmware '%s'\n",
2214 patch[dev]);
2215 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2216 &pci->dev, GFP_KERNEL, card,
2217 azx_firmware_cb);
2218 if (err < 0)
2219 goto out_free;
2220 schedule_probe = false; /* continued in azx_firmware_cb() */
2221 }
2222 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2223
2224 if (schedule_probe)
2225 schedule_delayed_work(&hda->probe_work, 0);
2226
2227 set_bit(dev, probed_devs);
2228 if (chip->disabled)
2229 complete_all(&hda->probe_wait);
2230 return 0;
2231
2232 out_free:
2233 pci_set_drvdata(pci, NULL);
2234 snd_card_free(card);
2235 return err;
2236 }
2237
2238 /* On some boards setting power_save to a non 0 value leads to clicking /
2239 * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2240 * figure out how to avoid these sounds, but that is not always feasible.
2241 * So we keep a list of devices where we disable powersaving as its known
2242 * to causes problems on these devices.
2243 */
2244 static const struct snd_pci_quirk power_save_denylist[] = {
2245 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2246 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2247 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2248 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2249 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2250 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2251 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2252 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2253 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2254 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2255 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2256 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2257 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2258 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2259 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2260 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2261 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2262 /* https://bugs.launchpad.net/bugs/1821663 */
2263 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2264 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2265 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2266 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2267 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2268 SND_PCI_QUIRK(0x17aa, 0x316e, "Lenovo ThinkCentre M70q", 0),
2269 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2270 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2271 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2272 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2273 /* https://bugs.launchpad.net/bugs/1821663 */
2274 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2275 /* KONTRON SinglePC may cause a stall at runtime resume */
2276 SND_PCI_QUIRK(0x1734, 0x1232, "KONTRON SinglePC", 0),
2277 /* Dell ALC3271 */
2278 SND_PCI_QUIRK(0x1028, 0x0962, "Dell ALC3271", 0),
2279 {}
2280 };
2281
set_default_power_save(struct azx * chip)2282 static void set_default_power_save(struct azx *chip)
2283 {
2284 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2285 int val = power_save;
2286
2287 if (pm_blacklist < 0) {
2288 const struct snd_pci_quirk *q;
2289
2290 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist);
2291 if (q && val) {
2292 dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n",
2293 q->subvendor, q->subdevice);
2294 val = 0;
2295 hda->runtime_pm_disabled = 1;
2296 }
2297 } else if (pm_blacklist > 0) {
2298 dev_info(chip->card->dev, "Forcing power_save to 0 via option\n");
2299 val = 0;
2300 }
2301 snd_hda_set_power_save(&chip->bus, val * 1000);
2302 }
2303
2304 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2305 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2306 [AZX_DRIVER_NVIDIA] = 8,
2307 [AZX_DRIVER_TERA] = 1,
2308 };
2309
azx_probe_continue(struct azx * chip)2310 static int azx_probe_continue(struct azx *chip)
2311 {
2312 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2313 struct hdac_bus *bus = azx_bus(chip);
2314 struct pci_dev *pci = chip->pci;
2315 int dev = chip->dev_index;
2316 int err;
2317
2318 if (chip->disabled || hda->init_failed)
2319 return -EIO;
2320 if (hda->probe_retry)
2321 goto probe_retry;
2322
2323 to_hda_bus(bus)->bus_probing = 1;
2324 hda->probe_continued = 1;
2325
2326 /* Request display power well for the HDA controller or codec. For
2327 * Haswell/Broadwell, both the display HDA controller and codec need
2328 * this power. For other platforms, like Baytrail/Braswell, only the
2329 * display codec needs the power and it can be released after probe.
2330 */
2331 display_power(chip, true);
2332
2333 err = azx_first_init(chip);
2334 if (err < 0)
2335 goto out_free;
2336
2337 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2338 chip->beep_mode = beep_mode[dev];
2339 #endif
2340
2341 chip->ctl_dev_id = ctl_dev_id;
2342
2343 /* create codec instances */
2344 if (bus->codec_mask) {
2345 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2346 if (err < 0)
2347 goto out_free;
2348 }
2349
2350 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2351 if (chip->fw) {
2352 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2353 chip->fw->data);
2354 if (err < 0)
2355 goto out_free;
2356 }
2357 #endif
2358
2359 probe_retry:
2360 if (bus->codec_mask && !(probe_only[dev] & 1)) {
2361 err = azx_codec_configure(chip);
2362 if (err) {
2363 if ((chip->driver_caps & AZX_DCAPS_RETRY_PROBE) &&
2364 ++hda->probe_retry < 60) {
2365 schedule_delayed_work(&hda->probe_work,
2366 msecs_to_jiffies(1000));
2367 return 0; /* keep things up */
2368 }
2369 dev_err(chip->card->dev, "Cannot probe codecs, giving up\n");
2370 goto out_free;
2371 }
2372 }
2373
2374 err = snd_card_register(chip->card);
2375 if (err < 0)
2376 goto out_free;
2377
2378 setup_vga_switcheroo_runtime_pm(chip);
2379
2380 chip->running = 1;
2381 azx_add_card_list(chip);
2382
2383 set_default_power_save(chip);
2384
2385 if (azx_has_pm_runtime(chip)) {
2386 pm_runtime_use_autosuspend(&pci->dev);
2387 pm_runtime_allow(&pci->dev);
2388 pm_runtime_put_autosuspend(&pci->dev);
2389 }
2390
2391 out_free:
2392 if (err < 0) {
2393 pci_set_drvdata(pci, NULL);
2394 snd_card_free(chip->card);
2395 return err;
2396 }
2397
2398 if (!hda->need_i915_power)
2399 display_power(chip, false);
2400 complete_all(&hda->probe_wait);
2401 to_hda_bus(bus)->bus_probing = 0;
2402 hda->probe_retry = 0;
2403 return 0;
2404 }
2405
azx_remove(struct pci_dev * pci)2406 static void azx_remove(struct pci_dev *pci)
2407 {
2408 struct snd_card *card = pci_get_drvdata(pci);
2409 struct azx *chip;
2410 struct hda_intel *hda;
2411
2412 if (card) {
2413 /* cancel the pending probing work */
2414 chip = card->private_data;
2415 hda = container_of(chip, struct hda_intel, chip);
2416 /* FIXME: below is an ugly workaround.
2417 * Both device_release_driver() and driver_probe_device()
2418 * take *both* the device's and its parent's lock before
2419 * calling the remove() and probe() callbacks. The codec
2420 * probe takes the locks of both the codec itself and its
2421 * parent, i.e. the PCI controller dev. Meanwhile, when
2422 * the PCI controller is unbound, it takes its lock, too
2423 * ==> ouch, a deadlock!
2424 * As a workaround, we unlock temporarily here the controller
2425 * device during cancel_work_sync() call.
2426 */
2427 device_unlock(&pci->dev);
2428 cancel_delayed_work_sync(&hda->probe_work);
2429 device_lock(&pci->dev);
2430
2431 clear_bit(chip->dev_index, probed_devs);
2432 pci_set_drvdata(pci, NULL);
2433 snd_card_free(card);
2434 }
2435 }
2436
azx_shutdown(struct pci_dev * pci)2437 static void azx_shutdown(struct pci_dev *pci)
2438 {
2439 struct snd_card *card = pci_get_drvdata(pci);
2440 struct azx *chip;
2441
2442 if (!card)
2443 return;
2444 chip = card->private_data;
2445 if (chip && chip->running)
2446 __azx_shutdown_chip(chip, true);
2447 }
2448
2449 /* PCI IDs */
2450 static const struct pci_device_id azx_ids[] = {
2451 /* CPT */
2452 { PCI_DEVICE_DATA(INTEL, HDA_CPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) },
2453 /* PBG */
2454 { PCI_DEVICE_DATA(INTEL, HDA_PBG, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) },
2455 /* Panther Point */
2456 { PCI_DEVICE_DATA(INTEL, HDA_PPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) },
2457 /* Lynx Point */
2458 { PCI_DEVICE_DATA(INTEL, HDA_LPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2459 /* 9 Series */
2460 { PCI_DEVICE_DATA(INTEL, HDA_9_SERIES, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2461 /* Wellsburg */
2462 { PCI_DEVICE_DATA(INTEL, HDA_WBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2463 { PCI_DEVICE_DATA(INTEL, HDA_WBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2464 /* Lewisburg */
2465 { PCI_DEVICE_DATA(INTEL, HDA_LBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) },
2466 { PCI_DEVICE_DATA(INTEL, HDA_LBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) },
2467 /* Lynx Point-LP */
2468 { PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2469 /* Lynx Point-LP */
2470 { PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2471 /* Wildcat Point-LP */
2472 { PCI_DEVICE_DATA(INTEL, HDA_WPT_LP, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2473 /* Skylake (Sunrise Point) */
2474 { PCI_DEVICE_DATA(INTEL, HDA_SKL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2475 /* Skylake-LP (Sunrise Point-LP) */
2476 { PCI_DEVICE_DATA(INTEL, HDA_SKL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2477 /* Kabylake */
2478 { PCI_DEVICE_DATA(INTEL, HDA_KBL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2479 /* Kabylake-LP */
2480 { PCI_DEVICE_DATA(INTEL, HDA_KBL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2481 /* Kabylake-H */
2482 { PCI_DEVICE_DATA(INTEL, HDA_KBL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2483 /* Coffelake */
2484 { PCI_DEVICE_DATA(INTEL, HDA_CNL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2485 /* Cannonlake */
2486 { PCI_DEVICE_DATA(INTEL, HDA_CNL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2487 /* CometLake-LP */
2488 { PCI_DEVICE_DATA(INTEL, HDA_CML_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2489 /* CometLake-H */
2490 { PCI_DEVICE_DATA(INTEL, HDA_CML_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2491 { PCI_DEVICE_DATA(INTEL, HDA_RKL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2492 /* CometLake-S */
2493 { PCI_DEVICE_DATA(INTEL, HDA_CML_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2494 /* CometLake-R */
2495 { PCI_DEVICE_DATA(INTEL, HDA_CML_R, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2496 /* Icelake */
2497 { PCI_DEVICE_DATA(INTEL, HDA_ICL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2498 /* Icelake-H */
2499 { PCI_DEVICE_DATA(INTEL, HDA_ICL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2500 /* Jasperlake */
2501 { PCI_DEVICE_DATA(INTEL, HDA_ICL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2502 { PCI_DEVICE_DATA(INTEL, HDA_JSL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2503 /* Tigerlake */
2504 { PCI_DEVICE_DATA(INTEL, HDA_TGL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2505 /* Tigerlake-H */
2506 { PCI_DEVICE_DATA(INTEL, HDA_TGL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2507 /* DG1 */
2508 { PCI_DEVICE_DATA(INTEL, HDA_DG1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2509 /* DG2 */
2510 { PCI_DEVICE_DATA(INTEL, HDA_DG2_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2511 { PCI_DEVICE_DATA(INTEL, HDA_DG2_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2512 { PCI_DEVICE_DATA(INTEL, HDA_DG2_2, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2513 /* Alderlake-S */
2514 { PCI_DEVICE_DATA(INTEL, HDA_ADL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2515 /* Alderlake-P */
2516 { PCI_DEVICE_DATA(INTEL, HDA_ADL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2517 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PS, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2518 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2519 /* Alderlake-M */
2520 { PCI_DEVICE_DATA(INTEL, HDA_ADL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2521 /* Alderlake-N */
2522 { PCI_DEVICE_DATA(INTEL, HDA_ADL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2523 /* Elkhart Lake */
2524 { PCI_DEVICE_DATA(INTEL, HDA_EHL_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2525 { PCI_DEVICE_DATA(INTEL, HDA_EHL_3, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2526 /* Raptor Lake */
2527 { PCI_DEVICE_DATA(INTEL, HDA_RPL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2528 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2529 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2530 { PCI_DEVICE_DATA(INTEL, HDA_RPL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2531 { PCI_DEVICE_DATA(INTEL, HDA_RPL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2532 { PCI_DEVICE_DATA(INTEL, HDA_MTL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2533 /* Battlemage */
2534 { PCI_DEVICE_DATA(INTEL, HDA_BMG, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2535 /* Lunarlake-P */
2536 { PCI_DEVICE_DATA(INTEL, HDA_LNL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) },
2537 /* Arrow Lake-S */
2538 { PCI_DEVICE_DATA(INTEL, HDA_ARL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2539 /* Arrow Lake */
2540 { PCI_DEVICE_DATA(INTEL, HDA_ARL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2541 /* Panther Lake */
2542 { PCI_DEVICE_DATA(INTEL, HDA_PTL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) },
2543 /* Panther Lake-H */
2544 { PCI_DEVICE_DATA(INTEL, HDA_PTL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) },
2545 /* Apollolake (Broxton-P) */
2546 { PCI_DEVICE_DATA(INTEL, HDA_APL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) },
2547 /* Gemini-Lake */
2548 { PCI_DEVICE_DATA(INTEL, HDA_GML, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) },
2549 /* Haswell */
2550 { PCI_DEVICE_DATA(INTEL, HDA_HSW_0, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) },
2551 { PCI_DEVICE_DATA(INTEL, HDA_HSW_2, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) },
2552 { PCI_DEVICE_DATA(INTEL, HDA_HSW_3, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) },
2553 /* Broadwell */
2554 { PCI_DEVICE_DATA(INTEL, HDA_BDW, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL) },
2555 /* 5 Series/3400 */
2556 { PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_0, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) },
2557 { PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_1, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) },
2558 /* Poulsbo */
2559 { PCI_DEVICE_DATA(INTEL, HDA_POULSBO, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE |
2560 AZX_DCAPS_POSFIX_LPIB) },
2561 /* Oaktrail */
2562 { PCI_DEVICE_DATA(INTEL, HDA_OAKTRAIL, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE) },
2563 /* BayTrail */
2564 { PCI_DEVICE_DATA(INTEL, HDA_BYT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL) },
2565 /* Braswell */
2566 { PCI_DEVICE_DATA(INTEL, HDA_BSW, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL) },
2567 /* ICH6 */
2568 { PCI_DEVICE_DATA(INTEL, HDA_ICH6, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2569 /* ICH7 */
2570 { PCI_DEVICE_DATA(INTEL, HDA_ICH7, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2571 /* ESB2 */
2572 { PCI_DEVICE_DATA(INTEL, HDA_ESB2, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2573 /* ICH8 */
2574 { PCI_DEVICE_DATA(INTEL, HDA_ICH8, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2575 /* ICH9 */
2576 { PCI_DEVICE_DATA(INTEL, HDA_ICH9_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2577 /* ICH9 */
2578 { PCI_DEVICE_DATA(INTEL, HDA_ICH9_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2579 /* ICH10 */
2580 { PCI_DEVICE_DATA(INTEL, HDA_ICH10_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2581 /* ICH10 */
2582 { PCI_DEVICE_DATA(INTEL, HDA_ICH10_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2583 /* Generic Intel */
2584 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2585 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2586 .class_mask = 0xffffff,
2587 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2588 /* ATI SB 450/600/700/800/900 */
2589 { PCI_VDEVICE(ATI, 0x437b),
2590 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2591 { PCI_VDEVICE(ATI, 0x4383),
2592 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2593 /* AMD Hudson */
2594 { PCI_VDEVICE(AMD, 0x780d),
2595 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2596 /* AMD, X370 & co */
2597 { PCI_VDEVICE(AMD, 0x1457),
2598 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2599 /* AMD, X570 & co */
2600 { PCI_VDEVICE(AMD, 0x1487),
2601 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2602 /* AMD Stoney */
2603 { PCI_VDEVICE(AMD, 0x157a),
2604 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2605 AZX_DCAPS_PM_RUNTIME },
2606 /* AMD Raven */
2607 { PCI_VDEVICE(AMD, 0x15e3),
2608 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2609 /* ATI HDMI */
2610 { PCI_VDEVICE(ATI, 0x0002),
2611 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2612 AZX_DCAPS_PM_RUNTIME },
2613 { PCI_VDEVICE(ATI, 0x1308),
2614 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2615 { PCI_VDEVICE(ATI, 0x157a),
2616 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2617 { PCI_VDEVICE(ATI, 0x15b3),
2618 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2619 { PCI_VDEVICE(ATI, 0x793b),
2620 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2621 { PCI_VDEVICE(ATI, 0x7919),
2622 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2623 { PCI_VDEVICE(ATI, 0x960f),
2624 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2625 { PCI_VDEVICE(ATI, 0x970f),
2626 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2627 { PCI_VDEVICE(ATI, 0x9840),
2628 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2629 { PCI_VDEVICE(ATI, 0xaa00),
2630 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2631 { PCI_VDEVICE(ATI, 0xaa08),
2632 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2633 { PCI_VDEVICE(ATI, 0xaa10),
2634 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2635 { PCI_VDEVICE(ATI, 0xaa18),
2636 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2637 { PCI_VDEVICE(ATI, 0xaa20),
2638 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2639 { PCI_VDEVICE(ATI, 0xaa28),
2640 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2641 { PCI_VDEVICE(ATI, 0xaa30),
2642 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2643 { PCI_VDEVICE(ATI, 0xaa38),
2644 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2645 { PCI_VDEVICE(ATI, 0xaa40),
2646 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2647 { PCI_VDEVICE(ATI, 0xaa48),
2648 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2649 { PCI_VDEVICE(ATI, 0xaa50),
2650 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2651 { PCI_VDEVICE(ATI, 0xaa58),
2652 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2653 { PCI_VDEVICE(ATI, 0xaa60),
2654 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2655 { PCI_VDEVICE(ATI, 0xaa68),
2656 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2657 { PCI_VDEVICE(ATI, 0xaa80),
2658 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2659 { PCI_VDEVICE(ATI, 0xaa88),
2660 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2661 { PCI_VDEVICE(ATI, 0xaa90),
2662 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2663 { PCI_VDEVICE(ATI, 0xaa98),
2664 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2665 { PCI_VDEVICE(ATI, 0x9902),
2666 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2667 { PCI_VDEVICE(ATI, 0xaaa0),
2668 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2669 { PCI_VDEVICE(ATI, 0xaaa8),
2670 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2671 { PCI_VDEVICE(ATI, 0xaab0),
2672 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2673 { PCI_VDEVICE(ATI, 0xaac0),
2674 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2675 AZX_DCAPS_PM_RUNTIME },
2676 { PCI_VDEVICE(ATI, 0xaac8),
2677 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2678 AZX_DCAPS_PM_RUNTIME },
2679 { PCI_VDEVICE(ATI, 0xaad8),
2680 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2681 AZX_DCAPS_PM_RUNTIME },
2682 { PCI_VDEVICE(ATI, 0xaae0),
2683 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2684 AZX_DCAPS_PM_RUNTIME },
2685 { PCI_VDEVICE(ATI, 0xaae8),
2686 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2687 AZX_DCAPS_PM_RUNTIME },
2688 { PCI_VDEVICE(ATI, 0xaaf0),
2689 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2690 AZX_DCAPS_PM_RUNTIME },
2691 { PCI_VDEVICE(ATI, 0xaaf8),
2692 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2693 AZX_DCAPS_PM_RUNTIME },
2694 { PCI_VDEVICE(ATI, 0xab00),
2695 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2696 AZX_DCAPS_PM_RUNTIME },
2697 { PCI_VDEVICE(ATI, 0xab08),
2698 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2699 AZX_DCAPS_PM_RUNTIME },
2700 { PCI_VDEVICE(ATI, 0xab10),
2701 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2702 AZX_DCAPS_PM_RUNTIME },
2703 { PCI_VDEVICE(ATI, 0xab18),
2704 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2705 AZX_DCAPS_PM_RUNTIME },
2706 { PCI_VDEVICE(ATI, 0xab20),
2707 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2708 AZX_DCAPS_PM_RUNTIME },
2709 { PCI_VDEVICE(ATI, 0xab28),
2710 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2711 AZX_DCAPS_PM_RUNTIME },
2712 { PCI_VDEVICE(ATI, 0xab30),
2713 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2714 AZX_DCAPS_PM_RUNTIME },
2715 { PCI_VDEVICE(ATI, 0xab38),
2716 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2717 AZX_DCAPS_PM_RUNTIME },
2718 /* GLENFLY */
2719 { PCI_DEVICE(PCI_VENDOR_ID_GLENFLY, PCI_ANY_ID),
2720 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2721 .class_mask = 0xffffff,
2722 .driver_data = AZX_DRIVER_GFHDMI | AZX_DCAPS_POSFIX_LPIB |
2723 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT },
2724 /* VIA VT8251/VT8237A */
2725 { PCI_VDEVICE(VIA, 0x3288), .driver_data = AZX_DRIVER_VIA },
2726 /* VIA GFX VT7122/VX900 */
2727 { PCI_VDEVICE(VIA, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2728 /* VIA GFX VT6122/VX11 */
2729 { PCI_VDEVICE(VIA, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2730 /* SIS966 */
2731 { PCI_VDEVICE(SI, 0x7502), .driver_data = AZX_DRIVER_SIS },
2732 /* ULI M5461 */
2733 { PCI_VDEVICE(AL, 0x5461), .driver_data = AZX_DRIVER_ULI },
2734 /* NVIDIA MCP */
2735 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2736 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2737 .class_mask = 0xffffff,
2738 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2739 /* Teradici */
2740 { PCI_DEVICE(0x6549, 0x1200),
2741 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2742 { PCI_DEVICE(0x6549, 0x2200),
2743 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2744 /* Creative X-Fi (CA0110-IBG) */
2745 /* CTHDA chips */
2746 { PCI_VDEVICE(CREATIVE, 0x0010),
2747 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2748 { PCI_VDEVICE(CREATIVE, 0x0012),
2749 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2750 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2751 /* the following entry conflicts with snd-ctxfi driver,
2752 * as ctxfi driver mutates from HD-audio to native mode with
2753 * a special command sequence.
2754 */
2755 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2756 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2757 .class_mask = 0xffffff,
2758 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2759 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2760 #else
2761 /* this entry seems still valid -- i.e. without emu20kx chip */
2762 { PCI_VDEVICE(CREATIVE, 0x0009),
2763 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2764 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2765 #endif
2766 /* CM8888 */
2767 { PCI_VDEVICE(CMEDIA, 0x5011),
2768 .driver_data = AZX_DRIVER_CMEDIA |
2769 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2770 /* Vortex86MX */
2771 { PCI_VDEVICE(RDC, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2772 /* VMware HDAudio */
2773 { PCI_VDEVICE(VMWARE, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2774 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2775 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2776 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2777 .class_mask = 0xffffff,
2778 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2779 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2780 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2781 .class_mask = 0xffffff,
2782 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2783 /* Zhaoxin */
2784 { PCI_VDEVICE(ZHAOXIN, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
2785 /* Loongson HDAudio*/
2786 { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDA),
2787 .driver_data = AZX_DRIVER_LOONGSON | AZX_DCAPS_NO_TCSEL },
2788 { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDMI),
2789 .driver_data = AZX_DRIVER_LOONGSON | AZX_DCAPS_NO_TCSEL },
2790 { 0, }
2791 };
2792 MODULE_DEVICE_TABLE(pci, azx_ids);
2793
2794 /* pci_driver definition */
2795 static struct pci_driver azx_driver = {
2796 .name = KBUILD_MODNAME,
2797 .id_table = azx_ids,
2798 .probe = azx_probe,
2799 .remove = azx_remove,
2800 .shutdown = azx_shutdown,
2801 .driver = {
2802 .pm = pm_ptr(&azx_pm),
2803 },
2804 };
2805
2806 module_pci_driver(azx_driver);
2807