1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2021-2022, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/mod_devicetable.h>
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
10 #include <linux/regmap.h>
11
12 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
13
14 #include "clk-alpha-pll.h"
15 #include "clk-branch.h"
16 #include "clk-rcg.h"
17 #include "clk-regmap-divider.h"
18 #include "common.h"
19 #include "gdsc.h"
20 #include "reset.h"
21
22 enum {
23 P_BI_TCXO,
24 P_DISP_CC_PLL0_OUT_EVEN,
25 P_DISP_CC_PLL0_OUT_MAIN,
26 P_DP_PHY_PLL_LINK_CLK,
27 P_DP_PHY_PLL_VCO_DIV_CLK,
28 P_DSI0_PHY_PLL_OUT_BYTECLK,
29 P_DSI0_PHY_PLL_OUT_DSICLK,
30 P_EDP_PHY_PLL_LINK_CLK,
31 P_EDP_PHY_PLL_VCO_DIV_CLK,
32 P_GCC_DISP_GPLL0_CLK,
33 };
34
35 static const struct pll_vco lucid_vco[] = {
36 { 249600000, 2000000000, 0 },
37 };
38
39 /* 1520MHz Configuration*/
40 static const struct alpha_pll_config disp_cc_pll0_config = {
41 .l = 0x4F,
42 .alpha = 0x2AAA,
43 .config_ctl_val = 0x20485699,
44 .config_ctl_hi_val = 0x00002261,
45 .config_ctl_hi1_val = 0x329A299C,
46 .user_ctl_val = 0x00000001,
47 .user_ctl_hi_val = 0x00000805,
48 .user_ctl_hi1_val = 0x00000000,
49 };
50
51 static struct clk_alpha_pll disp_cc_pll0 = {
52 .offset = 0x0,
53 .vco_table = lucid_vco,
54 .num_vco = ARRAY_SIZE(lucid_vco),
55 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
56 .clkr = {
57 .hw.init = &(struct clk_init_data){
58 .name = "disp_cc_pll0",
59 .parent_data = &(const struct clk_parent_data){
60 .fw_name = "bi_tcxo",
61 },
62 .num_parents = 1,
63 .ops = &clk_alpha_pll_lucid_ops,
64 },
65 },
66 };
67
68 static const struct parent_map disp_cc_parent_map_0[] = {
69 { P_BI_TCXO, 0 },
70 };
71
72 static const struct clk_parent_data disp_cc_parent_data_0[] = {
73 { .fw_name = "bi_tcxo" },
74 };
75
76 static const struct parent_map disp_cc_parent_map_1[] = {
77 { P_BI_TCXO, 0 },
78 { P_DP_PHY_PLL_LINK_CLK, 1 },
79 { P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
80 };
81
82 static const struct clk_parent_data disp_cc_parent_data_1[] = {
83 { .fw_name = "bi_tcxo" },
84 { .fw_name = "dp_phy_pll_link_clk" },
85 { .fw_name = "dp_phy_pll_vco_div_clk" },
86 };
87
88 static const struct parent_map disp_cc_parent_map_2[] = {
89 { P_BI_TCXO, 0 },
90 { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
91 };
92
93 static const struct clk_parent_data disp_cc_parent_data_2[] = {
94 { .fw_name = "bi_tcxo" },
95 { .fw_name = "dsi0_phy_pll_out_byteclk" },
96 };
97
98 static const struct parent_map disp_cc_parent_map_3[] = {
99 { P_BI_TCXO, 0 },
100 { P_EDP_PHY_PLL_LINK_CLK, 1 },
101 { P_EDP_PHY_PLL_VCO_DIV_CLK, 2 },
102 };
103
104 static const struct clk_parent_data disp_cc_parent_data_3[] = {
105 { .fw_name = "bi_tcxo" },
106 { .fw_name = "edp_phy_pll_link_clk" },
107 { .fw_name = "edp_phy_pll_vco_div_clk" },
108 };
109
110 static const struct parent_map disp_cc_parent_map_4[] = {
111 { P_BI_TCXO, 0 },
112 { P_DISP_CC_PLL0_OUT_MAIN, 1 },
113 { P_GCC_DISP_GPLL0_CLK, 4 },
114 { P_DISP_CC_PLL0_OUT_EVEN, 5 },
115 };
116
117 static const struct clk_parent_data disp_cc_parent_data_4[] = {
118 { .fw_name = "bi_tcxo" },
119 { .hw = &disp_cc_pll0.clkr.hw },
120 { .fw_name = "gcc_disp_gpll0_clk" },
121 { .hw = &disp_cc_pll0.clkr.hw },
122 };
123
124 static const struct parent_map disp_cc_parent_map_5[] = {
125 { P_BI_TCXO, 0 },
126 { P_GCC_DISP_GPLL0_CLK, 4 },
127 };
128
129 static const struct clk_parent_data disp_cc_parent_data_5[] = {
130 { .fw_name = "bi_tcxo" },
131 { .fw_name = "gcc_disp_gpll0_clk" },
132 };
133
134 static const struct parent_map disp_cc_parent_map_6[] = {
135 { P_BI_TCXO, 0 },
136 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
137 };
138
139 static const struct clk_parent_data disp_cc_parent_data_6[] = {
140 { .fw_name = "bi_tcxo" },
141 { .fw_name = "dsi0_phy_pll_out_dsiclk" },
142 };
143
144 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
145 F(19200000, P_BI_TCXO, 1, 0, 0),
146 F(37500000, P_GCC_DISP_GPLL0_CLK, 16, 0, 0),
147 F(75000000, P_GCC_DISP_GPLL0_CLK, 8, 0, 0),
148 { }
149 };
150
151 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
152 .cmd_rcgr = 0x1170,
153 .mnd_width = 0,
154 .hid_width = 5,
155 .parent_map = disp_cc_parent_map_5,
156 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
157 .clkr.hw.init = &(struct clk_init_data){
158 .name = "disp_cc_mdss_ahb_clk_src",
159 .parent_data = disp_cc_parent_data_5,
160 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
161 .ops = &clk_rcg2_shared_ops,
162 },
163 };
164
165 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
166 .cmd_rcgr = 0x10d8,
167 .mnd_width = 0,
168 .hid_width = 5,
169 .parent_map = disp_cc_parent_map_2,
170 .clkr.hw.init = &(struct clk_init_data){
171 .name = "disp_cc_mdss_byte0_clk_src",
172 .parent_data = disp_cc_parent_data_2,
173 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
174 .flags = CLK_SET_RATE_PARENT,
175 .ops = &clk_byte2_ops,
176 },
177 };
178
179 static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = {
180 F(19200000, P_BI_TCXO, 1, 0, 0),
181 { }
182 };
183
184 static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
185 .cmd_rcgr = 0x1158,
186 .mnd_width = 0,
187 .hid_width = 5,
188 .parent_map = disp_cc_parent_map_0,
189 .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
190 .clkr.hw.init = &(struct clk_init_data){
191 .name = "disp_cc_mdss_dp_aux_clk_src",
192 .parent_data = disp_cc_parent_data_0,
193 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
194 .ops = &clk_rcg2_ops,
195 },
196 };
197
198 static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
199 .cmd_rcgr = 0x1128,
200 .mnd_width = 0,
201 .hid_width = 5,
202 .parent_map = disp_cc_parent_map_1,
203 .clkr.hw.init = &(struct clk_init_data){
204 .name = "disp_cc_mdss_dp_crypto_clk_src",
205 .parent_data = disp_cc_parent_data_1,
206 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
207 .ops = &clk_byte2_ops,
208 },
209 };
210
211 static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
212 .cmd_rcgr = 0x110c,
213 .mnd_width = 0,
214 .hid_width = 5,
215 .parent_map = disp_cc_parent_map_1,
216 .clkr.hw.init = &(struct clk_init_data){
217 .name = "disp_cc_mdss_dp_link_clk_src",
218 .parent_data = disp_cc_parent_data_1,
219 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
220 .ops = &clk_byte2_ops,
221 },
222 };
223
224 static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
225 .cmd_rcgr = 0x1140,
226 .mnd_width = 16,
227 .hid_width = 5,
228 .parent_map = disp_cc_parent_map_1,
229 .clkr.hw.init = &(struct clk_init_data){
230 .name = "disp_cc_mdss_dp_pixel_clk_src",
231 .parent_data = disp_cc_parent_data_1,
232 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
233 .ops = &clk_dp_ops,
234 },
235 };
236
237 static struct clk_rcg2 disp_cc_mdss_edp_aux_clk_src = {
238 .cmd_rcgr = 0x11d0,
239 .mnd_width = 0,
240 .hid_width = 5,
241 .parent_map = disp_cc_parent_map_0,
242 .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
243 .clkr.hw.init = &(struct clk_init_data){
244 .name = "disp_cc_mdss_edp_aux_clk_src",
245 .parent_data = disp_cc_parent_data_0,
246 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
247 .ops = &clk_rcg2_ops,
248 },
249 };
250
251 static struct clk_rcg2 disp_cc_mdss_edp_link_clk_src = {
252 .cmd_rcgr = 0x11a0,
253 .mnd_width = 0,
254 .hid_width = 5,
255 .parent_map = disp_cc_parent_map_3,
256 .clkr.hw.init = &(struct clk_init_data){
257 .name = "disp_cc_mdss_edp_link_clk_src",
258 .parent_data = disp_cc_parent_data_3,
259 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
260 .flags = CLK_SET_RATE_PARENT,
261 .ops = &clk_byte2_ops,
262 },
263 };
264
265 static struct clk_rcg2 disp_cc_mdss_edp_pixel_clk_src = {
266 .cmd_rcgr = 0x1188,
267 .mnd_width = 16,
268 .hid_width = 5,
269 .parent_map = disp_cc_parent_map_3,
270 .clkr.hw.init = &(struct clk_init_data){
271 .name = "disp_cc_mdss_edp_pixel_clk_src",
272 .parent_data = disp_cc_parent_data_3,
273 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
274 .ops = &clk_dp_ops,
275 },
276 };
277
278 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
279 .cmd_rcgr = 0x10f4,
280 .mnd_width = 0,
281 .hid_width = 5,
282 .parent_map = disp_cc_parent_map_2,
283 .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
284 .clkr.hw.init = &(struct clk_init_data){
285 .name = "disp_cc_mdss_esc0_clk_src",
286 .parent_data = disp_cc_parent_data_2,
287 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
288 .ops = &clk_rcg2_ops,
289 },
290 };
291
292 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
293 F(200000000, P_GCC_DISP_GPLL0_CLK, 3, 0, 0),
294 F(300000000, P_GCC_DISP_GPLL0_CLK, 2, 0, 0),
295 F(380000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
296 F(506666667, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
297 F(608000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
298 { }
299 };
300
301 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
302 .cmd_rcgr = 0x1090,
303 .mnd_width = 0,
304 .hid_width = 5,
305 .parent_map = disp_cc_parent_map_4,
306 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
307 .clkr.hw.init = &(struct clk_init_data){
308 .name = "disp_cc_mdss_mdp_clk_src",
309 .parent_data = disp_cc_parent_data_4,
310 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
311 .ops = &clk_rcg2_shared_ops,
312 },
313 };
314
315 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
316 .cmd_rcgr = 0x1078,
317 .mnd_width = 8,
318 .hid_width = 5,
319 .parent_map = disp_cc_parent_map_6,
320 .clkr.hw.init = &(struct clk_init_data){
321 .name = "disp_cc_mdss_pclk0_clk_src",
322 .parent_data = disp_cc_parent_data_6,
323 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
324 .flags = CLK_SET_RATE_PARENT,
325 .ops = &clk_pixel_ops,
326 },
327 };
328
329 static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
330 .cmd_rcgr = 0x10a8,
331 .mnd_width = 0,
332 .hid_width = 5,
333 .parent_map = disp_cc_parent_map_4,
334 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
335 .clkr.hw.init = &(struct clk_init_data){
336 .name = "disp_cc_mdss_rot_clk_src",
337 .parent_data = disp_cc_parent_data_4,
338 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
339 .ops = &clk_rcg2_shared_ops,
340 },
341 };
342
343 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
344 .cmd_rcgr = 0x10c0,
345 .mnd_width = 0,
346 .hid_width = 5,
347 .parent_map = disp_cc_parent_map_0,
348 .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
349 .clkr.hw.init = &(struct clk_init_data){
350 .name = "disp_cc_mdss_vsync_clk_src",
351 .parent_data = disp_cc_parent_data_0,
352 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
353 .ops = &clk_rcg2_ops,
354 },
355 };
356
357 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
358 .reg = 0x10f0,
359 .shift = 0,
360 .width = 4,
361 .clkr.hw.init = &(struct clk_init_data) {
362 .name = "disp_cc_mdss_byte0_div_clk_src",
363 .parent_hws = (const struct clk_hw*[]){
364 &disp_cc_mdss_byte0_clk_src.clkr.hw,
365 },
366 .num_parents = 1,
367 .ops = &clk_regmap_div_ops,
368 },
369 };
370
371 static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = {
372 .reg = 0x1124,
373 .shift = 0,
374 .width = 4,
375 .clkr.hw.init = &(struct clk_init_data) {
376 .name = "disp_cc_mdss_dp_link_div_clk_src",
377 .parent_hws = (const struct clk_hw*[]){
378 &disp_cc_mdss_dp_link_clk_src.clkr.hw,
379 },
380 .num_parents = 1,
381 .ops = &clk_regmap_div_ro_ops,
382 },
383 };
384
385 static struct clk_regmap_div disp_cc_mdss_edp_link_div_clk_src = {
386 .reg = 0x11b8,
387 .shift = 0,
388 .width = 4,
389 .clkr.hw.init = &(struct clk_init_data) {
390 .name = "disp_cc_mdss_edp_link_div_clk_src",
391 .parent_hws = (const struct clk_hw*[]){
392 &disp_cc_mdss_edp_link_clk_src.clkr.hw,
393 },
394 .num_parents = 1,
395 .ops = &clk_regmap_div_ro_ops,
396 },
397 };
398
399 static struct clk_branch disp_cc_mdss_ahb_clk = {
400 .halt_reg = 0x1050,
401 .halt_check = BRANCH_HALT,
402 .clkr = {
403 .enable_reg = 0x1050,
404 .enable_mask = BIT(0),
405 .hw.init = &(struct clk_init_data){
406 .name = "disp_cc_mdss_ahb_clk",
407 .parent_hws = (const struct clk_hw*[]){
408 &disp_cc_mdss_ahb_clk_src.clkr.hw,
409 },
410 .num_parents = 1,
411 .flags = CLK_SET_RATE_PARENT,
412 .ops = &clk_branch2_ops,
413 },
414 },
415 };
416
417 static struct clk_branch disp_cc_mdss_byte0_clk = {
418 .halt_reg = 0x1030,
419 .halt_check = BRANCH_HALT,
420 .clkr = {
421 .enable_reg = 0x1030,
422 .enable_mask = BIT(0),
423 .hw.init = &(struct clk_init_data){
424 .name = "disp_cc_mdss_byte0_clk",
425 .parent_hws = (const struct clk_hw*[]){
426 &disp_cc_mdss_byte0_clk_src.clkr.hw,
427 },
428 .num_parents = 1,
429 .flags = CLK_SET_RATE_PARENT,
430 .ops = &clk_branch2_ops,
431 },
432 },
433 };
434
435 static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
436 .halt_reg = 0x1034,
437 .halt_check = BRANCH_HALT,
438 .clkr = {
439 .enable_reg = 0x1034,
440 .enable_mask = BIT(0),
441 .hw.init = &(struct clk_init_data){
442 .name = "disp_cc_mdss_byte0_intf_clk",
443 .parent_hws = (const struct clk_hw*[]){
444 &disp_cc_mdss_byte0_div_clk_src.clkr.hw,
445 },
446 .num_parents = 1,
447 .flags = CLK_SET_RATE_PARENT,
448 .ops = &clk_branch2_ops,
449 },
450 },
451 };
452
453 static struct clk_branch disp_cc_mdss_dp_aux_clk = {
454 .halt_reg = 0x104c,
455 .halt_check = BRANCH_HALT,
456 .clkr = {
457 .enable_reg = 0x104c,
458 .enable_mask = BIT(0),
459 .hw.init = &(struct clk_init_data){
460 .name = "disp_cc_mdss_dp_aux_clk",
461 .parent_hws = (const struct clk_hw*[]){
462 &disp_cc_mdss_dp_aux_clk_src.clkr.hw,
463 },
464 .num_parents = 1,
465 .flags = CLK_SET_RATE_PARENT,
466 .ops = &clk_branch2_ops,
467 },
468 },
469 };
470
471 static struct clk_branch disp_cc_mdss_dp_crypto_clk = {
472 .halt_reg = 0x1044,
473 .halt_check = BRANCH_HALT,
474 .clkr = {
475 .enable_reg = 0x1044,
476 .enable_mask = BIT(0),
477 .hw.init = &(struct clk_init_data){
478 .name = "disp_cc_mdss_dp_crypto_clk",
479 .parent_hws = (const struct clk_hw*[]){
480 &disp_cc_mdss_dp_crypto_clk_src.clkr.hw,
481 },
482 .num_parents = 1,
483 .flags = CLK_SET_RATE_PARENT,
484 .ops = &clk_branch2_ops,
485 },
486 },
487 };
488
489 static struct clk_branch disp_cc_mdss_dp_link_clk = {
490 .halt_reg = 0x103c,
491 .halt_check = BRANCH_HALT,
492 .clkr = {
493 .enable_reg = 0x103c,
494 .enable_mask = BIT(0),
495 .hw.init = &(struct clk_init_data){
496 .name = "disp_cc_mdss_dp_link_clk",
497 .parent_hws = (const struct clk_hw*[]){
498 &disp_cc_mdss_dp_link_clk_src.clkr.hw,
499 },
500 .num_parents = 1,
501 .flags = CLK_SET_RATE_PARENT,
502 .ops = &clk_branch2_ops,
503 },
504 },
505 };
506
507 static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
508 .halt_reg = 0x1040,
509 .halt_check = BRANCH_HALT,
510 .clkr = {
511 .enable_reg = 0x1040,
512 .enable_mask = BIT(0),
513 .hw.init = &(struct clk_init_data){
514 .name = "disp_cc_mdss_dp_link_intf_clk",
515 .parent_hws = (const struct clk_hw*[]){
516 &disp_cc_mdss_dp_link_div_clk_src.clkr.hw,
517 },
518 .num_parents = 1,
519 .flags = CLK_SET_RATE_PARENT,
520 .ops = &clk_branch2_ops,
521 },
522 },
523 };
524
525 static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
526 .halt_reg = 0x1048,
527 .halt_check = BRANCH_HALT,
528 .clkr = {
529 .enable_reg = 0x1048,
530 .enable_mask = BIT(0),
531 .hw.init = &(struct clk_init_data){
532 .name = "disp_cc_mdss_dp_pixel_clk",
533 .parent_hws = (const struct clk_hw*[]){
534 &disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
535 },
536 .num_parents = 1,
537 .flags = CLK_SET_RATE_PARENT,
538 .ops = &clk_branch2_ops,
539 },
540 },
541 };
542
543 static struct clk_branch disp_cc_mdss_edp_aux_clk = {
544 .halt_reg = 0x1060,
545 .halt_check = BRANCH_HALT,
546 .clkr = {
547 .enable_reg = 0x1060,
548 .enable_mask = BIT(0),
549 .hw.init = &(struct clk_init_data){
550 .name = "disp_cc_mdss_edp_aux_clk",
551 .parent_hws = (const struct clk_hw*[]){
552 &disp_cc_mdss_edp_aux_clk_src.clkr.hw,
553 },
554 .num_parents = 1,
555 .flags = CLK_SET_RATE_PARENT,
556 .ops = &clk_branch2_ops,
557 },
558 },
559 };
560
561 static struct clk_branch disp_cc_mdss_edp_link_clk = {
562 .halt_reg = 0x1058,
563 .halt_check = BRANCH_HALT,
564 .clkr = {
565 .enable_reg = 0x1058,
566 .enable_mask = BIT(0),
567 .hw.init = &(struct clk_init_data){
568 .name = "disp_cc_mdss_edp_link_clk",
569 .parent_hws = (const struct clk_hw*[]){
570 &disp_cc_mdss_edp_link_clk_src.clkr.hw,
571 },
572 .num_parents = 1,
573 .flags = CLK_SET_RATE_PARENT,
574 .ops = &clk_branch2_ops,
575 },
576 },
577 };
578
579 static struct clk_branch disp_cc_mdss_edp_link_intf_clk = {
580 .halt_reg = 0x105c,
581 .halt_check = BRANCH_HALT,
582 .clkr = {
583 .enable_reg = 0x105c,
584 .enable_mask = BIT(0),
585 .hw.init = &(struct clk_init_data){
586 .name = "disp_cc_mdss_edp_link_intf_clk",
587 .parent_hws = (const struct clk_hw*[]){
588 &disp_cc_mdss_edp_link_div_clk_src.clkr.hw
589 },
590 .num_parents = 1,
591 .flags = CLK_SET_RATE_PARENT,
592 .ops = &clk_branch2_ops,
593 },
594 },
595 };
596
597 static struct clk_branch disp_cc_mdss_edp_pixel_clk = {
598 .halt_reg = 0x1054,
599 .halt_check = BRANCH_HALT,
600 .clkr = {
601 .enable_reg = 0x1054,
602 .enable_mask = BIT(0),
603 .hw.init = &(struct clk_init_data){
604 .name = "disp_cc_mdss_edp_pixel_clk",
605 .parent_hws = (const struct clk_hw*[]){
606 &disp_cc_mdss_edp_pixel_clk_src.clkr.hw,
607 },
608 .num_parents = 1,
609 .flags = CLK_SET_RATE_PARENT,
610 .ops = &clk_branch2_ops,
611 },
612 },
613 };
614
615 static struct clk_branch disp_cc_mdss_esc0_clk = {
616 .halt_reg = 0x1038,
617 .halt_check = BRANCH_HALT,
618 .clkr = {
619 .enable_reg = 0x1038,
620 .enable_mask = BIT(0),
621 .hw.init = &(struct clk_init_data){
622 .name = "disp_cc_mdss_esc0_clk",
623 .parent_hws = (const struct clk_hw*[]){
624 &disp_cc_mdss_esc0_clk_src.clkr.hw,
625 },
626 .num_parents = 1,
627 .flags = CLK_SET_RATE_PARENT,
628 .ops = &clk_branch2_ops,
629 },
630 },
631 };
632
633 static struct clk_branch disp_cc_mdss_mdp_clk = {
634 .halt_reg = 0x1014,
635 .halt_check = BRANCH_HALT,
636 .clkr = {
637 .enable_reg = 0x1014,
638 .enable_mask = BIT(0),
639 .hw.init = &(struct clk_init_data){
640 .name = "disp_cc_mdss_mdp_clk",
641 .parent_hws = (const struct clk_hw*[]){
642 &disp_cc_mdss_mdp_clk_src.clkr.hw,
643 },
644 .num_parents = 1,
645 .flags = CLK_SET_RATE_PARENT,
646 .ops = &clk_branch2_ops,
647 },
648 },
649 };
650
651 static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
652 .halt_reg = 0x1024,
653 .halt_check = BRANCH_HALT_VOTED,
654 .clkr = {
655 .enable_reg = 0x1024,
656 .enable_mask = BIT(0),
657 .hw.init = &(struct clk_init_data){
658 .name = "disp_cc_mdss_mdp_lut_clk",
659 .parent_hws = (const struct clk_hw*[]){
660 &disp_cc_mdss_mdp_clk_src.clkr.hw,
661 },
662 .num_parents = 1,
663 .flags = CLK_SET_RATE_PARENT,
664 .ops = &clk_branch2_ops,
665 },
666 },
667 };
668
669 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
670 .halt_reg = 0x2004,
671 .halt_check = BRANCH_HALT_VOTED,
672 .clkr = {
673 .enable_reg = 0x2004,
674 .enable_mask = BIT(0),
675 .hw.init = &(struct clk_init_data){
676 .name = "disp_cc_mdss_non_gdsc_ahb_clk",
677 .parent_hws = (const struct clk_hw*[]){
678 &disp_cc_mdss_ahb_clk_src.clkr.hw,
679 },
680 .num_parents = 1,
681 .flags = CLK_SET_RATE_PARENT,
682 .ops = &clk_branch2_ops,
683 },
684 },
685 };
686
687 static struct clk_branch disp_cc_mdss_pclk0_clk = {
688 .halt_reg = 0x1010,
689 .halt_check = BRANCH_HALT,
690 .clkr = {
691 .enable_reg = 0x1010,
692 .enable_mask = BIT(0),
693 .hw.init = &(struct clk_init_data){
694 .name = "disp_cc_mdss_pclk0_clk",
695 .parent_hws = (const struct clk_hw*[]){
696 &disp_cc_mdss_pclk0_clk_src.clkr.hw,
697 },
698 .num_parents = 1,
699 .flags = CLK_SET_RATE_PARENT,
700 .ops = &clk_branch2_ops,
701 },
702 },
703 };
704
705 static struct clk_branch disp_cc_mdss_rot_clk = {
706 .halt_reg = 0x101c,
707 .halt_check = BRANCH_HALT,
708 .clkr = {
709 .enable_reg = 0x101c,
710 .enable_mask = BIT(0),
711 .hw.init = &(struct clk_init_data){
712 .name = "disp_cc_mdss_rot_clk",
713 .parent_hws = (const struct clk_hw*[]){
714 &disp_cc_mdss_rot_clk_src.clkr.hw,
715 },
716 .num_parents = 1,
717 .flags = CLK_SET_RATE_PARENT,
718 .ops = &clk_branch2_ops,
719 },
720 },
721 };
722
723 static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
724 .halt_reg = 0x200c,
725 .halt_check = BRANCH_HALT,
726 .clkr = {
727 .enable_reg = 0x200c,
728 .enable_mask = BIT(0),
729 .hw.init = &(struct clk_init_data){
730 .name = "disp_cc_mdss_rscc_ahb_clk",
731 .parent_hws = (const struct clk_hw*[]){
732 &disp_cc_mdss_ahb_clk_src.clkr.hw,
733 },
734 .num_parents = 1,
735 .flags = CLK_SET_RATE_PARENT,
736 .ops = &clk_branch2_ops,
737 },
738 },
739 };
740
741 static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
742 .halt_reg = 0x2008,
743 .halt_check = BRANCH_HALT,
744 .clkr = {
745 .enable_reg = 0x2008,
746 .enable_mask = BIT(0),
747 .hw.init = &(struct clk_init_data){
748 .name = "disp_cc_mdss_rscc_vsync_clk",
749 .parent_hws = (const struct clk_hw*[]){
750 &disp_cc_mdss_vsync_clk_src.clkr.hw,
751 },
752 .num_parents = 1,
753 .flags = CLK_SET_RATE_PARENT,
754 .ops = &clk_branch2_ops,
755 },
756 },
757 };
758
759 static struct clk_branch disp_cc_mdss_vsync_clk = {
760 .halt_reg = 0x102c,
761 .halt_check = BRANCH_HALT,
762 .clkr = {
763 .enable_reg = 0x102c,
764 .enable_mask = BIT(0),
765 .hw.init = &(struct clk_init_data){
766 .name = "disp_cc_mdss_vsync_clk",
767 .parent_hws = (const struct clk_hw*[]){
768 &disp_cc_mdss_vsync_clk_src.clkr.hw,
769 },
770 .num_parents = 1,
771 .flags = CLK_SET_RATE_PARENT,
772 .ops = &clk_branch2_ops,
773 },
774 },
775 };
776
777 static struct clk_branch disp_cc_sleep_clk = {
778 .halt_reg = 0x5004,
779 .halt_check = BRANCH_HALT,
780 .clkr = {
781 .enable_reg = 0x5004,
782 .enable_mask = BIT(0),
783 .hw.init = &(struct clk_init_data){
784 .name = "disp_cc_sleep_clk",
785 .ops = &clk_branch2_ops,
786 },
787 },
788 };
789
790 static struct gdsc disp_cc_mdss_core_gdsc = {
791 .gdscr = 0x1004,
792 .en_rest_wait_val = 0x2,
793 .en_few_wait_val = 0x2,
794 .clk_dis_wait_val = 0xf,
795 .pd = {
796 .name = "disp_cc_mdss_core_gdsc",
797 },
798 .pwrsts = PWRSTS_OFF_ON,
799 .flags = HW_CTRL | RETAIN_FF_ENABLE,
800 };
801
802 static struct clk_regmap *disp_cc_sc7280_clocks[] = {
803 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
804 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
805 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
806 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
807 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
808 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
809 [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
810 [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
811 [DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr,
812 [DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] = &disp_cc_mdss_dp_crypto_clk_src.clkr,
813 [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
814 [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
815 [DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] =
816 &disp_cc_mdss_dp_link_div_clk_src.clkr,
817 [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
818 [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
819 [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
820 [DISP_CC_MDSS_EDP_AUX_CLK] = &disp_cc_mdss_edp_aux_clk.clkr,
821 [DISP_CC_MDSS_EDP_AUX_CLK_SRC] = &disp_cc_mdss_edp_aux_clk_src.clkr,
822 [DISP_CC_MDSS_EDP_LINK_CLK] = &disp_cc_mdss_edp_link_clk.clkr,
823 [DISP_CC_MDSS_EDP_LINK_CLK_SRC] = &disp_cc_mdss_edp_link_clk_src.clkr,
824 [DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC] =
825 &disp_cc_mdss_edp_link_div_clk_src.clkr,
826 [DISP_CC_MDSS_EDP_LINK_INTF_CLK] = &disp_cc_mdss_edp_link_intf_clk.clkr,
827 [DISP_CC_MDSS_EDP_PIXEL_CLK] = &disp_cc_mdss_edp_pixel_clk.clkr,
828 [DISP_CC_MDSS_EDP_PIXEL_CLK_SRC] = &disp_cc_mdss_edp_pixel_clk_src.clkr,
829 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
830 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
831 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
832 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
833 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
834 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
835 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
836 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
837 [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
838 [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
839 [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
840 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
841 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
842 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
843 [DISP_CC_PLL0] = &disp_cc_pll0.clkr,
844 [DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr,
845 };
846
847 static struct gdsc *disp_cc_sc7280_gdscs[] = {
848 [DISP_CC_MDSS_CORE_GDSC] = &disp_cc_mdss_core_gdsc,
849 };
850
851 static const struct qcom_reset_map disp_cc_sc7280_resets[] = {
852 [DISP_CC_MDSS_CORE_BCR] = { 0x1000 },
853 [DISP_CC_MDSS_RSCC_BCR] = { 0x2000 },
854 };
855
856 static const struct regmap_config disp_cc_sc7280_regmap_config = {
857 .reg_bits = 32,
858 .reg_stride = 4,
859 .val_bits = 32,
860 .max_register = 0x10000,
861 .fast_io = true,
862 };
863
864 static const struct qcom_cc_desc disp_cc_sc7280_desc = {
865 .config = &disp_cc_sc7280_regmap_config,
866 .clks = disp_cc_sc7280_clocks,
867 .num_clks = ARRAY_SIZE(disp_cc_sc7280_clocks),
868 .gdscs = disp_cc_sc7280_gdscs,
869 .num_gdscs = ARRAY_SIZE(disp_cc_sc7280_gdscs),
870 .resets = disp_cc_sc7280_resets,
871 .num_resets = ARRAY_SIZE(disp_cc_sc7280_resets),
872 };
873
874 static const struct of_device_id disp_cc_sc7280_match_table[] = {
875 { .compatible = "qcom,sc7280-dispcc" },
876 { }
877 };
878 MODULE_DEVICE_TABLE(of, disp_cc_sc7280_match_table);
879
disp_cc_sc7280_probe(struct platform_device * pdev)880 static int disp_cc_sc7280_probe(struct platform_device *pdev)
881 {
882 struct regmap *regmap;
883
884 regmap = qcom_cc_map(pdev, &disp_cc_sc7280_desc);
885 if (IS_ERR(regmap))
886 return PTR_ERR(regmap);
887
888 clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
889
890 /* Keep some clocks always-on */
891 qcom_branch_set_clk_en(regmap, 0x5008); /* DISP_CC_XO_CLK */
892
893 return qcom_cc_really_probe(&pdev->dev, &disp_cc_sc7280_desc, regmap);
894 }
895
896 static struct platform_driver disp_cc_sc7280_driver = {
897 .probe = disp_cc_sc7280_probe,
898 .driver = {
899 .name = "disp_cc-sc7280",
900 .of_match_table = disp_cc_sc7280_match_table,
901 },
902 };
903
904 module_platform_driver(disp_cc_sc7280_driver);
905
906 MODULE_DESCRIPTION("QTI DISP_CC sc7280 Driver");
907 MODULE_LICENSE("GPL v2");
908