1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2025, Qualcomm Technologies, Inc. and/or its subsidiaries.
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/mod_devicetable.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/platform_device.h>
11 #include <linux/pm_runtime.h>
12 #include <linux/regmap.h>
13
14 #include <dt-bindings/clock/qcom,glymur-dispcc.h>
15
16 #include "clk-alpha-pll.h"
17 #include "clk-branch.h"
18 #include "clk-pll.h"
19 #include "clk-rcg.h"
20 #include "clk-regmap.h"
21 #include "clk-regmap-divider.h"
22 #include "clk-regmap-mux.h"
23 #include "common.h"
24 #include "gdsc.h"
25 #include "reset.h"
26
27 enum {
28 DT_BI_TCXO,
29 DT_SLEEP_CLK,
30 DT_DP0_PHY_PLL_LINK_CLK,
31 DT_DP0_PHY_PLL_VCO_DIV_CLK,
32 DT_DP1_PHY_PLL_LINK_CLK,
33 DT_DP1_PHY_PLL_VCO_DIV_CLK,
34 DT_DP2_PHY_PLL_LINK_CLK,
35 DT_DP2_PHY_PLL_VCO_DIV_CLK,
36 DT_DP3_PHY_PLL_LINK_CLK,
37 DT_DP3_PHY_PLL_VCO_DIV_CLK,
38 DT_DSI0_PHY_PLL_OUT_BYTECLK,
39 DT_DSI0_PHY_PLL_OUT_DSICLK,
40 DT_DSI1_PHY_PLL_OUT_BYTECLK,
41 DT_DSI1_PHY_PLL_OUT_DSICLK,
42 DT_STANDALONE_PHY_PLL0_LINK_CLK,
43 DT_STANDALONE_PHY_PLL0_VCO_DIV_CLK,
44 DT_STANDALONE_PHY_PLL1_LINK_CLK,
45 DT_STANDALONE_PHY_PLL1_VCO_DIV_CLK,
46 };
47
48 enum {
49 P_BI_TCXO,
50 P_SLEEP_CLK,
51 P_DISP_CC_PLL0_OUT_MAIN,
52 P_DISP_CC_PLL1_OUT_EVEN,
53 P_DISP_CC_PLL1_OUT_MAIN,
54 P_DP0_PHY_PLL_LINK_CLK,
55 P_DP0_PHY_PLL_VCO_DIV_CLK,
56 P_DP1_PHY_PLL_LINK_CLK,
57 P_DP1_PHY_PLL_VCO_DIV_CLK,
58 P_DP2_PHY_PLL_LINK_CLK,
59 P_DP2_PHY_PLL_VCO_DIV_CLK,
60 P_DP3_PHY_PLL_LINK_CLK,
61 P_DP3_PHY_PLL_VCO_DIV_CLK,
62 P_DSI0_PHY_PLL_OUT_BYTECLK,
63 P_DSI0_PHY_PLL_OUT_DSICLK,
64 P_DSI1_PHY_PLL_OUT_BYTECLK,
65 P_DSI1_PHY_PLL_OUT_DSICLK,
66 P_STANDALONE_PHY_PLL0_LINK_CLK,
67 P_STANDALONE_PHY_PLL0_VCO_DIV_CLK,
68 P_STANDALONE_PHY_PLL1_LINK_CLK,
69 P_STANDALONE_PHY_PLL1_VCO_DIV_CLK,
70 };
71
72 static const struct pll_vco taycan_eko_t_vco[] = {
73 { 249600000, 2500000000, 0 },
74 };
75
76 /* 257.142858 MHz Configuration */
77 static const struct alpha_pll_config disp_cc_pll0_config = {
78 .l = 0xd,
79 .alpha = 0x6492,
80 .config_ctl_val = 0x25c400e7,
81 .config_ctl_hi_val = 0x0a8060e0,
82 .config_ctl_hi1_val = 0xf51dea20,
83 .user_ctl_val = 0x00000008,
84 .user_ctl_hi_val = 0x00000002,
85 };
86
87 static struct clk_alpha_pll disp_cc_pll0 = {
88 .offset = 0x0,
89 .config = &disp_cc_pll0_config,
90 .vco_table = taycan_eko_t_vco,
91 .num_vco = ARRAY_SIZE(taycan_eko_t_vco),
92 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T],
93 .clkr = {
94 .hw.init = &(const struct clk_init_data) {
95 .name = "disp_cc_pll0",
96 .parent_data = &(const struct clk_parent_data) {
97 .index = DT_BI_TCXO,
98 },
99 .num_parents = 1,
100 .ops = &clk_alpha_pll_taycan_eko_t_ops,
101 },
102 },
103 };
104
105 /* 600.0 MHz Configuration */
106 static const struct alpha_pll_config disp_cc_pll1_config = {
107 .l = 0x1f,
108 .alpha = 0x4000,
109 .config_ctl_val = 0x25c400e7,
110 .config_ctl_hi_val = 0x0a8060e0,
111 .config_ctl_hi1_val = 0xf51dea20,
112 .user_ctl_val = 0x00000008,
113 .user_ctl_hi_val = 0x00000002,
114 };
115
116 static struct clk_alpha_pll disp_cc_pll1 = {
117 .offset = 0x1000,
118 .config = &disp_cc_pll1_config,
119 .vco_table = taycan_eko_t_vco,
120 .num_vco = ARRAY_SIZE(taycan_eko_t_vco),
121 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T],
122 .clkr = {
123 .hw.init = &(const struct clk_init_data) {
124 .name = "disp_cc_pll1",
125 .parent_data = &(const struct clk_parent_data) {
126 .index = DT_BI_TCXO,
127 },
128 .num_parents = 1,
129 .ops = &clk_alpha_pll_taycan_eko_t_ops,
130 },
131 },
132 };
133
134 static const struct parent_map disp_cc_parent_map_0[] = {
135 { P_BI_TCXO, 0 },
136 { P_STANDALONE_PHY_PLL0_VCO_DIV_CLK, 1 },
137 { P_DP0_PHY_PLL_VCO_DIV_CLK, 2 },
138 { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 },
139 { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 },
140 { P_STANDALONE_PHY_PLL1_VCO_DIV_CLK, 5 },
141 { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 },
142 };
143
144 static const struct clk_parent_data disp_cc_parent_data_0[] = {
145 { .index = DT_BI_TCXO },
146 { .index = DT_STANDALONE_PHY_PLL0_VCO_DIV_CLK },
147 { .index = DT_DP0_PHY_PLL_VCO_DIV_CLK },
148 { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK },
149 { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK },
150 { .index = DT_STANDALONE_PHY_PLL1_VCO_DIV_CLK },
151 { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK },
152 };
153
154 static const struct parent_map disp_cc_parent_map_1[] = {
155 { P_BI_TCXO, 0 },
156 };
157
158 static const struct clk_parent_data disp_cc_parent_data_1[] = {
159 { .index = DT_BI_TCXO },
160 };
161
162 static const struct parent_map disp_cc_parent_map_2[] = {
163 { P_BI_TCXO, 0 },
164 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
165 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
166 { P_DSI1_PHY_PLL_OUT_DSICLK, 3 },
167 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
168 };
169
170 static const struct clk_parent_data disp_cc_parent_data_2[] = {
171 { .index = DT_BI_TCXO },
172 { .index = DT_DSI0_PHY_PLL_OUT_DSICLK },
173 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
174 { .index = DT_DSI1_PHY_PLL_OUT_DSICLK },
175 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },
176 };
177
178 static const struct parent_map disp_cc_parent_map_3[] = {
179 { P_BI_TCXO, 0 },
180 { P_DP0_PHY_PLL_LINK_CLK, 1 },
181 { P_DP1_PHY_PLL_LINK_CLK, 2 },
182 { P_DP2_PHY_PLL_LINK_CLK, 3 },
183 { P_DP3_PHY_PLL_LINK_CLK, 4 },
184 { P_STANDALONE_PHY_PLL1_LINK_CLK, 5 },
185 { P_STANDALONE_PHY_PLL0_LINK_CLK, 6 },
186 };
187
188 static const struct clk_parent_data disp_cc_parent_data_3[] = {
189 { .index = DT_BI_TCXO },
190 { .index = DT_DP0_PHY_PLL_LINK_CLK },
191 { .index = DT_DP1_PHY_PLL_LINK_CLK },
192 { .index = DT_DP2_PHY_PLL_LINK_CLK },
193 { .index = DT_DP3_PHY_PLL_LINK_CLK },
194 { .index = DT_STANDALONE_PHY_PLL1_LINK_CLK },
195 { .index = DT_STANDALONE_PHY_PLL0_LINK_CLK },
196 };
197
198 static const struct parent_map disp_cc_parent_map_4[] = {
199 { P_BI_TCXO, 0 },
200 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
201 { P_DSI1_PHY_PLL_OUT_DSICLK, 3 },
202 };
203
204 static const struct clk_parent_data disp_cc_parent_data_4[] = {
205 { .index = DT_BI_TCXO },
206 { .index = DT_DSI0_PHY_PLL_OUT_DSICLK },
207 { .index = DT_DSI1_PHY_PLL_OUT_DSICLK },
208 };
209
210 static const struct parent_map disp_cc_parent_map_5[] = {
211 { P_BI_TCXO, 0 },
212 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
213 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
214 };
215
216 static const struct clk_parent_data disp_cc_parent_data_5[] = {
217 { .index = DT_BI_TCXO },
218 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
219 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },
220 };
221
222 static const struct parent_map disp_cc_parent_map_6[] = {
223 { P_BI_TCXO, 0 },
224 { P_DISP_CC_PLL1_OUT_MAIN, 4 },
225 { P_DISP_CC_PLL1_OUT_EVEN, 6 },
226 };
227
228 static const struct clk_parent_data disp_cc_parent_data_6[] = {
229 { .index = DT_BI_TCXO },
230 { .hw = &disp_cc_pll1.clkr.hw },
231 { .hw = &disp_cc_pll1.clkr.hw },
232 };
233
234 static const struct parent_map disp_cc_parent_map_7[] = {
235 { P_BI_TCXO, 0 },
236 { P_DISP_CC_PLL0_OUT_MAIN, 1 },
237 { P_DISP_CC_PLL1_OUT_MAIN, 4 },
238 { P_DISP_CC_PLL1_OUT_EVEN, 6 },
239 };
240
241 static const struct clk_parent_data disp_cc_parent_data_7[] = {
242 { .index = DT_BI_TCXO },
243 { .hw = &disp_cc_pll0.clkr.hw },
244 { .hw = &disp_cc_pll1.clkr.hw },
245 { .hw = &disp_cc_pll1.clkr.hw },
246 };
247
248 static const struct parent_map disp_cc_parent_map_8[] = {
249 { P_BI_TCXO, 0 },
250 };
251
252 static const struct clk_parent_data disp_cc_parent_data_8[] = {
253 { .index = DT_BI_TCXO },
254 };
255
256 static const struct parent_map disp_cc_parent_map_9[] = {
257 { P_SLEEP_CLK, 0 },
258 };
259
260 static const struct clk_parent_data disp_cc_parent_data_9[] = {
261 { .index = DT_SLEEP_CLK },
262 };
263
264 static const struct freq_tbl ftbl_disp_cc_esync0_clk_src[] = {
265 F(19200000, P_BI_TCXO, 1, 0, 0),
266 { }
267 };
268
269 static struct clk_rcg2 disp_cc_esync0_clk_src = {
270 .cmd_rcgr = 0x80c0,
271 .mnd_width = 16,
272 .hid_width = 5,
273 .parent_map = disp_cc_parent_map_4,
274 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
275 .clkr.hw.init = &(const struct clk_init_data) {
276 .name = "disp_cc_esync0_clk_src",
277 .parent_data = disp_cc_parent_data_4,
278 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
279 .flags = CLK_SET_RATE_PARENT,
280 .ops = &clk_rcg2_shared_ops,
281 },
282 };
283
284 static struct clk_rcg2 disp_cc_esync1_clk_src = {
285 .cmd_rcgr = 0x80d8,
286 .mnd_width = 16,
287 .hid_width = 5,
288 .parent_map = disp_cc_parent_map_4,
289 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
290 .clkr.hw.init = &(const struct clk_init_data) {
291 .name = "disp_cc_esync1_clk_src",
292 .parent_data = disp_cc_parent_data_4,
293 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
294 .flags = CLK_SET_RATE_PARENT,
295 .ops = &clk_rcg2_shared_ops,
296 },
297 };
298
299 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
300 F(19200000, P_BI_TCXO, 1, 0, 0),
301 F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
302 F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
303 { }
304 };
305
306 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
307 .cmd_rcgr = 0x8360,
308 .mnd_width = 0,
309 .hid_width = 5,
310 .parent_map = disp_cc_parent_map_6,
311 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
312 .hw_clk_ctrl = true,
313 .clkr.hw.init = &(const struct clk_init_data) {
314 .name = "disp_cc_mdss_ahb_clk_src",
315 .parent_data = disp_cc_parent_data_6,
316 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
317 .flags = CLK_SET_RATE_PARENT,
318 .ops = &clk_rcg2_shared_ops,
319 },
320 };
321
322 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
323 .cmd_rcgr = 0x8180,
324 .mnd_width = 0,
325 .hid_width = 5,
326 .parent_map = disp_cc_parent_map_2,
327 .clkr.hw.init = &(const struct clk_init_data) {
328 .name = "disp_cc_mdss_byte0_clk_src",
329 .parent_data = disp_cc_parent_data_2,
330 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
331 .flags = CLK_SET_RATE_PARENT,
332 .ops = &clk_byte2_ops,
333 },
334 };
335
336 static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
337 .cmd_rcgr = 0x819c,
338 .mnd_width = 0,
339 .hid_width = 5,
340 .parent_map = disp_cc_parent_map_2,
341 .clkr.hw.init = &(const struct clk_init_data) {
342 .name = "disp_cc_mdss_byte1_clk_src",
343 .parent_data = disp_cc_parent_data_2,
344 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
345 .flags = CLK_SET_RATE_PARENT,
346 .ops = &clk_byte2_ops,
347 },
348 };
349
350 static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = {
351 .cmd_rcgr = 0x8234,
352 .mnd_width = 0,
353 .hid_width = 5,
354 .parent_map = disp_cc_parent_map_1,
355 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
356 .clkr.hw.init = &(const struct clk_init_data) {
357 .name = "disp_cc_mdss_dptx0_aux_clk_src",
358 .parent_data = disp_cc_parent_data_1,
359 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
360 .flags = CLK_SET_RATE_PARENT,
361 .ops = &clk_rcg2_shared_ops,
362 },
363 };
364
365 static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = {
366 .cmd_rcgr = 0x81e8,
367 .mnd_width = 0,
368 .hid_width = 5,
369 .parent_map = disp_cc_parent_map_3,
370 .clkr.hw.init = &(const struct clk_init_data) {
371 .name = "disp_cc_mdss_dptx0_link_clk_src",
372 .parent_data = disp_cc_parent_data_3,
373 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
374 .flags = CLK_SET_RATE_PARENT,
375 .ops = &clk_byte2_ops,
376 },
377 };
378
379 static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src = {
380 .cmd_rcgr = 0x8204,
381 .mnd_width = 16,
382 .hid_width = 5,
383 .parent_map = disp_cc_parent_map_0,
384 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
385 .clkr.hw.init = &(const struct clk_init_data) {
386 .name = "disp_cc_mdss_dptx0_pixel0_clk_src",
387 .parent_data = disp_cc_parent_data_0,
388 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
389 .flags = CLK_SET_RATE_PARENT,
390 .ops = &clk_dp_ops,
391 },
392 };
393
394 static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src = {
395 .cmd_rcgr = 0x821c,
396 .mnd_width = 16,
397 .hid_width = 5,
398 .parent_map = disp_cc_parent_map_0,
399 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
400 .clkr.hw.init = &(const struct clk_init_data) {
401 .name = "disp_cc_mdss_dptx0_pixel1_clk_src",
402 .parent_data = disp_cc_parent_data_0,
403 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
404 .flags = CLK_SET_RATE_PARENT,
405 .ops = &clk_dp_ops,
406 },
407 };
408
409 static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = {
410 .cmd_rcgr = 0x8298,
411 .mnd_width = 0,
412 .hid_width = 5,
413 .parent_map = disp_cc_parent_map_1,
414 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
415 .clkr.hw.init = &(const struct clk_init_data) {
416 .name = "disp_cc_mdss_dptx1_aux_clk_src",
417 .parent_data = disp_cc_parent_data_1,
418 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
419 .flags = CLK_SET_RATE_PARENT,
420 .ops = &clk_dp_ops,
421 },
422 };
423
424 static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = {
425 .cmd_rcgr = 0x827c,
426 .mnd_width = 0,
427 .hid_width = 5,
428 .parent_map = disp_cc_parent_map_3,
429 .clkr.hw.init = &(const struct clk_init_data) {
430 .name = "disp_cc_mdss_dptx1_link_clk_src",
431 .parent_data = disp_cc_parent_data_3,
432 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
433 .flags = CLK_SET_RATE_PARENT,
434 .ops = &clk_byte2_ops,
435 },
436 };
437
438 static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src = {
439 .cmd_rcgr = 0x824c,
440 .mnd_width = 16,
441 .hid_width = 5,
442 .parent_map = disp_cc_parent_map_0,
443 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
444 .clkr.hw.init = &(const struct clk_init_data) {
445 .name = "disp_cc_mdss_dptx1_pixel0_clk_src",
446 .parent_data = disp_cc_parent_data_0,
447 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
448 .flags = CLK_SET_RATE_PARENT,
449 .ops = &clk_dp_ops,
450 },
451 };
452
453 static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src = {
454 .cmd_rcgr = 0x8264,
455 .mnd_width = 16,
456 .hid_width = 5,
457 .parent_map = disp_cc_parent_map_0,
458 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
459 .clkr.hw.init = &(const struct clk_init_data) {
460 .name = "disp_cc_mdss_dptx1_pixel1_clk_src",
461 .parent_data = disp_cc_parent_data_0,
462 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
463 .flags = CLK_SET_RATE_PARENT,
464 .ops = &clk_dp_ops,
465 },
466 };
467
468 static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = {
469 .cmd_rcgr = 0x82fc,
470 .mnd_width = 0,
471 .hid_width = 5,
472 .parent_map = disp_cc_parent_map_1,
473 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
474 .clkr.hw.init = &(const struct clk_init_data) {
475 .name = "disp_cc_mdss_dptx2_aux_clk_src",
476 .parent_data = disp_cc_parent_data_1,
477 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
478 .flags = CLK_SET_RATE_PARENT,
479 .ops = &clk_rcg2_shared_ops,
480 },
481 };
482
483 static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = {
484 .cmd_rcgr = 0x82b0,
485 .mnd_width = 0,
486 .hid_width = 5,
487 .parent_map = disp_cc_parent_map_3,
488 .clkr.hw.init = &(const struct clk_init_data) {
489 .name = "disp_cc_mdss_dptx2_link_clk_src",
490 .parent_data = disp_cc_parent_data_3,
491 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
492 .flags = CLK_SET_RATE_PARENT,
493 .ops = &clk_byte2_ops,
494 },
495 };
496
497 static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src = {
498 .cmd_rcgr = 0x82cc,
499 .mnd_width = 16,
500 .hid_width = 5,
501 .parent_map = disp_cc_parent_map_0,
502 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
503 .clkr.hw.init = &(const struct clk_init_data) {
504 .name = "disp_cc_mdss_dptx2_pixel0_clk_src",
505 .parent_data = disp_cc_parent_data_0,
506 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
507 .flags = CLK_SET_RATE_PARENT,
508 .ops = &clk_dp_ops,
509 },
510 };
511
512 static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src = {
513 .cmd_rcgr = 0x82e4,
514 .mnd_width = 16,
515 .hid_width = 5,
516 .parent_map = disp_cc_parent_map_0,
517 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
518 .clkr.hw.init = &(const struct clk_init_data) {
519 .name = "disp_cc_mdss_dptx2_pixel1_clk_src",
520 .parent_data = disp_cc_parent_data_0,
521 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
522 .flags = CLK_SET_RATE_PARENT,
523 .ops = &clk_dp_ops,
524 },
525 };
526
527 static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = {
528 .cmd_rcgr = 0x8348,
529 .mnd_width = 0,
530 .hid_width = 5,
531 .parent_map = disp_cc_parent_map_1,
532 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
533 .clkr.hw.init = &(const struct clk_init_data) {
534 .name = "disp_cc_mdss_dptx3_aux_clk_src",
535 .parent_data = disp_cc_parent_data_1,
536 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
537 .flags = CLK_SET_RATE_PARENT,
538 .ops = &clk_rcg2_shared_ops,
539 },
540 };
541
542 static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = {
543 .cmd_rcgr = 0x832c,
544 .mnd_width = 0,
545 .hid_width = 5,
546 .parent_map = disp_cc_parent_map_3,
547 .clkr.hw.init = &(const struct clk_init_data) {
548 .name = "disp_cc_mdss_dptx3_link_clk_src",
549 .parent_data = disp_cc_parent_data_3,
550 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
551 .flags = CLK_SET_RATE_PARENT,
552 .ops = &clk_byte2_ops,
553 },
554 };
555
556 static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src = {
557 .cmd_rcgr = 0x8314,
558 .mnd_width = 16,
559 .hid_width = 5,
560 .parent_map = disp_cc_parent_map_0,
561 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
562 .clkr.hw.init = &(const struct clk_init_data) {
563 .name = "disp_cc_mdss_dptx3_pixel0_clk_src",
564 .parent_data = disp_cc_parent_data_0,
565 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
566 .flags = CLK_SET_RATE_PARENT,
567 .ops = &clk_dp_ops,
568 },
569 };
570
571 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
572 .cmd_rcgr = 0x81b8,
573 .mnd_width = 0,
574 .hid_width = 5,
575 .parent_map = disp_cc_parent_map_5,
576 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
577 .clkr.hw.init = &(const struct clk_init_data) {
578 .name = "disp_cc_mdss_esc0_clk_src",
579 .parent_data = disp_cc_parent_data_5,
580 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
581 .flags = CLK_SET_RATE_PARENT,
582 .ops = &clk_rcg2_shared_ops,
583 },
584 };
585
586 static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
587 .cmd_rcgr = 0x81d0,
588 .mnd_width = 0,
589 .hid_width = 5,
590 .parent_map = disp_cc_parent_map_5,
591 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
592 .clkr.hw.init = &(const struct clk_init_data) {
593 .name = "disp_cc_mdss_esc1_clk_src",
594 .parent_data = disp_cc_parent_data_5,
595 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
596 .flags = CLK_SET_RATE_PARENT,
597 .ops = &clk_rcg2_shared_ops,
598 },
599 };
600
601 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
602 F(19200000, P_BI_TCXO, 1, 0, 0),
603 F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
604 F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
605 F(150000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
606 F(156000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
607 F(205000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
608 F(337000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
609 F(417000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
610 F(532000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
611 F(600000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
612 F(660000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
613 F(717000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
614 { }
615 };
616
617 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
618 .cmd_rcgr = 0x8150,
619 .mnd_width = 0,
620 .hid_width = 5,
621 .parent_map = disp_cc_parent_map_7,
622 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
623 .hw_clk_ctrl = true,
624 .clkr.hw.init = &(const struct clk_init_data) {
625 .name = "disp_cc_mdss_mdp_clk_src",
626 .parent_data = disp_cc_parent_data_7,
627 .num_parents = ARRAY_SIZE(disp_cc_parent_data_7),
628 .flags = CLK_SET_RATE_PARENT,
629 .ops = &clk_rcg2_shared_ops,
630 },
631 };
632
633 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
634 .cmd_rcgr = 0x8108,
635 .mnd_width = 8,
636 .hid_width = 5,
637 .parent_map = disp_cc_parent_map_2,
638 .clkr.hw.init = &(const struct clk_init_data) {
639 .name = "disp_cc_mdss_pclk0_clk_src",
640 .parent_data = disp_cc_parent_data_2,
641 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
642 .flags = CLK_SET_RATE_PARENT,
643 .ops = &clk_pixel_ops,
644 },
645 };
646
647 static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {
648 .cmd_rcgr = 0x8120,
649 .mnd_width = 8,
650 .hid_width = 5,
651 .parent_map = disp_cc_parent_map_2,
652 .clkr.hw.init = &(const struct clk_init_data) {
653 .name = "disp_cc_mdss_pclk1_clk_src",
654 .parent_data = disp_cc_parent_data_2,
655 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
656 .flags = CLK_SET_RATE_PARENT,
657 .ops = &clk_pixel_ops,
658 },
659 };
660
661 static struct clk_rcg2 disp_cc_mdss_pclk2_clk_src = {
662 .cmd_rcgr = 0x8138,
663 .mnd_width = 8,
664 .hid_width = 5,
665 .parent_map = disp_cc_parent_map_2,
666 .clkr.hw.init = &(const struct clk_init_data) {
667 .name = "disp_cc_mdss_pclk2_clk_src",
668 .parent_data = disp_cc_parent_data_2,
669 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
670 .flags = CLK_SET_RATE_PARENT,
671 .ops = &clk_pixel_ops,
672 },
673 };
674
675 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
676 .cmd_rcgr = 0x8168,
677 .mnd_width = 0,
678 .hid_width = 5,
679 .parent_map = disp_cc_parent_map_1,
680 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
681 .clkr.hw.init = &(const struct clk_init_data) {
682 .name = "disp_cc_mdss_vsync_clk_src",
683 .parent_data = disp_cc_parent_data_1,
684 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
685 .flags = CLK_SET_RATE_PARENT,
686 .ops = &clk_rcg2_shared_ops,
687 },
688 };
689
690 static struct clk_rcg2 disp_cc_osc_clk_src = {
691 .cmd_rcgr = 0x80f0,
692 .mnd_width = 0,
693 .hid_width = 5,
694 .parent_map = disp_cc_parent_map_8,
695 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
696 .clkr.hw.init = &(const struct clk_init_data) {
697 .name = "disp_cc_osc_clk_src",
698 .parent_data = disp_cc_parent_data_8,
699 .num_parents = ARRAY_SIZE(disp_cc_parent_data_8),
700 .flags = CLK_SET_RATE_PARENT,
701 .ops = &clk_rcg2_shared_ops,
702 },
703 };
704
705 static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = {
706 F(32000, P_SLEEP_CLK, 1, 0, 0),
707 { }
708 };
709
710 static struct clk_rcg2 disp_cc_sleep_clk_src = {
711 .cmd_rcgr = 0xe064,
712 .mnd_width = 0,
713 .hid_width = 5,
714 .parent_map = disp_cc_parent_map_9,
715 .freq_tbl = ftbl_disp_cc_sleep_clk_src,
716 .clkr.hw.init = &(const struct clk_init_data) {
717 .name = "disp_cc_sleep_clk_src",
718 .parent_data = disp_cc_parent_data_9,
719 .num_parents = ARRAY_SIZE(disp_cc_parent_data_9),
720 .flags = CLK_SET_RATE_PARENT,
721 .ops = &clk_rcg2_shared_ops,
722 },
723 };
724
725 static struct clk_rcg2 disp_cc_xo_clk_src = {
726 .cmd_rcgr = 0xe044,
727 .mnd_width = 0,
728 .hid_width = 5,
729 .parent_map = disp_cc_parent_map_1,
730 .freq_tbl = ftbl_disp_cc_esync0_clk_src,
731 .clkr.hw.init = &(const struct clk_init_data) {
732 .name = "disp_cc_xo_clk_src",
733 .parent_data = disp_cc_parent_data_1,
734 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
735 .flags = CLK_SET_RATE_PARENT,
736 .ops = &clk_rcg2_shared_ops,
737 },
738 };
739
740 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
741 .reg = 0x8198,
742 .shift = 0,
743 .width = 4,
744 .clkr.hw.init = &(const struct clk_init_data) {
745 .name = "disp_cc_mdss_byte0_div_clk_src",
746 .parent_hws = (const struct clk_hw*[]) {
747 &disp_cc_mdss_byte0_clk_src.clkr.hw,
748 },
749 .num_parents = 1,
750 .flags = CLK_SET_RATE_PARENT,
751 .ops = &clk_regmap_div_ops,
752 },
753 };
754
755 static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
756 .reg = 0x81b4,
757 .shift = 0,
758 .width = 4,
759 .clkr.hw.init = &(const struct clk_init_data) {
760 .name = "disp_cc_mdss_byte1_div_clk_src",
761 .parent_hws = (const struct clk_hw*[]) {
762 &disp_cc_mdss_byte1_clk_src.clkr.hw,
763 },
764 .num_parents = 1,
765 .flags = CLK_SET_RATE_PARENT,
766 .ops = &clk_regmap_div_ops,
767 },
768 };
769
770 static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src = {
771 .reg = 0x8200,
772 .shift = 0,
773 .width = 4,
774 .clkr.hw.init = &(const struct clk_init_data) {
775 .name = "disp_cc_mdss_dptx0_link_div_clk_src",
776 .parent_hws = (const struct clk_hw*[]) {
777 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
778 },
779 .num_parents = 1,
780 .flags = CLK_SET_RATE_PARENT,
781 .ops = &clk_regmap_div_ro_ops,
782 },
783 };
784
785 static struct clk_regmap_div disp_cc_mdss_dptx0_link_dpin_div_clk_src = {
786 .reg = 0x838c,
787 .shift = 0,
788 .width = 4,
789 .clkr.hw.init = &(const struct clk_init_data) {
790 .name = "disp_cc_mdss_dptx0_link_dpin_div_clk_src",
791 .parent_hws = (const struct clk_hw*[]) {
792 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
793 },
794 .num_parents = 1,
795 .flags = CLK_SET_RATE_PARENT,
796 .ops = &clk_regmap_div_ro_ops,
797 },
798 };
799
800 static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src = {
801 .reg = 0x8294,
802 .shift = 0,
803 .width = 4,
804 .clkr.hw.init = &(const struct clk_init_data) {
805 .name = "disp_cc_mdss_dptx1_link_div_clk_src",
806 .parent_hws = (const struct clk_hw*[]) {
807 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
808 },
809 .num_parents = 1,
810 .flags = CLK_SET_RATE_PARENT,
811 .ops = &clk_regmap_div_ro_ops,
812 },
813 };
814
815 static struct clk_regmap_div disp_cc_mdss_dptx1_link_dpin_div_clk_src = {
816 .reg = 0x8390,
817 .shift = 0,
818 .width = 4,
819 .clkr.hw.init = &(const struct clk_init_data) {
820 .name = "disp_cc_mdss_dptx1_link_dpin_div_clk_src",
821 .parent_hws = (const struct clk_hw*[]) {
822 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
823 },
824 .num_parents = 1,
825 .flags = CLK_SET_RATE_PARENT,
826 .ops = &clk_regmap_div_ro_ops,
827 },
828 };
829
830 static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src = {
831 .reg = 0x82c8,
832 .shift = 0,
833 .width = 4,
834 .clkr.hw.init = &(const struct clk_init_data) {
835 .name = "disp_cc_mdss_dptx2_link_div_clk_src",
836 .parent_hws = (const struct clk_hw*[]) {
837 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
838 },
839 .num_parents = 1,
840 .flags = CLK_SET_RATE_PARENT,
841 .ops = &clk_regmap_div_ro_ops,
842 },
843 };
844
845 static struct clk_regmap_div disp_cc_mdss_dptx2_link_dpin_div_clk_src = {
846 .reg = 0x8394,
847 .shift = 0,
848 .width = 4,
849 .clkr.hw.init = &(const struct clk_init_data) {
850 .name = "disp_cc_mdss_dptx2_link_dpin_div_clk_src",
851 .parent_hws = (const struct clk_hw*[]) {
852 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
853 },
854 .num_parents = 1,
855 .flags = CLK_SET_RATE_PARENT,
856 .ops = &clk_regmap_div_ro_ops,
857 },
858 };
859
860 static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src = {
861 .reg = 0x8344,
862 .shift = 0,
863 .width = 4,
864 .clkr.hw.init = &(const struct clk_init_data) {
865 .name = "disp_cc_mdss_dptx3_link_div_clk_src",
866 .parent_hws = (const struct clk_hw*[]) {
867 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
868 },
869 .num_parents = 1,
870 .flags = CLK_SET_RATE_PARENT,
871 .ops = &clk_regmap_div_ro_ops,
872 },
873 };
874
875 static struct clk_regmap_div disp_cc_mdss_dptx3_link_dpin_div_clk_src = {
876 .reg = 0x8398,
877 .shift = 0,
878 .width = 4,
879 .clkr.hw.init = &(const struct clk_init_data) {
880 .name = "disp_cc_mdss_dptx3_link_dpin_div_clk_src",
881 .parent_hws = (const struct clk_hw*[]) {
882 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
883 },
884 .num_parents = 1,
885 .flags = CLK_SET_RATE_PARENT,
886 .ops = &clk_regmap_div_ro_ops,
887 },
888 };
889
890 static struct clk_branch disp_cc_esync0_clk = {
891 .halt_reg = 0x80b8,
892 .halt_check = BRANCH_HALT,
893 .clkr = {
894 .enable_reg = 0x80b8,
895 .enable_mask = BIT(0),
896 .hw.init = &(const struct clk_init_data) {
897 .name = "disp_cc_esync0_clk",
898 .parent_hws = (const struct clk_hw*[]) {
899 &disp_cc_esync0_clk_src.clkr.hw,
900 },
901 .num_parents = 1,
902 .flags = CLK_SET_RATE_PARENT,
903 .ops = &clk_branch2_ops,
904 },
905 },
906 };
907
908 static struct clk_branch disp_cc_esync1_clk = {
909 .halt_reg = 0x80bc,
910 .halt_check = BRANCH_HALT,
911 .clkr = {
912 .enable_reg = 0x80bc,
913 .enable_mask = BIT(0),
914 .hw.init = &(const struct clk_init_data) {
915 .name = "disp_cc_esync1_clk",
916 .parent_hws = (const struct clk_hw*[]) {
917 &disp_cc_esync1_clk_src.clkr.hw,
918 },
919 .num_parents = 1,
920 .flags = CLK_SET_RATE_PARENT,
921 .ops = &clk_branch2_ops,
922 },
923 },
924 };
925
926 static struct clk_branch disp_cc_mdss_accu_shift_clk = {
927 .halt_reg = 0xe060,
928 .halt_check = BRANCH_HALT_VOTED,
929 .clkr = {
930 .enable_reg = 0xe060,
931 .enable_mask = BIT(0),
932 .hw.init = &(const struct clk_init_data) {
933 .name = "disp_cc_mdss_accu_shift_clk",
934 .parent_hws = (const struct clk_hw*[]) {
935 &disp_cc_xo_clk_src.clkr.hw,
936 },
937 .num_parents = 1,
938 .flags = CLK_SET_RATE_PARENT,
939 .ops = &clk_branch2_ops,
940 },
941 },
942 };
943
944 static struct clk_branch disp_cc_mdss_ahb1_clk = {
945 .halt_reg = 0xa028,
946 .halt_check = BRANCH_HALT,
947 .clkr = {
948 .enable_reg = 0xa028,
949 .enable_mask = BIT(0),
950 .hw.init = &(const struct clk_init_data) {
951 .name = "disp_cc_mdss_ahb1_clk",
952 .parent_hws = (const struct clk_hw*[]) {
953 &disp_cc_mdss_ahb_clk_src.clkr.hw,
954 },
955 .num_parents = 1,
956 .flags = CLK_SET_RATE_PARENT,
957 .ops = &clk_branch2_ops,
958 },
959 },
960 };
961
962 static struct clk_branch disp_cc_mdss_ahb_clk = {
963 .halt_reg = 0x80b0,
964 .halt_check = BRANCH_HALT,
965 .clkr = {
966 .enable_reg = 0x80b0,
967 .enable_mask = BIT(0),
968 .hw.init = &(const struct clk_init_data) {
969 .name = "disp_cc_mdss_ahb_clk",
970 .parent_hws = (const struct clk_hw*[]) {
971 &disp_cc_mdss_ahb_clk_src.clkr.hw,
972 },
973 .num_parents = 1,
974 .flags = CLK_SET_RATE_PARENT,
975 .ops = &clk_branch2_ops,
976 },
977 },
978 };
979
980 static struct clk_branch disp_cc_mdss_byte0_clk = {
981 .halt_reg = 0x8034,
982 .halt_check = BRANCH_HALT,
983 .clkr = {
984 .enable_reg = 0x8034,
985 .enable_mask = BIT(0),
986 .hw.init = &(const struct clk_init_data) {
987 .name = "disp_cc_mdss_byte0_clk",
988 .parent_hws = (const struct clk_hw*[]) {
989 &disp_cc_mdss_byte0_clk_src.clkr.hw,
990 },
991 .num_parents = 1,
992 .flags = CLK_SET_RATE_PARENT,
993 .ops = &clk_branch2_ops,
994 },
995 },
996 };
997
998 static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
999 .halt_reg = 0x8038,
1000 .halt_check = BRANCH_HALT,
1001 .clkr = {
1002 .enable_reg = 0x8038,
1003 .enable_mask = BIT(0),
1004 .hw.init = &(const struct clk_init_data) {
1005 .name = "disp_cc_mdss_byte0_intf_clk",
1006 .parent_hws = (const struct clk_hw*[]) {
1007 &disp_cc_mdss_byte0_div_clk_src.clkr.hw,
1008 },
1009 .num_parents = 1,
1010 .flags = CLK_SET_RATE_PARENT,
1011 .ops = &clk_branch2_ops,
1012 },
1013 },
1014 };
1015
1016 static struct clk_branch disp_cc_mdss_byte1_clk = {
1017 .halt_reg = 0x803c,
1018 .halt_check = BRANCH_HALT,
1019 .clkr = {
1020 .enable_reg = 0x803c,
1021 .enable_mask = BIT(0),
1022 .hw.init = &(const struct clk_init_data) {
1023 .name = "disp_cc_mdss_byte1_clk",
1024 .parent_hws = (const struct clk_hw*[]) {
1025 &disp_cc_mdss_byte1_clk_src.clkr.hw,
1026 },
1027 .num_parents = 1,
1028 .flags = CLK_SET_RATE_PARENT,
1029 .ops = &clk_branch2_ops,
1030 },
1031 },
1032 };
1033
1034 static struct clk_branch disp_cc_mdss_byte1_intf_clk = {
1035 .halt_reg = 0x8040,
1036 .halt_check = BRANCH_HALT,
1037 .clkr = {
1038 .enable_reg = 0x8040,
1039 .enable_mask = BIT(0),
1040 .hw.init = &(const struct clk_init_data) {
1041 .name = "disp_cc_mdss_byte1_intf_clk",
1042 .parent_hws = (const struct clk_hw*[]) {
1043 &disp_cc_mdss_byte1_div_clk_src.clkr.hw,
1044 },
1045 .num_parents = 1,
1046 .flags = CLK_SET_RATE_PARENT,
1047 .ops = &clk_branch2_ops,
1048 },
1049 },
1050 };
1051
1052 static struct clk_branch disp_cc_mdss_dptx0_aux_clk = {
1053 .halt_reg = 0x8064,
1054 .halt_check = BRANCH_HALT,
1055 .clkr = {
1056 .enable_reg = 0x8064,
1057 .enable_mask = BIT(0),
1058 .hw.init = &(const struct clk_init_data) {
1059 .name = "disp_cc_mdss_dptx0_aux_clk",
1060 .parent_hws = (const struct clk_hw*[]) {
1061 &disp_cc_mdss_dptx0_aux_clk_src.clkr.hw,
1062 },
1063 .num_parents = 1,
1064 .flags = CLK_SET_RATE_PARENT,
1065 .ops = &clk_branch2_ops,
1066 },
1067 },
1068 };
1069
1070 static struct clk_branch disp_cc_mdss_dptx0_link_clk = {
1071 .halt_reg = 0x804c,
1072 .halt_check = BRANCH_HALT,
1073 .clkr = {
1074 .enable_reg = 0x804c,
1075 .enable_mask = BIT(0),
1076 .hw.init = &(const struct clk_init_data) {
1077 .name = "disp_cc_mdss_dptx0_link_clk",
1078 .parent_hws = (const struct clk_hw*[]) {
1079 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
1080 },
1081 .num_parents = 1,
1082 .flags = CLK_SET_RATE_PARENT,
1083 .ops = &clk_branch2_ops,
1084 },
1085 },
1086 };
1087
1088 static struct clk_branch disp_cc_mdss_dptx0_link_dpin_clk = {
1089 .halt_reg = 0x837c,
1090 .halt_check = BRANCH_HALT,
1091 .clkr = {
1092 .enable_reg = 0x837c,
1093 .enable_mask = BIT(0),
1094 .hw.init = &(const struct clk_init_data) {
1095 .name = "disp_cc_mdss_dptx0_link_dpin_clk",
1096 .parent_hws = (const struct clk_hw*[]) {
1097 &disp_cc_mdss_dptx0_link_dpin_div_clk_src.clkr.hw,
1098 },
1099 .num_parents = 1,
1100 .flags = CLK_SET_RATE_PARENT,
1101 .ops = &clk_branch2_ops,
1102 },
1103 },
1104 };
1105
1106 static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk = {
1107 .halt_reg = 0x8054,
1108 .halt_check = BRANCH_HALT,
1109 .clkr = {
1110 .enable_reg = 0x8054,
1111 .enable_mask = BIT(0),
1112 .hw.init = &(const struct clk_init_data) {
1113 .name = "disp_cc_mdss_dptx0_link_intf_clk",
1114 .parent_hws = (const struct clk_hw*[]) {
1115 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
1116 },
1117 .num_parents = 1,
1118 .flags = CLK_SET_RATE_PARENT,
1119 .ops = &clk_branch2_ops,
1120 },
1121 },
1122 };
1123
1124 static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = {
1125 .halt_reg = 0x805c,
1126 .halt_check = BRANCH_HALT,
1127 .clkr = {
1128 .enable_reg = 0x805c,
1129 .enable_mask = BIT(0),
1130 .hw.init = &(const struct clk_init_data) {
1131 .name = "disp_cc_mdss_dptx0_pixel0_clk",
1132 .parent_hws = (const struct clk_hw*[]) {
1133 &disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw,
1134 },
1135 .num_parents = 1,
1136 .flags = CLK_SET_RATE_PARENT,
1137 .ops = &clk_branch2_ops,
1138 },
1139 },
1140 };
1141
1142 static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = {
1143 .halt_reg = 0x8060,
1144 .halt_check = BRANCH_HALT,
1145 .clkr = {
1146 .enable_reg = 0x8060,
1147 .enable_mask = BIT(0),
1148 .hw.init = &(const struct clk_init_data) {
1149 .name = "disp_cc_mdss_dptx0_pixel1_clk",
1150 .parent_hws = (const struct clk_hw*[]) {
1151 &disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw,
1152 },
1153 .num_parents = 1,
1154 .flags = CLK_SET_RATE_PARENT,
1155 .ops = &clk_branch2_ops,
1156 },
1157 },
1158 };
1159
1160 static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk = {
1161 .halt_reg = 0x8050,
1162 .halt_check = BRANCH_HALT,
1163 .clkr = {
1164 .enable_reg = 0x8050,
1165 .enable_mask = BIT(0),
1166 .hw.init = &(const struct clk_init_data) {
1167 .name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk",
1168 .parent_hws = (const struct clk_hw*[]) {
1169 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
1170 },
1171 .num_parents = 1,
1172 .flags = CLK_SET_RATE_PARENT,
1173 .ops = &clk_branch2_ops,
1174 },
1175 },
1176 };
1177
1178 static struct clk_branch disp_cc_mdss_dptx1_aux_clk = {
1179 .halt_reg = 0x8080,
1180 .halt_check = BRANCH_HALT,
1181 .clkr = {
1182 .enable_reg = 0x8080,
1183 .enable_mask = BIT(0),
1184 .hw.init = &(const struct clk_init_data) {
1185 .name = "disp_cc_mdss_dptx1_aux_clk",
1186 .parent_hws = (const struct clk_hw*[]) {
1187 &disp_cc_mdss_dptx1_aux_clk_src.clkr.hw,
1188 },
1189 .num_parents = 1,
1190 .flags = CLK_SET_RATE_PARENT,
1191 .ops = &clk_branch2_ops,
1192 },
1193 },
1194 };
1195
1196 static struct clk_branch disp_cc_mdss_dptx1_link_clk = {
1197 .halt_reg = 0x8070,
1198 .halt_check = BRANCH_HALT,
1199 .clkr = {
1200 .enable_reg = 0x8070,
1201 .enable_mask = BIT(0),
1202 .hw.init = &(const struct clk_init_data) {
1203 .name = "disp_cc_mdss_dptx1_link_clk",
1204 .parent_hws = (const struct clk_hw*[]) {
1205 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
1206 },
1207 .num_parents = 1,
1208 .flags = CLK_SET_RATE_PARENT,
1209 .ops = &clk_branch2_ops,
1210 },
1211 },
1212 };
1213
1214 static struct clk_branch disp_cc_mdss_dptx1_link_dpin_clk = {
1215 .halt_reg = 0x8380,
1216 .halt_check = BRANCH_HALT,
1217 .clkr = {
1218 .enable_reg = 0x8380,
1219 .enable_mask = BIT(0),
1220 .hw.init = &(const struct clk_init_data) {
1221 .name = "disp_cc_mdss_dptx1_link_dpin_clk",
1222 .parent_hws = (const struct clk_hw*[]) {
1223 &disp_cc_mdss_dptx1_link_dpin_div_clk_src.clkr.hw,
1224 },
1225 .num_parents = 1,
1226 .flags = CLK_SET_RATE_PARENT,
1227 .ops = &clk_branch2_ops,
1228 },
1229 },
1230 };
1231
1232 static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk = {
1233 .halt_reg = 0x8078,
1234 .halt_check = BRANCH_HALT,
1235 .clkr = {
1236 .enable_reg = 0x8078,
1237 .enable_mask = BIT(0),
1238 .hw.init = &(const struct clk_init_data) {
1239 .name = "disp_cc_mdss_dptx1_link_intf_clk",
1240 .parent_hws = (const struct clk_hw*[]) {
1241 &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
1242 },
1243 .num_parents = 1,
1244 .flags = CLK_SET_RATE_PARENT,
1245 .ops = &clk_branch2_ops,
1246 },
1247 },
1248 };
1249
1250 static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk = {
1251 .halt_reg = 0x8068,
1252 .halt_check = BRANCH_HALT,
1253 .clkr = {
1254 .enable_reg = 0x8068,
1255 .enable_mask = BIT(0),
1256 .hw.init = &(const struct clk_init_data) {
1257 .name = "disp_cc_mdss_dptx1_pixel0_clk",
1258 .parent_hws = (const struct clk_hw*[]) {
1259 &disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw,
1260 },
1261 .num_parents = 1,
1262 .flags = CLK_SET_RATE_PARENT,
1263 .ops = &clk_branch2_ops,
1264 },
1265 },
1266 };
1267
1268 static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk = {
1269 .halt_reg = 0x806c,
1270 .halt_check = BRANCH_HALT,
1271 .clkr = {
1272 .enable_reg = 0x806c,
1273 .enable_mask = BIT(0),
1274 .hw.init = &(const struct clk_init_data) {
1275 .name = "disp_cc_mdss_dptx1_pixel1_clk",
1276 .parent_hws = (const struct clk_hw*[]) {
1277 &disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw,
1278 },
1279 .num_parents = 1,
1280 .flags = CLK_SET_RATE_PARENT,
1281 .ops = &clk_branch2_ops,
1282 },
1283 },
1284 };
1285
1286 static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk = {
1287 .halt_reg = 0x8074,
1288 .halt_check = BRANCH_HALT,
1289 .clkr = {
1290 .enable_reg = 0x8074,
1291 .enable_mask = BIT(0),
1292 .hw.init = &(const struct clk_init_data) {
1293 .name = "disp_cc_mdss_dptx1_usb_router_link_intf_clk",
1294 .parent_hws = (const struct clk_hw*[]) {
1295 &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
1296 },
1297 .num_parents = 1,
1298 .flags = CLK_SET_RATE_PARENT,
1299 .ops = &clk_branch2_ops,
1300 },
1301 },
1302 };
1303
1304 static struct clk_branch disp_cc_mdss_dptx2_aux_clk = {
1305 .halt_reg = 0x8098,
1306 .halt_check = BRANCH_HALT,
1307 .clkr = {
1308 .enable_reg = 0x8098,
1309 .enable_mask = BIT(0),
1310 .hw.init = &(const struct clk_init_data) {
1311 .name = "disp_cc_mdss_dptx2_aux_clk",
1312 .parent_hws = (const struct clk_hw*[]) {
1313 &disp_cc_mdss_dptx2_aux_clk_src.clkr.hw,
1314 },
1315 .num_parents = 1,
1316 .flags = CLK_SET_RATE_PARENT,
1317 .ops = &clk_branch2_ops,
1318 },
1319 },
1320 };
1321
1322 static struct clk_branch disp_cc_mdss_dptx2_link_clk = {
1323 .halt_reg = 0x808c,
1324 .halt_check = BRANCH_HALT,
1325 .clkr = {
1326 .enable_reg = 0x808c,
1327 .enable_mask = BIT(0),
1328 .hw.init = &(const struct clk_init_data) {
1329 .name = "disp_cc_mdss_dptx2_link_clk",
1330 .parent_hws = (const struct clk_hw*[]) {
1331 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
1332 },
1333 .num_parents = 1,
1334 .flags = CLK_SET_RATE_PARENT,
1335 .ops = &clk_branch2_ops,
1336 },
1337 },
1338 };
1339
1340 static struct clk_branch disp_cc_mdss_dptx2_link_dpin_clk = {
1341 .halt_reg = 0x8384,
1342 .halt_check = BRANCH_HALT,
1343 .clkr = {
1344 .enable_reg = 0x8384,
1345 .enable_mask = BIT(0),
1346 .hw.init = &(const struct clk_init_data) {
1347 .name = "disp_cc_mdss_dptx2_link_dpin_clk",
1348 .parent_hws = (const struct clk_hw*[]) {
1349 &disp_cc_mdss_dptx2_link_dpin_div_clk_src.clkr.hw,
1350 },
1351 .num_parents = 1,
1352 .flags = CLK_SET_RATE_PARENT,
1353 .ops = &clk_branch2_ops,
1354 },
1355 },
1356 };
1357
1358 static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk = {
1359 .halt_reg = 0x8090,
1360 .halt_check = BRANCH_HALT,
1361 .clkr = {
1362 .enable_reg = 0x8090,
1363 .enable_mask = BIT(0),
1364 .hw.init = &(const struct clk_init_data) {
1365 .name = "disp_cc_mdss_dptx2_link_intf_clk",
1366 .parent_hws = (const struct clk_hw*[]) {
1367 &disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw,
1368 },
1369 .num_parents = 1,
1370 .flags = CLK_SET_RATE_PARENT,
1371 .ops = &clk_branch2_ops,
1372 },
1373 },
1374 };
1375
1376 static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk = {
1377 .halt_reg = 0x8084,
1378 .halt_check = BRANCH_HALT,
1379 .clkr = {
1380 .enable_reg = 0x8084,
1381 .enable_mask = BIT(0),
1382 .hw.init = &(const struct clk_init_data) {
1383 .name = "disp_cc_mdss_dptx2_pixel0_clk",
1384 .parent_hws = (const struct clk_hw*[]) {
1385 &disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw,
1386 },
1387 .num_parents = 1,
1388 .flags = CLK_SET_RATE_PARENT,
1389 .ops = &clk_branch2_ops,
1390 },
1391 },
1392 };
1393
1394 static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk = {
1395 .halt_reg = 0x8088,
1396 .halt_check = BRANCH_HALT,
1397 .clkr = {
1398 .enable_reg = 0x8088,
1399 .enable_mask = BIT(0),
1400 .hw.init = &(const struct clk_init_data) {
1401 .name = "disp_cc_mdss_dptx2_pixel1_clk",
1402 .parent_hws = (const struct clk_hw*[]) {
1403 &disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw,
1404 },
1405 .num_parents = 1,
1406 .flags = CLK_SET_RATE_PARENT,
1407 .ops = &clk_branch2_ops,
1408 },
1409 },
1410 };
1411
1412 static struct clk_branch disp_cc_mdss_dptx2_usb_router_link_intf_clk = {
1413 .halt_reg = 0x8378,
1414 .halt_check = BRANCH_HALT,
1415 .clkr = {
1416 .enable_reg = 0x8378,
1417 .enable_mask = BIT(0),
1418 .hw.init = &(const struct clk_init_data) {
1419 .name = "disp_cc_mdss_dptx2_usb_router_link_intf_clk",
1420 .parent_hws = (const struct clk_hw*[]) {
1421 &disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw,
1422 },
1423 .num_parents = 1,
1424 .flags = CLK_SET_RATE_PARENT,
1425 .ops = &clk_branch2_ops,
1426 },
1427 },
1428 };
1429
1430 static struct clk_branch disp_cc_mdss_dptx3_aux_clk = {
1431 .halt_reg = 0x80a8,
1432 .halt_check = BRANCH_HALT,
1433 .clkr = {
1434 .enable_reg = 0x80a8,
1435 .enable_mask = BIT(0),
1436 .hw.init = &(const struct clk_init_data) {
1437 .name = "disp_cc_mdss_dptx3_aux_clk",
1438 .parent_hws = (const struct clk_hw*[]) {
1439 &disp_cc_mdss_dptx3_aux_clk_src.clkr.hw,
1440 },
1441 .num_parents = 1,
1442 .flags = CLK_SET_RATE_PARENT,
1443 .ops = &clk_branch2_ops,
1444 },
1445 },
1446 };
1447
1448 static struct clk_branch disp_cc_mdss_dptx3_link_clk = {
1449 .halt_reg = 0x80a0,
1450 .halt_check = BRANCH_HALT,
1451 .clkr = {
1452 .enable_reg = 0x80a0,
1453 .enable_mask = BIT(0),
1454 .hw.init = &(const struct clk_init_data) {
1455 .name = "disp_cc_mdss_dptx3_link_clk",
1456 .parent_hws = (const struct clk_hw*[]) {
1457 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
1458 },
1459 .num_parents = 1,
1460 .flags = CLK_SET_RATE_PARENT,
1461 .ops = &clk_branch2_ops,
1462 },
1463 },
1464 };
1465
1466 static struct clk_branch disp_cc_mdss_dptx3_link_dpin_clk = {
1467 .halt_reg = 0x8388,
1468 .halt_check = BRANCH_HALT,
1469 .clkr = {
1470 .enable_reg = 0x8388,
1471 .enable_mask = BIT(0),
1472 .hw.init = &(const struct clk_init_data) {
1473 .name = "disp_cc_mdss_dptx3_link_dpin_clk",
1474 .parent_hws = (const struct clk_hw*[]) {
1475 &disp_cc_mdss_dptx3_link_dpin_div_clk_src.clkr.hw,
1476 },
1477 .num_parents = 1,
1478 .flags = CLK_SET_RATE_PARENT,
1479 .ops = &clk_branch2_ops,
1480 },
1481 },
1482 };
1483
1484 static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk = {
1485 .halt_reg = 0x80a4,
1486 .halt_check = BRANCH_HALT,
1487 .clkr = {
1488 .enable_reg = 0x80a4,
1489 .enable_mask = BIT(0),
1490 .hw.init = &(const struct clk_init_data) {
1491 .name = "disp_cc_mdss_dptx3_link_intf_clk",
1492 .parent_hws = (const struct clk_hw*[]) {
1493 &disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw,
1494 },
1495 .num_parents = 1,
1496 .flags = CLK_SET_RATE_PARENT,
1497 .ops = &clk_branch2_ops,
1498 },
1499 },
1500 };
1501
1502 static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk = {
1503 .halt_reg = 0x809c,
1504 .halt_check = BRANCH_HALT,
1505 .clkr = {
1506 .enable_reg = 0x809c,
1507 .enable_mask = BIT(0),
1508 .hw.init = &(const struct clk_init_data) {
1509 .name = "disp_cc_mdss_dptx3_pixel0_clk",
1510 .parent_hws = (const struct clk_hw*[]) {
1511 &disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw,
1512 },
1513 .num_parents = 1,
1514 .flags = CLK_SET_RATE_PARENT,
1515 .ops = &clk_branch2_ops,
1516 },
1517 },
1518 };
1519
1520 static struct clk_branch disp_cc_mdss_esc0_clk = {
1521 .halt_reg = 0x8044,
1522 .halt_check = BRANCH_HALT,
1523 .clkr = {
1524 .enable_reg = 0x8044,
1525 .enable_mask = BIT(0),
1526 .hw.init = &(const struct clk_init_data) {
1527 .name = "disp_cc_mdss_esc0_clk",
1528 .parent_hws = (const struct clk_hw*[]) {
1529 &disp_cc_mdss_esc0_clk_src.clkr.hw,
1530 },
1531 .num_parents = 1,
1532 .flags = CLK_SET_RATE_PARENT,
1533 .ops = &clk_branch2_ops,
1534 },
1535 },
1536 };
1537
1538 static struct clk_branch disp_cc_mdss_esc1_clk = {
1539 .halt_reg = 0x8048,
1540 .halt_check = BRANCH_HALT,
1541 .clkr = {
1542 .enable_reg = 0x8048,
1543 .enable_mask = BIT(0),
1544 .hw.init = &(const struct clk_init_data) {
1545 .name = "disp_cc_mdss_esc1_clk",
1546 .parent_hws = (const struct clk_hw*[]) {
1547 &disp_cc_mdss_esc1_clk_src.clkr.hw,
1548 },
1549 .num_parents = 1,
1550 .flags = CLK_SET_RATE_PARENT,
1551 .ops = &clk_branch2_ops,
1552 },
1553 },
1554 };
1555
1556 static struct clk_branch disp_cc_mdss_mdp1_clk = {
1557 .halt_reg = 0xa004,
1558 .halt_check = BRANCH_HALT,
1559 .clkr = {
1560 .enable_reg = 0xa004,
1561 .enable_mask = BIT(0),
1562 .hw.init = &(const struct clk_init_data) {
1563 .name = "disp_cc_mdss_mdp1_clk",
1564 .parent_hws = (const struct clk_hw*[]) {
1565 &disp_cc_mdss_mdp_clk_src.clkr.hw,
1566 },
1567 .num_parents = 1,
1568 .flags = CLK_SET_RATE_PARENT,
1569 .ops = &clk_branch2_ops,
1570 },
1571 },
1572 };
1573
1574 static struct clk_branch disp_cc_mdss_mdp_clk = {
1575 .halt_reg = 0x8010,
1576 .halt_check = BRANCH_HALT,
1577 .clkr = {
1578 .enable_reg = 0x8010,
1579 .enable_mask = BIT(0),
1580 .hw.init = &(const struct clk_init_data) {
1581 .name = "disp_cc_mdss_mdp_clk",
1582 .parent_hws = (const struct clk_hw*[]) {
1583 &disp_cc_mdss_mdp_clk_src.clkr.hw,
1584 },
1585 .num_parents = 1,
1586 .flags = CLK_SET_RATE_PARENT,
1587 .ops = &clk_branch2_ops,
1588 },
1589 },
1590 };
1591
1592 static struct clk_branch disp_cc_mdss_mdp_lut1_clk = {
1593 .halt_reg = 0xa014,
1594 .halt_check = BRANCH_HALT_VOTED,
1595 .clkr = {
1596 .enable_reg = 0xa014,
1597 .enable_mask = BIT(0),
1598 .hw.init = &(const struct clk_init_data) {
1599 .name = "disp_cc_mdss_mdp_lut1_clk",
1600 .parent_hws = (const struct clk_hw*[]) {
1601 &disp_cc_mdss_mdp_clk_src.clkr.hw,
1602 },
1603 .num_parents = 1,
1604 .flags = CLK_SET_RATE_PARENT,
1605 .ops = &clk_branch2_ops,
1606 },
1607 },
1608 };
1609
1610 static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
1611 .halt_reg = 0x8020,
1612 .halt_check = BRANCH_HALT_VOTED,
1613 .clkr = {
1614 .enable_reg = 0x8020,
1615 .enable_mask = BIT(0),
1616 .hw.init = &(const struct clk_init_data) {
1617 .name = "disp_cc_mdss_mdp_lut_clk",
1618 .parent_hws = (const struct clk_hw*[]) {
1619 &disp_cc_mdss_mdp_clk_src.clkr.hw,
1620 },
1621 .num_parents = 1,
1622 .flags = CLK_SET_RATE_PARENT,
1623 .ops = &clk_branch2_ops,
1624 },
1625 },
1626 };
1627
1628 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
1629 .halt_reg = 0xc004,
1630 .halt_check = BRANCH_HALT_VOTED,
1631 .clkr = {
1632 .enable_reg = 0xc004,
1633 .enable_mask = BIT(0),
1634 .hw.init = &(const struct clk_init_data) {
1635 .name = "disp_cc_mdss_non_gdsc_ahb_clk",
1636 .parent_hws = (const struct clk_hw*[]) {
1637 &disp_cc_mdss_ahb_clk_src.clkr.hw,
1638 },
1639 .num_parents = 1,
1640 .flags = CLK_SET_RATE_PARENT,
1641 .ops = &clk_branch2_ops,
1642 },
1643 },
1644 };
1645
1646 static struct clk_branch disp_cc_mdss_pclk0_clk = {
1647 .halt_reg = 0x8004,
1648 .halt_check = BRANCH_HALT,
1649 .clkr = {
1650 .enable_reg = 0x8004,
1651 .enable_mask = BIT(0),
1652 .hw.init = &(const struct clk_init_data) {
1653 .name = "disp_cc_mdss_pclk0_clk",
1654 .parent_hws = (const struct clk_hw*[]) {
1655 &disp_cc_mdss_pclk0_clk_src.clkr.hw,
1656 },
1657 .num_parents = 1,
1658 .flags = CLK_SET_RATE_PARENT,
1659 .ops = &clk_branch2_ops,
1660 },
1661 },
1662 };
1663
1664 static struct clk_branch disp_cc_mdss_pclk1_clk = {
1665 .halt_reg = 0x8008,
1666 .halt_check = BRANCH_HALT,
1667 .clkr = {
1668 .enable_reg = 0x8008,
1669 .enable_mask = BIT(0),
1670 .hw.init = &(const struct clk_init_data) {
1671 .name = "disp_cc_mdss_pclk1_clk",
1672 .parent_hws = (const struct clk_hw*[]) {
1673 &disp_cc_mdss_pclk1_clk_src.clkr.hw,
1674 },
1675 .num_parents = 1,
1676 .flags = CLK_SET_RATE_PARENT,
1677 .ops = &clk_branch2_ops,
1678 },
1679 },
1680 };
1681
1682 static struct clk_branch disp_cc_mdss_pclk2_clk = {
1683 .halt_reg = 0x800c,
1684 .halt_check = BRANCH_HALT,
1685 .clkr = {
1686 .enable_reg = 0x800c,
1687 .enable_mask = BIT(0),
1688 .hw.init = &(const struct clk_init_data) {
1689 .name = "disp_cc_mdss_pclk2_clk",
1690 .parent_hws = (const struct clk_hw*[]) {
1691 &disp_cc_mdss_pclk2_clk_src.clkr.hw,
1692 },
1693 .num_parents = 1,
1694 .flags = CLK_SET_RATE_PARENT,
1695 .ops = &clk_branch2_ops,
1696 },
1697 },
1698 };
1699
1700 static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
1701 .halt_reg = 0xc00c,
1702 .halt_check = BRANCH_HALT,
1703 .clkr = {
1704 .enable_reg = 0xc00c,
1705 .enable_mask = BIT(0),
1706 .hw.init = &(const struct clk_init_data) {
1707 .name = "disp_cc_mdss_rscc_ahb_clk",
1708 .parent_hws = (const struct clk_hw*[]) {
1709 &disp_cc_mdss_ahb_clk_src.clkr.hw,
1710 },
1711 .num_parents = 1,
1712 .flags = CLK_SET_RATE_PARENT,
1713 .ops = &clk_branch2_ops,
1714 },
1715 },
1716 };
1717
1718 static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
1719 .halt_reg = 0xc008,
1720 .halt_check = BRANCH_HALT,
1721 .clkr = {
1722 .enable_reg = 0xc008,
1723 .enable_mask = BIT(0),
1724 .hw.init = &(const struct clk_init_data) {
1725 .name = "disp_cc_mdss_rscc_vsync_clk",
1726 .parent_hws = (const struct clk_hw*[]) {
1727 &disp_cc_mdss_vsync_clk_src.clkr.hw,
1728 },
1729 .num_parents = 1,
1730 .flags = CLK_SET_RATE_PARENT,
1731 .ops = &clk_branch2_ops,
1732 },
1733 },
1734 };
1735
1736 static struct clk_branch disp_cc_mdss_vsync1_clk = {
1737 .halt_reg = 0xa024,
1738 .halt_check = BRANCH_HALT,
1739 .clkr = {
1740 .enable_reg = 0xa024,
1741 .enable_mask = BIT(0),
1742 .hw.init = &(const struct clk_init_data) {
1743 .name = "disp_cc_mdss_vsync1_clk",
1744 .parent_hws = (const struct clk_hw*[]) {
1745 &disp_cc_mdss_vsync_clk_src.clkr.hw,
1746 },
1747 .num_parents = 1,
1748 .flags = CLK_SET_RATE_PARENT,
1749 .ops = &clk_branch2_ops,
1750 },
1751 },
1752 };
1753
1754 static struct clk_branch disp_cc_mdss_vsync_clk = {
1755 .halt_reg = 0x8030,
1756 .halt_check = BRANCH_HALT,
1757 .clkr = {
1758 .enable_reg = 0x8030,
1759 .enable_mask = BIT(0),
1760 .hw.init = &(const struct clk_init_data) {
1761 .name = "disp_cc_mdss_vsync_clk",
1762 .parent_hws = (const struct clk_hw*[]) {
1763 &disp_cc_mdss_vsync_clk_src.clkr.hw,
1764 },
1765 .num_parents = 1,
1766 .flags = CLK_SET_RATE_PARENT,
1767 .ops = &clk_branch2_ops,
1768 },
1769 },
1770 };
1771
1772 static struct clk_branch disp_cc_osc_clk = {
1773 .halt_reg = 0x80b4,
1774 .halt_check = BRANCH_HALT,
1775 .clkr = {
1776 .enable_reg = 0x80b4,
1777 .enable_mask = BIT(0),
1778 .hw.init = &(const struct clk_init_data) {
1779 .name = "disp_cc_osc_clk",
1780 .parent_hws = (const struct clk_hw*[]) {
1781 &disp_cc_osc_clk_src.clkr.hw,
1782 },
1783 .num_parents = 1,
1784 .flags = CLK_SET_RATE_PARENT,
1785 .ops = &clk_branch2_ops,
1786 },
1787 },
1788 };
1789
1790 static struct gdsc disp_cc_mdss_core_gdsc = {
1791 .gdscr = 0x9000,
1792 .en_rest_wait_val = 0x2,
1793 .en_few_wait_val = 0x2,
1794 .clk_dis_wait_val = 0xf,
1795 .pd = {
1796 .name = "disp_cc_mdss_core_gdsc",
1797 },
1798 .pwrsts = PWRSTS_OFF_ON,
1799 .flags = HW_CTRL | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
1800 };
1801
1802 static struct gdsc disp_cc_mdss_core_int2_gdsc = {
1803 .gdscr = 0xb000,
1804 .en_rest_wait_val = 0x2,
1805 .en_few_wait_val = 0x2,
1806 .clk_dis_wait_val = 0xf,
1807 .pd = {
1808 .name = "disp_cc_mdss_core_int2_gdsc",
1809 },
1810 .pwrsts = PWRSTS_OFF_ON,
1811 .flags = HW_CTRL | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
1812 };
1813
1814 static struct clk_regmap *disp_cc_glymur_clocks[] = {
1815 [DISP_CC_ESYNC0_CLK] = &disp_cc_esync0_clk.clkr,
1816 [DISP_CC_ESYNC0_CLK_SRC] = &disp_cc_esync0_clk_src.clkr,
1817 [DISP_CC_ESYNC1_CLK] = &disp_cc_esync1_clk.clkr,
1818 [DISP_CC_ESYNC1_CLK_SRC] = &disp_cc_esync1_clk_src.clkr,
1819 [DISP_CC_MDSS_ACCU_SHIFT_CLK] = &disp_cc_mdss_accu_shift_clk.clkr,
1820 [DISP_CC_MDSS_AHB1_CLK] = &disp_cc_mdss_ahb1_clk.clkr,
1821 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
1822 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
1823 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
1824 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
1825 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
1826 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
1827 [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr,
1828 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
1829 [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr,
1830 [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr,
1831 [DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp_cc_mdss_dptx0_aux_clk.clkr,
1832 [DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp_cc_mdss_dptx0_aux_clk_src.clkr,
1833 [DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp_cc_mdss_dptx0_link_clk.clkr,
1834 [DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp_cc_mdss_dptx0_link_clk_src.clkr,
1835 [DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx0_link_div_clk_src.clkr,
1836 [DISP_CC_MDSS_DPTX0_LINK_DPIN_CLK] = &disp_cc_mdss_dptx0_link_dpin_clk.clkr,
1837 [DISP_CC_MDSS_DPTX0_LINK_DPIN_DIV_CLK_SRC] = &disp_cc_mdss_dptx0_link_dpin_div_clk_src.clkr,
1838 [DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp_cc_mdss_dptx0_link_intf_clk.clkr,
1839 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp_cc_mdss_dptx0_pixel0_clk.clkr,
1840 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx0_pixel0_clk_src.clkr,
1841 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp_cc_mdss_dptx0_pixel1_clk.clkr,
1842 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx0_pixel1_clk_src.clkr,
1843 [DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] =
1844 &disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr,
1845 [DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp_cc_mdss_dptx1_aux_clk.clkr,
1846 [DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp_cc_mdss_dptx1_aux_clk_src.clkr,
1847 [DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp_cc_mdss_dptx1_link_clk.clkr,
1848 [DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp_cc_mdss_dptx1_link_clk_src.clkr,
1849 [DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx1_link_div_clk_src.clkr,
1850 [DISP_CC_MDSS_DPTX1_LINK_DPIN_CLK] = &disp_cc_mdss_dptx1_link_dpin_clk.clkr,
1851 [DISP_CC_MDSS_DPTX1_LINK_DPIN_DIV_CLK_SRC] = &disp_cc_mdss_dptx1_link_dpin_div_clk_src.clkr,
1852 [DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp_cc_mdss_dptx1_link_intf_clk.clkr,
1853 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp_cc_mdss_dptx1_pixel0_clk.clkr,
1854 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx1_pixel0_clk_src.clkr,
1855 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp_cc_mdss_dptx1_pixel1_clk.clkr,
1856 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx1_pixel1_clk_src.clkr,
1857 [DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] =
1858 &disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr,
1859 [DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp_cc_mdss_dptx2_aux_clk.clkr,
1860 [DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp_cc_mdss_dptx2_aux_clk_src.clkr,
1861 [DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp_cc_mdss_dptx2_link_clk.clkr,
1862 [DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp_cc_mdss_dptx2_link_clk_src.clkr,
1863 [DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx2_link_div_clk_src.clkr,
1864 [DISP_CC_MDSS_DPTX2_LINK_DPIN_CLK] = &disp_cc_mdss_dptx2_link_dpin_clk.clkr,
1865 [DISP_CC_MDSS_DPTX2_LINK_DPIN_DIV_CLK_SRC] = &disp_cc_mdss_dptx2_link_dpin_div_clk_src.clkr,
1866 [DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp_cc_mdss_dptx2_link_intf_clk.clkr,
1867 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp_cc_mdss_dptx2_pixel0_clk.clkr,
1868 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx2_pixel0_clk_src.clkr,
1869 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp_cc_mdss_dptx2_pixel1_clk.clkr,
1870 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx2_pixel1_clk_src.clkr,
1871 [DISP_CC_MDSS_DPTX2_USB_ROUTER_LINK_INTF_CLK] =
1872 &disp_cc_mdss_dptx2_usb_router_link_intf_clk.clkr,
1873 [DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp_cc_mdss_dptx3_aux_clk.clkr,
1874 [DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp_cc_mdss_dptx3_aux_clk_src.clkr,
1875 [DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp_cc_mdss_dptx3_link_clk.clkr,
1876 [DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp_cc_mdss_dptx3_link_clk_src.clkr,
1877 [DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx3_link_div_clk_src.clkr,
1878 [DISP_CC_MDSS_DPTX3_LINK_DPIN_CLK] = &disp_cc_mdss_dptx3_link_dpin_clk.clkr,
1879 [DISP_CC_MDSS_DPTX3_LINK_DPIN_DIV_CLK_SRC] = &disp_cc_mdss_dptx3_link_dpin_div_clk_src.clkr,
1880 [DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp_cc_mdss_dptx3_link_intf_clk.clkr,
1881 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp_cc_mdss_dptx3_pixel0_clk.clkr,
1882 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx3_pixel0_clk_src.clkr,
1883 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
1884 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
1885 [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr,
1886 [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr,
1887 [DISP_CC_MDSS_MDP1_CLK] = &disp_cc_mdss_mdp1_clk.clkr,
1888 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
1889 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
1890 [DISP_CC_MDSS_MDP_LUT1_CLK] = &disp_cc_mdss_mdp_lut1_clk.clkr,
1891 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
1892 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
1893 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
1894 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
1895 [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr,
1896 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr,
1897 [DISP_CC_MDSS_PCLK2_CLK] = &disp_cc_mdss_pclk2_clk.clkr,
1898 [DISP_CC_MDSS_PCLK2_CLK_SRC] = &disp_cc_mdss_pclk2_clk_src.clkr,
1899 [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
1900 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
1901 [DISP_CC_MDSS_VSYNC1_CLK] = &disp_cc_mdss_vsync1_clk.clkr,
1902 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
1903 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
1904 [DISP_CC_OSC_CLK] = &disp_cc_osc_clk.clkr,
1905 [DISP_CC_OSC_CLK_SRC] = &disp_cc_osc_clk_src.clkr,
1906 [DISP_CC_PLL0] = &disp_cc_pll0.clkr,
1907 [DISP_CC_PLL1] = &disp_cc_pll1.clkr,
1908 [DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr,
1909 [DISP_CC_XO_CLK_SRC] = &disp_cc_xo_clk_src.clkr,
1910 };
1911
1912 static struct gdsc *disp_cc_glymur_gdscs[] = {
1913 [DISP_CC_MDSS_CORE_GDSC] = &disp_cc_mdss_core_gdsc,
1914 [DISP_CC_MDSS_CORE_INT2_GDSC] = &disp_cc_mdss_core_int2_gdsc,
1915 };
1916
1917 static const struct qcom_reset_map disp_cc_glymur_resets[] = {
1918 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
1919 [DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },
1920 [DISP_CC_MDSS_RSCC_BCR] = { 0xc000 },
1921 };
1922
1923 static struct clk_alpha_pll *disp_cc_glymur_plls[] = {
1924 &disp_cc_pll0,
1925 &disp_cc_pll1,
1926 };
1927
1928 static u32 disp_cc_glymur_critical_cbcrs[] = {
1929 0xe07c, /* DISP_CC_SLEEP_CLK */
1930 0xe05c, /* DISP_CC_XO_CLK */
1931 };
1932
1933 static const struct regmap_config disp_cc_glymur_regmap_config = {
1934 .reg_bits = 32,
1935 .reg_stride = 4,
1936 .val_bits = 32,
1937 .max_register = 0x11014,
1938 .fast_io = true,
1939 };
1940
1941 static struct qcom_cc_driver_data disp_cc_glymur_driver_data = {
1942 .alpha_plls = disp_cc_glymur_plls,
1943 .num_alpha_plls = ARRAY_SIZE(disp_cc_glymur_plls),
1944 .clk_cbcrs = disp_cc_glymur_critical_cbcrs,
1945 .num_clk_cbcrs = ARRAY_SIZE(disp_cc_glymur_critical_cbcrs),
1946 };
1947
1948 static const struct qcom_cc_desc disp_cc_glymur_desc = {
1949 .config = &disp_cc_glymur_regmap_config,
1950 .clks = disp_cc_glymur_clocks,
1951 .num_clks = ARRAY_SIZE(disp_cc_glymur_clocks),
1952 .resets = disp_cc_glymur_resets,
1953 .num_resets = ARRAY_SIZE(disp_cc_glymur_resets),
1954 .gdscs = disp_cc_glymur_gdscs,
1955 .num_gdscs = ARRAY_SIZE(disp_cc_glymur_gdscs),
1956 .use_rpm = true,
1957 .driver_data = &disp_cc_glymur_driver_data,
1958 };
1959
1960 static const struct of_device_id disp_cc_glymur_match_table[] = {
1961 { .compatible = "qcom,glymur-dispcc" },
1962 { }
1963 };
1964 MODULE_DEVICE_TABLE(of, disp_cc_glymur_match_table);
1965
disp_cc_glymur_probe(struct platform_device * pdev)1966 static int disp_cc_glymur_probe(struct platform_device *pdev)
1967 {
1968 return qcom_cc_probe(pdev, &disp_cc_glymur_desc);
1969 }
1970
1971 static struct platform_driver disp_cc_glymur_driver = {
1972 .probe = disp_cc_glymur_probe,
1973 .driver = {
1974 .name = "dispcc-glymur",
1975 .of_match_table = disp_cc_glymur_match_table,
1976 },
1977 };
1978
1979 module_platform_driver(disp_cc_glymur_driver);
1980
1981 MODULE_DESCRIPTION("QTI DISPCC GLYMUR Driver");
1982 MODULE_LICENSE("GPL");
1983