1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_HW_SEQUENCER_PRIVATE_H__ 27 #define __DC_HW_SEQUENCER_PRIVATE_H__ 28 29 #include "dc_types.h" 30 31 enum pipe_gating_control { 32 PIPE_GATING_CONTROL_DISABLE = 0, 33 PIPE_GATING_CONTROL_ENABLE, 34 PIPE_GATING_CONTROL_INIT 35 }; 36 37 struct dce_hwseq_wa { 38 bool blnd_crtc_trigger; 39 bool DEGVIDCN10_253; 40 bool false_optc_underflow; 41 bool DEGVIDCN10_254; 42 bool DEGVIDCN21; 43 bool disallow_self_refresh_during_multi_plane_transition; 44 bool dp_hpo_and_otg_sequence; 45 bool wait_hubpret_read_start_during_mpo_transition; 46 }; 47 48 struct hwseq_wa_state { 49 bool DEGVIDCN10_253_applied; 50 bool disallow_self_refresh_during_multi_plane_transition_applied; 51 unsigned int disallow_self_refresh_during_multi_plane_transition_applied_on_frame; 52 bool skip_blank_stream; 53 }; 54 55 struct pipe_ctx; 56 struct dc_state; 57 struct dc_stream_status; 58 struct dc_writeback_info; 59 struct dchub_init_data; 60 struct dc_static_screen_params; 61 struct resource_pool; 62 struct resource_context; 63 struct stream_resource; 64 struct dc_phy_addr_space_config; 65 struct dc_virtual_addr_space_config; 66 struct hubp; 67 struct dpp; 68 struct dce_hwseq; 69 struct timing_generator; 70 struct tg_color; 71 struct output_pixel_processor; 72 struct mpcc_blnd_cfg; 73 74 struct hwseq_private_funcs { 75 76 void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx); 77 void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx); 78 void (*init_pipes)(struct dc *dc, struct dc_state *context); 79 void (*reset_hw_ctx_wrap)(struct dc *dc, struct dc_state *context); 80 void (*plane_atomic_disconnect)(struct dc *dc, 81 struct dc_state *state, 82 struct pipe_ctx *pipe_ctx); 83 void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx); 84 bool (*set_input_transfer_func)(struct dc *dc, 85 struct pipe_ctx *pipe_ctx, 86 const struct dc_plane_state *plane_state); 87 bool (*set_output_transfer_func)(struct dc *dc, 88 struct pipe_ctx *pipe_ctx, 89 const struct dc_stream_state *stream); 90 void (*power_down)(struct dc *dc); 91 void (*enable_display_pipe_clock_gating)(struct dc_context *ctx, 92 bool clock_gating); 93 bool (*enable_display_power_gating)(struct dc *dc, 94 uint8_t controller_id, 95 struct dc_bios *dcb, 96 enum pipe_gating_control power_gating); 97 void (*blank_pixel_data)(struct dc *dc, 98 struct pipe_ctx *pipe_ctx, 99 bool blank); 100 enum dc_status (*enable_stream_timing)( 101 struct pipe_ctx *pipe_ctx, 102 struct dc_state *context, 103 struct dc *dc); 104 void (*edp_backlight_control)(struct dc_link *link, 105 bool enable); 106 void (*setup_vupdate_interrupt)(struct dc *dc, 107 struct pipe_ctx *pipe_ctx); 108 bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx); 109 void (*init_blank)(struct dc *dc, struct timing_generator *tg); 110 void (*disable_vga)(struct dce_hwseq *hws); 111 void (*bios_golden_init)(struct dc *dc); 112 void (*plane_atomic_power_down)(struct dc *dc, 113 struct dpp *dpp, 114 struct hubp *hubp); 115 void (*plane_atomic_disable)(struct dc *dc, struct pipe_ctx *pipe_ctx); 116 void (*enable_power_gating_plane)(struct dce_hwseq *hws, 117 bool enable); 118 void (*dpp_root_clock_control)( 119 struct dce_hwseq *hws, 120 unsigned int dpp_inst, 121 bool clock_on); 122 void (*dpstream_root_clock_control)( 123 struct dce_hwseq *hws, 124 unsigned int dpp_inst, 125 bool clock_on); 126 void (*physymclk_root_clock_control)( 127 struct dce_hwseq *hws, 128 unsigned int phy_inst, 129 bool clock_on); 130 void (*dpp_pg_control)(struct dce_hwseq *hws, 131 unsigned int dpp_inst, 132 bool power_on); 133 void (*hubp_pg_control)(struct dce_hwseq *hws, 134 unsigned int hubp_inst, 135 bool power_on); 136 void (*dsc_pg_control)(struct dce_hwseq *hws, 137 unsigned int dsc_inst, 138 bool power_on); 139 bool (*dsc_pg_status)(struct dce_hwseq *hws, 140 unsigned int dsc_inst); 141 void (*update_odm)(struct dc *dc, struct dc_state *context, 142 struct pipe_ctx *pipe_ctx); 143 void (*program_all_writeback_pipes_in_tree)(struct dc *dc, 144 const struct dc_stream_state *stream, 145 struct dc_state *context); 146 bool (*s0i3_golden_init_wa)(struct dc *dc); 147 void (*set_hdr_multiplier)(struct pipe_ctx *pipe_ctx); 148 void (*verify_allow_pstate_change_high)(struct dc *dc); 149 void (*program_pipe)(struct dc *dc, 150 struct pipe_ctx *pipe_ctx, 151 struct dc_state *context); 152 bool (*wait_for_blank_complete)(struct output_pixel_processor *opp); 153 void (*dccg_init)(struct dce_hwseq *hws); 154 bool (*set_blend_lut)(struct pipe_ctx *pipe_ctx, 155 const struct dc_plane_state *plane_state); 156 bool (*set_shaper_3dlut)(struct pipe_ctx *pipe_ctx, 157 const struct dc_plane_state *plane_state); 158 bool (*set_mcm_luts)(struct pipe_ctx *pipe_ctx, 159 const struct dc_plane_state *plane_state); 160 void (*PLAT_58856_wa)(struct dc_state *context, 161 struct pipe_ctx *pipe_ctx); 162 void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable); 163 void (*enable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx, 164 struct dc_state *context); 165 void (*program_mall_pipe_config)(struct dc *dc, struct dc_state *context); 166 void (*update_force_pstate)(struct dc *dc, struct dc_state *context); 167 void (*update_mall_sel)(struct dc *dc, struct dc_state *context); 168 unsigned int (*calculate_dccg_k1_k2_values)(struct pipe_ctx *pipe_ctx, 169 unsigned int *k1_div, 170 unsigned int *k2_div); 171 void (*resync_fifo_dccg_dio)(struct dce_hwseq *hws, struct dc *dc, 172 struct dc_state *context, 173 unsigned int current_pipe_idx); 174 enum dc_status (*apply_single_controller_ctx_to_hw)( 175 struct pipe_ctx *pipe_ctx, 176 struct dc_state *context, 177 struct dc *dc); 178 bool (*is_dp_dig_pixel_rate_div_policy)(struct pipe_ctx *pipe_ctx); 179 void (*reset_back_end_for_pipe)(struct dc *dc, 180 struct pipe_ctx *pipe_ctx, 181 struct dc_state *context); 182 void (*populate_mcm_luts)(struct dc *dc, 183 struct pipe_ctx *pipe_ctx, 184 struct dc_cm2_func_luts mcm_luts, 185 bool lut_bank_a); 186 void (*perform_3dlut_wa_unlock)(struct pipe_ctx *pipe_ctx); 187 void (*wait_for_pipe_update_if_needed)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool is_surface_update_only); 188 void (*set_wait_for_update_needed_for_pipe)(struct dc *dc, struct pipe_ctx *pipe_ctx); 189 }; 190 191 struct dce_hwseq { 192 struct dc_context *ctx; 193 const struct dce_hwseq_registers *regs; 194 const struct dce_hwseq_shift *shifts; 195 const struct dce_hwseq_mask *masks; 196 struct dce_hwseq_wa wa; 197 struct hwseq_wa_state wa_state; 198 struct hwseq_private_funcs funcs; 199 200 PHYSICAL_ADDRESS_LOC fb_base; 201 PHYSICAL_ADDRESS_LOC fb_top; 202 PHYSICAL_ADDRESS_LOC fb_offset; 203 PHYSICAL_ADDRESS_LOC uma_top; 204 }; 205 206 #endif /* __DC_HW_SEQUENCER_PRIVATE_H__ */ 207