1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2017, 2019, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/clk.h>
7 #include <linux/delay.h>
8 #include <linux/err.h>
9 #include <linux/io.h>
10 #include <linux/kernel.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/module.h>
13 #include <linux/nvmem-consumer.h>
14 #include <linux/of.h>
15 #include <linux/phy/phy.h>
16 #include <linux/platform_device.h>
17 #include <linux/regmap.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/reset.h>
20 #include <linux/slab.h>
21
22 #include <dt-bindings/phy/phy-qcom-qusb2.h>
23
24 #define QUSB2PHY_PLL 0x0
25 #define QUSB2PHY_PLL_TEST 0x04
26 #define CLK_REF_SEL BIT(7)
27
28 #define QUSB2PHY_PLL_TUNE 0x08
29 #define QUSB2PHY_PLL_USER_CTL1 0x0c
30 #define QUSB2PHY_PLL_USER_CTL2 0x10
31 #define QUSB2PHY_PLL_AUTOPGM_CTL1 0x1c
32 #define QUSB2PHY_PLL_PWR_CTRL 0x18
33
34 /* QUSB2PHY_PLL_STATUS register bits */
35 #define PLL_LOCKED BIT(5)
36
37 /* QUSB2PHY_PLL_COMMON_STATUS_ONE register bits */
38 #define CORE_READY_STATUS BIT(0)
39
40 /* QUSB2PHY_PORT_POWERDOWN register bits */
41 #define CLAMP_N_EN BIT(5)
42 #define FREEZIO_N BIT(1)
43 #define POWER_DOWN BIT(0)
44
45 /* QUSB2PHY_PWR_CTRL1 register bits */
46 #define PWR_CTRL1_VREF_SUPPLY_TRIM BIT(5)
47 #define PWR_CTRL1_CLAMP_N_EN BIT(1)
48
49 #define QUSB2PHY_REFCLK_ENABLE BIT(0)
50
51 #define PHY_CLK_SCHEME_SEL BIT(0)
52
53 /* QUSB2PHY_INTR_CTRL register bits */
54 #define DMSE_INTR_HIGH_SEL BIT(4)
55 #define DPSE_INTR_HIGH_SEL BIT(3)
56 #define CHG_DET_INTR_EN BIT(2)
57 #define DMSE_INTR_EN BIT(1)
58 #define DPSE_INTR_EN BIT(0)
59
60 /* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE register bits */
61 #define CORE_PLL_EN_FROM_RESET BIT(4)
62 #define CORE_RESET BIT(5)
63 #define CORE_RESET_MUX BIT(6)
64
65 /* QUSB2PHY_IMP_CTRL1 register bits */
66 #define IMP_RES_OFFSET_MASK GENMASK(5, 0)
67 #define IMP_RES_OFFSET_SHIFT 0x0
68
69 /* QUSB2PHY_PLL_BIAS_CONTROL_2 register bits */
70 #define BIAS_CTRL2_RES_OFFSET_MASK GENMASK(5, 0)
71 #define BIAS_CTRL2_RES_OFFSET_SHIFT 0x0
72
73 /* QUSB2PHY_CHG_CONTROL_2 register bits */
74 #define CHG_CTRL2_OFFSET_MASK GENMASK(5, 4)
75 #define CHG_CTRL2_OFFSET_SHIFT 0x4
76
77 /* QUSB2PHY_PORT_TUNE1 register bits */
78 #define HSTX_TRIM_MASK GENMASK(7, 4)
79 #define HSTX_TRIM_SHIFT 0x4
80 #define PREEMPH_WIDTH_HALF_BIT BIT(2)
81 #define PREEMPHASIS_EN_MASK GENMASK(1, 0)
82 #define PREEMPHASIS_EN_SHIFT 0x0
83
84 /* QUSB2PHY_PORT_TUNE2 register bits */
85 #define HSDISC_TRIM_MASK GENMASK(1, 0)
86 #define HSDISC_TRIM_SHIFT 0x0
87
88 #define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x04
89 #define QUSB2PHY_PLL_CLOCK_INVERTERS 0x18c
90 #define QUSB2PHY_PLL_CMODE 0x2c
91 #define QUSB2PHY_PLL_LOCK_DELAY 0x184
92 #define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0xb4
93 #define QUSB2PHY_PLL_BIAS_CONTROL_1 0x194
94 #define QUSB2PHY_PLL_BIAS_CONTROL_2 0x198
95 #define QUSB2PHY_PWR_CTRL2 0x214
96 #define QUSB2PHY_IMP_CTRL1 0x220
97 #define QUSB2PHY_IMP_CTRL2 0x224
98 #define QUSB2PHY_CHG_CTRL2 0x23c
99
100 struct qusb2_phy_init_tbl {
101 unsigned int offset;
102 unsigned int val;
103 /*
104 * register part of layout ?
105 * if yes, then offset gives index in the reg-layout
106 */
107 int in_layout;
108 };
109
110 #define QUSB2_PHY_INIT_CFG(o, v) \
111 { \
112 .offset = o, \
113 .val = v, \
114 }
115
116 #define QUSB2_PHY_INIT_CFG_L(o, v) \
117 { \
118 .offset = o, \
119 .val = v, \
120 .in_layout = 1, \
121 }
122
123 /* set of registers with offsets different per-PHY */
124 enum qusb2phy_reg_layout {
125 QUSB2PHY_PLL_CORE_INPUT_OVERRIDE,
126 QUSB2PHY_PLL_STATUS,
127 QUSB2PHY_PORT_TUNE1,
128 QUSB2PHY_PORT_TUNE2,
129 QUSB2PHY_PORT_TUNE3,
130 QUSB2PHY_PORT_TUNE4,
131 QUSB2PHY_PORT_TUNE5,
132 QUSB2PHY_PORT_TEST1,
133 QUSB2PHY_PORT_TEST2,
134 QUSB2PHY_PORT_POWERDOWN,
135 QUSB2PHY_INTR_CTRL,
136 };
137
138 static const struct qusb2_phy_init_tbl ipq6018_init_tbl[] = {
139 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL, 0x14),
140 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xF8),
141 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xB3),
142 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83),
143 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xC0),
144 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
145 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
146 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
147 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x00),
148 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
149 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),
150 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TEST, 0x80),
151 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9F),
152 };
153
154 static const struct qusb2_phy_init_tbl qcs615_init_tbl[] = {
155 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xc8),
156 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3),
157 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83),
158 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xc0),
159 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
160 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
161 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
162 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),
163 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f),
164 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
165 };
166
167 static const unsigned int ipq6018_regs_layout[] = {
168 [QUSB2PHY_PLL_STATUS] = 0x38,
169 [QUSB2PHY_PORT_TUNE1] = 0x80,
170 [QUSB2PHY_PORT_TUNE2] = 0x84,
171 [QUSB2PHY_PORT_TUNE3] = 0x88,
172 [QUSB2PHY_PORT_TUNE4] = 0x8C,
173 [QUSB2PHY_PORT_TUNE5] = 0x90,
174 [QUSB2PHY_PORT_TEST1] = 0x98,
175 [QUSB2PHY_PORT_TEST2] = 0x9C,
176 [QUSB2PHY_PORT_POWERDOWN] = 0xB4,
177 [QUSB2PHY_INTR_CTRL] = 0xBC,
178 };
179
180 static const unsigned int msm8996_regs_layout[] = {
181 [QUSB2PHY_PLL_STATUS] = 0x38,
182 [QUSB2PHY_PORT_TUNE1] = 0x80,
183 [QUSB2PHY_PORT_TUNE2] = 0x84,
184 [QUSB2PHY_PORT_TUNE3] = 0x88,
185 [QUSB2PHY_PORT_TUNE4] = 0x8c,
186 [QUSB2PHY_PORT_TUNE5] = 0x90,
187 [QUSB2PHY_PORT_TEST1] = 0xb8,
188 [QUSB2PHY_PORT_TEST2] = 0x9c,
189 [QUSB2PHY_PORT_POWERDOWN] = 0xb4,
190 [QUSB2PHY_INTR_CTRL] = 0xbc,
191 };
192
193 static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = {
194 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8),
195 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3),
196 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83),
197 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xc0),
198
199 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
200 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
201 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
202
203 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),
204
205 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f),
206 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
207 };
208
209 static const unsigned int msm8998_regs_layout[] = {
210 [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8,
211 [QUSB2PHY_PLL_STATUS] = 0x1a0,
212 [QUSB2PHY_PORT_TUNE1] = 0x23c,
213 [QUSB2PHY_PORT_TUNE2] = 0x240,
214 [QUSB2PHY_PORT_TUNE3] = 0x244,
215 [QUSB2PHY_PORT_TUNE4] = 0x248,
216 [QUSB2PHY_PORT_TEST1] = 0x24c,
217 [QUSB2PHY_PORT_TEST2] = 0x250,
218 [QUSB2PHY_PORT_POWERDOWN] = 0x210,
219 [QUSB2PHY_INTR_CTRL] = 0x22c,
220 };
221
222 static const struct qusb2_phy_init_tbl msm8998_init_tbl[] = {
223 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x13),
224 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c),
225 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80),
226 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a),
227
228 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xa5),
229 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x09),
230
231 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19),
232 };
233
234 static const struct qusb2_phy_init_tbl sm6115_init_tbl[] = {
235 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8),
236 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x53),
237 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x81),
238 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x17),
239
240 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
241 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
242 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
243
244 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),
245
246 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f),
247 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
248 };
249
250 static const unsigned int qusb2_v2_regs_layout[] = {
251 [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8,
252 [QUSB2PHY_PLL_STATUS] = 0x1a0,
253 [QUSB2PHY_PORT_TUNE1] = 0x240,
254 [QUSB2PHY_PORT_TUNE2] = 0x244,
255 [QUSB2PHY_PORT_TUNE3] = 0x248,
256 [QUSB2PHY_PORT_TUNE4] = 0x24c,
257 [QUSB2PHY_PORT_TUNE5] = 0x250,
258 [QUSB2PHY_PORT_TEST1] = 0x254,
259 [QUSB2PHY_PORT_TEST2] = 0x258,
260 [QUSB2PHY_PORT_POWERDOWN] = 0x210,
261 [QUSB2PHY_INTR_CTRL] = 0x230,
262 };
263
264 static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] = {
265 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x03),
266 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c),
267 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80),
268 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a),
269 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19),
270 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_1, 0x40),
271 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_2, 0x20),
272 QUSB2_PHY_INIT_CFG(QUSB2PHY_PWR_CTRL2, 0x21),
273 QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL1, 0x0),
274 QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL2, 0x58),
275
276 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0x30),
277 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x29),
278 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0xca),
279 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x04),
280 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x03),
281
282 QUSB2_PHY_INIT_CFG(QUSB2PHY_CHG_CTRL2, 0x0),
283 };
284
285 struct qusb2_phy_cfg {
286 const struct qusb2_phy_init_tbl *tbl;
287 /* number of entries in the table */
288 unsigned int tbl_num;
289 /* offset to PHY_CLK_SCHEME register in TCSR map */
290 unsigned int clk_scheme_offset;
291
292 /* array of registers with different offsets */
293 const unsigned int *regs;
294 unsigned int mask_core_ready;
295 unsigned int disable_ctrl;
296 unsigned int autoresume_en;
297
298 /* true if PHY has PLL_TEST register to select clk_scheme */
299 bool has_pll_test;
300
301 /* true if TUNE1 register must be updated by fused value, else TUNE2 */
302 bool update_tune1_with_efuse;
303
304 /* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */
305 bool has_pll_override;
306
307 /* true if PHY default clk scheme is single-ended */
308 bool se_clk_scheme_default;
309 };
310
311 static const struct qusb2_phy_cfg msm8996_phy_cfg = {
312 .tbl = msm8996_init_tbl,
313 .tbl_num = ARRAY_SIZE(msm8996_init_tbl),
314 .regs = msm8996_regs_layout,
315
316 .has_pll_test = true,
317 .se_clk_scheme_default = true,
318 .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
319 .mask_core_ready = PLL_LOCKED,
320 .autoresume_en = BIT(3),
321 };
322
323 static const struct qusb2_phy_cfg msm8998_phy_cfg = {
324 .tbl = msm8998_init_tbl,
325 .tbl_num = ARRAY_SIZE(msm8998_init_tbl),
326 .regs = msm8998_regs_layout,
327
328 .disable_ctrl = POWER_DOWN,
329 .mask_core_ready = CORE_READY_STATUS,
330 .has_pll_override = true,
331 .se_clk_scheme_default = true,
332 .autoresume_en = BIT(0),
333 .update_tune1_with_efuse = true,
334 };
335
336 static const struct qusb2_phy_cfg ipq6018_phy_cfg = {
337 .tbl = ipq6018_init_tbl,
338 .tbl_num = ARRAY_SIZE(ipq6018_init_tbl),
339 .regs = ipq6018_regs_layout,
340
341 .disable_ctrl = POWER_DOWN,
342 .mask_core_ready = PLL_LOCKED,
343 /* autoresume not used */
344 .autoresume_en = BIT(0),
345 };
346
347 static const struct qusb2_phy_cfg qcs615_phy_cfg = {
348 .tbl = qcs615_init_tbl,
349 .tbl_num = ARRAY_SIZE(qcs615_init_tbl),
350 .regs = ipq6018_regs_layout,
351
352 .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
353 .mask_core_ready = PLL_LOCKED,
354 /* autoresume not used */
355 .autoresume_en = BIT(0),
356 };
357
358 static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
359 .tbl = qusb2_v2_init_tbl,
360 .tbl_num = ARRAY_SIZE(qusb2_v2_init_tbl),
361 .regs = qusb2_v2_regs_layout,
362
363 .disable_ctrl = (PWR_CTRL1_VREF_SUPPLY_TRIM | PWR_CTRL1_CLAMP_N_EN |
364 POWER_DOWN),
365 .mask_core_ready = CORE_READY_STATUS,
366 .has_pll_override = true,
367 .se_clk_scheme_default = true,
368 .autoresume_en = BIT(0),
369 .update_tune1_with_efuse = true,
370 };
371
372 static const struct qusb2_phy_cfg sdm660_phy_cfg = {
373 .tbl = msm8996_init_tbl,
374 .tbl_num = ARRAY_SIZE(msm8996_init_tbl),
375 .regs = msm8996_regs_layout,
376
377 .has_pll_test = true,
378 .se_clk_scheme_default = false,
379 .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
380 .mask_core_ready = PLL_LOCKED,
381 .autoresume_en = BIT(3),
382 };
383
384 static const struct qusb2_phy_cfg shikra_phy_cfg = {
385 .tbl = qcs615_init_tbl,
386 .tbl_num = ARRAY_SIZE(qcs615_init_tbl),
387 .regs = msm8996_regs_layout,
388
389 .has_pll_test = true,
390 .se_clk_scheme_default = true,
391 .disable_ctrl = CLAMP_N_EN | FREEZIO_N | POWER_DOWN,
392 .mask_core_ready = PLL_LOCKED,
393 };
394
395 static const struct qusb2_phy_cfg sm6115_phy_cfg = {
396 .tbl = sm6115_init_tbl,
397 .tbl_num = ARRAY_SIZE(sm6115_init_tbl),
398 .regs = msm8996_regs_layout,
399
400 .has_pll_test = true,
401 .se_clk_scheme_default = true,
402 .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
403 .mask_core_ready = PLL_LOCKED,
404 .autoresume_en = BIT(3),
405 };
406
407 static const char * const qusb2_phy_vreg_names[] = {
408 "vdd", "vdda-pll", "vdda-phy-dpdm",
409 };
410
411 #define QUSB2_NUM_VREGS ARRAY_SIZE(qusb2_phy_vreg_names)
412
413 /* struct override_param - structure holding qusb2 v2 phy overriding param
414 * set override true if the device tree property exists and read and assign
415 * to value
416 */
417 struct override_param {
418 bool override;
419 u8 value;
420 };
421
422 /*struct override_params - structure holding qusb2 v2 phy overriding params
423 * @imp_res_offset: rescode offset to be updated in IMP_CTRL1 register
424 * @hstx_trim: HSTX_TRIM to be updated in TUNE1 register
425 * @preemphasis: Amplitude Pre-Emphasis to be updated in TUNE1 register
426 * @preemphasis_width: half/full-width Pre-Emphasis updated via TUNE1
427 * @bias_ctrl: bias ctrl to be updated in BIAS_CONTROL_2 register
428 * @charge_ctrl: charge ctrl to be updated in CHG_CTRL2 register
429 * @hsdisc_trim: disconnect threshold to be updated in TUNE2 register
430 */
431 struct override_params {
432 struct override_param imp_res_offset;
433 struct override_param hstx_trim;
434 struct override_param preemphasis;
435 struct override_param preemphasis_width;
436 struct override_param bias_ctrl;
437 struct override_param charge_ctrl;
438 struct override_param hsdisc_trim;
439 };
440
441 /**
442 * struct qusb2_phy - structure holding qusb2 phy attributes
443 *
444 * @phy: generic phy
445 * @base: iomapped memory space for qubs2 phy
446 *
447 * @cfg_ahb_clk: AHB2PHY interface clock
448 * @ref_clk: phy reference clock
449 * @iface_clk: phy interface clock
450 * @phy_reset: phy reset control
451 * @vregs: regulator supplies bulk data
452 *
453 * @tcsr: TCSR syscon register map
454 * @cell: nvmem cell containing phy tuning value
455 *
456 * @overrides: pointer to structure for all overriding tuning params
457 *
458 * @cfg: phy config data
459 * @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme
460 * @phy_initialized: indicate if PHY has been initialized
461 * @mode: current PHY mode
462 */
463 struct qusb2_phy {
464 struct phy *phy;
465 void __iomem *base;
466
467 struct clk *cfg_ahb_clk;
468 struct clk *ref_clk;
469 struct clk *iface_clk;
470 struct reset_control *phy_reset;
471 struct regulator_bulk_data vregs[QUSB2_NUM_VREGS];
472
473 struct regmap *tcsr;
474 struct nvmem_cell *cell;
475
476 struct override_params overrides;
477
478 const struct qusb2_phy_cfg *cfg;
479 bool has_se_clk_scheme;
480 bool phy_initialized;
481 enum phy_mode mode;
482 };
483
qusb2_write_mask(void __iomem * base,u32 offset,u32 val,u32 mask)484 static inline void qusb2_write_mask(void __iomem *base, u32 offset,
485 u32 val, u32 mask)
486 {
487 u32 reg;
488
489 reg = readl(base + offset);
490 reg &= ~mask;
491 reg |= val & mask;
492 writel(reg, base + offset);
493
494 /* Ensure above write is completed */
495 readl(base + offset);
496 }
497
qusb2_setbits(void __iomem * base,u32 offset,u32 val)498 static inline void qusb2_setbits(void __iomem *base, u32 offset, u32 val)
499 {
500 u32 reg;
501
502 reg = readl(base + offset);
503 reg |= val;
504 writel(reg, base + offset);
505
506 /* Ensure above write is completed */
507 readl(base + offset);
508 }
509
qusb2_clrbits(void __iomem * base,u32 offset,u32 val)510 static inline void qusb2_clrbits(void __iomem *base, u32 offset, u32 val)
511 {
512 u32 reg;
513
514 reg = readl(base + offset);
515 reg &= ~val;
516 writel(reg, base + offset);
517
518 /* Ensure above write is completed */
519 readl(base + offset);
520 }
521
522 static inline
qcom_qusb2_phy_configure(void __iomem * base,const unsigned int * regs,const struct qusb2_phy_init_tbl tbl[],int num)523 void qcom_qusb2_phy_configure(void __iomem *base,
524 const unsigned int *regs,
525 const struct qusb2_phy_init_tbl tbl[], int num)
526 {
527 int i;
528
529 for (i = 0; i < num; i++) {
530 if (tbl[i].in_layout)
531 writel(tbl[i].val, base + regs[tbl[i].offset]);
532 else
533 writel(tbl[i].val, base + tbl[i].offset);
534 }
535 }
536
537 /*
538 * Update board specific PHY tuning override values if specified from
539 * device tree.
540 */
qusb2_phy_override_phy_params(struct qusb2_phy * qphy)541 static void qusb2_phy_override_phy_params(struct qusb2_phy *qphy)
542 {
543 const struct qusb2_phy_cfg *cfg = qphy->cfg;
544 struct override_params *or = &qphy->overrides;
545
546 if (or->imp_res_offset.override)
547 qusb2_write_mask(qphy->base, QUSB2PHY_IMP_CTRL1,
548 or->imp_res_offset.value << IMP_RES_OFFSET_SHIFT,
549 IMP_RES_OFFSET_MASK);
550
551 if (or->bias_ctrl.override)
552 qusb2_write_mask(qphy->base, QUSB2PHY_PLL_BIAS_CONTROL_2,
553 or->bias_ctrl.value << BIAS_CTRL2_RES_OFFSET_SHIFT,
554 BIAS_CTRL2_RES_OFFSET_MASK);
555
556 if (or->charge_ctrl.override)
557 qusb2_write_mask(qphy->base, QUSB2PHY_CHG_CTRL2,
558 or->charge_ctrl.value << CHG_CTRL2_OFFSET_SHIFT,
559 CHG_CTRL2_OFFSET_MASK);
560
561 if (or->hstx_trim.override)
562 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
563 or->hstx_trim.value << HSTX_TRIM_SHIFT,
564 HSTX_TRIM_MASK);
565
566 if (or->preemphasis.override)
567 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
568 or->preemphasis.value << PREEMPHASIS_EN_SHIFT,
569 PREEMPHASIS_EN_MASK);
570
571 if (or->preemphasis_width.override) {
572 if (or->preemphasis_width.value ==
573 QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT)
574 qusb2_setbits(qphy->base,
575 cfg->regs[QUSB2PHY_PORT_TUNE1],
576 PREEMPH_WIDTH_HALF_BIT);
577 else
578 qusb2_clrbits(qphy->base,
579 cfg->regs[QUSB2PHY_PORT_TUNE1],
580 PREEMPH_WIDTH_HALF_BIT);
581 }
582
583 if (or->hsdisc_trim.override)
584 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],
585 or->hsdisc_trim.value << HSDISC_TRIM_SHIFT,
586 HSDISC_TRIM_MASK);
587 }
588
589 /*
590 * Fetches HS Tx tuning value from nvmem and sets the
591 * QUSB2PHY_PORT_TUNE1/2 register.
592 * For error case, skip setting the value and use the default value.
593 */
qusb2_phy_set_tune2_param(struct qusb2_phy * qphy)594 static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)
595 {
596 struct device *dev = &qphy->phy->dev;
597 const struct qusb2_phy_cfg *cfg = qphy->cfg;
598 u8 *val, hstx_trim;
599
600 /* efuse register is optional */
601 if (!qphy->cell)
602 return;
603
604 /*
605 * Read efuse register having TUNE2/1 parameter's high nibble.
606 * If efuse register shows value as 0x0 (indicating value is not
607 * fused), or if we fail to find a valid efuse register setting,
608 * then use default value for high nibble that we have already
609 * set while configuring the phy.
610 */
611 val = nvmem_cell_read(qphy->cell, NULL);
612 if (IS_ERR(val)) {
613 dev_dbg(dev, "failed to read a valid hs-tx trim value\n");
614 return;
615 }
616 hstx_trim = val[0];
617 kfree(val);
618 if (!hstx_trim) {
619 dev_dbg(dev, "failed to read a valid hs-tx trim value\n");
620 return;
621 }
622
623 /* Fused TUNE1/2 value is the higher nibble only */
624 if (cfg->update_tune1_with_efuse)
625 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
626 hstx_trim << HSTX_TRIM_SHIFT, HSTX_TRIM_MASK);
627 else
628 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],
629 hstx_trim << HSTX_TRIM_SHIFT, HSTX_TRIM_MASK);
630 }
631
qusb2_phy_set_mode(struct phy * phy,enum phy_mode mode,int submode)632 static int qusb2_phy_set_mode(struct phy *phy,
633 enum phy_mode mode, int submode)
634 {
635 struct qusb2_phy *qphy = phy_get_drvdata(phy);
636
637 qphy->mode = mode;
638
639 return 0;
640 }
641
qusb2_phy_runtime_suspend(struct device * dev)642 static int __maybe_unused qusb2_phy_runtime_suspend(struct device *dev)
643 {
644 struct qusb2_phy *qphy = dev_get_drvdata(dev);
645 const struct qusb2_phy_cfg *cfg = qphy->cfg;
646 u32 intr_mask;
647
648 dev_vdbg(dev, "Suspending QUSB2 Phy, mode:%d\n", qphy->mode);
649
650 if (!qphy->phy_initialized) {
651 dev_vdbg(dev, "PHY not initialized, bailing out\n");
652 return 0;
653 }
654
655 /*
656 * Enable DP/DM interrupts to detect line state changes based on current
657 * speed. In other words, enable the triggers _opposite_ of what the
658 * current D+/D- levels are e.g. if currently D+ high, D- low
659 * (HS 'J'/Suspend), configure the mask to trigger on D+ low OR D- high
660 */
661 intr_mask = DPSE_INTR_EN | DMSE_INTR_EN;
662 switch (qphy->mode) {
663 case PHY_MODE_USB_HOST_HS:
664 case PHY_MODE_USB_HOST_FS:
665 case PHY_MODE_USB_DEVICE_HS:
666 case PHY_MODE_USB_DEVICE_FS:
667 intr_mask |= DMSE_INTR_HIGH_SEL;
668 break;
669 case PHY_MODE_USB_HOST_LS:
670 case PHY_MODE_USB_DEVICE_LS:
671 intr_mask |= DPSE_INTR_HIGH_SEL;
672 break;
673 default:
674 /* No device connected, enable both DP/DM high interrupt */
675 intr_mask |= DMSE_INTR_HIGH_SEL;
676 intr_mask |= DPSE_INTR_HIGH_SEL;
677 break;
678 }
679
680 writel(intr_mask, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);
681
682 /* hold core PLL into reset */
683 if (cfg->has_pll_override) {
684 qusb2_setbits(qphy->base,
685 cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE],
686 CORE_PLL_EN_FROM_RESET | CORE_RESET |
687 CORE_RESET_MUX);
688 }
689
690 /* enable phy auto-resume only if device is connected on bus */
691 if (qphy->mode != PHY_MODE_INVALID) {
692 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
693 cfg->autoresume_en);
694 /* Autoresume bit has to be toggled in order to enable it */
695 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
696 cfg->autoresume_en);
697 }
698
699 if (!qphy->has_se_clk_scheme)
700 clk_disable_unprepare(qphy->ref_clk);
701
702 clk_disable_unprepare(qphy->cfg_ahb_clk);
703 clk_disable_unprepare(qphy->iface_clk);
704
705 return 0;
706 }
707
qusb2_phy_runtime_resume(struct device * dev)708 static int __maybe_unused qusb2_phy_runtime_resume(struct device *dev)
709 {
710 struct qusb2_phy *qphy = dev_get_drvdata(dev);
711 const struct qusb2_phy_cfg *cfg = qphy->cfg;
712 int ret;
713
714 dev_vdbg(dev, "Resuming QUSB2 phy, mode:%d\n", qphy->mode);
715
716 if (!qphy->phy_initialized) {
717 dev_vdbg(dev, "PHY not initialized, bailing out\n");
718 return 0;
719 }
720
721 ret = clk_prepare_enable(qphy->iface_clk);
722 if (ret) {
723 dev_err(dev, "failed to enable iface_clk, %d\n", ret);
724 return ret;
725 }
726
727 ret = clk_prepare_enable(qphy->cfg_ahb_clk);
728 if (ret) {
729 dev_err(dev, "failed to enable cfg ahb clock, %d\n", ret);
730 goto disable_iface_clk;
731 }
732
733 if (!qphy->has_se_clk_scheme) {
734 ret = clk_prepare_enable(qphy->ref_clk);
735 if (ret) {
736 dev_err(dev, "failed to enable ref clk, %d\n", ret);
737 goto disable_ahb_clk;
738 }
739 }
740
741 writel(0x0, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);
742
743 /* bring core PLL out of reset */
744 if (cfg->has_pll_override) {
745 qusb2_clrbits(qphy->base,
746 cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE],
747 CORE_RESET | CORE_RESET_MUX);
748 }
749
750 return 0;
751
752 disable_ahb_clk:
753 clk_disable_unprepare(qphy->cfg_ahb_clk);
754 disable_iface_clk:
755 clk_disable_unprepare(qphy->iface_clk);
756
757 return ret;
758 }
759
qusb2_phy_init(struct phy * phy)760 static int qusb2_phy_init(struct phy *phy)
761 {
762 struct qusb2_phy *qphy = phy_get_drvdata(phy);
763 const struct qusb2_phy_cfg *cfg = qphy->cfg;
764 unsigned int val = 0;
765 unsigned int clk_scheme;
766 int ret;
767
768 dev_vdbg(&phy->dev, "%s(): Initializing QUSB2 phy\n", __func__);
769
770 /* turn on regulator supplies */
771 ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
772 if (ret)
773 return ret;
774
775 ret = clk_prepare_enable(qphy->iface_clk);
776 if (ret) {
777 dev_err(&phy->dev, "failed to enable iface_clk, %d\n", ret);
778 goto poweroff_phy;
779 }
780
781 /* enable ahb interface clock to program phy */
782 ret = clk_prepare_enable(qphy->cfg_ahb_clk);
783 if (ret) {
784 dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret);
785 goto disable_iface_clk;
786 }
787
788 /* Perform phy reset */
789 ret = reset_control_assert(qphy->phy_reset);
790 if (ret) {
791 dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret);
792 goto disable_ahb_clk;
793 }
794
795 /* 100 us delay to keep PHY in reset mode */
796 usleep_range(100, 150);
797
798 ret = reset_control_deassert(qphy->phy_reset);
799 if (ret) {
800 dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret);
801 goto disable_ahb_clk;
802 }
803
804 /* Disable the PHY */
805 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN],
806 qphy->cfg->disable_ctrl);
807
808 if (cfg->has_pll_test) {
809 /* save reset value to override reference clock scheme later */
810 val = readl(qphy->base + QUSB2PHY_PLL_TEST);
811 }
812
813 qcom_qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl,
814 cfg->tbl_num);
815
816 /* Override board specific PHY tuning values */
817 qusb2_phy_override_phy_params(qphy);
818
819 /* Set efuse value for tuning the PHY */
820 qusb2_phy_set_tune2_param(qphy);
821
822 /* Enable the PHY */
823 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN],
824 POWER_DOWN);
825
826 /* Required to get phy pll lock successfully */
827 usleep_range(150, 160);
828
829 /*
830 * Not all the SoCs have got a readable TCSR_PHY_CLK_SCHEME
831 * register in the TCSR so, if there's none, use the default
832 * value hardcoded in the configuration.
833 */
834 qphy->has_se_clk_scheme = cfg->se_clk_scheme_default;
835
836 /*
837 * read TCSR_PHY_CLK_SCHEME register to check if single-ended
838 * clock scheme is selected. If yes, then disable differential
839 * ref_clk and use single-ended clock, otherwise use differential
840 * ref_clk only.
841 */
842 if (qphy->tcsr) {
843 ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset,
844 &clk_scheme);
845 if (ret) {
846 dev_err(&phy->dev, "failed to read clk scheme reg\n");
847 goto assert_phy_reset;
848 }
849
850 /* is it a differential clock scheme ? */
851 if (!(clk_scheme & PHY_CLK_SCHEME_SEL)) {
852 dev_vdbg(&phy->dev, "%s(): select differential clk\n",
853 __func__);
854 qphy->has_se_clk_scheme = false;
855 } else {
856 dev_vdbg(&phy->dev, "%s(): select single-ended clk\n",
857 __func__);
858 }
859 }
860
861 if (!qphy->has_se_clk_scheme) {
862 ret = clk_prepare_enable(qphy->ref_clk);
863 if (ret) {
864 dev_err(&phy->dev, "failed to enable ref clk, %d\n",
865 ret);
866 goto assert_phy_reset;
867 }
868 }
869
870 if (cfg->has_pll_test) {
871 if (!qphy->has_se_clk_scheme)
872 val &= ~CLK_REF_SEL;
873 else
874 val |= CLK_REF_SEL;
875
876 writel(val, qphy->base + QUSB2PHY_PLL_TEST);
877
878 /* ensure above write is through */
879 readl(qphy->base + QUSB2PHY_PLL_TEST);
880 }
881
882 /* Required to get phy pll lock successfully */
883 usleep_range(100, 110);
884
885 val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]);
886 if (!(val & cfg->mask_core_ready)) {
887 dev_err(&phy->dev,
888 "QUSB2PHY pll lock failed: status reg = %x\n", val);
889 ret = -EBUSY;
890 goto disable_ref_clk;
891 }
892 qphy->phy_initialized = true;
893
894 return 0;
895
896 disable_ref_clk:
897 if (!qphy->has_se_clk_scheme)
898 clk_disable_unprepare(qphy->ref_clk);
899 assert_phy_reset:
900 reset_control_assert(qphy->phy_reset);
901 disable_ahb_clk:
902 clk_disable_unprepare(qphy->cfg_ahb_clk);
903 disable_iface_clk:
904 clk_disable_unprepare(qphy->iface_clk);
905 poweroff_phy:
906 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
907
908 return ret;
909 }
910
qusb2_phy_exit(struct phy * phy)911 static int qusb2_phy_exit(struct phy *phy)
912 {
913 struct qusb2_phy *qphy = phy_get_drvdata(phy);
914
915 /* Disable the PHY */
916 qusb2_setbits(qphy->base, qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN],
917 qphy->cfg->disable_ctrl);
918
919 if (!qphy->has_se_clk_scheme)
920 clk_disable_unprepare(qphy->ref_clk);
921
922 reset_control_assert(qphy->phy_reset);
923
924 clk_disable_unprepare(qphy->cfg_ahb_clk);
925 clk_disable_unprepare(qphy->iface_clk);
926
927 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
928
929 qphy->phy_initialized = false;
930
931 return 0;
932 }
933
934 static const struct phy_ops qusb2_phy_gen_ops = {
935 .init = qusb2_phy_init,
936 .exit = qusb2_phy_exit,
937 .set_mode = qusb2_phy_set_mode,
938 .owner = THIS_MODULE,
939 };
940
941 static const struct of_device_id qusb2_phy_of_match_table[] = {
942 {
943 .compatible = "qcom,ipq5424-qusb2-phy",
944 .data = &ipq6018_phy_cfg,
945 }, {
946 .compatible = "qcom,ipq6018-qusb2-phy",
947 .data = &ipq6018_phy_cfg,
948 }, {
949 .compatible = "qcom,ipq8074-qusb2-phy",
950 .data = &msm8996_phy_cfg,
951 }, {
952 .compatible = "qcom,ipq9574-qusb2-phy",
953 .data = &ipq6018_phy_cfg,
954 }, {
955 .compatible = "qcom,msm8953-qusb2-phy",
956 .data = &msm8996_phy_cfg,
957 }, {
958 .compatible = "qcom,msm8996-qusb2-phy",
959 .data = &msm8996_phy_cfg,
960 }, {
961 .compatible = "qcom,msm8998-qusb2-phy",
962 .data = &msm8998_phy_cfg,
963 }, {
964 .compatible = "qcom,qcs615-qusb2-phy",
965 .data = &qcs615_phy_cfg,
966 }, {
967 .compatible = "qcom,qcm2290-qusb2-phy",
968 .data = &sm6115_phy_cfg,
969 }, {
970 .compatible = "qcom,sdm660-qusb2-phy",
971 .data = &sdm660_phy_cfg,
972 }, {
973 .compatible = "qcom,shikra-qusb2-phy",
974 .data = &shikra_phy_cfg,
975 }, {
976 .compatible = "qcom,sm4250-qusb2-phy",
977 .data = &sm6115_phy_cfg,
978 }, {
979 .compatible = "qcom,sm6115-qusb2-phy",
980 .data = &sm6115_phy_cfg,
981 }, {
982 /*
983 * Deprecated. Only here to support legacy device
984 * trees that didn't include "qcom,qusb2-v2-phy"
985 */
986 .compatible = "qcom,sdm845-qusb2-phy",
987 .data = &qusb2_v2_phy_cfg,
988 }, {
989 .compatible = "qcom,qusb2-v2-phy",
990 .data = &qusb2_v2_phy_cfg,
991 },
992 { },
993 };
994 MODULE_DEVICE_TABLE(of, qusb2_phy_of_match_table);
995
996 static const struct dev_pm_ops qusb2_phy_pm_ops = {
997 SET_RUNTIME_PM_OPS(qusb2_phy_runtime_suspend,
998 qusb2_phy_runtime_resume, NULL)
999 };
1000
qusb2_phy_probe(struct platform_device * pdev)1001 static int qusb2_phy_probe(struct platform_device *pdev)
1002 {
1003 struct device *dev = &pdev->dev;
1004 struct qusb2_phy *qphy;
1005 struct phy_provider *phy_provider;
1006 struct phy *generic_phy;
1007 int ret, i;
1008 int num;
1009 u32 value;
1010 struct override_params *or;
1011
1012 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
1013 if (!qphy)
1014 return -ENOMEM;
1015 or = &qphy->overrides;
1016
1017 qphy->base = devm_platform_ioremap_resource(pdev, 0);
1018 if (IS_ERR(qphy->base))
1019 return PTR_ERR(qphy->base);
1020
1021 qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb");
1022 if (IS_ERR(qphy->cfg_ahb_clk))
1023 return dev_err_probe(dev, PTR_ERR(qphy->cfg_ahb_clk),
1024 "failed to get cfg ahb clk\n");
1025
1026 qphy->ref_clk = devm_clk_get(dev, "ref");
1027 if (IS_ERR(qphy->ref_clk))
1028 return dev_err_probe(dev, PTR_ERR(qphy->ref_clk),
1029 "failed to get ref clk\n");
1030
1031 qphy->iface_clk = devm_clk_get_optional(dev, "iface");
1032 if (IS_ERR(qphy->iface_clk))
1033 return PTR_ERR(qphy->iface_clk);
1034
1035 qphy->phy_reset = devm_reset_control_get_by_index(&pdev->dev, 0);
1036 if (IS_ERR(qphy->phy_reset)) {
1037 dev_err(dev, "failed to get phy core reset\n");
1038 return PTR_ERR(qphy->phy_reset);
1039 }
1040
1041 num = ARRAY_SIZE(qphy->vregs);
1042 for (i = 0; i < num; i++)
1043 qphy->vregs[i].supply = qusb2_phy_vreg_names[i];
1044
1045 ret = devm_regulator_bulk_get(dev, num, qphy->vregs);
1046 if (ret)
1047 return dev_err_probe(dev, ret,
1048 "failed to get regulator supplies\n");
1049
1050 /* Get the specific init parameters of QMP phy */
1051 qphy->cfg = of_device_get_match_data(dev);
1052
1053 qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node,
1054 "qcom,tcsr-syscon");
1055 if (IS_ERR(qphy->tcsr)) {
1056 dev_dbg(dev, "failed to lookup TCSR regmap\n");
1057 qphy->tcsr = NULL;
1058 }
1059
1060 qphy->cell = devm_nvmem_cell_get(dev, NULL);
1061 if (IS_ERR(qphy->cell)) {
1062 if (PTR_ERR(qphy->cell) == -EPROBE_DEFER)
1063 return -EPROBE_DEFER;
1064 qphy->cell = NULL;
1065 dev_dbg(dev, "failed to lookup tune2 hstx trim value\n");
1066 }
1067
1068 if (!of_property_read_u32(dev->of_node, "qcom,imp-res-offset-value",
1069 &value)) {
1070 or->imp_res_offset.value = (u8)value;
1071 or->imp_res_offset.override = true;
1072 }
1073
1074 if (!of_property_read_u32(dev->of_node, "qcom,bias-ctrl-value",
1075 &value)) {
1076 or->bias_ctrl.value = (u8)value;
1077 or->bias_ctrl.override = true;
1078 }
1079
1080 if (!of_property_read_u32(dev->of_node, "qcom,charge-ctrl-value",
1081 &value)) {
1082 or->charge_ctrl.value = (u8)value;
1083 or->charge_ctrl.override = true;
1084 }
1085
1086 if (!of_property_read_u32(dev->of_node, "qcom,hstx-trim-value",
1087 &value)) {
1088 or->hstx_trim.value = (u8)value;
1089 or->hstx_trim.override = true;
1090 }
1091
1092 if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-level",
1093 &value)) {
1094 or->preemphasis.value = (u8)value;
1095 or->preemphasis.override = true;
1096 }
1097
1098 if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-width",
1099 &value)) {
1100 or->preemphasis_width.value = (u8)value;
1101 or->preemphasis_width.override = true;
1102 }
1103
1104 if (!of_property_read_u32(dev->of_node, "qcom,hsdisc-trim-value",
1105 &value)) {
1106 or->hsdisc_trim.value = (u8)value;
1107 or->hsdisc_trim.override = true;
1108 }
1109
1110 dev_set_drvdata(dev, qphy);
1111
1112 /*
1113 * Enable runtime PM support, but forbid it by default.
1114 * Users can allow it again via the power/control attribute in sysfs.
1115 */
1116 pm_runtime_set_active(dev);
1117 pm_runtime_forbid(dev);
1118 ret = devm_pm_runtime_enable(dev);
1119 if (ret)
1120 return ret;
1121
1122 generic_phy = devm_phy_create(dev, NULL, &qusb2_phy_gen_ops);
1123 if (IS_ERR(generic_phy)) {
1124 ret = PTR_ERR(generic_phy);
1125 dev_err(dev, "failed to create phy, %d\n", ret);
1126 return ret;
1127 }
1128 qphy->phy = generic_phy;
1129
1130 phy_set_drvdata(generic_phy, qphy);
1131
1132 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1133
1134 return PTR_ERR_OR_ZERO(phy_provider);
1135 }
1136
1137 static struct platform_driver qusb2_phy_driver = {
1138 .probe = qusb2_phy_probe,
1139 .driver = {
1140 .name = "qcom-qusb2-phy",
1141 .pm = &qusb2_phy_pm_ops,
1142 .of_match_table = qusb2_phy_of_match_table,
1143 },
1144 };
1145
1146 module_platform_driver(qusb2_phy_driver);
1147
1148 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
1149 MODULE_DESCRIPTION("Qualcomm QUSB2 PHY driver");
1150 MODULE_LICENSE("GPL v2");
1151