1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * hal.c - DIM2 HAL implementation 4 * (MediaLB, Device Interface Macro IP, OS62420) 5 * 6 * Copyright (C) 2015-2016, Microchip Technology Germany II GmbH & Co. KG 7 */ 8 9 /* Author: Andrey Shvetsov <andrey.shvetsov@k2l.de> */ 10 11 #include "hal.h" 12 #include "errors.h" 13 #include "reg.h" 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 17 /* 18 * Size factor for isochronous DBR buffer. 19 * Minimal value is 3. 20 */ 21 #define ISOC_DBR_FACTOR 3u 22 23 /* 24 * Number of 32-bit units for DBR map. 25 * 26 * 1: block size is 512, max allocation is 16K 27 * 2: block size is 256, max allocation is 8K 28 * 4: block size is 128, max allocation is 4K 29 * 8: block size is 64, max allocation is 2K 30 * 31 * Min allocated space is block size. 32 * Max possible allocated space is 32 blocks. 33 */ 34 #define DBR_MAP_SIZE 2 35 36 /* -------------------------------------------------------------------------- */ 37 /* not configurable area */ 38 39 #define CDT 0x00 40 #define ADT 0x40 41 #define MLB_CAT 0x80 42 #define AHB_CAT 0x88 43 44 #define DBR_SIZE (16 * 1024) /* specified by IP */ 45 #define DBR_BLOCK_SIZE (DBR_SIZE / 32 / DBR_MAP_SIZE) 46 47 /* -------------------------------------------------------------------------- */ 48 /* generic helper functions and macros */ 49 50 static inline u32 bit_mask(u8 position) 51 { 52 return (u32)1 << position; 53 } 54 55 static inline bool dim_on_error(u8 error_id, const char *error_message) 56 { 57 dimcb_on_error(error_id, error_message); 58 return false; 59 } 60 61 /* -------------------------------------------------------------------------- */ 62 /* types and local variables */ 63 64 struct async_tx_dbr { 65 u8 ch_addr; 66 u16 rpc; 67 u16 wpc; 68 u16 rest_size; 69 u16 sz_queue[CDT0_RPC_MASK + 1]; 70 }; 71 72 struct lld_global_vars_t { 73 bool dim_is_initialized; 74 bool mcm_is_initialized; 75 struct dim2_regs __iomem *dim2; /* DIM2 core base address */ 76 struct async_tx_dbr atx_dbr; 77 u32 fcnt; 78 u32 dbr_map[DBR_MAP_SIZE]; 79 }; 80 81 static struct lld_global_vars_t g = { false }; 82 83 /* -------------------------------------------------------------------------- */ 84 85 static int dbr_get_mask_size(u16 size) 86 { 87 int i; 88 89 for (i = 0; i < 6; i++) 90 if (size <= (DBR_BLOCK_SIZE << i)) 91 return 1 << i; 92 return 0; 93 } 94 95 /** 96 * alloc_dbr() - Allocates DBR memory. 97 * @size: Allocating memory size. 98 * Returns: Offset in DBR memory by success or DBR_SIZE if out of memory. 99 */ 100 static int alloc_dbr(u16 size) 101 { 102 int mask_size; 103 int i, block_idx = 0; 104 105 if (size <= 0) 106 return DBR_SIZE; /* out of memory */ 107 108 mask_size = dbr_get_mask_size(size); 109 if (mask_size == 0) 110 return DBR_SIZE; /* out of memory */ 111 112 for (i = 0; i < DBR_MAP_SIZE; i++) { 113 u32 const blocks = DIV_ROUND_UP(size, DBR_BLOCK_SIZE); 114 u32 mask = ~((~(u32)0) << blocks); 115 116 do { 117 if ((g.dbr_map[i] & mask) == 0) { 118 g.dbr_map[i] |= mask; 119 return block_idx * DBR_BLOCK_SIZE; 120 } 121 block_idx += mask_size; 122 /* do shift left with 2 steps in case mask_size == 32 */ 123 mask <<= mask_size - 1; 124 } while ((mask <<= 1) != 0); 125 } 126 127 return DBR_SIZE; /* out of memory */ 128 } 129 130 static void free_dbr(int offs, int size) 131 { 132 int block_idx = offs / DBR_BLOCK_SIZE; 133 u32 const blocks = DIV_ROUND_UP(size, DBR_BLOCK_SIZE); 134 u32 mask = ~((~(u32)0) << blocks); 135 136 mask <<= block_idx % 32; 137 g.dbr_map[block_idx / 32] &= ~mask; 138 } 139 140 /* -------------------------------------------------------------------------- */ 141 142 static void dim2_transfer_madr(u32 val) 143 { 144 writel(val, &g.dim2->MADR); 145 146 /* wait for transfer completion */ 147 while ((readl(&g.dim2->MCTL) & 1) != 1) 148 continue; 149 150 writel(0, &g.dim2->MCTL); /* clear transfer complete */ 151 } 152 153 static void dim2_clear_dbr(u16 addr, u16 size) 154 { 155 enum { MADR_TB_BIT = 30, MADR_WNR_BIT = 31 }; 156 157 u16 const end_addr = addr + size; 158 u32 const cmd = bit_mask(MADR_WNR_BIT) | bit_mask(MADR_TB_BIT); 159 160 writel(0, &g.dim2->MCTL); /* clear transfer complete */ 161 writel(0, &g.dim2->MDAT0); 162 163 for (; addr < end_addr; addr++) 164 dim2_transfer_madr(cmd | addr); 165 } 166 167 static u32 dim2_read_ctr(u32 ctr_addr, u16 mdat_idx) 168 { 169 dim2_transfer_madr(ctr_addr); 170 171 return readl((&g.dim2->MDAT0) + mdat_idx); 172 } 173 174 static void dim2_write_ctr_mask(u32 ctr_addr, const u32 *mask, const u32 *value) 175 { 176 enum { MADR_WNR_BIT = 31 }; 177 178 writel(0, &g.dim2->MCTL); /* clear transfer complete */ 179 180 if (mask[0] != 0) 181 writel(value[0], &g.dim2->MDAT0); 182 if (mask[1] != 0) 183 writel(value[1], &g.dim2->MDAT1); 184 if (mask[2] != 0) 185 writel(value[2], &g.dim2->MDAT2); 186 if (mask[3] != 0) 187 writel(value[3], &g.dim2->MDAT3); 188 189 writel(mask[0], &g.dim2->MDWE0); 190 writel(mask[1], &g.dim2->MDWE1); 191 writel(mask[2], &g.dim2->MDWE2); 192 writel(mask[3], &g.dim2->MDWE3); 193 194 dim2_transfer_madr(bit_mask(MADR_WNR_BIT) | ctr_addr); 195 } 196 197 static inline void dim2_write_ctr(u32 ctr_addr, const u32 *value) 198 { 199 u32 const mask[4] = { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF }; 200 201 dim2_write_ctr_mask(ctr_addr, mask, value); 202 } 203 204 static inline void dim2_clear_ctr(u32 ctr_addr) 205 { 206 u32 const value[4] = { 0, 0, 0, 0 }; 207 208 dim2_write_ctr(ctr_addr, value); 209 } 210 211 static void dim2_configure_cat(u8 cat_base, u8 ch_addr, u8 ch_type, 212 bool read_not_write) 213 { 214 bool isoc_fce = ch_type == CAT_CT_VAL_ISOC; 215 bool sync_mfe = ch_type == CAT_CT_VAL_SYNC; 216 u16 const cat = 217 (read_not_write << CAT_RNW_BIT) | 218 (ch_type << CAT_CT_SHIFT) | 219 (ch_addr << CAT_CL_SHIFT) | 220 (isoc_fce << CAT_FCE_BIT) | 221 (sync_mfe << CAT_MFE_BIT) | 222 (false << CAT_MT_BIT) | 223 (true << CAT_CE_BIT); 224 u8 const ctr_addr = cat_base + ch_addr / 8; 225 u8 const idx = (ch_addr % 8) / 2; 226 u8 const shift = (ch_addr % 2) * 16; 227 u32 mask[4] = { 0, 0, 0, 0 }; 228 u32 value[4] = { 0, 0, 0, 0 }; 229 230 mask[idx] = (u32)0xFFFF << shift; 231 value[idx] = cat << shift; 232 dim2_write_ctr_mask(ctr_addr, mask, value); 233 } 234 235 static void dim2_clear_cat(u8 cat_base, u8 ch_addr) 236 { 237 u8 const ctr_addr = cat_base + ch_addr / 8; 238 u8 const idx = (ch_addr % 8) / 2; 239 u8 const shift = (ch_addr % 2) * 16; 240 u32 mask[4] = { 0, 0, 0, 0 }; 241 u32 value[4] = { 0, 0, 0, 0 }; 242 243 mask[idx] = (u32)0xFFFF << shift; 244 dim2_write_ctr_mask(ctr_addr, mask, value); 245 } 246 247 static void dim2_configure_cdt(u8 ch_addr, u16 dbr_address, u16 hw_buffer_size, 248 u16 packet_length) 249 { 250 u32 cdt[4] = { 0, 0, 0, 0 }; 251 252 if (packet_length) 253 cdt[1] = ((packet_length - 1) << CDT1_BS_ISOC_SHIFT); 254 255 cdt[3] = 256 ((hw_buffer_size - 1) << CDT3_BD_SHIFT) | 257 (dbr_address << CDT3_BA_SHIFT); 258 dim2_write_ctr(CDT + ch_addr, cdt); 259 } 260 261 static u16 dim2_rpc(u8 ch_addr) 262 { 263 u32 cdt0 = dim2_read_ctr(CDT + ch_addr, 0); 264 265 return (cdt0 >> CDT0_RPC_SHIFT) & CDT0_RPC_MASK; 266 } 267 268 static void dim2_clear_cdt(u8 ch_addr) 269 { 270 u32 cdt[4] = { 0, 0, 0, 0 }; 271 272 dim2_write_ctr(CDT + ch_addr, cdt); 273 } 274 275 static void dim2_configure_adt(u8 ch_addr) 276 { 277 u32 adt[4] = { 0, 0, 0, 0 }; 278 279 adt[0] = 280 (true << ADT0_CE_BIT) | 281 (true << ADT0_LE_BIT) | 282 (0 << ADT0_PG_BIT); 283 284 dim2_write_ctr(ADT + ch_addr, adt); 285 } 286 287 static void dim2_clear_adt(u8 ch_addr) 288 { 289 u32 adt[4] = { 0, 0, 0, 0 }; 290 291 dim2_write_ctr(ADT + ch_addr, adt); 292 } 293 294 static void dim2_start_ctrl_async(u8 ch_addr, u8 idx, u32 buf_addr, 295 u16 buffer_size) 296 { 297 u8 const shift = idx * 16; 298 299 u32 mask[4] = { 0, 0, 0, 0 }; 300 u32 adt[4] = { 0, 0, 0, 0 }; 301 302 mask[1] = 303 bit_mask(ADT1_PS_BIT + shift) | 304 bit_mask(ADT1_RDY_BIT + shift) | 305 (ADT1_CTRL_ASYNC_BD_MASK << (ADT1_BD_SHIFT + shift)); 306 adt[1] = 307 (true << (ADT1_PS_BIT + shift)) | 308 (true << (ADT1_RDY_BIT + shift)) | 309 ((buffer_size - 1) << (ADT1_BD_SHIFT + shift)); 310 311 mask[idx + 2] = 0xFFFFFFFF; 312 adt[idx + 2] = buf_addr; 313 314 dim2_write_ctr_mask(ADT + ch_addr, mask, adt); 315 } 316 317 static void dim2_start_isoc_sync(u8 ch_addr, u8 idx, u32 buf_addr, 318 u16 buffer_size) 319 { 320 u8 const shift = idx * 16; 321 322 u32 mask[4] = { 0, 0, 0, 0 }; 323 u32 adt[4] = { 0, 0, 0, 0 }; 324 325 mask[1] = 326 bit_mask(ADT1_RDY_BIT + shift) | 327 (ADT1_ISOC_SYNC_BD_MASK << (ADT1_BD_SHIFT + shift)); 328 adt[1] = 329 (true << (ADT1_RDY_BIT + shift)) | 330 ((buffer_size - 1) << (ADT1_BD_SHIFT + shift)); 331 332 mask[idx + 2] = 0xFFFFFFFF; 333 adt[idx + 2] = buf_addr; 334 335 dim2_write_ctr_mask(ADT + ch_addr, mask, adt); 336 } 337 338 static void dim2_clear_ctram(void) 339 { 340 u32 ctr_addr; 341 342 for (ctr_addr = 0; ctr_addr < 0x90; ctr_addr++) 343 dim2_clear_ctr(ctr_addr); 344 } 345 346 static void dim2_configure_channel(u8 ch_addr, u8 type, u8 is_tx, u16 dbr_address, 347 u16 hw_buffer_size, u16 packet_length) 348 { 349 dim2_configure_cdt(ch_addr, dbr_address, hw_buffer_size, packet_length); 350 dim2_configure_cat(MLB_CAT, ch_addr, type, is_tx ? 1 : 0); 351 352 dim2_configure_adt(ch_addr); 353 dim2_configure_cat(AHB_CAT, ch_addr, type, is_tx ? 0 : 1); 354 355 /* unmask interrupt for used channel, enable mlb_sys_int[0] interrupt */ 356 writel(readl(&g.dim2->ACMR0) | bit_mask(ch_addr), &g.dim2->ACMR0); 357 } 358 359 static void dim2_clear_channel(u8 ch_addr) 360 { 361 /* mask interrupt for used channel, disable mlb_sys_int[0] interrupt */ 362 writel(readl(&g.dim2->ACMR0) & ~bit_mask(ch_addr), &g.dim2->ACMR0); 363 364 dim2_clear_cat(AHB_CAT, ch_addr); 365 dim2_clear_adt(ch_addr); 366 367 dim2_clear_cat(MLB_CAT, ch_addr); 368 dim2_clear_cdt(ch_addr); 369 370 /* clear channel status bit */ 371 writel(bit_mask(ch_addr), &g.dim2->ACSR0); 372 } 373 374 /* -------------------------------------------------------------------------- */ 375 /* trace async tx dbr fill state */ 376 377 static inline u16 norm_pc(u16 pc) 378 { 379 return pc & CDT0_RPC_MASK; 380 } 381 382 static void dbrcnt_init(u8 ch_addr, u16 dbr_size) 383 { 384 g.atx_dbr.rest_size = dbr_size; 385 g.atx_dbr.rpc = dim2_rpc(ch_addr); 386 g.atx_dbr.wpc = g.atx_dbr.rpc; 387 } 388 389 static void dbrcnt_enq(int buf_sz) 390 { 391 g.atx_dbr.rest_size -= buf_sz; 392 g.atx_dbr.sz_queue[norm_pc(g.atx_dbr.wpc)] = buf_sz; 393 g.atx_dbr.wpc++; 394 } 395 396 u16 dim_dbr_space(struct dim_channel *ch) 397 { 398 u16 cur_rpc; 399 struct async_tx_dbr *dbr = &g.atx_dbr; 400 401 if (ch->addr != dbr->ch_addr) 402 return 0xFFFF; 403 404 cur_rpc = dim2_rpc(ch->addr); 405 406 while (norm_pc(dbr->rpc) != cur_rpc) { 407 dbr->rest_size += dbr->sz_queue[norm_pc(dbr->rpc)]; 408 dbr->rpc++; 409 } 410 411 if ((u16)(dbr->wpc - dbr->rpc) >= CDT0_RPC_MASK) 412 return 0; 413 414 return dbr->rest_size; 415 } 416 417 /* -------------------------------------------------------------------------- */ 418 /* channel state helpers */ 419 420 static void state_init(struct int_ch_state *state) 421 { 422 state->request_counter = 0; 423 state->service_counter = 0; 424 425 state->idx1 = 0; 426 state->idx2 = 0; 427 state->level = 0; 428 } 429 430 /* -------------------------------------------------------------------------- */ 431 /* macro helper functions */ 432 433 static inline bool check_channel_address(u32 ch_address) 434 { 435 return ch_address > 0 && (ch_address % 2) == 0 && 436 (ch_address / 2) <= (u32)CAT_CL_MASK; 437 } 438 439 static inline bool check_packet_length(u32 packet_length) 440 { 441 u16 const max_size = ((u16)CDT3_BD_ISOC_MASK + 1u) / ISOC_DBR_FACTOR; 442 443 if (packet_length <= 0) 444 return false; /* too small */ 445 446 if (packet_length > max_size) 447 return false; /* too big */ 448 449 if (packet_length - 1u > (u32)CDT1_BS_ISOC_MASK) 450 return false; /* too big */ 451 452 return true; 453 } 454 455 static inline bool check_bytes_per_frame(u32 bytes_per_frame) 456 { 457 u16 const bd_factor = g.fcnt + 2; 458 u16 const max_size = ((u16)CDT3_BD_MASK + 1u) >> bd_factor; 459 460 if (bytes_per_frame <= 0) 461 return false; /* too small */ 462 463 if (bytes_per_frame > max_size) 464 return false; /* too big */ 465 466 return true; 467 } 468 469 u16 dim_norm_ctrl_async_buffer_size(u16 buf_size) 470 { 471 u16 const max_size = (u16)ADT1_CTRL_ASYNC_BD_MASK + 1u; 472 473 if (buf_size > max_size) 474 return max_size; 475 476 return buf_size; 477 } 478 479 static inline u16 norm_isoc_buffer_size(u16 buf_size, u16 packet_length) 480 { 481 u16 n; 482 u16 const max_size = (u16)ADT1_ISOC_SYNC_BD_MASK + 1u; 483 484 if (buf_size > max_size) 485 buf_size = max_size; 486 487 n = buf_size / packet_length; 488 489 if (n < 2u) 490 return 0; /* too small buffer for given packet_length */ 491 492 return packet_length * n; 493 } 494 495 static inline u16 norm_sync_buffer_size(u16 buf_size, u16 bytes_per_frame) 496 { 497 u16 n; 498 u16 const max_size = (u16)ADT1_ISOC_SYNC_BD_MASK + 1u; 499 u32 const unit = bytes_per_frame << g.fcnt; 500 501 if (buf_size > max_size) 502 buf_size = max_size; 503 504 n = buf_size / unit; 505 506 if (n < 1u) 507 return 0; /* too small buffer for given bytes_per_frame */ 508 509 return unit * n; 510 } 511 512 static void dim2_cleanup(void) 513 { 514 /* disable MediaLB */ 515 writel(false << MLBC0_MLBEN_BIT, &g.dim2->MLBC0); 516 517 dim2_clear_ctram(); 518 519 /* disable mlb_int interrupt */ 520 writel(0, &g.dim2->MIEN); 521 522 /* clear status for all dma channels */ 523 writel(0xFFFFFFFF, &g.dim2->ACSR0); 524 writel(0xFFFFFFFF, &g.dim2->ACSR1); 525 526 /* mask interrupts for all channels */ 527 writel(0, &g.dim2->ACMR0); 528 writel(0, &g.dim2->ACMR1); 529 } 530 531 static void dim2_initialize(bool enable_6pin, u8 mlb_clock) 532 { 533 dim2_cleanup(); 534 535 /* configure and enable MediaLB */ 536 writel(enable_6pin << MLBC0_MLBPEN_BIT | 537 mlb_clock << MLBC0_MLBCLK_SHIFT | 538 g.fcnt << MLBC0_FCNT_SHIFT | 539 true << MLBC0_MLBEN_BIT, 540 &g.dim2->MLBC0); 541 542 /* activate all HBI channels */ 543 writel(0xFFFFFFFF, &g.dim2->HCMR0); 544 writel(0xFFFFFFFF, &g.dim2->HCMR1); 545 546 /* enable HBI */ 547 writel(bit_mask(HCTL_EN_BIT), &g.dim2->HCTL); 548 549 /* configure DMA */ 550 writel(ACTL_DMA_MODE_VAL_DMA_MODE_1 << ACTL_DMA_MODE_BIT | 551 true << ACTL_SCE_BIT, &g.dim2->ACTL); 552 } 553 554 static bool dim2_is_mlb_locked(void) 555 { 556 u32 const mask0 = bit_mask(MLBC0_MLBLK_BIT); 557 u32 const mask1 = bit_mask(MLBC1_CLKMERR_BIT) | 558 bit_mask(MLBC1_LOCKERR_BIT); 559 u32 const c1 = readl(&g.dim2->MLBC1); 560 u32 const nda_mask = (u32)MLBC1_NDA_MASK << MLBC1_NDA_SHIFT; 561 562 writel(c1 & nda_mask, &g.dim2->MLBC1); 563 return (readl(&g.dim2->MLBC1) & mask1) == 0 && 564 (readl(&g.dim2->MLBC0) & mask0) != 0; 565 } 566 567 /* -------------------------------------------------------------------------- */ 568 /* channel help routines */ 569 570 static inline bool service_channel(u8 ch_addr, u8 idx) 571 { 572 u8 const shift = idx * 16; 573 u32 const adt1 = dim2_read_ctr(ADT + ch_addr, 1); 574 u32 mask[4] = { 0, 0, 0, 0 }; 575 u32 adt_w[4] = { 0, 0, 0, 0 }; 576 577 if (((adt1 >> (ADT1_DNE_BIT + shift)) & 1) == 0) 578 return false; 579 580 mask[1] = 581 bit_mask(ADT1_DNE_BIT + shift) | 582 bit_mask(ADT1_ERR_BIT + shift) | 583 bit_mask(ADT1_RDY_BIT + shift); 584 dim2_write_ctr_mask(ADT + ch_addr, mask, adt_w); 585 586 /* clear channel status bit */ 587 writel(bit_mask(ch_addr), &g.dim2->ACSR0); 588 589 return true; 590 } 591 592 /* -------------------------------------------------------------------------- */ 593 /* channel init routines */ 594 595 static void isoc_init(struct dim_channel *ch, u8 ch_addr, u16 packet_length) 596 { 597 state_init(&ch->state); 598 599 ch->addr = ch_addr; 600 601 ch->packet_length = packet_length; 602 ch->bytes_per_frame = 0; 603 ch->done_sw_buffers_number = 0; 604 } 605 606 static void sync_init(struct dim_channel *ch, u8 ch_addr, u16 bytes_per_frame) 607 { 608 state_init(&ch->state); 609 610 ch->addr = ch_addr; 611 612 ch->packet_length = 0; 613 ch->bytes_per_frame = bytes_per_frame; 614 ch->done_sw_buffers_number = 0; 615 } 616 617 static void channel_init(struct dim_channel *ch, u8 ch_addr) 618 { 619 state_init(&ch->state); 620 621 ch->addr = ch_addr; 622 623 ch->packet_length = 0; 624 ch->bytes_per_frame = 0; 625 ch->done_sw_buffers_number = 0; 626 } 627 628 /* returns true if channel interrupt state is cleared */ 629 static bool channel_service_interrupt(struct dim_channel *ch) 630 { 631 struct int_ch_state *const state = &ch->state; 632 633 if (!service_channel(ch->addr, state->idx2)) 634 return false; 635 636 state->idx2 ^= 1; 637 state->request_counter++; 638 return true; 639 } 640 641 static bool channel_start(struct dim_channel *ch, u32 buf_addr, u16 buf_size) 642 { 643 struct int_ch_state *const state = &ch->state; 644 645 if (buf_size <= 0) 646 return dim_on_error(DIM_ERR_BAD_BUFFER_SIZE, "Bad buffer size"); 647 648 if (ch->packet_length == 0 && ch->bytes_per_frame == 0 && 649 buf_size != dim_norm_ctrl_async_buffer_size(buf_size)) 650 return dim_on_error(DIM_ERR_BAD_BUFFER_SIZE, 651 "Bad control/async buffer size"); 652 653 if (ch->packet_length && 654 buf_size != norm_isoc_buffer_size(buf_size, ch->packet_length)) 655 return dim_on_error(DIM_ERR_BAD_BUFFER_SIZE, 656 "Bad isochronous buffer size"); 657 658 if (ch->bytes_per_frame && 659 buf_size != norm_sync_buffer_size(buf_size, ch->bytes_per_frame)) 660 return dim_on_error(DIM_ERR_BAD_BUFFER_SIZE, 661 "Bad synchronous buffer size"); 662 663 if (state->level >= 2u) 664 return dim_on_error(DIM_ERR_OVERFLOW, "Channel overflow"); 665 666 ++state->level; 667 668 if (ch->addr == g.atx_dbr.ch_addr) 669 dbrcnt_enq(buf_size); 670 671 if (ch->packet_length || ch->bytes_per_frame) 672 dim2_start_isoc_sync(ch->addr, state->idx1, buf_addr, buf_size); 673 else 674 dim2_start_ctrl_async(ch->addr, state->idx1, buf_addr, 675 buf_size); 676 state->idx1 ^= 1; 677 678 return true; 679 } 680 681 static u8 channel_service(struct dim_channel *ch) 682 { 683 struct int_ch_state *const state = &ch->state; 684 685 if (state->service_counter != state->request_counter) { 686 state->service_counter++; 687 if (state->level == 0) 688 return DIM_ERR_UNDERFLOW; 689 690 --state->level; 691 ch->done_sw_buffers_number++; 692 } 693 694 return DIM_NO_ERROR; 695 } 696 697 static bool channel_detach_buffers(struct dim_channel *ch, u16 buffers_number) 698 { 699 if (buffers_number > ch->done_sw_buffers_number) 700 return dim_on_error(DIM_ERR_UNDERFLOW, "Channel underflow"); 701 702 ch->done_sw_buffers_number -= buffers_number; 703 return true; 704 } 705 706 /* -------------------------------------------------------------------------- */ 707 /* API */ 708 709 u8 dim_startup(struct dim2_regs __iomem *dim_base_address, u32 mlb_clock, 710 u32 fcnt) 711 { 712 g.dim_is_initialized = false; 713 714 if (!dim_base_address) 715 return DIM_INIT_ERR_DIM_ADDR; 716 717 /* MediaLB clock: 0 - 256 fs, 1 - 512 fs, 2 - 1024 fs, 3 - 2048 fs */ 718 /* MediaLB clock: 4 - 3072 fs, 5 - 4096 fs, 6 - 6144 fs, 7 - 8192 fs */ 719 if (mlb_clock >= 8) 720 return DIM_INIT_ERR_MLB_CLOCK; 721 722 if (fcnt > MLBC0_FCNT_MAX_VAL) 723 return DIM_INIT_ERR_MLB_CLOCK; 724 725 g.dim2 = dim_base_address; 726 g.fcnt = fcnt; 727 g.dbr_map[0] = 0; 728 g.dbr_map[1] = 0; 729 730 dim2_initialize(mlb_clock >= 3, mlb_clock); 731 732 g.dim_is_initialized = true; 733 734 return DIM_NO_ERROR; 735 } 736 737 void dim_shutdown(void) 738 { 739 g.dim_is_initialized = false; 740 dim2_cleanup(); 741 } 742 743 bool dim_get_lock_state(void) 744 { 745 return dim2_is_mlb_locked(); 746 } 747 748 static u8 init_ctrl_async(struct dim_channel *ch, u8 type, u8 is_tx, 749 u16 ch_address, u16 hw_buffer_size) 750 { 751 if (!g.dim_is_initialized || !ch) 752 return DIM_ERR_DRIVER_NOT_INITIALIZED; 753 754 if (!check_channel_address(ch_address)) 755 return DIM_INIT_ERR_CHANNEL_ADDRESS; 756 757 if (!ch->dbr_size) 758 ch->dbr_size = round_up(hw_buffer_size, DBR_BLOCK_SIZE); 759 ch->dbr_addr = alloc_dbr(ch->dbr_size); 760 if (ch->dbr_addr >= DBR_SIZE) 761 return DIM_INIT_ERR_OUT_OF_MEMORY; 762 763 channel_init(ch, ch_address / 2); 764 765 dim2_configure_channel(ch->addr, type, is_tx, 766 ch->dbr_addr, ch->dbr_size, 0); 767 768 return DIM_NO_ERROR; 769 } 770 771 void dim_service_mlb_int_irq(void) 772 { 773 writel(0, &g.dim2->MS0); 774 writel(0, &g.dim2->MS1); 775 } 776 777 /* 778 * Retrieves maximal possible correct buffer size for isochronous data type 779 * conform to given packet length and not bigger than given buffer size. 780 * 781 * Returns non-zero correct buffer size or zero by error. 782 */ 783 u16 dim_norm_isoc_buffer_size(u16 buf_size, u16 packet_length) 784 { 785 if (!check_packet_length(packet_length)) 786 return 0; 787 788 return norm_isoc_buffer_size(buf_size, packet_length); 789 } 790 791 /* 792 * Retrieves maximal possible correct buffer size for synchronous data type 793 * conform to given bytes per frame and not bigger than given buffer size. 794 * 795 * Returns non-zero correct buffer size or zero by error. 796 */ 797 u16 dim_norm_sync_buffer_size(u16 buf_size, u16 bytes_per_frame) 798 { 799 if (!check_bytes_per_frame(bytes_per_frame)) 800 return 0; 801 802 return norm_sync_buffer_size(buf_size, bytes_per_frame); 803 } 804 805 u8 dim_init_control(struct dim_channel *ch, u8 is_tx, u16 ch_address, 806 u16 max_buffer_size) 807 { 808 return init_ctrl_async(ch, CAT_CT_VAL_CONTROL, is_tx, ch_address, 809 max_buffer_size); 810 } 811 812 u8 dim_init_async(struct dim_channel *ch, u8 is_tx, u16 ch_address, 813 u16 max_buffer_size) 814 { 815 u8 ret = init_ctrl_async(ch, CAT_CT_VAL_ASYNC, is_tx, ch_address, 816 max_buffer_size); 817 818 if (is_tx && !g.atx_dbr.ch_addr) { 819 g.atx_dbr.ch_addr = ch->addr; 820 dbrcnt_init(ch->addr, ch->dbr_size); 821 writel(bit_mask(20), &g.dim2->MIEN); 822 } 823 824 return ret; 825 } 826 827 u8 dim_init_isoc(struct dim_channel *ch, u8 is_tx, u16 ch_address, 828 u16 packet_length) 829 { 830 if (!g.dim_is_initialized || !ch) 831 return DIM_ERR_DRIVER_NOT_INITIALIZED; 832 833 if (!check_channel_address(ch_address)) 834 return DIM_INIT_ERR_CHANNEL_ADDRESS; 835 836 if (!check_packet_length(packet_length)) 837 return DIM_ERR_BAD_CONFIG; 838 839 if (!ch->dbr_size) 840 ch->dbr_size = packet_length * ISOC_DBR_FACTOR; 841 ch->dbr_addr = alloc_dbr(ch->dbr_size); 842 if (ch->dbr_addr >= DBR_SIZE) 843 return DIM_INIT_ERR_OUT_OF_MEMORY; 844 845 isoc_init(ch, ch_address / 2, packet_length); 846 847 dim2_configure_channel(ch->addr, CAT_CT_VAL_ISOC, is_tx, ch->dbr_addr, 848 ch->dbr_size, packet_length); 849 850 return DIM_NO_ERROR; 851 } 852 853 u8 dim_init_sync(struct dim_channel *ch, u8 is_tx, u16 ch_address, 854 u16 bytes_per_frame) 855 { 856 u16 bd_factor = g.fcnt + 2; 857 858 if (!g.dim_is_initialized || !ch) 859 return DIM_ERR_DRIVER_NOT_INITIALIZED; 860 861 if (!check_channel_address(ch_address)) 862 return DIM_INIT_ERR_CHANNEL_ADDRESS; 863 864 if (!check_bytes_per_frame(bytes_per_frame)) 865 return DIM_ERR_BAD_CONFIG; 866 867 if (!ch->dbr_size) 868 ch->dbr_size = bytes_per_frame << bd_factor; 869 ch->dbr_addr = alloc_dbr(ch->dbr_size); 870 if (ch->dbr_addr >= DBR_SIZE) 871 return DIM_INIT_ERR_OUT_OF_MEMORY; 872 873 sync_init(ch, ch_address / 2, bytes_per_frame); 874 875 dim2_clear_dbr(ch->dbr_addr, ch->dbr_size); 876 dim2_configure_channel(ch->addr, CAT_CT_VAL_SYNC, is_tx, 877 ch->dbr_addr, ch->dbr_size, 0); 878 879 return DIM_NO_ERROR; 880 } 881 882 u8 dim_destroy_channel(struct dim_channel *ch) 883 { 884 if (!g.dim_is_initialized || !ch) 885 return DIM_ERR_DRIVER_NOT_INITIALIZED; 886 887 if (ch->addr == g.atx_dbr.ch_addr) { 888 writel(0, &g.dim2->MIEN); 889 g.atx_dbr.ch_addr = 0; 890 } 891 892 dim2_clear_channel(ch->addr); 893 if (ch->dbr_addr < DBR_SIZE) 894 free_dbr(ch->dbr_addr, ch->dbr_size); 895 ch->dbr_addr = DBR_SIZE; 896 897 return DIM_NO_ERROR; 898 } 899 900 void dim_service_ahb_int_irq(struct dim_channel *const *channels) 901 { 902 bool state_changed; 903 904 if (!g.dim_is_initialized) { 905 dim_on_error(DIM_ERR_DRIVER_NOT_INITIALIZED, 906 "DIM is not initialized"); 907 return; 908 } 909 910 if (!channels) { 911 dim_on_error(DIM_ERR_DRIVER_NOT_INITIALIZED, "Bad channels"); 912 return; 913 } 914 915 /* 916 * Use while-loop and a flag to make sure the age is changed back at 917 * least once, otherwise the interrupt may never come if CPU generates 918 * interrupt on changing age. 919 * This cycle runs not more than number of channels, because 920 * channel_service_interrupt() routine doesn't start the channel again. 921 */ 922 do { 923 struct dim_channel *const *ch = channels; 924 925 state_changed = false; 926 927 while (*ch) { 928 state_changed |= channel_service_interrupt(*ch); 929 ++ch; 930 } 931 } while (state_changed); 932 } 933 934 u8 dim_service_channel(struct dim_channel *ch) 935 { 936 if (!g.dim_is_initialized || !ch) 937 return DIM_ERR_DRIVER_NOT_INITIALIZED; 938 939 return channel_service(ch); 940 } 941 942 struct dim_ch_state *dim_get_channel_state(struct dim_channel *ch, 943 struct dim_ch_state *state_ptr) 944 { 945 if (!ch || !state_ptr) 946 return NULL; 947 948 state_ptr->ready = ch->state.level < 2; 949 state_ptr->done_buffers = ch->done_sw_buffers_number; 950 951 return state_ptr; 952 } 953 954 bool dim_enqueue_buffer(struct dim_channel *ch, u32 buffer_addr, 955 u16 buffer_size) 956 { 957 if (!ch) 958 return dim_on_error(DIM_ERR_DRIVER_NOT_INITIALIZED, 959 "Bad channel"); 960 961 return channel_start(ch, buffer_addr, buffer_size); 962 } 963 964 bool dim_detach_buffers(struct dim_channel *ch, u16 buffers_number) 965 { 966 if (!ch) 967 return dim_on_error(DIM_ERR_DRIVER_NOT_INITIALIZED, 968 "Bad channel"); 969 970 return channel_detach_buffers(ch, buffers_number); 971 } 972