1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2023 Advanced Micro Devices, Inc */
3
4 #ifndef _PDSC_H_
5 #define _PDSC_H_
6
7 #include <linux/debugfs.h>
8 #include <linux/mmzone.h>
9 #include <net/devlink.h>
10
11 #include <linux/pds/pds_common.h>
12 #include <linux/pds/pds_core_if.h>
13 #include <linux/pds/pds_adminq.h>
14 #include <linux/pds/pds_intr.h>
15
16 #define PDSC_DRV_DESCRIPTION "AMD/Pensando Core Driver"
17
18 #define PDSC_WATCHDOG_SECS 5
19 #define PDSC_QUEUE_NAME_MAX_SZ 16
20 #define PDSC_ADMINQ_MAX_LENGTH 16 /* must be a power of two */
21 #define PDSC_NOTIFYQ_LENGTH 64 /* must be a power of two */
22 #define PDSC_TEARDOWN_RECOVERY false
23 #define PDSC_TEARDOWN_REMOVING true
24 #define PDSC_SETUP_RECOVERY false
25 #define PDSC_SETUP_INIT true
26
27 /* Use fixed 4MB instead of PAGE_SIZE << MAX_PAGE_ORDER to avoid
28 * cpu_to_le32() truncation on large-page configs
29 */
30 #define PDSC_HOST_MEM_MAX_CONTIG (4 * 1024 * 1024)
31 #define PDSC_HOST_MEM_MAX_COUNT 256
32
33 struct pdsc_deferred_dma {
34 struct list_head list;
35 dma_addr_t dma_addr;
36 void *va;
37 size_t size;
38 enum dma_data_direction dir;
39 };
40
41 struct pdsc_dev_bar {
42 void __iomem *vaddr;
43 phys_addr_t bus_addr;
44 unsigned long len;
45 int res_index;
46 };
47
48 struct pdsc;
49
50 struct pdsc_vf {
51 struct pds_auxiliary_dev *padev;
52 struct pdsc *vf;
53 u16 index;
54 __le16 vif_types[PDS_DEV_TYPE_MAX];
55 };
56
57 struct pdsc_devinfo {
58 u8 asic_type;
59 u8 asic_rev;
60 char fw_version[PDS_CORE_DEVINFO_FWVERS_BUFLEN + 1];
61 char serial_num[PDS_CORE_DEVINFO_SERIAL_BUFLEN + 1];
62 };
63
64 struct pdsc_queue {
65 struct pdsc_q_info *info;
66 u64 dbval;
67 u16 head_idx;
68 u16 tail_idx;
69 u8 hw_type;
70 unsigned int index;
71 unsigned int num_descs;
72 u64 dbell_count;
73 u64 features;
74 unsigned int type;
75 unsigned int hw_index;
76 union {
77 void *base;
78 struct pds_core_admin_cmd *adminq;
79 };
80 dma_addr_t base_pa; /* must be page aligned */
81 unsigned int desc_size;
82 unsigned int pid;
83 char name[PDSC_QUEUE_NAME_MAX_SZ];
84 };
85
86 #define PDSC_INTR_NAME_MAX_SZ 32
87
88 struct pdsc_intr_info {
89 char name[PDSC_INTR_NAME_MAX_SZ];
90 unsigned int index;
91 unsigned int vector;
92 void *data;
93 };
94
95 struct pdsc_cq_info {
96 void *comp;
97 };
98
99 struct pdsc_buf_info {
100 struct page *page;
101 dma_addr_t dma_addr;
102 u32 page_offset;
103 u32 len;
104 };
105
106 struct pdsc_q_info {
107 union {
108 void *desc;
109 struct pdsc_admin_cmd *adminq_desc;
110 };
111 unsigned int bytes;
112 unsigned int nbufs;
113 struct pdsc_buf_info bufs[PDS_CORE_MAX_FRAGS];
114 struct completion completion;
115 void *dest;
116 };
117
118 struct pdsc_cq {
119 struct pdsc_cq_info *info;
120 struct pdsc_queue *bound_q;
121 struct pdsc_intr_info *bound_intr;
122 u16 tail_idx;
123 bool done_color;
124 unsigned int num_descs;
125 unsigned int desc_size;
126 void *base;
127 dma_addr_t base_pa; /* must be page aligned */
128 } ____cacheline_aligned_in_smp;
129
130 struct pdsc_qcq {
131 struct pdsc *pdsc;
132 void *q_base;
133 dma_addr_t q_base_pa; /* might not be page aligned */
134 void *cq_base;
135 dma_addr_t cq_base_pa; /* might not be page aligned */
136 u32 q_size;
137 u32 cq_size;
138 bool armed;
139 unsigned int flags;
140
141 struct work_struct work;
142 struct pdsc_queue q;
143 struct pdsc_cq cq;
144 int intx;
145
146 u32 accum_work;
147 struct dentry *dentry;
148 };
149
150 struct pdsc_viftype {
151 char *name;
152 bool supported;
153 bool enabled;
154 int dl_id;
155 int vif_id;
156 struct pds_auxiliary_dev *padev;
157 };
158
159 struct pdsc_host_mem {
160 u32 size;
161 u16 tag;
162 u8 order;
163 struct page *pg;
164 dma_addr_t pa;
165 };
166
167 /* No state flags set means we are in a steady running state */
168 enum pdsc_state_flags {
169 PDSC_S_FW_DEAD, /* stopped, wait on startup or recovery */
170 PDSC_S_INITING_DRIVER, /* initial startup from probe */
171 PDSC_S_STOPPING_DRIVER, /* driver remove */
172
173 /* leave this as last */
174 PDSC_S_STATE_SIZE
175 };
176
177 struct pdsc {
178 struct pci_dev *pdev;
179 struct dentry *dentry;
180 struct device *dev;
181 struct pdsc_dev_bar bars[PDS_CORE_BARS_MAX];
182 struct pds_auxiliary_dev *padev;
183 struct pdsc_vf *vfs;
184 int num_vfs;
185 int vf_id;
186 int hw_index;
187 int uid;
188
189 unsigned long state;
190 u8 fw_status;
191 u8 fw_generation;
192 unsigned long last_fw_time;
193 u32 last_hb;
194 struct timer_list wdtimer;
195 unsigned int wdtimer_period;
196 struct work_struct health_work;
197 bool health_stopped;
198 struct devlink_health_reporter *fw_reporter;
199 u32 fw_recoveries;
200
201 struct pdsc_devinfo dev_info;
202 struct pds_core_dev_identity dev_ident;
203 unsigned int nintrs;
204 struct pdsc_intr_info *intr_info; /* array of nintrs elements */
205
206 struct workqueue_struct *wq;
207
208 unsigned int devcmd_timeout;
209 struct mutex devcmd_lock; /* lock for dev_cmd operations */
210 struct mutex config_lock; /* lock for configuration operations */
211 spinlock_t adminq_lock; /* lock for adminq operations */
212 struct list_head deferred_dma_list;
213 spinlock_t deferred_dma_lock; /* lock for deferred DMA list */
214 refcount_t adminq_refcnt;
215 struct pds_core_dev_info_regs __iomem *info_regs;
216 struct pds_core_dev_cmd_regs __iomem *cmd_regs;
217 struct pds_core_intr __iomem *intr_ctrl;
218 u64 __iomem *intr_status;
219 u64 __iomem *db_pages;
220 dma_addr_t phy_db_pages;
221 u64 __iomem *kern_dbpage;
222
223 struct pdsc_qcq adminqcq;
224 struct pdsc_qcq notifyqcq;
225 u64 last_eid;
226 struct pdsc_viftype *viftype_status;
227 struct work_struct pci_reset_work;
228
229 struct pdsc_host_mem *host_mem_reqs;
230 u16 num_host_mem_reqs;
231
232 struct pds_core_component_list_info fw_components;
233 };
234
235 /** enum pds_core_dbell_bits - bitwise composition of dbell values.
236 *
237 * @PDS_CORE_DBELL_QID_MASK: unshifted mask of valid queue id bits.
238 * @PDS_CORE_DBELL_QID_SHIFT: queue id shift amount in dbell value.
239 * @PDS_CORE_DBELL_QID: macro to build QID component of dbell value.
240 *
241 * @PDS_CORE_DBELL_RING_MASK: unshifted mask of valid ring bits.
242 * @PDS_CORE_DBELL_RING_SHIFT: ring shift amount in dbell value.
243 * @PDS_CORE_DBELL_RING: macro to build ring component of dbell value.
244 *
245 * @PDS_CORE_DBELL_RING_0: ring zero dbell component value.
246 * @PDS_CORE_DBELL_RING_1: ring one dbell component value.
247 * @PDS_CORE_DBELL_RING_2: ring two dbell component value.
248 * @PDS_CORE_DBELL_RING_3: ring three dbell component value.
249 *
250 * @PDS_CORE_DBELL_INDEX_MASK: bit mask of valid index bits, no shift needed.
251 */
252 enum pds_core_dbell_bits {
253 PDS_CORE_DBELL_QID_MASK = 0xffffff,
254 PDS_CORE_DBELL_QID_SHIFT = 24,
255
256 #define PDS_CORE_DBELL_QID(n) \
257 (((u64)(n) & PDS_CORE_DBELL_QID_MASK) << PDS_CORE_DBELL_QID_SHIFT)
258
259 PDS_CORE_DBELL_RING_MASK = 0x7,
260 PDS_CORE_DBELL_RING_SHIFT = 16,
261
262 #define PDS_CORE_DBELL_RING(n) \
263 (((u64)(n) & PDS_CORE_DBELL_RING_MASK) << PDS_CORE_DBELL_RING_SHIFT)
264
265 PDS_CORE_DBELL_RING_0 = 0,
266 PDS_CORE_DBELL_RING_1 = PDS_CORE_DBELL_RING(1),
267 PDS_CORE_DBELL_RING_2 = PDS_CORE_DBELL_RING(2),
268 PDS_CORE_DBELL_RING_3 = PDS_CORE_DBELL_RING(3),
269
270 PDS_CORE_DBELL_INDEX_MASK = 0xffff,
271 };
272
pds_core_dbell_ring(u64 __iomem * db_page,enum pds_core_logical_qtype qtype,u64 val)273 static inline void pds_core_dbell_ring(u64 __iomem *db_page,
274 enum pds_core_logical_qtype qtype,
275 u64 val)
276 {
277 writeq(val, &db_page[qtype]);
278 }
279
280 int pdsc_fw_reporter_diagnose(struct devlink_health_reporter *reporter,
281 struct devlink_fmsg *fmsg,
282 struct netlink_ext_ack *extack);
283 int pdsc_dl_info_get(struct devlink *dl, struct devlink_info_req *req,
284 struct netlink_ext_ack *extack);
285 int pdsc_dl_flash_update(struct devlink *dl,
286 struct devlink_flash_update_params *params,
287 struct netlink_ext_ack *extack);
288 int pdsc_dl_enable_get(struct devlink *dl, u32 id,
289 struct devlink_param_gset_ctx *ctx,
290 struct netlink_ext_ack *extack);
291 int pdsc_dl_enable_set(struct devlink *dl, u32 id,
292 struct devlink_param_gset_ctx *ctx,
293 struct netlink_ext_ack *extack);
294 int pdsc_dl_enable_validate(struct devlink *dl, u32 id,
295 union devlink_param_value *val,
296 struct netlink_ext_ack *extack);
297
298 void __iomem *pdsc_map_dbpage(struct pdsc *pdsc, int page_num);
299
300 void pdsc_debugfs_create(void);
301 void pdsc_debugfs_destroy(void);
302 void pdsc_debugfs_add_dev(struct pdsc *pdsc);
303 void pdsc_debugfs_del_dev(struct pdsc *pdsc);
304 void pdsc_debugfs_add_ident(struct pdsc *pdsc);
305 void pdsc_debugfs_add_viftype(struct pdsc *pdsc);
306 void pdsc_debugfs_add_irqs(struct pdsc *pdsc);
307 void pdsc_debugfs_add_qcq(struct pdsc *pdsc, struct pdsc_qcq *qcq);
308 void pdsc_debugfs_del_qcq(struct pdsc_qcq *qcq);
309 void pdsc_debugfs_add_host_mem(struct pdsc *pdsc);
310 void pdsc_debugfs_del_host_mem(struct pdsc *pdsc);
311
312 int pdsc_err_to_errno(enum pds_core_status_code code);
313 bool pdsc_is_fw_running(struct pdsc *pdsc);
314 bool pdsc_is_fw_good(struct pdsc *pdsc);
315 int pdsc_devcmd(struct pdsc *pdsc, union pds_core_dev_cmd *cmd,
316 union pds_core_dev_comp *comp, int max_seconds);
317 int pdsc_devcmd_with_data(struct pdsc *pdsc, union pds_core_dev_cmd *cmd,
318 const void *data, size_t data_len,
319 union pds_core_dev_comp *comp, int max_seconds);
320 int pdsc_devcmd_with_data_nomsg(struct pdsc *pdsc, union pds_core_dev_cmd *cmd,
321 const void *data, size_t data_len,
322 union pds_core_dev_comp *comp, int max_seconds);
323 int pdsc_devcmd_locked(struct pdsc *pdsc, union pds_core_dev_cmd *cmd,
324 union pds_core_dev_comp *comp, int max_seconds);
325 int pdsc_devcmd_locked_nomsg(struct pdsc *pdsc, union pds_core_dev_cmd *cmd,
326 union pds_core_dev_comp *comp, int max_seconds);
327 int pdsc_devcmd_init(struct pdsc *pdsc);
328 int pdsc_devcmd_reset(struct pdsc *pdsc);
329 int pdsc_dev_init(struct pdsc *pdsc);
330 void pdsc_dev_uninit(struct pdsc *pdsc);
331
332 int pdsc_intr_alloc(struct pdsc *pdsc, char *name,
333 irq_handler_t handler, void *data);
334 void pdsc_intr_free(struct pdsc *pdsc, int index);
335 void pdsc_qcq_free(struct pdsc *pdsc, struct pdsc_qcq *qcq);
336 int pdsc_qcq_alloc(struct pdsc *pdsc, unsigned int type, unsigned int index,
337 const char *name, unsigned int flags, unsigned int num_descs,
338 unsigned int desc_size, unsigned int cq_desc_size,
339 unsigned int pid, struct pdsc_qcq *qcq);
340 int pdsc_setup(struct pdsc *pdsc, bool init);
341 void pdsc_teardown(struct pdsc *pdsc, bool removing);
342 int pdsc_start(struct pdsc *pdsc);
343 void pdsc_stop(struct pdsc *pdsc);
344 void pdsc_health_thread(struct work_struct *work);
345
346 int pdsc_register_notify(struct notifier_block *nb);
347 void pdsc_unregister_notify(struct notifier_block *nb);
348 void pdsc_notify(unsigned long event, void *data);
349 int pdsc_auxbus_dev_add(struct pdsc *cf, struct pdsc *pf,
350 enum pds_core_vif_types vt,
351 struct pds_auxiliary_dev **pd_ptr);
352 void pdsc_auxbus_dev_del(struct pdsc *cf, struct pdsc *pf,
353 struct pds_auxiliary_dev **pd_ptr);
354
355 void pdsc_process_adminq(struct pdsc_qcq *qcq);
356 void pdsc_work_thread(struct work_struct *work);
357 irqreturn_t pdsc_adminq_isr(int irq, void *data);
358
359 int pdsc_firmware_update(struct pdsc *pdsc,
360 struct devlink_flash_update_params *params,
361 struct netlink_ext_ack *extack);
362 int pdsc_get_component_info(struct pdsc *pdsc);
363 const char *pdsc_fw_type_to_name(u8 type);
364 void pdsc_fw_components_invalidate(struct pdsc *pdsc);
365
366 void pdsc_fw_down(struct pdsc *pdsc);
367 void pdsc_fw_up(struct pdsc *pdsc);
368 void pdsc_pci_reset_thread(struct work_struct *work);
369
370 void pdsc_host_mem_add(struct pdsc *pdsc);
371 void pdsc_host_mem_free(struct pdsc *pdsc);
372
373 void pdsc_deferred_dma_add(struct pdsc *pdsc, struct pdsc_deferred_dma *entry,
374 dma_addr_t dma_addr, void *va, size_t size,
375 enum dma_data_direction dir);
376 void pdsc_deferred_dma_free(struct pdsc *pdsc);
377
378 #endif /* _PDSC_H_ */
379