1 /* SPDX-License-Identifier: GPL-2.0+ */
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3
4 #ifndef __HNAE3_H
5 #define __HNAE3_H
6
7 /* Names used in this framework:
8 * ae handle (handle):
9 * a set of queues provided by AE
10 * ring buffer queue (rbq):
11 * the channel between upper layer and the AE, can do tx and rx
12 * ring:
13 * a tx or rx channel within a rbq
14 * ring description (desc):
15 * an element in the ring with packet information
16 * buffer:
17 * a memory region referred by desc with the full packet payload
18 *
19 * "num" means a static number set as a parameter, "count" mean a dynamic
20 * number set while running
21 * "cb" means control block
22 */
23
24 #include <linux/acpi.h>
25 #include <linux/dcbnl.h>
26 #include <linux/delay.h>
27 #include <linux/device.h>
28 #include <linux/ethtool.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
31 #include <linux/pci.h>
32 #include <linux/pkt_sched.h>
33 #include <linux/types.h>
34 #include <linux/bitmap.h>
35 #include <net/pkt_cls.h>
36 #include <net/pkt_sched.h>
37
38 #define HNAE3_MOD_VERSION "1.0"
39
40 #define HNAE3_MIN_VECTOR_NUM 2 /* first one for misc, another for IO */
41
42 /* Device version */
43 #define HNAE3_DEVICE_VERSION_V1 0x00020
44 #define HNAE3_DEVICE_VERSION_V2 0x00021
45 #define HNAE3_DEVICE_VERSION_V3 0x00030
46
47 #define HNAE3_PCI_REVISION_BIT_SIZE 8
48
49 /* Device IDs */
50 #define HNAE3_DEV_ID_GE 0xA220
51 #define HNAE3_DEV_ID_25GE 0xA221
52 #define HNAE3_DEV_ID_25GE_RDMA 0xA222
53 #define HNAE3_DEV_ID_25GE_RDMA_MACSEC 0xA223
54 #define HNAE3_DEV_ID_50GE_RDMA 0xA224
55 #define HNAE3_DEV_ID_50GE_RDMA_MACSEC 0xA225
56 #define HNAE3_DEV_ID_100G_RDMA_MACSEC 0xA226
57 #define HNAE3_DEV_ID_200G_RDMA 0xA228
58 #define HNAE3_DEV_ID_VF 0xA22E
59 #define HNAE3_DEV_ID_RDMA_DCB_PFC_VF 0xA22F
60
61 #define HNAE3_CLASS_NAME_SIZE 16
62
63 #define HNAE3_DEV_INITED_B 0x0
64 #define HNAE3_DEV_SUPPORT_ROCE_B 0x1
65 #define HNAE3_DEV_SUPPORT_DCB_B 0x2
66 #define HNAE3_KNIC_CLIENT_INITED_B 0x3
67 #define HNAE3_UNIC_CLIENT_INITED_B 0x4
68 #define HNAE3_ROCE_CLIENT_INITED_B 0x5
69
70 #define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS (BIT(HNAE3_DEV_SUPPORT_DCB_B) | \
71 BIT(HNAE3_DEV_SUPPORT_ROCE_B))
72
73 #define hnae3_dev_roce_supported(hdev) \
74 hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)
75
76 #define hnae3_dev_dcb_supported(hdev) \
77 hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_DCB_B)
78
79 enum HNAE3_DEV_CAP_BITS {
80 HNAE3_DEV_SUPPORT_FD_B,
81 HNAE3_DEV_SUPPORT_GRO_B,
82 HNAE3_DEV_SUPPORT_FEC_B,
83 HNAE3_DEV_SUPPORT_UDP_GSO_B,
84 HNAE3_DEV_SUPPORT_QB_B,
85 HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B,
86 HNAE3_DEV_SUPPORT_PTP_B,
87 HNAE3_DEV_SUPPORT_INT_QL_B,
88 HNAE3_DEV_SUPPORT_HW_TX_CSUM_B,
89 HNAE3_DEV_SUPPORT_TX_PUSH_B,
90 HNAE3_DEV_SUPPORT_PHY_IMP_B,
91 HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B,
92 HNAE3_DEV_SUPPORT_HW_PAD_B,
93 HNAE3_DEV_SUPPORT_STASH_B,
94 HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B,
95 HNAE3_DEV_SUPPORT_PAUSE_B,
96 HNAE3_DEV_SUPPORT_RAS_IMP_B,
97 HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B,
98 HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B,
99 HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B,
100 HNAE3_DEV_SUPPORT_MC_MAC_MNG_B,
101 HNAE3_DEV_SUPPORT_CQ_B,
102 HNAE3_DEV_SUPPORT_FEC_STATS_B,
103 HNAE3_DEV_SUPPORT_LANE_NUM_B,
104 HNAE3_DEV_SUPPORT_WOL_B,
105 HNAE3_DEV_SUPPORT_TM_FLUSH_B,
106 HNAE3_DEV_SUPPORT_VF_FAULT_B,
107 HNAE3_DEV_SUPPORT_ERR_MOD_GEN_REG_B,
108 };
109
110 #define hnae3_ae_dev_fd_supported(ae_dev) \
111 test_bit(HNAE3_DEV_SUPPORT_FD_B, (ae_dev)->caps)
112
113 #define hnae3_ae_dev_gro_supported(ae_dev) \
114 test_bit(HNAE3_DEV_SUPPORT_GRO_B, (ae_dev)->caps)
115
116 #define hnae3_dev_fec_supported(hdev) \
117 test_bit(HNAE3_DEV_SUPPORT_FEC_B, (hdev)->ae_dev->caps)
118
119 #define hnae3_dev_udp_gso_supported(hdev) \
120 test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, (hdev)->ae_dev->caps)
121
122 #define hnae3_dev_qb_supported(hdev) \
123 test_bit(HNAE3_DEV_SUPPORT_QB_B, (hdev)->ae_dev->caps)
124
125 #define hnae3_dev_fd_forward_tc_supported(hdev) \
126 test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, (hdev)->ae_dev->caps)
127
128 #define hnae3_dev_ptp_supported(hdev) \
129 test_bit(HNAE3_DEV_SUPPORT_PTP_B, (hdev)->ae_dev->caps)
130
131 #define hnae3_dev_int_ql_supported(hdev) \
132 test_bit(HNAE3_DEV_SUPPORT_INT_QL_B, (hdev)->ae_dev->caps)
133
134 #define hnae3_dev_hw_csum_supported(hdev) \
135 test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, (hdev)->ae_dev->caps)
136
137 #define hnae3_dev_tx_push_supported(hdev) \
138 test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, (hdev)->ae_dev->caps)
139
140 #define hnae3_dev_phy_imp_supported(hdev) \
141 test_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, (hdev)->ae_dev->caps)
142
143 #define hnae3_dev_ras_imp_supported(hdev) \
144 test_bit(HNAE3_DEV_SUPPORT_RAS_IMP_B, (hdev)->ae_dev->caps)
145
146 #define hnae3_dev_tqp_txrx_indep_supported(hdev) \
147 test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (hdev)->ae_dev->caps)
148
149 #define hnae3_dev_hw_pad_supported(hdev) \
150 test_bit(HNAE3_DEV_SUPPORT_HW_PAD_B, (hdev)->ae_dev->caps)
151
152 #define hnae3_dev_stash_supported(hdev) \
153 test_bit(HNAE3_DEV_SUPPORT_STASH_B, (hdev)->ae_dev->caps)
154
155 #define hnae3_dev_pause_supported(hdev) \
156 test_bit(HNAE3_DEV_SUPPORT_PAUSE_B, (hdev)->ae_dev->caps)
157
158 #define hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev) \
159 test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (ae_dev)->caps)
160
161 #define hnae3_ae_dev_rxd_adv_layout_supported(ae_dev) \
162 test_bit(HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, (ae_dev)->caps)
163
164 #define hnae3_ae_dev_mc_mac_mng_supported(ae_dev) \
165 test_bit(HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, (ae_dev)->caps)
166
167 #define hnae3_ae_dev_cq_supported(ae_dev) \
168 test_bit(HNAE3_DEV_SUPPORT_CQ_B, (ae_dev)->caps)
169
170 #define hnae3_ae_dev_fec_stats_supported(ae_dev) \
171 test_bit(HNAE3_DEV_SUPPORT_FEC_STATS_B, (ae_dev)->caps)
172
173 #define hnae3_ae_dev_lane_num_supported(ae_dev) \
174 test_bit(HNAE3_DEV_SUPPORT_LANE_NUM_B, (ae_dev)->caps)
175
176 #define hnae3_ae_dev_wol_supported(ae_dev) \
177 test_bit(HNAE3_DEV_SUPPORT_WOL_B, (ae_dev)->caps)
178
179 #define hnae3_ae_dev_tm_flush_supported(hdev) \
180 test_bit(HNAE3_DEV_SUPPORT_TM_FLUSH_B, (hdev)->ae_dev->caps)
181
182 #define hnae3_ae_dev_vf_fault_supported(ae_dev) \
183 test_bit(HNAE3_DEV_SUPPORT_VF_FAULT_B, (ae_dev)->caps)
184
185 #define hnae3_ae_dev_gen_reg_dfx_supported(hdev) \
186 test_bit(HNAE3_DEV_SUPPORT_ERR_MOD_GEN_REG_B, (hdev)->ae_dev->caps)
187
188 enum HNAE3_PF_CAP_BITS {
189 HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B = 0,
190 };
191 #define ring_ptr_move_fw(ring, p) \
192 ((ring)->p = ((ring)->p + 1) % (ring)->desc_num)
193 #define ring_ptr_move_bw(ring, p) \
194 ((ring)->p = ((ring)->p - 1 + (ring)->desc_num) % (ring)->desc_num)
195
196 struct hnae3_handle;
197
198 struct hnae3_queue {
199 void __iomem *io_base;
200 void __iomem *mem_base;
201 struct hnae3_ae_algo *ae_algo;
202 struct hnae3_handle *handle;
203 int tqp_index; /* index in a handle */
204 u32 buf_size; /* size for hnae_desc->addr, preset by AE */
205 u16 tx_desc_num; /* total number of tx desc */
206 u16 rx_desc_num; /* total number of rx desc */
207 };
208
209 struct hns3_mac_stats {
210 u64 tx_pause_cnt;
211 u64 rx_pause_cnt;
212 };
213
214 /* hnae3 loop mode */
215 enum hnae3_loop {
216 HNAE3_LOOP_EXTERNAL,
217 HNAE3_LOOP_APP,
218 HNAE3_LOOP_SERIAL_SERDES,
219 HNAE3_LOOP_PARALLEL_SERDES,
220 HNAE3_LOOP_PHY,
221 HNAE3_LOOP_NONE,
222 };
223
224 enum hnae3_client_type {
225 HNAE3_CLIENT_KNIC,
226 HNAE3_CLIENT_ROCE,
227 };
228
229 /* mac media type */
230 enum hnae3_media_type {
231 HNAE3_MEDIA_TYPE_UNKNOWN,
232 HNAE3_MEDIA_TYPE_FIBER,
233 HNAE3_MEDIA_TYPE_COPPER,
234 HNAE3_MEDIA_TYPE_BACKPLANE,
235 HNAE3_MEDIA_TYPE_NONE,
236 };
237
238 /* must be consistent with definition in firmware */
239 enum hnae3_module_type {
240 HNAE3_MODULE_TYPE_UNKNOWN = 0x00,
241 HNAE3_MODULE_TYPE_FIBRE_LR = 0x01,
242 HNAE3_MODULE_TYPE_FIBRE_SR = 0x02,
243 HNAE3_MODULE_TYPE_AOC = 0x03,
244 HNAE3_MODULE_TYPE_CR = 0x04,
245 HNAE3_MODULE_TYPE_KR = 0x05,
246 HNAE3_MODULE_TYPE_TP = 0x06,
247 };
248
249 enum hnae3_fec_mode {
250 HNAE3_FEC_AUTO = 0,
251 HNAE3_FEC_BASER,
252 HNAE3_FEC_RS,
253 HNAE3_FEC_LLRS,
254 HNAE3_FEC_NONE,
255 HNAE3_FEC_USER_DEF,
256 };
257
258 enum hnae3_reset_notify_type {
259 HNAE3_UP_CLIENT,
260 HNAE3_DOWN_CLIENT,
261 HNAE3_INIT_CLIENT,
262 HNAE3_UNINIT_CLIENT,
263 };
264
265 enum hnae3_hw_error_type {
266 HNAE3_PPU_POISON_ERROR,
267 HNAE3_CMDQ_ECC_ERROR,
268 HNAE3_IMP_RD_POISON_ERROR,
269 HNAE3_ROCEE_AXI_RESP_ERROR,
270 };
271
272 enum hnae3_reset_type {
273 HNAE3_VF_RESET,
274 HNAE3_VF_FUNC_RESET,
275 HNAE3_VF_PF_FUNC_RESET,
276 HNAE3_VF_FULL_RESET,
277 HNAE3_FLR_RESET,
278 HNAE3_FUNC_RESET,
279 HNAE3_GLOBAL_RESET,
280 HNAE3_IMP_RESET,
281 HNAE3_NONE_RESET,
282 HNAE3_VF_EXP_RESET,
283 HNAE3_MAX_RESET,
284 };
285
286 enum hnae3_port_base_vlan_state {
287 HNAE3_PORT_BASE_VLAN_DISABLE,
288 HNAE3_PORT_BASE_VLAN_ENABLE,
289 HNAE3_PORT_BASE_VLAN_MODIFY,
290 HNAE3_PORT_BASE_VLAN_NOCHANGE,
291 };
292
293 enum hnae3_dbg_cmd {
294 HNAE3_DBG_CMD_TM_NODES,
295 HNAE3_DBG_CMD_TM_PRI,
296 HNAE3_DBG_CMD_TM_QSET,
297 HNAE3_DBG_CMD_TM_MAP,
298 HNAE3_DBG_CMD_TM_PG,
299 HNAE3_DBG_CMD_TM_PORT,
300 HNAE3_DBG_CMD_TC_SCH_INFO,
301 HNAE3_DBG_CMD_QOS_PAUSE_CFG,
302 HNAE3_DBG_CMD_QOS_PRI_MAP,
303 HNAE3_DBG_CMD_QOS_DSCP_MAP,
304 HNAE3_DBG_CMD_QOS_BUF_CFG,
305 HNAE3_DBG_CMD_DEV_INFO,
306 HNAE3_DBG_CMD_TX_BD,
307 HNAE3_DBG_CMD_RX_BD,
308 HNAE3_DBG_CMD_MAC_UC,
309 HNAE3_DBG_CMD_MAC_MC,
310 HNAE3_DBG_CMD_MNG_TBL,
311 HNAE3_DBG_CMD_LOOPBACK,
312 HNAE3_DBG_CMD_PTP_INFO,
313 HNAE3_DBG_CMD_INTERRUPT_INFO,
314 HNAE3_DBG_CMD_RESET_INFO,
315 HNAE3_DBG_CMD_IMP_INFO,
316 HNAE3_DBG_CMD_NCL_CONFIG,
317 HNAE3_DBG_CMD_REG_BIOS_COMMON,
318 HNAE3_DBG_CMD_REG_SSU,
319 HNAE3_DBG_CMD_REG_IGU_EGU,
320 HNAE3_DBG_CMD_REG_RPU,
321 HNAE3_DBG_CMD_REG_NCSI,
322 HNAE3_DBG_CMD_REG_RTC,
323 HNAE3_DBG_CMD_REG_PPP,
324 HNAE3_DBG_CMD_REG_RCB,
325 HNAE3_DBG_CMD_REG_TQP,
326 HNAE3_DBG_CMD_REG_MAC,
327 HNAE3_DBG_CMD_REG_DCB,
328 HNAE3_DBG_CMD_VLAN_CONFIG,
329 HNAE3_DBG_CMD_QUEUE_MAP,
330 HNAE3_DBG_CMD_RX_QUEUE_INFO,
331 HNAE3_DBG_CMD_TX_QUEUE_INFO,
332 HNAE3_DBG_CMD_FD_TCAM,
333 HNAE3_DBG_CMD_FD_COUNTER,
334 HNAE3_DBG_CMD_FD_RULE,
335 HNAE3_DBG_CMD_MAC_TNL_STATUS,
336 HNAE3_DBG_CMD_SERV_INFO,
337 HNAE3_DBG_CMD_UMV_INFO,
338 HNAE3_DBG_CMD_PAGE_POOL_INFO,
339 HNAE3_DBG_CMD_COAL_INFO,
340 HNAE3_DBG_CMD_UNKNOWN,
341 };
342
343 #define hnae3_seq_file_to_ae_dev(s) (dev_get_drvdata((s)->private))
344 #define hnae3_seq_file_to_handle(s) \
345 (((struct hnae3_ae_dev *)hnae3_seq_file_to_ae_dev(s))->handle)
346
347 enum hnae3_tc_map_mode {
348 HNAE3_TC_MAP_MODE_PRIO,
349 HNAE3_TC_MAP_MODE_DSCP,
350 };
351
352 struct hnae3_vector_info {
353 u8 __iomem *io_addr;
354 int vector;
355 };
356
357 #define HNAE3_RING_TYPE_B 0
358 #define HNAE3_RING_TYPE_TX 0
359 #define HNAE3_RING_TYPE_RX 1
360 #define HNAE3_RING_GL_IDX_S 0
361 #define HNAE3_RING_GL_IDX_M GENMASK(1, 0)
362 #define HNAE3_RING_GL_RX 0
363 #define HNAE3_RING_GL_TX 1
364
365 #define HNAE3_FW_VERSION_BYTE3_SHIFT 24
366 #define HNAE3_FW_VERSION_BYTE3_MASK GENMASK(31, 24)
367 #define HNAE3_FW_VERSION_BYTE2_SHIFT 16
368 #define HNAE3_FW_VERSION_BYTE2_MASK GENMASK(23, 16)
369 #define HNAE3_FW_VERSION_BYTE1_SHIFT 8
370 #define HNAE3_FW_VERSION_BYTE1_MASK GENMASK(15, 8)
371 #define HNAE3_FW_VERSION_BYTE0_SHIFT 0
372 #define HNAE3_FW_VERSION_BYTE0_MASK GENMASK(7, 0)
373
374 #define HNAE3_SCC_VERSION_BYTE3_SHIFT 24
375 #define HNAE3_SCC_VERSION_BYTE3_MASK GENMASK(31, 24)
376 #define HNAE3_SCC_VERSION_BYTE2_SHIFT 16
377 #define HNAE3_SCC_VERSION_BYTE2_MASK GENMASK(23, 16)
378 #define HNAE3_SCC_VERSION_BYTE1_SHIFT 8
379 #define HNAE3_SCC_VERSION_BYTE1_MASK GENMASK(15, 8)
380 #define HNAE3_SCC_VERSION_BYTE0_SHIFT 0
381 #define HNAE3_SCC_VERSION_BYTE0_MASK GENMASK(7, 0)
382
383 struct hnae3_ring_chain_node {
384 struct hnae3_ring_chain_node *next;
385 u32 tqp_index;
386 u32 flag;
387 u32 int_gl_idx;
388 };
389
390 #define HNAE3_IS_TX_RING(node) \
391 (((node)->flag & 1 << HNAE3_RING_TYPE_B) == HNAE3_RING_TYPE_TX)
392
393 /* device specification info from firmware */
394 struct hnae3_dev_specs {
395 u32 mac_entry_num; /* number of mac-vlan table entry */
396 u32 mng_entry_num; /* number of manager table entry */
397 u32 max_tm_rate;
398 u16 rss_ind_tbl_size;
399 u16 rss_key_size;
400 u16 int_ql_max; /* max value of interrupt coalesce based on INT_QL */
401 u16 max_int_gl; /* max value of interrupt coalesce based on INT_GL */
402 u8 max_non_tso_bd_num; /* max BD number of one non-TSO packet */
403 u16 max_frm_size;
404 u16 max_qset_num;
405 u16 umv_size;
406 u16 mc_mac_size;
407 u32 mac_stats_num;
408 u8 tnl_num;
409 u8 hilink_version;
410 };
411
412 struct hnae3_client_ops {
413 int (*init_instance)(struct hnae3_handle *handle);
414 void (*uninit_instance)(struct hnae3_handle *handle, bool reset);
415 void (*link_status_change)(struct hnae3_handle *handle, bool state);
416 int (*reset_notify)(struct hnae3_handle *handle,
417 enum hnae3_reset_notify_type type);
418 void (*process_hw_error)(struct hnae3_handle *handle,
419 enum hnae3_hw_error_type);
420 };
421
422 #define HNAE3_CLIENT_NAME_LENGTH 16
423 struct hnae3_client {
424 char name[HNAE3_CLIENT_NAME_LENGTH];
425 unsigned long state;
426 enum hnae3_client_type type;
427 const struct hnae3_client_ops *ops;
428 struct list_head node;
429 };
430
431 #define HNAE3_DEV_CAPS_MAX_NUM 96
432 struct hnae3_ae_dev {
433 struct pci_dev *pdev;
434 const struct hnae3_ae_ops *ops;
435 struct list_head node;
436 u32 flag;
437 unsigned long hw_err_reset_req;
438 struct hnae3_dev_specs dev_specs;
439 u32 dev_version;
440 DECLARE_BITMAP(caps, HNAE3_DEV_CAPS_MAX_NUM);
441 void *priv;
442 struct hnae3_handle *handle;
443 };
444
445 typedef int (*read_func)(struct seq_file *s, void *data);
446
447 /* This struct defines the operation on the handle.
448 *
449 * init_ae_dev(): (mandatory)
450 * Get PF configure from pci_dev and initialize PF hardware
451 * uninit_ae_dev()
452 * Disable PF device and release PF resource
453 * register_client
454 * Register client to ae_dev
455 * unregister_client()
456 * Unregister client from ae_dev
457 * start()
458 * Enable the hardware
459 * stop()
460 * Disable the hardware
461 * start_client()
462 * Inform the hclge that client has been started
463 * stop_client()
464 * Inform the hclge that client has been stopped
465 * get_status()
466 * Get the carrier state of the back channel of the handle, 1 for ok, 0 for
467 * non-ok
468 * get_ksettings_an_result()
469 * Get negotiation status,speed and duplex
470 * get_media_type()
471 * Get media type of MAC
472 * check_port_speed()
473 * Check target speed whether is supported
474 * adjust_link()
475 * Adjust link status
476 * set_loopback()
477 * Set loopback
478 * set_promisc_mode
479 * Set promisc mode
480 * request_update_promisc_mode
481 * request to hclge(vf) to update promisc mode
482 * set_mtu()
483 * set mtu
484 * get_pauseparam()
485 * get tx and rx of pause frame use
486 * set_pauseparam()
487 * set tx and rx of pause frame use
488 * set_autoneg()
489 * set auto autonegotiation of pause frame use
490 * get_autoneg()
491 * get auto autonegotiation of pause frame use
492 * restart_autoneg()
493 * restart autonegotiation
494 * halt_autoneg()
495 * halt/resume autonegotiation when autonegotiation on
496 * get_coalesce_usecs()
497 * get usecs to delay a TX interrupt after a packet is sent
498 * get_rx_max_coalesced_frames()
499 * get Maximum number of packets to be sent before a TX interrupt.
500 * set_coalesce_usecs()
501 * set usecs to delay a TX interrupt after a packet is sent
502 * set_coalesce_frames()
503 * set Maximum number of packets to be sent before a TX interrupt.
504 * get_mac_addr()
505 * get mac address
506 * set_mac_addr()
507 * set mac address
508 * add_uc_addr
509 * Add unicast addr to mac table
510 * rm_uc_addr
511 * Remove unicast addr from mac table
512 * set_mc_addr()
513 * Set multicast address
514 * add_mc_addr
515 * Add multicast address to mac table
516 * rm_mc_addr
517 * Remove multicast address from mac table
518 * update_stats()
519 * Update Old network device statistics
520 * get_mac_stats()
521 * get mac pause statistics including tx_cnt and rx_cnt
522 * get_ethtool_stats()
523 * Get ethtool network device statistics
524 * get_strings()
525 * Get a set of strings that describe the requested objects
526 * get_sset_count()
527 * Get number of strings that @get_strings will write
528 * update_led_status()
529 * Update the led status
530 * set_led_id()
531 * Set led id
532 * get_regs()
533 * Get regs dump
534 * get_regs_len()
535 * Get the len of the regs dump
536 * get_rss_key_size()
537 * Get rss key size
538 * get_rss()
539 * Get rss table
540 * set_rss()
541 * Set rss table
542 * get_tc_size()
543 * Get tc size of handle
544 * get_vector()
545 * Get vector number and vector information
546 * put_vector()
547 * Put the vector in hdev
548 * map_ring_to_vector()
549 * Map rings to vector
550 * unmap_ring_from_vector()
551 * Unmap rings from vector
552 * reset_queue()
553 * Reset queue
554 * get_fw_version()
555 * Get firmware version
556 * get_mdix_mode()
557 * Get media typr of phy
558 * enable_vlan_filter()
559 * Enable vlan filter
560 * set_vlan_filter()
561 * Set vlan filter config of Ports
562 * set_vf_vlan_filter()
563 * Set vlan filter config of vf
564 * enable_hw_strip_rxvtag()
565 * Enable/disable hardware strip vlan tag of packets received
566 * set_gro_en
567 * Enable/disable HW GRO
568 * add_arfs_entry
569 * Check the 5-tuples of flow, and create flow director rule
570 * get_vf_config
571 * Get the VF configuration setting by the host
572 * set_vf_link_state
573 * Set VF link status
574 * set_vf_spoofchk
575 * Enable/disable spoof check for specified vf
576 * set_vf_trust
577 * Enable/disable trust for specified vf, if the vf being trusted, then
578 * it can enable promisc mode
579 * set_vf_rate
580 * Set the max tx rate of specified vf.
581 * set_vf_mac
582 * Configure the default MAC for specified VF
583 * get_module_eeprom
584 * Get the optical module eeprom info.
585 * add_cls_flower
586 * Add clsflower rule
587 * del_cls_flower
588 * Delete clsflower rule
589 * cls_flower_active
590 * Check if any cls flower rule exist
591 * set_tx_hwts_info
592 * Save information for 1588 tx packet
593 * get_rx_hwts
594 * Get 1588 rx hwstamp
595 * get_ts_info
596 * Get phc info
597 * clean_vf_config
598 * Clean residual vf info after disable sriov
599 * get_wol
600 * Get wake on lan info
601 * set_wol
602 * Config wake on lan
603 * dbg_get_read_func
604 * Return the read func for debugfs seq file
605 * set_pfc_prevention_tout
606 * Set PFC storm prevention timeout
607 * get_pfc_prevention_tout
608 * Get PFC storm prevention timeout
609 */
610 struct hnae3_ae_ops {
611 int (*init_ae_dev)(struct hnae3_ae_dev *ae_dev);
612 void (*uninit_ae_dev)(struct hnae3_ae_dev *ae_dev);
613 void (*reset_prepare)(struct hnae3_ae_dev *ae_dev,
614 enum hnae3_reset_type rst_type);
615 void (*reset_done)(struct hnae3_ae_dev *ae_dev);
616 int (*init_client_instance)(struct hnae3_client *client,
617 struct hnae3_ae_dev *ae_dev);
618 void (*uninit_client_instance)(struct hnae3_client *client,
619 struct hnae3_ae_dev *ae_dev);
620 int (*start)(struct hnae3_handle *handle);
621 void (*stop)(struct hnae3_handle *handle);
622 int (*client_start)(struct hnae3_handle *handle);
623 void (*client_stop)(struct hnae3_handle *handle);
624 int (*get_status)(struct hnae3_handle *handle);
625 void (*get_ksettings_an_result)(struct hnae3_handle *handle,
626 u8 *auto_neg, u32 *speed, u8 *duplex,
627 u32 *lane_num);
628
629 int (*cfg_mac_speed_dup_h)(struct hnae3_handle *handle, int speed,
630 u8 duplex, u8 lane_num);
631
632 void (*get_media_type)(struct hnae3_handle *handle, u8 *media_type,
633 u8 *module_type);
634 int (*check_port_speed)(struct hnae3_handle *handle, u32 speed);
635 void (*get_fec_stats)(struct hnae3_handle *handle,
636 struct ethtool_fec_stats *fec_stats);
637 void (*get_fec)(struct hnae3_handle *handle, u8 *fec_ability,
638 u8 *fec_mode);
639 int (*set_fec)(struct hnae3_handle *handle, u32 fec_mode);
640 void (*adjust_link)(struct hnae3_handle *handle, int speed, int duplex);
641 int (*set_loopback)(struct hnae3_handle *handle,
642 enum hnae3_loop loop_mode, bool en);
643
644 int (*set_promisc_mode)(struct hnae3_handle *handle, bool en_uc_pmc,
645 bool en_mc_pmc);
646 void (*request_update_promisc_mode)(struct hnae3_handle *handle);
647 int (*set_mtu)(struct hnae3_handle *handle, int new_mtu);
648
649 void (*get_pauseparam)(struct hnae3_handle *handle,
650 u32 *auto_neg, u32 *rx_en, u32 *tx_en);
651 int (*set_pauseparam)(struct hnae3_handle *handle,
652 u32 auto_neg, u32 rx_en, u32 tx_en);
653
654 int (*set_autoneg)(struct hnae3_handle *handle, bool enable);
655 int (*get_autoneg)(struct hnae3_handle *handle);
656 int (*restart_autoneg)(struct hnae3_handle *handle);
657 int (*halt_autoneg)(struct hnae3_handle *handle, bool halt);
658
659 void (*get_coalesce_usecs)(struct hnae3_handle *handle,
660 u32 *tx_usecs, u32 *rx_usecs);
661 void (*get_rx_max_coalesced_frames)(struct hnae3_handle *handle,
662 u32 *tx_frames, u32 *rx_frames);
663 int (*set_coalesce_usecs)(struct hnae3_handle *handle, u32 timeout);
664 int (*set_coalesce_frames)(struct hnae3_handle *handle,
665 u32 coalesce_frames);
666 void (*get_coalesce_range)(struct hnae3_handle *handle,
667 u32 *tx_frames_low, u32 *rx_frames_low,
668 u32 *tx_frames_high, u32 *rx_frames_high,
669 u32 *tx_usecs_low, u32 *rx_usecs_low,
670 u32 *tx_usecs_high, u32 *rx_usecs_high);
671
672 void (*get_mac_addr)(struct hnae3_handle *handle, u8 *p);
673 int (*set_mac_addr)(struct hnae3_handle *handle, const void *p,
674 bool is_first);
675 int (*do_ioctl)(struct hnae3_handle *handle,
676 struct ifreq *ifr, int cmd);
677 int (*add_uc_addr)(struct hnae3_handle *handle,
678 const unsigned char *addr);
679 int (*rm_uc_addr)(struct hnae3_handle *handle,
680 const unsigned char *addr);
681 int (*set_mc_addr)(struct hnae3_handle *handle, void *addr);
682 int (*add_mc_addr)(struct hnae3_handle *handle,
683 const unsigned char *addr);
684 int (*rm_mc_addr)(struct hnae3_handle *handle,
685 const unsigned char *addr);
686 void (*set_tso_stats)(struct hnae3_handle *handle, int enable);
687 void (*update_stats)(struct hnae3_handle *handle);
688 void (*get_stats)(struct hnae3_handle *handle, u64 *data);
689 void (*get_mac_stats)(struct hnae3_handle *handle,
690 struct hns3_mac_stats *mac_stats);
691 void (*get_strings)(struct hnae3_handle *handle,
692 u32 stringset, u8 **data);
693 int (*get_sset_count)(struct hnae3_handle *handle, int stringset);
694
695 void (*get_regs)(struct hnae3_handle *handle, u32 *version,
696 void *data);
697 int (*get_regs_len)(struct hnae3_handle *handle);
698
699 u32 (*get_rss_key_size)(struct hnae3_handle *handle);
700 int (*get_rss)(struct hnae3_handle *handle, u32 *indir, u8 *key,
701 u8 *hfunc);
702 int (*set_rss)(struct hnae3_handle *handle, const u32 *indir,
703 const u8 *key, const u8 hfunc);
704 int (*set_rss_tuple)(struct hnae3_handle *handle,
705 const struct ethtool_rxfh_fields *cmd);
706 int (*get_rss_tuple)(struct hnae3_handle *handle,
707 struct ethtool_rxfh_fields *cmd);
708
709 int (*get_tc_size)(struct hnae3_handle *handle);
710
711 int (*get_vector)(struct hnae3_handle *handle, u16 vector_num,
712 struct hnae3_vector_info *vector_info);
713 int (*put_vector)(struct hnae3_handle *handle, int vector_num);
714 int (*map_ring_to_vector)(struct hnae3_handle *handle,
715 int vector_num,
716 struct hnae3_ring_chain_node *vr_chain);
717 int (*unmap_ring_from_vector)(struct hnae3_handle *handle,
718 int vector_num,
719 struct hnae3_ring_chain_node *vr_chain);
720
721 int (*reset_queue)(struct hnae3_handle *handle);
722 u32 (*get_fw_version)(struct hnae3_handle *handle);
723 void (*get_mdix_mode)(struct hnae3_handle *handle,
724 u8 *tp_mdix_ctrl, u8 *tp_mdix);
725
726 int (*enable_vlan_filter)(struct hnae3_handle *handle, bool enable);
727 int (*set_vlan_filter)(struct hnae3_handle *handle, __be16 proto,
728 u16 vlan_id, bool is_kill);
729 int (*set_vf_vlan_filter)(struct hnae3_handle *handle, int vfid,
730 u16 vlan, u8 qos, __be16 proto);
731 int (*enable_hw_strip_rxvtag)(struct hnae3_handle *handle, bool enable);
732 void (*reset_event)(struct pci_dev *pdev, struct hnae3_handle *handle);
733 enum hnae3_reset_type (*get_reset_level)(struct hnae3_ae_dev *ae_dev,
734 unsigned long *addr);
735 void (*set_default_reset_request)(struct hnae3_ae_dev *ae_dev,
736 enum hnae3_reset_type rst_type);
737 void (*get_channels)(struct hnae3_handle *handle,
738 struct ethtool_channels *ch);
739 void (*get_tqps_and_rss_info)(struct hnae3_handle *h,
740 u16 *alloc_tqps, u16 *max_rss_size);
741 int (*set_channels)(struct hnae3_handle *handle, u32 new_tqps_num,
742 bool rxfh_configured);
743 void (*get_flowctrl_adv)(struct hnae3_handle *handle,
744 u32 *flowctrl_adv);
745 int (*set_led_id)(struct hnae3_handle *handle,
746 enum ethtool_phys_id_state status);
747 void (*get_link_mode)(struct hnae3_handle *handle,
748 unsigned long *supported,
749 unsigned long *advertising);
750 int (*add_fd_entry)(struct hnae3_handle *handle,
751 struct ethtool_rxnfc *cmd);
752 int (*del_fd_entry)(struct hnae3_handle *handle,
753 struct ethtool_rxnfc *cmd);
754 int (*get_fd_rule_cnt)(struct hnae3_handle *handle,
755 struct ethtool_rxnfc *cmd);
756 int (*get_fd_rule_info)(struct hnae3_handle *handle,
757 struct ethtool_rxnfc *cmd);
758 int (*get_fd_all_rules)(struct hnae3_handle *handle,
759 struct ethtool_rxnfc *cmd, u32 *rule_locs);
760 void (*enable_fd)(struct hnae3_handle *handle, bool enable);
761 int (*add_arfs_entry)(struct hnae3_handle *handle, u16 queue_id,
762 u16 flow_id, struct flow_keys *fkeys);
763 pci_ers_result_t (*handle_hw_ras_error)(struct hnae3_ae_dev *ae_dev);
764 bool (*get_hw_reset_stat)(struct hnae3_handle *handle);
765 bool (*ae_dev_resetting)(struct hnae3_handle *handle);
766 unsigned long (*ae_dev_reset_cnt)(struct hnae3_handle *handle);
767 int (*set_gro_en)(struct hnae3_handle *handle, bool enable);
768 u16 (*get_global_queue_id)(struct hnae3_handle *handle, u16 queue_id);
769 void (*set_timer_task)(struct hnae3_handle *handle, bool enable);
770 int (*mac_connect_phy)(struct hnae3_handle *handle);
771 void (*mac_disconnect_phy)(struct hnae3_handle *handle);
772 int (*get_vf_config)(struct hnae3_handle *handle, int vf,
773 struct ifla_vf_info *ivf);
774 int (*set_vf_link_state)(struct hnae3_handle *handle, int vf,
775 int link_state);
776 int (*set_vf_spoofchk)(struct hnae3_handle *handle, int vf,
777 bool enable);
778 int (*set_vf_trust)(struct hnae3_handle *handle, int vf, bool enable);
779 int (*set_vf_rate)(struct hnae3_handle *handle, int vf,
780 int min_tx_rate, int max_tx_rate, bool force);
781 int (*set_vf_mac)(struct hnae3_handle *handle, int vf, u8 *p);
782 int (*get_module_eeprom)(struct hnae3_handle *handle, u32 offset,
783 u32 len, u8 *data);
784 bool (*get_cmdq_stat)(struct hnae3_handle *handle);
785 int (*add_cls_flower)(struct hnae3_handle *handle,
786 struct flow_cls_offload *cls_flower);
787 int (*del_cls_flower)(struct hnae3_handle *handle,
788 struct flow_cls_offload *cls_flower);
789 bool (*cls_flower_active)(struct hnae3_handle *handle);
790 int (*get_phy_link_ksettings)(struct hnae3_handle *handle,
791 struct ethtool_link_ksettings *cmd);
792 int (*set_phy_link_ksettings)(struct hnae3_handle *handle,
793 const struct ethtool_link_ksettings *cmd);
794 bool (*set_tx_hwts_info)(struct hnae3_handle *handle,
795 struct sk_buff *skb);
796 void (*get_rx_hwts)(struct hnae3_handle *handle, struct sk_buff *skb,
797 u32 nsec, u32 sec);
798 int (*get_ts_info)(struct hnae3_handle *handle,
799 struct kernel_ethtool_ts_info *info);
800 int (*get_link_diagnosis_info)(struct hnae3_handle *handle,
801 u32 *status_code);
802 void (*clean_vf_config)(struct hnae3_ae_dev *ae_dev, int num_vfs);
803 int (*get_dscp_prio)(struct hnae3_handle *handle, u8 dscp,
804 u8 *tc_map_mode, u8 *priority);
805 void (*get_wol)(struct hnae3_handle *handle,
806 struct ethtool_wolinfo *wol);
807 int (*set_wol)(struct hnae3_handle *handle,
808 struct ethtool_wolinfo *wol);
809 int (*dbg_get_read_func)(struct hnae3_handle *handle,
810 enum hnae3_dbg_cmd cmd,
811 read_func *func);
812 int (*hwtstamp_get)(struct hnae3_handle *handle,
813 struct kernel_hwtstamp_config *config);
814 int (*hwtstamp_set)(struct hnae3_handle *handle,
815 struct kernel_hwtstamp_config *config,
816 struct netlink_ext_ack *extack);
817 int (*set_pfc_prevention_tout)(struct hnae3_handle *handle, u16 times);
818 int (*get_pfc_prevention_tout)(struct hnae3_handle *handle, u16 *times);
819 };
820
821 struct hnae3_dcb_ops {
822 /* IEEE 802.1Qaz std */
823 int (*ieee_getets)(struct hnae3_handle *, struct ieee_ets *);
824 int (*ieee_setets)(struct hnae3_handle *, struct ieee_ets *);
825 int (*ieee_getpfc)(struct hnae3_handle *, struct ieee_pfc *);
826 int (*ieee_setpfc)(struct hnae3_handle *, struct ieee_pfc *);
827 int (*ieee_setapp)(struct hnae3_handle *h, struct dcb_app *app);
828 int (*ieee_delapp)(struct hnae3_handle *h, struct dcb_app *app);
829
830 /* DCBX configuration */
831 u8 (*getdcbx)(struct hnae3_handle *);
832 u8 (*setdcbx)(struct hnae3_handle *, u8);
833
834 int (*setup_tc)(struct hnae3_handle *handle,
835 struct tc_mqprio_qopt_offload *mqprio_qopt);
836 };
837
838 struct hnae3_ae_algo {
839 const struct hnae3_ae_ops *ops;
840 struct list_head node;
841 const struct pci_device_id *pdev_id_table;
842 };
843
844 #define HNAE3_INT_NAME_LEN 32
845 #define HNAE3_ITR_COUNTDOWN_START 100
846
847 #define HNAE3_MAX_TC 8
848 #define HNAE3_MAX_USER_PRIO 8
849 struct hnae3_tc_info {
850 u8 prio_tc[HNAE3_MAX_USER_PRIO]; /* TC indexed by prio */
851 u16 tqp_count[HNAE3_MAX_TC];
852 u16 tqp_offset[HNAE3_MAX_TC];
853 u8 max_tc; /* Total number of TCs */
854 u8 num_tc; /* Total number of enabled TCs */
855 bool mqprio_active;
856 bool mqprio_destroy;
857 bool dcb_ets_active;
858 };
859
860 #define HNAE3_MAX_DSCP 64
861 #define HNAE3_PRIO_ID_INVALID 0xff
862 struct hnae3_knic_private_info {
863 struct net_device *netdev; /* Set by KNIC client when init instance */
864 u16 rss_size; /* Allocated RSS queues */
865 u16 req_rss_size;
866 u16 rx_buf_len;
867 u16 num_tx_desc;
868 u16 num_rx_desc;
869 u32 tx_spare_buf_size;
870
871 struct hnae3_tc_info tc_info;
872 u8 tc_map_mode;
873 u8 dscp_app_cnt;
874 u8 dscp_prio[HNAE3_MAX_DSCP];
875
876 u16 num_tqps; /* total number of TQPs in this handle */
877 struct hnae3_queue **tqp; /* array base of all TQPs in this instance */
878 const struct hnae3_dcb_ops *dcb_ops;
879
880 u16 int_rl_setting;
881 void __iomem *io_base;
882 };
883
884 struct hnae3_roce_private_info {
885 struct net_device *netdev;
886 void __iomem *roce_io_base;
887 void __iomem *roce_mem_base;
888 int base_vector;
889 int num_vectors;
890
891 /* The below attributes defined for RoCE client, hnae3 gives
892 * initial values to them, and RoCE client can modify and use
893 * them.
894 */
895 unsigned long reset_state;
896 unsigned long instance_state;
897 unsigned long state;
898 };
899
900 struct hnae3_pfc_storm_para {
901 u32 dir;
902 u32 enable;
903 u32 period_ms;
904 u32 times;
905 u32 recovery_period_ms;
906 };
907
908 #define HNAE3_SUPPORT_APP_LOOPBACK BIT(0)
909 #define HNAE3_SUPPORT_PHY_LOOPBACK BIT(1)
910 #define HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK BIT(2)
911 #define HNAE3_SUPPORT_VF BIT(3)
912 #define HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK BIT(4)
913 #define HNAE3_SUPPORT_EXTERNAL_LOOPBACK BIT(5)
914
915 #define HNAE3_USER_UPE BIT(0) /* unicast promisc enabled by user */
916 #define HNAE3_USER_MPE BIT(1) /* mulitcast promisc enabled by user */
917 #define HNAE3_BPE BIT(2) /* broadcast promisc enable */
918 #define HNAE3_OVERFLOW_UPE BIT(3) /* unicast mac vlan overflow */
919 #define HNAE3_OVERFLOW_MPE BIT(4) /* multicast mac vlan overflow */
920 #define HNAE3_UPE (HNAE3_USER_UPE | HNAE3_OVERFLOW_UPE)
921 #define HNAE3_MPE (HNAE3_USER_MPE | HNAE3_OVERFLOW_MPE)
922
923 enum hnae3_pflag {
924 HNAE3_PFLAG_LIMIT_PROMISC,
925 HNAE3_PFLAG_MAX
926 };
927
928 struct hnae3_handle {
929 struct hnae3_client *client;
930 struct pci_dev *pdev;
931 void *priv;
932 struct hnae3_ae_algo *ae_algo; /* the class who provides this handle */
933 u64 flags; /* Indicate the capabilities for this handle */
934
935 union {
936 struct net_device *netdev; /* first member */
937 struct hnae3_knic_private_info kinfo;
938 struct hnae3_roce_private_info rinfo;
939 };
940
941 nodemask_t numa_node_mask; /* for multi-chip support */
942
943 enum hnae3_port_base_vlan_state port_base_vlan_state;
944
945 u8 netdev_flags;
946 struct dentry *hnae3_dbgfs;
947
948 /* Network interface message level enabled bits */
949 u32 msg_enable;
950
951 unsigned long supported_pflags;
952 unsigned long priv_flags;
953 };
954
955 #define hnae3_set_field(origin, mask, shift, val) \
956 do { \
957 (origin) &= (~(mask)); \
958 (origin) |= ((val) << (shift)) & (mask); \
959 } while (0)
960 #define hnae3_get_field(origin, mask, shift) (((origin) & (mask)) >> (shift))
961
962 #define hnae3_set_bit(origin, shift, val) \
963 hnae3_set_field(origin, 0x1 << (shift), shift, val)
964 #define hnae3_get_bit(origin, shift) \
965 hnae3_get_field(origin, 0x1 << (shift), shift)
966
967 #define HNAE3_FORMAT_MAC_ADDR_LEN 18
968 #define HNAE3_FORMAT_MAC_ADDR_OFFSET_0 0
969 #define HNAE3_FORMAT_MAC_ADDR_OFFSET_4 4
970 #define HNAE3_FORMAT_MAC_ADDR_OFFSET_5 5
971
hnae3_format_mac_addr(char * format_mac_addr,const u8 * mac_addr)972 static inline void hnae3_format_mac_addr(char *format_mac_addr,
973 const u8 *mac_addr)
974 {
975 snprintf(format_mac_addr, HNAE3_FORMAT_MAC_ADDR_LEN, "%02x:**:**:**:%02x:%02x",
976 mac_addr[HNAE3_FORMAT_MAC_ADDR_OFFSET_0],
977 mac_addr[HNAE3_FORMAT_MAC_ADDR_OFFSET_4],
978 mac_addr[HNAE3_FORMAT_MAC_ADDR_OFFSET_5]);
979 }
980
981 int hnae3_register_ae_dev(struct hnae3_ae_dev *ae_dev);
982 void hnae3_unregister_ae_dev(struct hnae3_ae_dev *ae_dev);
983
984 void hnae3_unregister_ae_algo_prepare(struct hnae3_ae_algo *ae_algo);
985 void hnae3_unregister_ae_algo(struct hnae3_ae_algo *ae_algo);
986 void hnae3_register_ae_algo(struct hnae3_ae_algo *ae_algo);
987
988 void hnae3_unregister_client(struct hnae3_client *client);
989 int hnae3_register_client(struct hnae3_client *client);
990
991 void hnae3_set_client_init_flag(struct hnae3_client *client,
992 struct hnae3_ae_dev *ae_dev,
993 unsigned int inited);
994 void hnae3_acquire_unload_lock(void);
995 void hnae3_release_unload_lock(void);
996 #endif
997