1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
4 *
5 * Author: Vitor Soares <vitor.soares@synopsys.com>
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/bitops.h>
10 #include <linux/cleanup.h>
11 #include <linux/clk.h>
12 #include <linux/completion.h>
13 #include <linux/err.h>
14 #include <linux/errno.h>
15 #include <linux/i3c/master.h>
16 #include <linux/interrupt.h>
17 #include <linux/ioport.h>
18 #include <linux/iopoll.h>
19 #include <linux/list.h>
20 #include <linux/module.h>
21 #include <linux/of.h>
22 #include <linux/pinctrl/consumer.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/reset.h>
26 #include <linux/slab.h>
27
28 #include "../internals.h"
29 #include "dw-i3c-master.h"
30
31 #define DEVICE_CTRL 0x0
32 #define DEV_CTRL_ENABLE BIT(31)
33 #define DEV_CTRL_RESUME BIT(30)
34 #define DEV_CTRL_HOT_JOIN_NACK BIT(8)
35 #define DEV_CTRL_I2C_SLAVE_PRESENT BIT(7)
36
37 #define DEVICE_ADDR 0x4
38 #define DEV_ADDR_DYNAMIC_ADDR_VALID BIT(31)
39 #define DEV_ADDR_DYNAMIC(x) (((x) << 16) & GENMASK(22, 16))
40
41 #define HW_CAPABILITY 0x8
42 #define COMMAND_QUEUE_PORT 0xc
43 #define COMMAND_PORT_TOC BIT(30)
44 #define COMMAND_PORT_READ_TRANSFER BIT(28)
45 #define COMMAND_PORT_SDAP BIT(27)
46 #define COMMAND_PORT_ROC BIT(26)
47 #define COMMAND_PORT_SPEED(x) (((x) << 21) & GENMASK(23, 21))
48 #define COMMAND_PORT_DEV_INDEX(x) (((x) << 16) & GENMASK(20, 16))
49 #define COMMAND_PORT_CP BIT(15)
50 #define COMMAND_PORT_CMD(x) (((x) << 7) & GENMASK(14, 7))
51 #define COMMAND_PORT_TID(x) (((x) << 3) & GENMASK(6, 3))
52
53 #define COMMAND_PORT_ARG_DATA_LEN(x) (((x) << 16) & GENMASK(31, 16))
54 #define COMMAND_PORT_ARG_DATA_LEN_MAX 65536
55 #define COMMAND_PORT_TRANSFER_ARG 0x01
56
57 #define COMMAND_PORT_SDA_DATA_BYTE_3(x) (((x) << 24) & GENMASK(31, 24))
58 #define COMMAND_PORT_SDA_DATA_BYTE_2(x) (((x) << 16) & GENMASK(23, 16))
59 #define COMMAND_PORT_SDA_DATA_BYTE_1(x) (((x) << 8) & GENMASK(15, 8))
60 #define COMMAND_PORT_SDA_BYTE_STRB_3 BIT(5)
61 #define COMMAND_PORT_SDA_BYTE_STRB_2 BIT(4)
62 #define COMMAND_PORT_SDA_BYTE_STRB_1 BIT(3)
63 #define COMMAND_PORT_SHORT_DATA_ARG 0x02
64
65 #define COMMAND_PORT_DEV_COUNT(x) (((x) << 21) & GENMASK(25, 21))
66 #define COMMAND_PORT_ADDR_ASSGN_CMD 0x03
67
68 #define RESPONSE_QUEUE_PORT 0x10
69 #define RESPONSE_PORT_ERR_STATUS(x) (((x) & GENMASK(31, 28)) >> 28)
70 #define RESPONSE_NO_ERROR 0
71 #define RESPONSE_ERROR_CRC 1
72 #define RESPONSE_ERROR_PARITY 2
73 #define RESPONSE_ERROR_FRAME 3
74 #define RESPONSE_ERROR_IBA_NACK 4
75 #define RESPONSE_ERROR_ADDRESS_NACK 5
76 #define RESPONSE_ERROR_OVER_UNDER_FLOW 6
77 #define RESPONSE_ERROR_TRANSF_ABORT 8
78 #define RESPONSE_ERROR_I2C_W_NACK_ERR 9
79 #define RESPONSE_PORT_TID(x) (((x) & GENMASK(27, 24)) >> 24)
80 #define RESPONSE_PORT_DATA_LEN(x) ((x) & GENMASK(15, 0))
81
82 #define RX_TX_DATA_PORT 0x14
83 #define IBI_QUEUE_STATUS 0x18
84 #define IBI_QUEUE_STATUS_IBI_ID(x) (((x) & GENMASK(15, 8)) >> 8)
85 #define IBI_QUEUE_STATUS_DATA_LEN(x) ((x) & GENMASK(7, 0))
86 #define IBI_QUEUE_IBI_ADDR(x) (IBI_QUEUE_STATUS_IBI_ID(x) >> 1)
87 #define IBI_QUEUE_IBI_RNW(x) (IBI_QUEUE_STATUS_IBI_ID(x) & BIT(0))
88 #define IBI_TYPE_MR(x) \
89 ((IBI_QUEUE_IBI_ADDR(x) != I3C_HOT_JOIN_ADDR) && !IBI_QUEUE_IBI_RNW(x))
90 #define IBI_TYPE_HJ(x) \
91 ((IBI_QUEUE_IBI_ADDR(x) == I3C_HOT_JOIN_ADDR) && !IBI_QUEUE_IBI_RNW(x))
92 #define IBI_TYPE_SIRQ(x) \
93 ((IBI_QUEUE_IBI_ADDR(x) != I3C_HOT_JOIN_ADDR) && IBI_QUEUE_IBI_RNW(x))
94
95 #define QUEUE_THLD_CTRL 0x1c
96 #define QUEUE_THLD_CTRL_IBI_STAT_MASK GENMASK(31, 24)
97 #define QUEUE_THLD_CTRL_IBI_STAT(x) (((x) - 1) << 24)
98 #define QUEUE_THLD_CTRL_IBI_DATA_MASK GENMASK(20, 16)
99 #define QUEUE_THLD_CTRL_IBI_DATA(x) ((x) << 16)
100 #define QUEUE_THLD_CTRL_RESP_BUF_MASK GENMASK(15, 8)
101 #define QUEUE_THLD_CTRL_RESP_BUF(x) (((x) - 1) << 8)
102
103 #define DATA_BUFFER_THLD_CTRL 0x20
104 #define DATA_BUFFER_THLD_CTRL_RX_BUF GENMASK(11, 8)
105
106 #define IBI_QUEUE_CTRL 0x24
107 #define IBI_MR_REQ_REJECT 0x2C
108 #define IBI_SIR_REQ_REJECT 0x30
109 #define IBI_REQ_REJECT_ALL GENMASK(31, 0)
110
111 #define RESET_CTRL 0x34
112 #define RESET_CTRL_IBI_QUEUE BIT(5)
113 #define RESET_CTRL_RX_FIFO BIT(4)
114 #define RESET_CTRL_TX_FIFO BIT(3)
115 #define RESET_CTRL_RESP_QUEUE BIT(2)
116 #define RESET_CTRL_CMD_QUEUE BIT(1)
117 #define RESET_CTRL_SOFT BIT(0)
118
119 #define SLV_EVENT_CTRL 0x38
120 #define INTR_STATUS 0x3c
121 #define INTR_STATUS_EN 0x40
122 #define INTR_SIGNAL_EN 0x44
123 #define INTR_FORCE 0x48
124 #define INTR_BUSOWNER_UPDATE_STAT BIT(13)
125 #define INTR_IBI_UPDATED_STAT BIT(12)
126 #define INTR_READ_REQ_RECV_STAT BIT(11)
127 #define INTR_DEFSLV_STAT BIT(10)
128 #define INTR_TRANSFER_ERR_STAT BIT(9)
129 #define INTR_DYN_ADDR_ASSGN_STAT BIT(8)
130 #define INTR_CCC_UPDATED_STAT BIT(6)
131 #define INTR_TRANSFER_ABORT_STAT BIT(5)
132 #define INTR_RESP_READY_STAT BIT(4)
133 #define INTR_CMD_QUEUE_READY_STAT BIT(3)
134 #define INTR_IBI_THLD_STAT BIT(2)
135 #define INTR_RX_THLD_STAT BIT(1)
136 #define INTR_TX_THLD_STAT BIT(0)
137 #define INTR_ALL (INTR_BUSOWNER_UPDATE_STAT | \
138 INTR_IBI_UPDATED_STAT | \
139 INTR_READ_REQ_RECV_STAT | \
140 INTR_DEFSLV_STAT | \
141 INTR_TRANSFER_ERR_STAT | \
142 INTR_DYN_ADDR_ASSGN_STAT | \
143 INTR_CCC_UPDATED_STAT | \
144 INTR_TRANSFER_ABORT_STAT | \
145 INTR_RESP_READY_STAT | \
146 INTR_CMD_QUEUE_READY_STAT | \
147 INTR_IBI_THLD_STAT | \
148 INTR_TX_THLD_STAT | \
149 INTR_RX_THLD_STAT)
150
151 #define INTR_MASTER_MASK (INTR_TRANSFER_ERR_STAT | \
152 INTR_RESP_READY_STAT)
153
154 #define QUEUE_STATUS_LEVEL 0x4c
155 #define QUEUE_STATUS_IBI_STATUS_CNT(x) (((x) & GENMASK(28, 24)) >> 24)
156 #define QUEUE_STATUS_IBI_BUF_BLR(x) (((x) & GENMASK(23, 16)) >> 16)
157 #define QUEUE_STATUS_LEVEL_RESP(x) (((x) & GENMASK(15, 8)) >> 8)
158 #define QUEUE_STATUS_LEVEL_CMD(x) ((x) & GENMASK(7, 0))
159
160 #define DATA_BUFFER_STATUS_LEVEL 0x50
161 #define DATA_BUFFER_STATUS_LEVEL_TX(x) ((x) & GENMASK(7, 0))
162
163 #define PRESENT_STATE 0x54
164 #define CCC_DEVICE_STATUS 0x58
165 #define DEVICE_ADDR_TABLE_POINTER 0x5c
166 #define DEVICE_ADDR_TABLE_DEPTH(x) (((x) & GENMASK(31, 16)) >> 16)
167 #define DEVICE_ADDR_TABLE_ADDR(x) ((x) & GENMASK(7, 0))
168
169 #define DEV_CHAR_TABLE_POINTER 0x60
170 #define VENDOR_SPECIFIC_REG_POINTER 0x6c
171 #define SLV_PID_VALUE 0x74
172 #define SLV_CHAR_CTRL 0x78
173 #define SLV_MAX_LEN 0x7c
174 #define MAX_READ_TURNAROUND 0x80
175 #define MAX_DATA_SPEED 0x84
176 #define SLV_DEBUG_STATUS 0x88
177 #define SLV_INTR_REQ 0x8c
178 #define DEVICE_CTRL_EXTENDED 0xb0
179 #define SCL_I3C_OD_TIMING 0xb4
180 #define SCL_I3C_PP_TIMING 0xb8
181 #define SCL_I3C_TIMING_HCNT(x) (((x) << 16) & GENMASK(23, 16))
182 #define SCL_I3C_TIMING_LCNT(x) ((x) & GENMASK(7, 0))
183 #define SCL_I3C_TIMING_CNT_MIN 5
184
185 #define SCL_I2C_FM_TIMING 0xbc
186 #define SCL_I2C_FM_TIMING_HCNT(x) (((x) << 16) & GENMASK(31, 16))
187 #define SCL_I2C_FM_TIMING_LCNT(x) ((x) & GENMASK(15, 0))
188
189 #define SCL_I2C_FMP_TIMING 0xc0
190 #define SCL_I2C_FMP_TIMING_HCNT(x) (((x) << 16) & GENMASK(23, 16))
191 #define SCL_I2C_FMP_TIMING_LCNT(x) ((x) & GENMASK(15, 0))
192
193 #define SCL_EXT_LCNT_TIMING 0xc8
194 #define SCL_EXT_LCNT_4(x) (((x) << 24) & GENMASK(31, 24))
195 #define SCL_EXT_LCNT_3(x) (((x) << 16) & GENMASK(23, 16))
196 #define SCL_EXT_LCNT_2(x) (((x) << 8) & GENMASK(15, 8))
197 #define SCL_EXT_LCNT_1(x) ((x) & GENMASK(7, 0))
198
199 #define SCL_EXT_TERMN_LCNT_TIMING 0xcc
200 #define BUS_FREE_TIMING 0xd4
201 #define BUS_I3C_MST_FREE(x) ((x) & GENMASK(15, 0))
202
203 #define BUS_IDLE_TIMING 0xd8
204 #define I3C_VER_ID 0xe0
205 #define I3C_VER_TYPE 0xe4
206 #define EXTENDED_CAPABILITY 0xe8
207 #define SLAVE_CONFIG 0xec
208
209 #define DYN_ADDR_LO_MASK GENMASK(4, 0)
210 #define DYN_ADDR_HI_MASK GENMASK(6, 5)
211 #define IBI_SIR_BIT_MOD 32 /* 32-bit vector */
212
213 #define DW_I3C_DEV_NACK_RETRY_CNT_MAX 0x3
214 #define DEV_ADDR_TABLE_DEV_NACK_RETRY_MASK GENMASK(30, 29)
215 #define DEV_ADDR_TABLE_DYNAMIC_MASK GENMASK(23, 16)
216 #define DEV_ADDR_TABLE_STATIC_MASK GENMASK(6, 0)
217 #define DEV_ADDR_TABLE_IBI_MDB BIT(12)
218 #define DEV_ADDR_TABLE_SIR_REJECT BIT(13)
219 #define DEV_ADDR_TABLE_DEV_NACK_RETRY_CNT(x) \
220 FIELD_PREP(DEV_ADDR_TABLE_DEV_NACK_RETRY_MASK, (x))
221 #define DEV_ADDR_TABLE_LEGACY_I2C_DEV BIT(31)
222 #define DEV_ADDR_TABLE_DYNAMIC_ADDR(x) FIELD_PREP(DEV_ADDR_TABLE_DYNAMIC_MASK, x)
223 #define DEV_ADDR_TABLE_STATIC_ADDR(x) FIELD_PREP(DEV_ADDR_TABLE_STATIC_MASK, x)
224 #define DEV_ADDR_TABLE_LOC(start, idx) ((start) + ((idx) << 2))
225 #define DEV_ADDR_TABLE_GET_DYNAMIC_ADDR(x) FIELD_GET(DEV_ADDR_TABLE_DYNAMIC_MASK, x)
226
227 #define I3C_BUS_SDR1_SCL_RATE 8000000
228 #define I3C_BUS_SDR2_SCL_RATE 6000000
229 #define I3C_BUS_SDR3_SCL_RATE 4000000
230 #define I3C_BUS_SDR4_SCL_RATE 2000000
231 #define I3C_BUS_I2C_FM_TLOW_MIN_NS 1300
232 #define I3C_BUS_I2C_FMP_TLOW_MIN_NS 500
233 #define I3C_BUS_THIGH_MAX_NS 41
234
235 #define XFER_TIMEOUT (msecs_to_jiffies(1000))
236 #define RPM_AUTOSUSPEND_TIMEOUT 1000 /* ms */
237
238 /* Timing values to configure 12.5MHz frequency */
239 #define AMD_I3C_OD_TIMING 0x4C007C
240 #define AMD_I3C_PP_TIMING 0x8001A
241
242 /* List of quirks */
243 #define AMD_I3C_OD_PP_TIMING BIT(1)
244 #define DW_I3C_DISABLE_RUNTIME_PM_QUIRK BIT(2)
245
246 struct dw_i3c_cmd {
247 u32 cmd_lo;
248 u32 cmd_hi;
249 u16 tx_len;
250 const void *tx_buf;
251 u16 rx_len;
252 void *rx_buf;
253 u8 error;
254 };
255
256 struct dw_i3c_xfer {
257 struct list_head node;
258 struct completion comp;
259 int ret;
260 unsigned int ncmds;
261 struct dw_i3c_cmd cmds[] __counted_by(ncmds);
262 };
263
264 struct dw_i3c_i2c_dev_data {
265 u8 index;
266 struct i3c_generic_ibi_pool *ibi_pool;
267 };
268
269 struct dw_i3c_drvdata {
270 u32 flags;
271 };
272
get_ibi_sir_bit_index(u8 addr)273 static inline u32 get_ibi_sir_bit_index(u8 addr)
274 {
275 u32 lo = FIELD_GET(DYN_ADDR_LO_MASK, addr);
276 u32 hi = FIELD_GET(DYN_ADDR_HI_MASK, addr);
277
278 return (lo + hi) % IBI_SIR_BIT_MOD;
279 }
280
dw_i3c_master_supports_ccc_cmd(struct i3c_master_controller * m,const struct i3c_ccc_cmd * cmd)281 static bool dw_i3c_master_supports_ccc_cmd(struct i3c_master_controller *m,
282 const struct i3c_ccc_cmd *cmd)
283 {
284 if (cmd->ndests > 1)
285 return false;
286
287 switch (cmd->id) {
288 case I3C_CCC_ENEC(true):
289 case I3C_CCC_ENEC(false):
290 case I3C_CCC_DISEC(true):
291 case I3C_CCC_DISEC(false):
292 case I3C_CCC_ENTAS(0, true):
293 case I3C_CCC_ENTAS(0, false):
294 case I3C_CCC_RSTDAA(true):
295 case I3C_CCC_RSTDAA(false):
296 case I3C_CCC_ENTDAA:
297 case I3C_CCC_SETMWL(true):
298 case I3C_CCC_SETMWL(false):
299 case I3C_CCC_SETMRL(true):
300 case I3C_CCC_SETMRL(false):
301 case I3C_CCC_ENTHDR(0):
302 case I3C_CCC_SETDASA:
303 case I3C_CCC_SETNEWDA:
304 case I3C_CCC_GETMWL:
305 case I3C_CCC_GETMRL:
306 case I3C_CCC_GETPID:
307 case I3C_CCC_GETBCR:
308 case I3C_CCC_GETDCR:
309 case I3C_CCC_GETSTATUS:
310 case I3C_CCC_GETMXDS:
311 case I3C_CCC_GETHDRCAP:
312 return true;
313 default:
314 return false;
315 }
316 }
317
318 static inline struct dw_i3c_master *
to_dw_i3c_master(struct i3c_master_controller * master)319 to_dw_i3c_master(struct i3c_master_controller *master)
320 {
321 return container_of(master, struct dw_i3c_master, base);
322 }
323
dw_i3c_master_disable(struct dw_i3c_master * master)324 static void dw_i3c_master_disable(struct dw_i3c_master *master)
325 {
326 writel(readl(master->regs + DEVICE_CTRL) & ~DEV_CTRL_ENABLE,
327 master->regs + DEVICE_CTRL);
328 }
329
dw_i3c_master_enable(struct dw_i3c_master * master)330 static void dw_i3c_master_enable(struct dw_i3c_master *master)
331 {
332 u32 dev_ctrl;
333
334 dev_ctrl = readl(master->regs + DEVICE_CTRL);
335 /* For now don't support Hot-Join */
336 dev_ctrl |= DEV_CTRL_HOT_JOIN_NACK;
337 if (master->i2c_slv_prsnt)
338 dev_ctrl |= DEV_CTRL_I2C_SLAVE_PRESENT;
339 writel(dev_ctrl | DEV_CTRL_ENABLE,
340 master->regs + DEVICE_CTRL);
341 }
342
dw_i3c_master_get_addr_pos(struct dw_i3c_master * master,u8 addr)343 static int dw_i3c_master_get_addr_pos(struct dw_i3c_master *master, u8 addr)
344 {
345 int pos;
346
347 for (pos = 0; pos < master->maxdevs; pos++) {
348 if (addr == master->devs[pos].addr)
349 return pos;
350 }
351
352 return -EINVAL;
353 }
354
dw_i3c_master_get_free_pos(struct dw_i3c_master * master)355 static int dw_i3c_master_get_free_pos(struct dw_i3c_master *master)
356 {
357 if (!(master->free_pos & GENMASK(master->maxdevs - 1, 0)))
358 return -ENOSPC;
359
360 return ffs(master->free_pos) - 1;
361 }
362
dw_i3c_master_wr_tx_fifo(struct dw_i3c_master * master,const u8 * bytes,int nbytes)363 static void dw_i3c_master_wr_tx_fifo(struct dw_i3c_master *master,
364 const u8 *bytes, int nbytes)
365 {
366 i3c_writel_fifo(master->regs + RX_TX_DATA_PORT, bytes, nbytes);
367 }
368
dw_i3c_master_read_rx_fifo(struct dw_i3c_master * master,u8 * bytes,int nbytes)369 static void dw_i3c_master_read_rx_fifo(struct dw_i3c_master *master,
370 u8 *bytes, int nbytes)
371 {
372 i3c_readl_fifo(master->regs + RX_TX_DATA_PORT, bytes, nbytes);
373 }
374
dw_i3c_master_read_ibi_fifo(struct dw_i3c_master * master,u8 * bytes,int nbytes)375 static void dw_i3c_master_read_ibi_fifo(struct dw_i3c_master *master,
376 u8 *bytes, int nbytes)
377 {
378 i3c_readl_fifo(master->regs + IBI_QUEUE_STATUS, bytes, nbytes);
379 }
380
381 static struct dw_i3c_xfer *
dw_i3c_master_alloc_xfer(struct dw_i3c_master * master,unsigned int ncmds)382 dw_i3c_master_alloc_xfer(struct dw_i3c_master *master, unsigned int ncmds)
383 {
384 struct dw_i3c_xfer *xfer;
385
386 xfer = kzalloc_flex(*xfer, cmds, ncmds);
387 if (!xfer)
388 return NULL;
389
390 INIT_LIST_HEAD(&xfer->node);
391 xfer->ncmds = ncmds;
392 xfer->ret = -ETIMEDOUT;
393
394 return xfer;
395 }
396
dw_i3c_master_start_xfer_locked(struct dw_i3c_master * master)397 static void dw_i3c_master_start_xfer_locked(struct dw_i3c_master *master)
398 {
399 struct dw_i3c_xfer *xfer = master->xferqueue.cur;
400 unsigned int i;
401 u32 thld_ctrl;
402
403 if (!xfer)
404 return;
405
406 for (i = 0; i < xfer->ncmds; i++) {
407 struct dw_i3c_cmd *cmd = &xfer->cmds[i];
408
409 dw_i3c_master_wr_tx_fifo(master, cmd->tx_buf, cmd->tx_len);
410 }
411
412 thld_ctrl = readl(master->regs + QUEUE_THLD_CTRL);
413 thld_ctrl &= ~QUEUE_THLD_CTRL_RESP_BUF_MASK;
414 thld_ctrl |= QUEUE_THLD_CTRL_RESP_BUF(xfer->ncmds);
415 writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL);
416
417 for (i = 0; i < xfer->ncmds; i++) {
418 struct dw_i3c_cmd *cmd = &xfer->cmds[i];
419
420 writel(cmd->cmd_hi, master->regs + COMMAND_QUEUE_PORT);
421 writel(cmd->cmd_lo, master->regs + COMMAND_QUEUE_PORT);
422 }
423 }
424
dw_i3c_master_enqueue_xfer(struct dw_i3c_master * master,struct dw_i3c_xfer * xfer)425 static void dw_i3c_master_enqueue_xfer(struct dw_i3c_master *master,
426 struct dw_i3c_xfer *xfer)
427 {
428 init_completion(&xfer->comp);
429 guard(spinlock_irqsave)(&master->xferqueue.lock);
430 if (master->xferqueue.cur) {
431 list_add_tail(&xfer->node, &master->xferqueue.list);
432 } else {
433 master->xferqueue.cur = xfer;
434 dw_i3c_master_start_xfer_locked(master);
435 }
436 }
437
dw_i3c_master_dequeue_xfer_locked(struct dw_i3c_master * master,struct dw_i3c_xfer * xfer)438 static void dw_i3c_master_dequeue_xfer_locked(struct dw_i3c_master *master,
439 struct dw_i3c_xfer *xfer)
440 {
441 if (master->xferqueue.cur == xfer) {
442 u32 status;
443
444 master->xferqueue.cur = NULL;
445
446 writel(RESET_CTRL_RX_FIFO | RESET_CTRL_TX_FIFO |
447 RESET_CTRL_RESP_QUEUE | RESET_CTRL_CMD_QUEUE,
448 master->regs + RESET_CTRL);
449
450 readl_poll_timeout_atomic(master->regs + RESET_CTRL, status,
451 !status, 10, 1000000);
452 } else {
453 list_del_init(&xfer->node);
454 }
455 }
456
dw_i3c_master_dequeue_xfer(struct dw_i3c_master * master,struct dw_i3c_xfer * xfer)457 static void dw_i3c_master_dequeue_xfer(struct dw_i3c_master *master,
458 struct dw_i3c_xfer *xfer)
459 {
460 guard(spinlock_irqsave)(&master->xferqueue.lock);
461 dw_i3c_master_dequeue_xfer_locked(master, xfer);
462 }
463
dw_i3c_master_end_xfer_locked(struct dw_i3c_master * master,u32 isr)464 static void dw_i3c_master_end_xfer_locked(struct dw_i3c_master *master, u32 isr)
465 {
466 struct dw_i3c_xfer *xfer = master->xferqueue.cur;
467 int i, ret = 0;
468 u32 nresp;
469
470 if (!xfer)
471 return;
472
473 nresp = readl(master->regs + QUEUE_STATUS_LEVEL);
474 nresp = QUEUE_STATUS_LEVEL_RESP(nresp);
475
476 for (i = 0; i < nresp; i++) {
477 struct dw_i3c_cmd *cmd;
478 u32 resp;
479
480 resp = readl(master->regs + RESPONSE_QUEUE_PORT);
481
482 cmd = &xfer->cmds[RESPONSE_PORT_TID(resp)];
483 cmd->rx_len = RESPONSE_PORT_DATA_LEN(resp);
484 cmd->error = RESPONSE_PORT_ERR_STATUS(resp);
485 if (cmd->rx_len && !cmd->error)
486 dw_i3c_master_read_rx_fifo(master, cmd->rx_buf,
487 cmd->rx_len);
488 }
489
490 for (i = 0; i < nresp; i++) {
491 switch (xfer->cmds[i].error) {
492 case RESPONSE_NO_ERROR:
493 break;
494 case RESPONSE_ERROR_PARITY:
495 case RESPONSE_ERROR_IBA_NACK:
496 case RESPONSE_ERROR_TRANSF_ABORT:
497 case RESPONSE_ERROR_CRC:
498 case RESPONSE_ERROR_FRAME:
499 ret = -EIO;
500 break;
501 case RESPONSE_ERROR_OVER_UNDER_FLOW:
502 ret = -ENOSPC;
503 break;
504 case RESPONSE_ERROR_I2C_W_NACK_ERR:
505 case RESPONSE_ERROR_ADDRESS_NACK:
506 default:
507 ret = -EINVAL;
508 break;
509 }
510 }
511
512 xfer->ret = ret;
513 complete(&xfer->comp);
514
515 if (ret < 0) {
516 dw_i3c_master_dequeue_xfer_locked(master, xfer);
517 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_RESUME,
518 master->regs + DEVICE_CTRL);
519 }
520
521 xfer = list_first_entry_or_null(&master->xferqueue.list,
522 struct dw_i3c_xfer,
523 node);
524 if (xfer)
525 list_del_init(&xfer->node);
526
527 master->xferqueue.cur = xfer;
528 dw_i3c_master_start_xfer_locked(master);
529 }
530
dw_i3c_master_set_intr_regs(struct dw_i3c_master * master)531 static void dw_i3c_master_set_intr_regs(struct dw_i3c_master *master)
532 {
533 u32 thld_ctrl;
534
535 thld_ctrl = readl(master->regs + QUEUE_THLD_CTRL);
536 thld_ctrl &= ~(QUEUE_THLD_CTRL_RESP_BUF_MASK |
537 QUEUE_THLD_CTRL_IBI_STAT_MASK |
538 QUEUE_THLD_CTRL_IBI_DATA_MASK);
539 thld_ctrl |= QUEUE_THLD_CTRL_IBI_STAT(1) |
540 QUEUE_THLD_CTRL_IBI_DATA(31);
541 writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL);
542
543 thld_ctrl = readl(master->regs + DATA_BUFFER_THLD_CTRL);
544 thld_ctrl &= ~DATA_BUFFER_THLD_CTRL_RX_BUF;
545 writel(thld_ctrl, master->regs + DATA_BUFFER_THLD_CTRL);
546
547 writel(INTR_ALL, master->regs + INTR_STATUS);
548 writel(INTR_MASTER_MASK, master->regs + INTR_STATUS_EN);
549 writel(INTR_MASTER_MASK, master->regs + INTR_SIGNAL_EN);
550
551 master->sir_rej_mask = IBI_REQ_REJECT_ALL;
552 writel(master->sir_rej_mask, master->regs + IBI_SIR_REQ_REJECT);
553
554 writel(IBI_REQ_REJECT_ALL, master->regs + IBI_MR_REQ_REJECT);
555 }
556
dw_i3c_clk_cfg(struct dw_i3c_master * master)557 static int dw_i3c_clk_cfg(struct dw_i3c_master *master)
558 {
559 unsigned long core_rate, core_period;
560 u32 scl_timing;
561 u8 hcnt, lcnt;
562
563 core_rate = clk_get_rate(master->core_clk);
564 if (!core_rate)
565 return -EINVAL;
566
567 core_period = DIV_ROUND_UP(1000000000, core_rate);
568
569 hcnt = DIV_ROUND_UP(I3C_BUS_THIGH_MAX_NS, core_period) - 1;
570 if (hcnt < SCL_I3C_TIMING_CNT_MIN)
571 hcnt = SCL_I3C_TIMING_CNT_MIN;
572
573 lcnt = DIV_ROUND_UP(core_rate, master->base.bus.scl_rate.i3c) - hcnt;
574 if (lcnt < SCL_I3C_TIMING_CNT_MIN)
575 lcnt = SCL_I3C_TIMING_CNT_MIN;
576
577 scl_timing = SCL_I3C_TIMING_HCNT(hcnt) | SCL_I3C_TIMING_LCNT(lcnt);
578 writel(scl_timing, master->regs + SCL_I3C_PP_TIMING);
579 master->i3c_pp_timing = scl_timing;
580
581 /*
582 * In pure i3c mode, MST_FREE represents tCAS. In shared mode, this
583 * will be set up by dw_i2c_clk_cfg as tLOW.
584 */
585 if (master->base.bus.mode == I3C_BUS_MODE_PURE) {
586 writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING);
587 master->bus_free_timing = BUS_I3C_MST_FREE(lcnt);
588 }
589
590 lcnt = max_t(u8,
591 DIV_ROUND_UP(I3C_BUS_TLOW_OD_MIN_NS, core_period), lcnt);
592 scl_timing = SCL_I3C_TIMING_HCNT(hcnt) | SCL_I3C_TIMING_LCNT(lcnt);
593 writel(scl_timing, master->regs + SCL_I3C_OD_TIMING);
594 master->i3c_od_timing = scl_timing;
595
596 lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR1_SCL_RATE) - hcnt;
597 scl_timing = SCL_EXT_LCNT_1(lcnt);
598 lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR2_SCL_RATE) - hcnt;
599 scl_timing |= SCL_EXT_LCNT_2(lcnt);
600 lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR3_SCL_RATE) - hcnt;
601 scl_timing |= SCL_EXT_LCNT_3(lcnt);
602 lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR4_SCL_RATE) - hcnt;
603 scl_timing |= SCL_EXT_LCNT_4(lcnt);
604 writel(scl_timing, master->regs + SCL_EXT_LCNT_TIMING);
605 master->ext_lcnt_timing = scl_timing;
606
607 return 0;
608 }
609
dw_i2c_clk_cfg(struct dw_i3c_master * master)610 static int dw_i2c_clk_cfg(struct dw_i3c_master *master)
611 {
612 unsigned long core_rate, core_period;
613 u16 hcnt, lcnt;
614 u32 scl_timing;
615
616 core_rate = clk_get_rate(master->core_clk);
617 if (!core_rate)
618 return -EINVAL;
619
620 core_period = DIV_ROUND_UP(1000000000, core_rate);
621
622 lcnt = DIV_ROUND_UP(I3C_BUS_I2C_FMP_TLOW_MIN_NS, core_period);
623 hcnt = DIV_ROUND_UP(core_rate, I3C_BUS_I2C_FM_PLUS_SCL_MAX_RATE) - lcnt;
624 scl_timing = SCL_I2C_FMP_TIMING_HCNT(hcnt) |
625 SCL_I2C_FMP_TIMING_LCNT(lcnt);
626 writel(scl_timing, master->regs + SCL_I2C_FMP_TIMING);
627 master->i2c_fmp_timing = scl_timing;
628
629 lcnt = DIV_ROUND_UP(I3C_BUS_I2C_FM_TLOW_MIN_NS, core_period);
630 hcnt = DIV_ROUND_UP(core_rate, I3C_BUS_I2C_FM_SCL_MAX_RATE) - lcnt;
631 scl_timing = SCL_I2C_FM_TIMING_HCNT(hcnt) |
632 SCL_I2C_FM_TIMING_LCNT(lcnt);
633 writel(scl_timing, master->regs + SCL_I2C_FM_TIMING);
634 master->i2c_fm_timing = scl_timing;
635
636 writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING);
637 master->bus_free_timing = BUS_I3C_MST_FREE(lcnt);
638
639 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_I2C_SLAVE_PRESENT,
640 master->regs + DEVICE_CTRL);
641 master->i2c_slv_prsnt = true;
642
643 return 0;
644 }
645
dw_i3c_master_bus_init(struct i3c_master_controller * m)646 static int dw_i3c_master_bus_init(struct i3c_master_controller *m)
647 {
648 struct dw_i3c_master *master = to_dw_i3c_master(m);
649 struct i3c_bus *bus = i3c_master_get_bus(m);
650 struct i3c_device_info info = { };
651 int ret;
652
653 ret = pm_runtime_resume_and_get(master->dev);
654 if (ret < 0) {
655 dev_err(master->dev,
656 "<%s> cannot resume i3c bus master, err: %d\n",
657 __func__, ret);
658 return ret;
659 }
660
661 ret = master->platform_ops->init(master);
662 if (ret)
663 goto rpm_out;
664
665 switch (bus->mode) {
666 case I3C_BUS_MODE_MIXED_FAST:
667 case I3C_BUS_MODE_MIXED_LIMITED:
668 ret = dw_i2c_clk_cfg(master);
669 if (ret)
670 goto rpm_out;
671 fallthrough;
672 case I3C_BUS_MODE_PURE:
673 ret = dw_i3c_clk_cfg(master);
674 if (ret)
675 goto rpm_out;
676 break;
677 default:
678 ret = -EINVAL;
679 goto rpm_out;
680 }
681
682 ret = i3c_master_get_free_addr(m, 0);
683 if (ret < 0)
684 goto rpm_out;
685
686 writel(DEV_ADDR_DYNAMIC_ADDR_VALID | DEV_ADDR_DYNAMIC(ret),
687 master->regs + DEVICE_ADDR);
688 master->dev_addr = ret;
689 memset(&info, 0, sizeof(info));
690 info.dyn_addr = ret;
691
692 ret = i3c_master_set_info(&master->base, &info);
693 if (ret)
694 goto rpm_out;
695
696 dw_i3c_master_set_intr_regs(master);
697 dw_i3c_master_enable(master);
698
699 rpm_out:
700 pm_runtime_put_autosuspend(master->dev);
701 return ret;
702 }
703
dw_i3c_master_bus_cleanup(struct i3c_master_controller * m)704 static void dw_i3c_master_bus_cleanup(struct i3c_master_controller *m)
705 {
706 struct dw_i3c_master *master = to_dw_i3c_master(m);
707
708 dw_i3c_master_disable(master);
709 }
710
dw_i3c_ccc_set(struct dw_i3c_master * master,struct i3c_ccc_cmd * ccc)711 static int dw_i3c_ccc_set(struct dw_i3c_master *master,
712 struct i3c_ccc_cmd *ccc)
713 {
714 struct dw_i3c_cmd *cmd;
715 int ret, pos = 0;
716
717 if (ccc->id & I3C_CCC_DIRECT) {
718 pos = dw_i3c_master_get_addr_pos(master, ccc->dests[0].addr);
719 if (pos < 0)
720 return pos;
721 }
722
723 struct dw_i3c_xfer *xfer __free(kfree) = dw_i3c_master_alloc_xfer(master, 1);
724 if (!xfer)
725 return -ENOMEM;
726
727 cmd = xfer->cmds;
728 cmd->tx_buf = ccc->dests[0].payload.data;
729 cmd->tx_len = ccc->dests[0].payload.len;
730
731 cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(ccc->dests[0].payload.len) |
732 COMMAND_PORT_TRANSFER_ARG;
733
734 cmd->cmd_lo = COMMAND_PORT_CP |
735 COMMAND_PORT_DEV_INDEX(pos) |
736 COMMAND_PORT_CMD(ccc->id) |
737 COMMAND_PORT_TOC |
738 COMMAND_PORT_ROC;
739
740 dw_i3c_master_enqueue_xfer(master, xfer);
741 if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT))
742 dw_i3c_master_dequeue_xfer(master, xfer);
743
744 ret = xfer->ret;
745 if (xfer->cmds[0].error == RESPONSE_ERROR_IBA_NACK)
746 ccc->err = I3C_ERROR_M2;
747
748 return ret;
749 }
750
dw_i3c_ccc_get(struct dw_i3c_master * master,struct i3c_ccc_cmd * ccc)751 static int dw_i3c_ccc_get(struct dw_i3c_master *master, struct i3c_ccc_cmd *ccc)
752 {
753 struct dw_i3c_cmd *cmd;
754 int ret, pos;
755
756 pos = dw_i3c_master_get_addr_pos(master, ccc->dests[0].addr);
757 if (pos < 0)
758 return pos;
759
760 struct dw_i3c_xfer *xfer __free(kfree) = dw_i3c_master_alloc_xfer(master, 1);
761 if (!xfer)
762 return -ENOMEM;
763
764 cmd = xfer->cmds;
765 cmd->rx_buf = ccc->dests[0].payload.data;
766 cmd->rx_len = ccc->dests[0].payload.len;
767
768 cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(ccc->dests[0].payload.len) |
769 COMMAND_PORT_TRANSFER_ARG;
770
771 cmd->cmd_lo = COMMAND_PORT_READ_TRANSFER |
772 COMMAND_PORT_CP |
773 COMMAND_PORT_DEV_INDEX(pos) |
774 COMMAND_PORT_CMD(ccc->id) |
775 COMMAND_PORT_TOC |
776 COMMAND_PORT_ROC;
777
778 dw_i3c_master_enqueue_xfer(master, xfer);
779 if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT))
780 dw_i3c_master_dequeue_xfer(master, xfer);
781
782 ret = xfer->ret;
783 if (xfer->cmds[0].error == RESPONSE_ERROR_IBA_NACK)
784 ccc->err = I3C_ERROR_M2;
785
786 return ret;
787 }
788
amd_configure_od_pp_quirk(struct dw_i3c_master * master)789 static void amd_configure_od_pp_quirk(struct dw_i3c_master *master)
790 {
791 master->i3c_od_timing = AMD_I3C_OD_TIMING;
792 master->i3c_pp_timing = AMD_I3C_PP_TIMING;
793 }
794
dw_i3c_master_send_ccc_cmd(struct i3c_master_controller * m,struct i3c_ccc_cmd * ccc)795 static int dw_i3c_master_send_ccc_cmd(struct i3c_master_controller *m,
796 struct i3c_ccc_cmd *ccc)
797 {
798 struct dw_i3c_master *master = to_dw_i3c_master(m);
799 int ret = 0;
800
801 if (ccc->id == I3C_CCC_ENTDAA)
802 return -EINVAL;
803
804 /* AMD platform specific OD and PP timings */
805 if (master->quirks & AMD_I3C_OD_PP_TIMING) {
806 amd_configure_od_pp_quirk(master);
807 writel(master->i3c_pp_timing, master->regs + SCL_I3C_PP_TIMING);
808 writel(master->i3c_od_timing, master->regs + SCL_I3C_OD_TIMING);
809 }
810
811 ret = pm_runtime_resume_and_get(master->dev);
812 if (ret < 0) {
813 dev_err(master->dev,
814 "<%s> cannot resume i3c bus master, err: %d\n",
815 __func__, ret);
816 return ret;
817 }
818
819 if (ccc->rnw)
820 ret = dw_i3c_ccc_get(master, ccc);
821 else
822 ret = dw_i3c_ccc_set(master, ccc);
823
824 pm_runtime_put_autosuspend(master->dev);
825 return ret;
826 }
827
dw_i3c_master_daa(struct i3c_master_controller * m)828 static int dw_i3c_master_daa(struct i3c_master_controller *m)
829 {
830 struct dw_i3c_master *master = to_dw_i3c_master(m);
831 struct dw_i3c_cmd *cmd;
832 u32 olddevs, newdevs;
833 u8 last_addr = 0;
834 int ret, pos;
835
836 struct dw_i3c_xfer *xfer __free(kfree) = dw_i3c_master_alloc_xfer(master, 1);
837 if (!xfer)
838 return -ENOMEM;
839
840 ret = pm_runtime_resume_and_get(master->dev);
841 if (ret < 0) {
842 dev_err(master->dev,
843 "<%s> cannot resume i3c bus master, err: %d\n",
844 __func__, ret);
845 return ret;
846 }
847
848 olddevs = ~(master->free_pos);
849
850 /* Prepare DAT before launching DAA. */
851 for (pos = 0; pos < master->maxdevs; pos++) {
852 if (olddevs & BIT(pos))
853 continue;
854
855 ret = i3c_master_get_free_addr(m, last_addr + 1);
856 if (ret < 0) {
857 ret = -ENOSPC;
858 goto rpm_out;
859 }
860
861 master->devs[pos].addr = ret;
862 last_addr = ret;
863
864 ret |= parity8(ret) ? 0 : BIT(7);
865
866 writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(ret),
867 master->regs +
868 DEV_ADDR_TABLE_LOC(master->datstartaddr, pos));
869
870 ret = 0;
871 }
872
873 pos = dw_i3c_master_get_free_pos(master);
874 if (pos < 0) {
875 ret = pos;
876 goto rpm_out;
877 }
878 cmd = &xfer->cmds[0];
879 cmd->cmd_hi = 0x1;
880 cmd->cmd_lo = COMMAND_PORT_DEV_COUNT(master->maxdevs - pos) |
881 COMMAND_PORT_DEV_INDEX(pos) |
882 COMMAND_PORT_CMD(I3C_CCC_ENTDAA) |
883 COMMAND_PORT_ADDR_ASSGN_CMD |
884 COMMAND_PORT_TOC |
885 COMMAND_PORT_ROC;
886
887 dw_i3c_master_enqueue_xfer(master, xfer);
888 if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT))
889 dw_i3c_master_dequeue_xfer(master, xfer);
890
891 newdevs = GENMASK(master->maxdevs - cmd->rx_len - 1, 0);
892 newdevs &= ~olddevs;
893
894 for (pos = 0; pos < master->maxdevs; pos++) {
895 if (newdevs & BIT(pos))
896 i3c_master_add_i3c_dev_locked(m, master->devs[pos].addr);
897 }
898
899 rpm_out:
900 pm_runtime_put_autosuspend(master->dev);
901 return ret;
902 }
903
dw_i3c_master_i3c_xfers(struct i3c_dev_desc * dev,struct i3c_xfer * i3c_xfers,int i3c_nxfers,enum i3c_xfer_mode mode)904 static int dw_i3c_master_i3c_xfers(struct i3c_dev_desc *dev,
905 struct i3c_xfer *i3c_xfers,
906 int i3c_nxfers, enum i3c_xfer_mode mode)
907 {
908 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
909 struct i3c_master_controller *m = i3c_dev_get_master(dev);
910 struct dw_i3c_master *master = to_dw_i3c_master(m);
911 unsigned int nrxwords = 0, ntxwords = 0;
912 int i, ret = 0;
913
914 if (!i3c_nxfers)
915 return 0;
916
917 if (i3c_nxfers > master->caps.cmdfifodepth)
918 return -EOPNOTSUPP;
919
920 for (i = 0; i < i3c_nxfers; i++) {
921 if (i3c_xfers[i].rnw)
922 nrxwords += DIV_ROUND_UP(i3c_xfers[i].len, 4);
923 else
924 ntxwords += DIV_ROUND_UP(i3c_xfers[i].len, 4);
925 }
926
927 if (ntxwords > master->caps.datafifodepth ||
928 nrxwords > master->caps.datafifodepth)
929 return -EOPNOTSUPP;
930
931 struct dw_i3c_xfer *xfer __free(kfree) = dw_i3c_master_alloc_xfer(master, i3c_nxfers);
932 if (!xfer)
933 return -ENOMEM;
934
935 ret = pm_runtime_resume_and_get(master->dev);
936 if (ret < 0) {
937 dev_err(master->dev,
938 "<%s> cannot resume i3c bus master, err: %d\n",
939 __func__, ret);
940 return ret;
941 }
942
943 for (i = 0; i < i3c_nxfers; i++) {
944 struct dw_i3c_cmd *cmd = &xfer->cmds[i];
945
946 cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(i3c_xfers[i].len) |
947 COMMAND_PORT_TRANSFER_ARG;
948
949 if (i3c_xfers[i].rnw) {
950 cmd->rx_buf = i3c_xfers[i].data.in;
951 cmd->rx_len = i3c_xfers[i].len;
952 cmd->cmd_lo = COMMAND_PORT_READ_TRANSFER |
953 COMMAND_PORT_SPEED(dev->info.max_read_ds);
954
955 } else {
956 cmd->tx_buf = i3c_xfers[i].data.out;
957 cmd->tx_len = i3c_xfers[i].len;
958 cmd->cmd_lo =
959 COMMAND_PORT_SPEED(dev->info.max_write_ds);
960 }
961
962 cmd->cmd_lo |= COMMAND_PORT_TID(i) |
963 COMMAND_PORT_DEV_INDEX(data->index) |
964 COMMAND_PORT_ROC;
965
966 if (i == (i3c_nxfers - 1))
967 cmd->cmd_lo |= COMMAND_PORT_TOC;
968 }
969
970 dw_i3c_master_enqueue_xfer(master, xfer);
971 if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT))
972 dw_i3c_master_dequeue_xfer(master, xfer);
973
974 for (i = 0; i < i3c_nxfers; i++) {
975 struct dw_i3c_cmd *cmd = &xfer->cmds[i];
976
977 if (i3c_xfers[i].rnw)
978 i3c_xfers[i].len = cmd->rx_len;
979 }
980
981 ret = xfer->ret;
982
983 pm_runtime_put_autosuspend(master->dev);
984 return ret;
985 }
986
dw_i3c_master_reattach_i3c_dev(struct i3c_dev_desc * dev,u8 old_dyn_addr)987 static int dw_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev,
988 u8 old_dyn_addr)
989 {
990 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
991 struct i3c_master_controller *m = i3c_dev_get_master(dev);
992 struct dw_i3c_master *master = to_dw_i3c_master(m);
993 int pos;
994
995 pos = dw_i3c_master_get_free_pos(master);
996
997 if (data->index > pos && pos > 0) {
998 writel(0,
999 master->regs +
1000 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
1001
1002 master->devs[data->index].addr = 0;
1003 master->free_pos |= BIT(data->index);
1004
1005 data->index = pos;
1006 master->devs[pos].addr = dev->info.dyn_addr;
1007 master->free_pos &= ~BIT(pos);
1008 }
1009
1010 writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(dev->info.dyn_addr) | DEV_ADDR_TABLE_SIR_REJECT,
1011 master->regs +
1012 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
1013
1014 master->devs[data->index].addr = dev->info.dyn_addr;
1015
1016 return 0;
1017 }
1018
dw_i3c_master_attach_i3c_dev(struct i3c_dev_desc * dev)1019 static int dw_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev)
1020 {
1021 struct i3c_master_controller *m = i3c_dev_get_master(dev);
1022 struct dw_i3c_master *master = to_dw_i3c_master(m);
1023 struct dw_i3c_i2c_dev_data *data;
1024 int pos;
1025
1026 pos = dw_i3c_master_get_free_pos(master);
1027 if (pos < 0)
1028 return pos;
1029
1030 data = kzalloc_obj(*data);
1031 if (!data)
1032 return -ENOMEM;
1033
1034 data->index = pos;
1035 master->devs[pos].addr = dev->info.dyn_addr ? : dev->info.static_addr;
1036 master->free_pos &= ~BIT(pos);
1037 i3c_dev_set_master_data(dev, data);
1038
1039 writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(master->devs[pos].addr) | DEV_ADDR_TABLE_SIR_REJECT,
1040 master->regs +
1041 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
1042
1043 return 0;
1044 }
1045
dw_i3c_master_detach_i3c_dev(struct i3c_dev_desc * dev)1046 static void dw_i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev)
1047 {
1048 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1049 struct i3c_master_controller *m = i3c_dev_get_master(dev);
1050 struct dw_i3c_master *master = to_dw_i3c_master(m);
1051
1052 writel(0,
1053 master->regs +
1054 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
1055
1056 i3c_dev_set_master_data(dev, NULL);
1057 master->devs[data->index].addr = 0;
1058 master->free_pos |= BIT(data->index);
1059 kfree(data);
1060 }
1061
dw_i3c_master_i2c_xfers(struct i2c_dev_desc * dev,struct i2c_msg * i2c_xfers,int i2c_nxfers)1062 static int dw_i3c_master_i2c_xfers(struct i2c_dev_desc *dev,
1063 struct i2c_msg *i2c_xfers,
1064 int i2c_nxfers)
1065 {
1066 struct dw_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev);
1067 struct i3c_master_controller *m = i2c_dev_get_master(dev);
1068 struct dw_i3c_master *master = to_dw_i3c_master(m);
1069 unsigned int nrxwords = 0, ntxwords = 0;
1070 int i, ret = 0;
1071
1072 if (!i2c_nxfers)
1073 return 0;
1074
1075 if (i2c_nxfers > master->caps.cmdfifodepth)
1076 return -EOPNOTSUPP;
1077
1078 for (i = 0; i < i2c_nxfers; i++) {
1079 if (i2c_xfers[i].flags & I2C_M_RD)
1080 nrxwords += DIV_ROUND_UP(i2c_xfers[i].len, 4);
1081 else
1082 ntxwords += DIV_ROUND_UP(i2c_xfers[i].len, 4);
1083 }
1084
1085 if (ntxwords > master->caps.datafifodepth ||
1086 nrxwords > master->caps.datafifodepth)
1087 return -EOPNOTSUPP;
1088
1089 struct dw_i3c_xfer *xfer __free(kfree) = dw_i3c_master_alloc_xfer(master, i2c_nxfers);
1090 if (!xfer)
1091 return -ENOMEM;
1092
1093 ret = pm_runtime_resume_and_get(master->dev);
1094 if (ret < 0) {
1095 dev_err(master->dev,
1096 "<%s> cannot resume i3c bus master, err: %d\n",
1097 __func__, ret);
1098 return ret;
1099 }
1100
1101 for (i = 0; i < i2c_nxfers; i++) {
1102 struct dw_i3c_cmd *cmd = &xfer->cmds[i];
1103
1104 cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(i2c_xfers[i].len) |
1105 COMMAND_PORT_TRANSFER_ARG;
1106
1107 cmd->cmd_lo = COMMAND_PORT_TID(i) |
1108 COMMAND_PORT_DEV_INDEX(data->index) |
1109 COMMAND_PORT_ROC;
1110
1111 if (i2c_xfers[i].flags & I2C_M_RD) {
1112 cmd->cmd_lo |= COMMAND_PORT_READ_TRANSFER;
1113 cmd->rx_buf = i2c_xfers[i].buf;
1114 cmd->rx_len = i2c_xfers[i].len;
1115 } else {
1116 cmd->tx_buf = i2c_xfers[i].buf;
1117 cmd->tx_len = i2c_xfers[i].len;
1118 }
1119
1120 if (i == (i2c_nxfers - 1))
1121 cmd->cmd_lo |= COMMAND_PORT_TOC;
1122 }
1123
1124 dw_i3c_master_enqueue_xfer(master, xfer);
1125 if (!wait_for_completion_timeout(&xfer->comp, m->i2c.timeout))
1126 dw_i3c_master_dequeue_xfer(master, xfer);
1127
1128 ret = xfer->ret;
1129
1130 pm_runtime_put_autosuspend(master->dev);
1131 return ret;
1132 }
1133
dw_i3c_master_attach_i2c_dev(struct i2c_dev_desc * dev)1134 static int dw_i3c_master_attach_i2c_dev(struct i2c_dev_desc *dev)
1135 {
1136 struct i3c_master_controller *m = i2c_dev_get_master(dev);
1137 struct dw_i3c_master *master = to_dw_i3c_master(m);
1138 struct dw_i3c_i2c_dev_data *data;
1139 int pos;
1140
1141 pos = dw_i3c_master_get_free_pos(master);
1142 if (pos < 0)
1143 return pos;
1144
1145 data = kzalloc_obj(*data);
1146 if (!data)
1147 return -ENOMEM;
1148
1149 data->index = pos;
1150 master->devs[pos].addr = dev->addr;
1151 master->devs[pos].is_i2c_addr = true;
1152 master->free_pos &= ~BIT(pos);
1153 i2c_dev_set_master_data(dev, data);
1154
1155 writel(DEV_ADDR_TABLE_LEGACY_I2C_DEV |
1156 DEV_ADDR_TABLE_STATIC_ADDR(dev->addr),
1157 master->regs +
1158 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
1159
1160 return 0;
1161 }
1162
dw_i3c_master_detach_i2c_dev(struct i2c_dev_desc * dev)1163 static void dw_i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev)
1164 {
1165 struct dw_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev);
1166 struct i3c_master_controller *m = i2c_dev_get_master(dev);
1167 struct dw_i3c_master *master = to_dw_i3c_master(m);
1168
1169 writel(0,
1170 master->regs +
1171 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
1172
1173 i2c_dev_set_master_data(dev, NULL);
1174 master->devs[data->index].addr = 0;
1175 master->free_pos |= BIT(data->index);
1176 kfree(data);
1177 }
1178
dw_i3c_master_request_ibi(struct i3c_dev_desc * dev,const struct i3c_ibi_setup * req)1179 static int dw_i3c_master_request_ibi(struct i3c_dev_desc *dev,
1180 const struct i3c_ibi_setup *req)
1181 {
1182 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1183 struct i3c_master_controller *m = i3c_dev_get_master(dev);
1184 struct dw_i3c_master *master = to_dw_i3c_master(m);
1185
1186 data->ibi_pool = i3c_generic_ibi_alloc_pool(dev, req);
1187 if (IS_ERR(data->ibi_pool))
1188 return PTR_ERR(data->ibi_pool);
1189
1190 guard(spinlock_irqsave)(&master->devs_lock);
1191 master->devs[data->index].ibi_dev = dev;
1192
1193 return 0;
1194 }
1195
dw_i3c_master_free_ibi(struct i3c_dev_desc * dev)1196 static void dw_i3c_master_free_ibi(struct i3c_dev_desc *dev)
1197 {
1198 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1199 struct i3c_master_controller *m = i3c_dev_get_master(dev);
1200 struct dw_i3c_master *master = to_dw_i3c_master(m);
1201
1202 scoped_guard(spinlock_irqsave, &master->devs_lock) {
1203 master->devs[data->index].ibi_dev = NULL;
1204 }
1205
1206 i3c_generic_ibi_free_pool(data->ibi_pool);
1207 data->ibi_pool = NULL;
1208 }
1209
dw_i3c_master_enable_sir_signal(struct dw_i3c_master * master,bool enable)1210 static void dw_i3c_master_enable_sir_signal(struct dw_i3c_master *master, bool enable)
1211 {
1212 u32 reg;
1213
1214 reg = readl(master->regs + INTR_STATUS_EN);
1215 reg &= ~INTR_IBI_THLD_STAT;
1216 if (enable)
1217 reg |= INTR_IBI_THLD_STAT;
1218 writel(reg, master->regs + INTR_STATUS_EN);
1219
1220 reg = readl(master->regs + INTR_SIGNAL_EN);
1221 reg &= ~INTR_IBI_THLD_STAT;
1222 if (enable)
1223 reg |= INTR_IBI_THLD_STAT;
1224 writel(reg, master->regs + INTR_SIGNAL_EN);
1225 }
1226
dw_i3c_master_set_sir_enabled(struct dw_i3c_master * master,struct i3c_dev_desc * dev,u8 idx,bool enable)1227 static void dw_i3c_master_set_sir_enabled(struct dw_i3c_master *master,
1228 struct i3c_dev_desc *dev,
1229 u8 idx, bool enable)
1230 {
1231 u32 dat_entry, reg;
1232 bool global;
1233 u8 dynamic_addr;
1234
1235 dat_entry = DEV_ADDR_TABLE_LOC(master->datstartaddr, idx);
1236
1237 guard(spinlock_irqsave)(&master->devs_lock);
1238 reg = readl(master->regs + dat_entry);
1239 dynamic_addr = DEV_ADDR_TABLE_GET_DYNAMIC_ADDR(reg);
1240
1241 if (!dynamic_addr)
1242 dev_warn(master->dev,
1243 "<%s> unassigned slave device, dynamic addr:%x\n",
1244 __func__, dynamic_addr);
1245
1246 if (enable) {
1247 reg &= ~DEV_ADDR_TABLE_SIR_REJECT;
1248 if (dev->info.bcr & I3C_BCR_IBI_PAYLOAD)
1249 reg |= DEV_ADDR_TABLE_IBI_MDB;
1250 } else {
1251 reg |= DEV_ADDR_TABLE_SIR_REJECT;
1252 }
1253 master->platform_ops->set_dat_ibi(master, dev, enable, ®);
1254 writel(reg, master->regs + dat_entry);
1255
1256 if (enable) {
1257 global = (master->sir_rej_mask == IBI_REQ_REJECT_ALL);
1258 master->sir_rej_mask &= ~BIT(get_ibi_sir_bit_index(dynamic_addr));
1259 } else {
1260 bool hj_rejected = !!(readl(master->regs + DEVICE_CTRL) & DEV_CTRL_HOT_JOIN_NACK);
1261
1262 master->sir_rej_mask |= BIT(get_ibi_sir_bit_index(dynamic_addr));
1263 global = (master->sir_rej_mask == IBI_REQ_REJECT_ALL) && hj_rejected;
1264 }
1265 writel(master->sir_rej_mask, master->regs + IBI_SIR_REQ_REJECT);
1266
1267 if (global)
1268 dw_i3c_master_enable_sir_signal(master, enable);
1269 }
1270
dw_i3c_master_enable_hotjoin(struct i3c_master_controller * m)1271 static int dw_i3c_master_enable_hotjoin(struct i3c_master_controller *m)
1272 {
1273 struct dw_i3c_master *master = to_dw_i3c_master(m);
1274 int ret;
1275
1276 ret = pm_runtime_resume_and_get(master->dev);
1277 if (ret < 0) {
1278 dev_err(master->dev,
1279 "<%s> cannot resume i3c bus master, err: %d\n",
1280 __func__, ret);
1281 return ret;
1282 }
1283
1284 dw_i3c_master_enable_sir_signal(master, true);
1285 writel(readl(master->regs + DEVICE_CTRL) & ~DEV_CTRL_HOT_JOIN_NACK,
1286 master->regs + DEVICE_CTRL);
1287
1288 return 0;
1289 }
1290
dw_i3c_master_disable_hotjoin(struct i3c_master_controller * m)1291 static int dw_i3c_master_disable_hotjoin(struct i3c_master_controller *m)
1292 {
1293 struct dw_i3c_master *master = to_dw_i3c_master(m);
1294
1295 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_HOT_JOIN_NACK,
1296 master->regs + DEVICE_CTRL);
1297
1298 pm_runtime_put_autosuspend(master->dev);
1299 return 0;
1300 }
1301
dw_i3c_master_enable_ibi(struct i3c_dev_desc * dev)1302 static int dw_i3c_master_enable_ibi(struct i3c_dev_desc *dev)
1303 {
1304 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1305 struct i3c_master_controller *m = i3c_dev_get_master(dev);
1306 struct dw_i3c_master *master = to_dw_i3c_master(m);
1307 int rc;
1308
1309 rc = pm_runtime_resume_and_get(master->dev);
1310 if (rc < 0) {
1311 dev_err(master->dev,
1312 "<%s> cannot resume i3c bus master, err: %d\n",
1313 __func__, rc);
1314 return rc;
1315 }
1316
1317 dw_i3c_master_set_sir_enabled(master, dev, data->index, true);
1318
1319 rc = i3c_master_enec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR);
1320
1321 if (rc) {
1322 dw_i3c_master_set_sir_enabled(master, dev, data->index, false);
1323 pm_runtime_put_autosuspend(master->dev);
1324 }
1325
1326 return rc;
1327 }
1328
dw_i3c_master_disable_ibi(struct i3c_dev_desc * dev)1329 static int dw_i3c_master_disable_ibi(struct i3c_dev_desc *dev)
1330 {
1331 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1332 struct i3c_master_controller *m = i3c_dev_get_master(dev);
1333 struct dw_i3c_master *master = to_dw_i3c_master(m);
1334 int rc;
1335
1336 rc = i3c_master_disec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR);
1337 if (rc)
1338 return rc;
1339
1340 dw_i3c_master_set_sir_enabled(master, dev, data->index, false);
1341
1342 pm_runtime_put_autosuspend(master->dev);
1343 return 0;
1344 }
1345
dw_i3c_master_recycle_ibi_slot(struct i3c_dev_desc * dev,struct i3c_ibi_slot * slot)1346 static void dw_i3c_master_recycle_ibi_slot(struct i3c_dev_desc *dev,
1347 struct i3c_ibi_slot *slot)
1348 {
1349 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1350
1351 i3c_generic_ibi_recycle_slot(data->ibi_pool, slot);
1352 }
1353
dw_i3c_master_drain_ibi_queue(struct dw_i3c_master * master,int len)1354 static void dw_i3c_master_drain_ibi_queue(struct dw_i3c_master *master,
1355 int len)
1356 {
1357 int i;
1358
1359 for (i = 0; i < DIV_ROUND_UP(len, 4); i++)
1360 readl(master->regs + IBI_QUEUE_STATUS);
1361 }
1362
dw_i3c_master_handle_ibi_sir(struct dw_i3c_master * master,u32 status)1363 static void dw_i3c_master_handle_ibi_sir(struct dw_i3c_master *master,
1364 u32 status)
1365 {
1366 struct dw_i3c_i2c_dev_data *data;
1367 struct i3c_ibi_slot *slot;
1368 struct i3c_dev_desc *dev;
1369 u8 addr, len;
1370 int idx;
1371
1372 addr = IBI_QUEUE_IBI_ADDR(status);
1373 len = IBI_QUEUE_STATUS_DATA_LEN(status);
1374
1375 /*
1376 * We be tempted to check the error status in bit 30; however, due
1377 * to the PEC errata workaround on some platform implementations (see
1378 * ast2600_i3c_set_dat_ibi()), those will almost always have a PEC
1379 * error on IBI payload data, as well as losing the last byte of
1380 * payload.
1381 *
1382 * If we implement error status checking on that bit, we may need
1383 * a new platform op to validate it.
1384 */
1385
1386 guard(spinlock_irqsave)(&master->devs_lock);
1387 idx = dw_i3c_master_get_addr_pos(master, addr);
1388 if (idx < 0) {
1389 dev_dbg_ratelimited(&master->base.dev,
1390 "IBI from unknown addr 0x%x\n", addr);
1391 goto err_drain;
1392 }
1393
1394 dev = master->devs[idx].ibi_dev;
1395 if (!dev || !dev->ibi) {
1396 dev_dbg_ratelimited(&master->base.dev,
1397 "IBI from non-requested dev idx %d\n", idx);
1398 goto err_drain;
1399 }
1400
1401 data = i3c_dev_get_master_data(dev);
1402 slot = i3c_generic_ibi_get_free_slot(data->ibi_pool);
1403 if (!slot) {
1404 dev_dbg_ratelimited(&master->base.dev,
1405 "No IBI slots available\n");
1406 goto err_drain;
1407 }
1408
1409 if (dev->ibi->max_payload_len < len) {
1410 dev_dbg_ratelimited(&master->base.dev,
1411 "IBI payload len %d greater than max %d\n",
1412 len, dev->ibi->max_payload_len);
1413 goto err_drain;
1414 }
1415
1416 if (len) {
1417 dw_i3c_master_read_ibi_fifo(master, slot->data, len);
1418 slot->len = len;
1419 }
1420 i3c_master_queue_ibi(dev, slot);
1421
1422 return;
1423
1424 err_drain:
1425 dw_i3c_master_drain_ibi_queue(master, len);
1426 }
1427
1428 /* "ibis": referring to In-Band Interrupts, and not
1429 * https://en.wikipedia.org/wiki/Australian_white_ibis. The latter should
1430 * not be handled.
1431 */
dw_i3c_master_irq_handle_ibis(struct dw_i3c_master * master)1432 static void dw_i3c_master_irq_handle_ibis(struct dw_i3c_master *master)
1433 {
1434 unsigned int i, len, n_ibis;
1435 u32 reg;
1436
1437 reg = readl(master->regs + QUEUE_STATUS_LEVEL);
1438 n_ibis = QUEUE_STATUS_IBI_STATUS_CNT(reg);
1439 if (!n_ibis)
1440 return;
1441
1442 for (i = 0; i < n_ibis; i++) {
1443 reg = readl(master->regs + IBI_QUEUE_STATUS);
1444
1445 if (IBI_TYPE_SIRQ(reg)) {
1446 dw_i3c_master_handle_ibi_sir(master, reg);
1447 } else if (IBI_TYPE_HJ(reg)) {
1448 queue_work(master->base.wq, &master->hj_work);
1449 } else {
1450 len = IBI_QUEUE_STATUS_DATA_LEN(reg);
1451 dev_info(&master->base.dev,
1452 "unsupported IBI type 0x%lx len %d\n",
1453 IBI_QUEUE_STATUS_IBI_ID(reg), len);
1454 dw_i3c_master_drain_ibi_queue(master, len);
1455 }
1456 }
1457 }
1458
dw_i3c_master_irq_handler(int irq,void * dev_id)1459 static irqreturn_t dw_i3c_master_irq_handler(int irq, void *dev_id)
1460 {
1461 struct dw_i3c_master *master = dev_id;
1462 u32 status;
1463
1464 status = readl(master->regs + INTR_STATUS);
1465
1466 if (!(status & readl(master->regs + INTR_STATUS_EN))) {
1467 writel(INTR_ALL, master->regs + INTR_STATUS);
1468 return IRQ_NONE;
1469 }
1470
1471 spin_lock(&master->xferqueue.lock);
1472 dw_i3c_master_end_xfer_locked(master, status);
1473 if (status & INTR_TRANSFER_ERR_STAT)
1474 writel(INTR_TRANSFER_ERR_STAT, master->regs + INTR_STATUS);
1475 spin_unlock(&master->xferqueue.lock);
1476
1477 if (status & INTR_IBI_THLD_STAT)
1478 dw_i3c_master_irq_handle_ibis(master);
1479
1480 return IRQ_HANDLED;
1481 }
1482
dw_i3c_master_set_dev_nack_retry(struct i3c_master_controller * m,unsigned long dev_nack_retry_cnt)1483 static int dw_i3c_master_set_dev_nack_retry(struct i3c_master_controller *m,
1484 unsigned long dev_nack_retry_cnt)
1485 {
1486 struct dw_i3c_master *master = to_dw_i3c_master(m);
1487 u32 reg;
1488 int i;
1489
1490 if (dev_nack_retry_cnt > DW_I3C_DEV_NACK_RETRY_CNT_MAX) {
1491 dev_err(&master->base.dev,
1492 "Value %ld exceeds maximum %d\n",
1493 dev_nack_retry_cnt, DW_I3C_DEV_NACK_RETRY_CNT_MAX);
1494 return -ERANGE;
1495 }
1496
1497 /*
1498 * Update DAT entries for all currently attached devices.
1499 * We directly iterate through the master's device array.
1500 */
1501 for (i = 0; i < master->maxdevs; i++) {
1502 /* Skip free/empty slots */
1503 if (master->free_pos & BIT(i))
1504 continue;
1505
1506 reg = readl(master->regs +
1507 DEV_ADDR_TABLE_LOC(master->datstartaddr, i));
1508 reg &= ~DEV_ADDR_TABLE_DEV_NACK_RETRY_MASK;
1509 reg |= DEV_ADDR_TABLE_DEV_NACK_RETRY_CNT(dev_nack_retry_cnt);
1510 writel(reg, master->regs +
1511 DEV_ADDR_TABLE_LOC(master->datstartaddr, i));
1512 }
1513
1514 return 0;
1515 }
1516
1517 static const struct i3c_master_controller_ops dw_mipi_i3c_ops = {
1518 .bus_init = dw_i3c_master_bus_init,
1519 .bus_cleanup = dw_i3c_master_bus_cleanup,
1520 .attach_i3c_dev = dw_i3c_master_attach_i3c_dev,
1521 .reattach_i3c_dev = dw_i3c_master_reattach_i3c_dev,
1522 .detach_i3c_dev = dw_i3c_master_detach_i3c_dev,
1523 .do_daa = dw_i3c_master_daa,
1524 .supports_ccc_cmd = dw_i3c_master_supports_ccc_cmd,
1525 .send_ccc_cmd = dw_i3c_master_send_ccc_cmd,
1526 .i3c_xfers = dw_i3c_master_i3c_xfers,
1527 .attach_i2c_dev = dw_i3c_master_attach_i2c_dev,
1528 .detach_i2c_dev = dw_i3c_master_detach_i2c_dev,
1529 .i2c_xfers = dw_i3c_master_i2c_xfers,
1530 .request_ibi = dw_i3c_master_request_ibi,
1531 .free_ibi = dw_i3c_master_free_ibi,
1532 .enable_ibi = dw_i3c_master_enable_ibi,
1533 .disable_ibi = dw_i3c_master_disable_ibi,
1534 .recycle_ibi_slot = dw_i3c_master_recycle_ibi_slot,
1535 .enable_hotjoin = dw_i3c_master_enable_hotjoin,
1536 .disable_hotjoin = dw_i3c_master_disable_hotjoin,
1537 .set_dev_nack_retry = dw_i3c_master_set_dev_nack_retry,
1538 };
1539
1540 /* default platform ops implementations */
dw_i3c_platform_init_nop(struct dw_i3c_master * i3c)1541 static int dw_i3c_platform_init_nop(struct dw_i3c_master *i3c)
1542 {
1543 return 0;
1544 }
1545
dw_i3c_platform_set_dat_ibi_nop(struct dw_i3c_master * i3c,struct i3c_dev_desc * dev,bool enable,u32 * dat)1546 static void dw_i3c_platform_set_dat_ibi_nop(struct dw_i3c_master *i3c,
1547 struct i3c_dev_desc *dev,
1548 bool enable, u32 *dat)
1549 {
1550 }
1551
1552 static const struct dw_i3c_platform_ops dw_i3c_platform_ops_default = {
1553 .init = dw_i3c_platform_init_nop,
1554 .set_dat_ibi = dw_i3c_platform_set_dat_ibi_nop,
1555 };
1556
dw_i3c_hj_work(struct work_struct * work)1557 static void dw_i3c_hj_work(struct work_struct *work)
1558 {
1559 struct dw_i3c_master *master =
1560 container_of(work, typeof(*master), hj_work);
1561
1562 i3c_master_do_daa(&master->base);
1563 }
1564
dw_i3c_common_probe(struct dw_i3c_master * master,struct platform_device * pdev)1565 int dw_i3c_common_probe(struct dw_i3c_master *master,
1566 struct platform_device *pdev)
1567 {
1568 int ret, irq;
1569 const struct dw_i3c_drvdata *drvdata;
1570 unsigned long quirks = 0;
1571
1572 if (!master->platform_ops)
1573 master->platform_ops = &dw_i3c_platform_ops_default;
1574
1575 master->dev = &pdev->dev;
1576
1577 master->regs = devm_platform_ioremap_resource(pdev, 0);
1578 if (IS_ERR(master->regs))
1579 return PTR_ERR(master->regs);
1580
1581 master->core_clk = devm_clk_get_enabled(&pdev->dev, NULL);
1582 if (IS_ERR(master->core_clk))
1583 return PTR_ERR(master->core_clk);
1584
1585 master->pclk = devm_clk_get_optional_enabled(&pdev->dev, "pclk");
1586 if (IS_ERR(master->pclk))
1587 return PTR_ERR(master->pclk);
1588
1589 master->core_rst = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev,
1590 "core_rst");
1591 if (IS_ERR(master->core_rst))
1592 return PTR_ERR(master->core_rst);
1593
1594 spin_lock_init(&master->xferqueue.lock);
1595 INIT_LIST_HEAD(&master->xferqueue.list);
1596
1597 spin_lock_init(&master->devs_lock);
1598
1599 writel(INTR_ALL, master->regs + INTR_STATUS);
1600 irq = platform_get_irq(pdev, 0);
1601 ret = devm_request_irq(&pdev->dev, irq,
1602 dw_i3c_master_irq_handler, 0,
1603 dev_name(&pdev->dev), master);
1604 if (ret)
1605 return ret;
1606
1607 platform_set_drvdata(pdev, master);
1608
1609 pm_runtime_set_autosuspend_delay(&pdev->dev, RPM_AUTOSUSPEND_TIMEOUT);
1610 pm_runtime_use_autosuspend(&pdev->dev);
1611 pm_runtime_set_active(&pdev->dev);
1612 pm_runtime_enable(&pdev->dev);
1613
1614 /* Information regarding the FIFOs/QUEUEs depth */
1615 ret = readl(master->regs + QUEUE_STATUS_LEVEL);
1616 master->caps.cmdfifodepth = QUEUE_STATUS_LEVEL_CMD(ret);
1617
1618 ret = readl(master->regs + DATA_BUFFER_STATUS_LEVEL);
1619 master->caps.datafifodepth = DATA_BUFFER_STATUS_LEVEL_TX(ret);
1620
1621 ret = readl(master->regs + DEVICE_ADDR_TABLE_POINTER);
1622 master->datstartaddr = ret;
1623 master->maxdevs = ret >> 16;
1624 master->free_pos = GENMASK(master->maxdevs - 1, 0);
1625
1626 if (has_acpi_companion(&pdev->dev)) {
1627 quirks = (unsigned long)device_get_match_data(&pdev->dev);
1628 } else if (pdev->dev.of_node) {
1629 drvdata = device_get_match_data(&pdev->dev);
1630 if (drvdata)
1631 quirks = drvdata->flags;
1632 }
1633 master->quirks = quirks;
1634
1635 /* Keep controller enabled by preventing runtime suspend */
1636 if (master->quirks & DW_I3C_DISABLE_RUNTIME_PM_QUIRK)
1637 pm_runtime_get_noresume(&pdev->dev);
1638
1639 INIT_WORK(&master->hj_work, dw_i3c_hj_work);
1640
1641 device_set_of_node_from_dev(&master->base.i2c.dev, &pdev->dev);
1642 ret = i3c_master_register(&master->base, &pdev->dev,
1643 &dw_mipi_i3c_ops, false);
1644 if (ret)
1645 goto err_disable_pm;
1646
1647 return 0;
1648
1649 err_disable_pm:
1650 if (master->quirks & DW_I3C_DISABLE_RUNTIME_PM_QUIRK)
1651 pm_runtime_put_noidle(&pdev->dev);
1652 pm_runtime_disable(&pdev->dev);
1653 pm_runtime_set_suspended(&pdev->dev);
1654 pm_runtime_dont_use_autosuspend(&pdev->dev);
1655
1656 return ret;
1657 }
1658 EXPORT_SYMBOL_GPL(dw_i3c_common_probe);
1659
dw_i3c_common_remove(struct dw_i3c_master * master)1660 void dw_i3c_common_remove(struct dw_i3c_master *master)
1661 {
1662 cancel_work_sync(&master->hj_work);
1663 i3c_master_unregister(&master->base);
1664
1665 /* Balance pm_runtime_get_noresume() from probe() */
1666 if (master->quirks & DW_I3C_DISABLE_RUNTIME_PM_QUIRK)
1667 pm_runtime_put_noidle(master->dev);
1668
1669 pm_runtime_disable(master->dev);
1670 pm_runtime_set_suspended(master->dev);
1671 pm_runtime_dont_use_autosuspend(master->dev);
1672 }
1673 EXPORT_SYMBOL_GPL(dw_i3c_common_remove);
1674
1675 /* base platform implementation */
1676
dw_i3c_probe(struct platform_device * pdev)1677 static int dw_i3c_probe(struct platform_device *pdev)
1678 {
1679 struct dw_i3c_master *master;
1680
1681 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
1682 if (!master)
1683 return -ENOMEM;
1684
1685 return dw_i3c_common_probe(master, pdev);
1686 }
1687
dw_i3c_remove(struct platform_device * pdev)1688 static void dw_i3c_remove(struct platform_device *pdev)
1689 {
1690 struct dw_i3c_master *master = platform_get_drvdata(pdev);
1691
1692 dw_i3c_common_remove(master);
1693 }
1694
dw_i3c_master_restore_addrs(struct dw_i3c_master * master)1695 static void dw_i3c_master_restore_addrs(struct dw_i3c_master *master)
1696 {
1697 u32 pos, reg_val;
1698
1699 writel(DEV_ADDR_DYNAMIC_ADDR_VALID | DEV_ADDR_DYNAMIC(master->dev_addr),
1700 master->regs + DEVICE_ADDR);
1701
1702 for (pos = 0; pos < master->maxdevs; pos++) {
1703 if (master->free_pos & BIT(pos))
1704 continue;
1705
1706 reg_val = readl(master->regs + DEV_ADDR_TABLE_LOC(master->datstartaddr, pos));
1707
1708 if (master->devs[pos].is_i2c_addr) {
1709 reg_val &= ~DEV_ADDR_TABLE_STATIC_MASK;
1710 reg_val |= DEV_ADDR_TABLE_LEGACY_I2C_DEV |
1711 DEV_ADDR_TABLE_STATIC_ADDR(master->devs[pos].addr);
1712 } else {
1713 reg_val &= ~DEV_ADDR_TABLE_DYNAMIC_MASK;
1714 reg_val |= DEV_ADDR_TABLE_DYNAMIC_ADDR(master->devs[pos].addr);
1715 }
1716
1717 writel(reg_val, master->regs + DEV_ADDR_TABLE_LOC(master->datstartaddr, pos));
1718 }
1719 }
1720
dw_i3c_master_restore_timing_regs(struct dw_i3c_master * master)1721 static void dw_i3c_master_restore_timing_regs(struct dw_i3c_master *master)
1722 {
1723 /* AMD platform specific OD and PP timings */
1724 if (master->quirks & AMD_I3C_OD_PP_TIMING)
1725 amd_configure_od_pp_quirk(master);
1726
1727 writel(master->i3c_pp_timing, master->regs + SCL_I3C_PP_TIMING);
1728 writel(master->bus_free_timing, master->regs + BUS_FREE_TIMING);
1729 writel(master->i3c_od_timing, master->regs + SCL_I3C_OD_TIMING);
1730 writel(master->ext_lcnt_timing, master->regs + SCL_EXT_LCNT_TIMING);
1731
1732 if (master->i2c_slv_prsnt) {
1733 writel(master->i2c_fmp_timing, master->regs + SCL_I2C_FMP_TIMING);
1734 writel(master->i2c_fm_timing, master->regs + SCL_I2C_FM_TIMING);
1735 }
1736 }
1737
dw_i3c_master_enable_clks(struct dw_i3c_master * master)1738 static int dw_i3c_master_enable_clks(struct dw_i3c_master *master)
1739 {
1740 int ret = 0;
1741
1742 ret = clk_prepare_enable(master->core_clk);
1743 if (ret)
1744 return ret;
1745
1746 ret = clk_prepare_enable(master->pclk);
1747 if (ret) {
1748 clk_disable_unprepare(master->core_clk);
1749 return ret;
1750 }
1751
1752 return 0;
1753 }
1754
dw_i3c_master_disable_clks(struct dw_i3c_master * master)1755 static inline void dw_i3c_master_disable_clks(struct dw_i3c_master *master)
1756 {
1757 clk_disable_unprepare(master->pclk);
1758 clk_disable_unprepare(master->core_clk);
1759 }
1760
dw_i3c_master_runtime_suspend(struct device * dev)1761 static int __maybe_unused dw_i3c_master_runtime_suspend(struct device *dev)
1762 {
1763 struct dw_i3c_master *master = dev_get_drvdata(dev);
1764
1765 dw_i3c_master_disable(master);
1766
1767 reset_control_assert(master->core_rst);
1768 dw_i3c_master_disable_clks(master);
1769 pinctrl_pm_select_sleep_state(dev);
1770 return 0;
1771 }
1772
dw_i3c_master_runtime_resume(struct device * dev)1773 static int __maybe_unused dw_i3c_master_runtime_resume(struct device *dev)
1774 {
1775 struct dw_i3c_master *master = dev_get_drvdata(dev);
1776
1777 pinctrl_pm_select_default_state(dev);
1778 dw_i3c_master_enable_clks(master);
1779 reset_control_deassert(master->core_rst);
1780
1781 dw_i3c_master_set_intr_regs(master);
1782 dw_i3c_master_restore_timing_regs(master);
1783 dw_i3c_master_restore_addrs(master);
1784
1785 dw_i3c_master_enable(master);
1786 return 0;
1787 }
1788
1789 static const struct dev_pm_ops dw_i3c_pm_ops = {
1790 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
1791 SET_RUNTIME_PM_OPS(dw_i3c_master_runtime_suspend, dw_i3c_master_runtime_resume, NULL)
1792 };
1793
dw_i3c_shutdown(struct platform_device * pdev)1794 static void dw_i3c_shutdown(struct platform_device *pdev)
1795 {
1796 struct dw_i3c_master *master = platform_get_drvdata(pdev);
1797 int ret;
1798
1799 ret = pm_runtime_resume_and_get(master->dev);
1800 if (ret < 0) {
1801 dev_err(master->dev,
1802 "<%s> cannot resume i3c bus master, err: %d\n",
1803 __func__, ret);
1804 return;
1805 }
1806
1807 cancel_work_sync(&master->hj_work);
1808
1809 /* Disable interrupts */
1810 writel((u32)~INTR_ALL, master->regs + INTR_STATUS_EN);
1811 writel((u32)~INTR_ALL, master->regs + INTR_SIGNAL_EN);
1812
1813 pm_runtime_put_autosuspend(master->dev);
1814 }
1815
1816 static const struct dw_i3c_drvdata altr_agilex5_drvdata = {
1817 .flags = DW_I3C_DISABLE_RUNTIME_PM_QUIRK,
1818 };
1819
1820 static const struct of_device_id dw_i3c_master_of_match[] = {
1821 { .compatible = "snps,dw-i3c-master-1.00a", },
1822 { .compatible = "altr,agilex5-dw-i3c-master",
1823 .data = &altr_agilex5_drvdata,
1824 },
1825 {},
1826 };
1827 MODULE_DEVICE_TABLE(of, dw_i3c_master_of_match);
1828
1829 static const struct acpi_device_id amd_i3c_device_match[] = {
1830 { "AMDI0015", AMD_I3C_OD_PP_TIMING },
1831 { }
1832 };
1833 MODULE_DEVICE_TABLE(acpi, amd_i3c_device_match);
1834
1835 static struct platform_driver dw_i3c_driver = {
1836 .probe = dw_i3c_probe,
1837 .remove = dw_i3c_remove,
1838 .shutdown = dw_i3c_shutdown,
1839 .driver = {
1840 .name = "dw-i3c-master",
1841 .of_match_table = dw_i3c_master_of_match,
1842 .acpi_match_table = amd_i3c_device_match,
1843 .pm = &dw_i3c_pm_ops,
1844 },
1845 };
1846 module_platform_driver(dw_i3c_driver);
1847
1848 MODULE_AUTHOR("Vitor Soares <vitor.soares@synopsys.com>");
1849 MODULE_DESCRIPTION("DesignWare MIPI I3C driver");
1850 MODULE_LICENSE("GPL v2");
1851