1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Promise PATA TX2/TX4/TX2000/133 IDE driver for pdc20268 to pdc20277. 4 * 5 * Ported to libata by: 6 * Albert Lee <albertcc@tw.ibm.com> IBM Corporation 7 * 8 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org> 9 * Portions Copyright (C) 1999 Promise Technology, Inc. 10 * 11 * Author: Frank Tiernan (frankt@promise.com) 12 * Released under terms of General Public License 13 * 14 * libata documentation is available via 'make {ps|pdf}docs', 15 * as Documentation/driver-api/libata.rst 16 * 17 * Hardware information only available under NDA. 18 */ 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/pci.h> 22 #include <linux/blkdev.h> 23 #include <linux/delay.h> 24 #include <linux/device.h> 25 #include <linux/ktime.h> 26 #include <scsi/scsi.h> 27 #include <scsi/scsi_host.h> 28 #include <scsi/scsi_cmnd.h> 29 #include <linux/libata.h> 30 31 #define DRV_NAME "pata_pdc2027x" 32 #define DRV_VERSION "1.0" 33 34 enum { 35 PDC_MMIO_BAR = 5, 36 37 PDC_UDMA_100 = 0, 38 PDC_UDMA_133 = 1, 39 40 PDC_100_MHZ = 100000000, 41 PDC_133_MHZ = 133333333, 42 43 PDC_SYS_CTL = 0x1100, 44 PDC_ATA_CTL = 0x1104, 45 PDC_GLOBAL_CTL = 0x1108, 46 PDC_CTCR0 = 0x110C, 47 PDC_CTCR1 = 0x1110, 48 PDC_BYTE_COUNT = 0x1120, 49 PDC_PLL_CTL = 0x1202, 50 }; 51 52 static int pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 53 #ifdef CONFIG_PM_SLEEP 54 static int pdc2027x_reinit_one(struct pci_dev *pdev); 55 #endif 56 static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline); 57 static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev); 58 static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev); 59 static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc); 60 static unsigned int pdc2027x_mode_filter(struct ata_device *adev, unsigned int mask); 61 static int pdc2027x_cable_detect(struct ata_port *ap); 62 static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed); 63 64 /* 65 * ATA Timing Tables based on 133MHz controller clock. 66 * These tables are only used when the controller is in 133MHz clock. 67 * If the controller is in 100MHz clock, the ASIC hardware will 68 * set the timing registers automatically when "set feature" command 69 * is issued to the device. However, if the controller clock is 133MHz, 70 * the following tables must be used. 71 */ 72 static const struct pdc2027x_pio_timing { 73 u8 value0, value1, value2; 74 } pdc2027x_pio_timing_tbl[] = { 75 { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */ 76 { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */ 77 { 0x23, 0x26, 0x64 }, /* PIO mode 2 */ 78 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */ 79 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */ 80 }; 81 82 static const struct pdc2027x_mdma_timing { 83 u8 value0, value1; 84 } pdc2027x_mdma_timing_tbl[] = { 85 { 0xdf, 0x5f }, /* MDMA mode 0 */ 86 { 0x6b, 0x27 }, /* MDMA mode 1 */ 87 { 0x69, 0x25 }, /* MDMA mode 2 */ 88 }; 89 90 static const struct pdc2027x_udma_timing { 91 u8 value0, value1, value2; 92 } pdc2027x_udma_timing_tbl[] = { 93 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */ 94 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */ 95 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */ 96 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */ 97 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */ 98 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */ 99 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */ 100 }; 101 102 static const struct pci_device_id pdc2027x_pci_tbl[] = { 103 { 104 PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), 105 .driver_data = PDC_UDMA_100, 106 }, { 107 PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), 108 .driver_data = PDC_UDMA_133, 109 }, { 110 PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), 111 .driver_data = PDC_UDMA_100, 112 }, { 113 PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), 114 .driver_data = PDC_UDMA_133, 115 }, { 116 PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), 117 .driver_data = PDC_UDMA_133, 118 }, { 119 PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), 120 .driver_data = PDC_UDMA_133, 121 }, { 122 PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), 123 .driver_data = PDC_UDMA_133, 124 }, 125 { } /* terminate list */ 126 }; 127 128 static struct pci_driver pdc2027x_pci_driver = { 129 .name = DRV_NAME, 130 .id_table = pdc2027x_pci_tbl, 131 .probe = pdc2027x_init_one, 132 .remove = ata_pci_remove_one, 133 #ifdef CONFIG_PM_SLEEP 134 .suspend = ata_pci_device_suspend, 135 .resume = pdc2027x_reinit_one, 136 #endif 137 }; 138 139 static const struct scsi_host_template pdc2027x_sht = { 140 ATA_BMDMA_SHT(DRV_NAME), 141 }; 142 143 static struct ata_port_operations pdc2027x_pata100_ops = { 144 .inherits = &ata_bmdma_port_ops, 145 .check_atapi_dma = pdc2027x_check_atapi_dma, 146 .cable_detect = pdc2027x_cable_detect, 147 .reset.prereset = pdc2027x_prereset, 148 }; 149 150 static struct ata_port_operations pdc2027x_pata133_ops = { 151 .inherits = &pdc2027x_pata100_ops, 152 .mode_filter = pdc2027x_mode_filter, 153 .set_piomode = pdc2027x_set_piomode, 154 .set_dmamode = pdc2027x_set_dmamode, 155 .set_mode = pdc2027x_set_mode, 156 }; 157 158 static struct ata_port_info pdc2027x_port_info[] = { 159 /* PDC_UDMA_100 */ 160 { 161 .flags = ATA_FLAG_SLAVE_POSS, 162 .pio_mask = ATA_PIO4, 163 .mwdma_mask = ATA_MWDMA2, 164 .udma_mask = ATA_UDMA5, 165 .port_ops = &pdc2027x_pata100_ops, 166 }, 167 /* PDC_UDMA_133 */ 168 { 169 .flags = ATA_FLAG_SLAVE_POSS, 170 .pio_mask = ATA_PIO4, 171 .mwdma_mask = ATA_MWDMA2, 172 .udma_mask = ATA_UDMA6, 173 .port_ops = &pdc2027x_pata133_ops, 174 }, 175 }; 176 177 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Albert Lee"); 178 MODULE_DESCRIPTION("libata driver module for Promise PDC20268 to PDC20277"); 179 MODULE_LICENSE("GPL"); 180 MODULE_VERSION(DRV_VERSION); 181 MODULE_DEVICE_TABLE(pci, pdc2027x_pci_tbl); 182 183 /** 184 * port_mmio - Get the MMIO address of PDC2027x extended registers 185 * @ap: Port 186 * @offset: offset from mmio base 187 */ 188 static inline void __iomem *port_mmio(struct ata_port *ap, unsigned int offset) 189 { 190 return ap->host->iomap[PDC_MMIO_BAR] + ap->port_no * 0x100 + offset; 191 } 192 193 /** 194 * dev_mmio - Get the MMIO address of PDC2027x extended registers 195 * @ap: Port 196 * @adev: device 197 * @offset: offset from mmio base 198 */ 199 static inline void __iomem *dev_mmio(struct ata_port *ap, struct ata_device *adev, unsigned int offset) 200 { 201 u8 adj = (adev->devno) ? 0x08 : 0x00; 202 return port_mmio(ap, offset) + adj; 203 } 204 205 /** 206 * pdc2027x_cable_detect - Probe host controller cable detect info 207 * @ap: Port for which cable detect info is desired 208 * 209 * Read 80c cable indicator from Promise extended register. 210 * This register is latched when the system is reset. 211 * 212 * LOCKING: 213 * None (inherited from caller). 214 */ 215 static int pdc2027x_cable_detect(struct ata_port *ap) 216 { 217 u32 cgcr; 218 219 /* check cable detect results */ 220 cgcr = ioread32(port_mmio(ap, PDC_GLOBAL_CTL)); 221 if (cgcr & (1 << 26)) 222 goto cbl40; 223 224 ata_port_dbg(ap, "No cable or 80-conductor cable\n"); 225 226 return ATA_CBL_PATA80; 227 cbl40: 228 ata_port_info(ap, DRV_NAME ":40-conductor cable detected\n"); 229 return ATA_CBL_PATA40; 230 } 231 232 /** 233 * pdc2027x_port_enabled - Check PDC ATA control register to see whether the port is enabled. 234 * @ap: Port to check 235 */ 236 static inline int pdc2027x_port_enabled(struct ata_port *ap) 237 { 238 return ioread8(port_mmio(ap, PDC_ATA_CTL)) & 0x02; 239 } 240 241 /** 242 * pdc2027x_prereset - prereset for PATA host controller 243 * @link: Target link 244 * @deadline: deadline jiffies for the operation 245 * 246 * Probeinit including cable detection. 247 * 248 * LOCKING: 249 * None (inherited from caller). 250 */ 251 252 static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline) 253 { 254 /* Check whether port enabled */ 255 if (!pdc2027x_port_enabled(link->ap)) 256 return -ENOENT; 257 return ata_sff_prereset(link, deadline); 258 } 259 260 /** 261 * pdc2027x_mode_filter - mode selection filter 262 * @adev: ATA device 263 * @mask: list of modes proposed 264 * 265 * Block UDMA on devices that cause trouble with this controller. 266 */ 267 268 static unsigned int pdc2027x_mode_filter(struct ata_device *adev, unsigned int mask) 269 { 270 unsigned char model_num[ATA_ID_PROD_LEN + 1]; 271 struct ata_device *pair = ata_dev_pair(adev); 272 273 if (adev->class != ATA_DEV_ATA || adev->devno == 0 || pair == NULL) 274 return mask; 275 276 /* Check for slave of a Maxtor at UDMA6 */ 277 ata_id_c_string(pair->id, model_num, ATA_ID_PROD, 278 ATA_ID_PROD_LEN + 1); 279 /* If the master is a maxtor in UDMA6 then the slave should not use UDMA 6 */ 280 if (strstr(model_num, "Maxtor") == NULL && pair->dma_mode == XFER_UDMA_6) 281 mask &= ~ (1 << (6 + ATA_SHIFT_UDMA)); 282 283 return mask; 284 } 285 286 /** 287 * pdc2027x_set_piomode - Initialize host controller PATA PIO timings 288 * @ap: Port to configure 289 * @adev: um 290 * 291 * Set PIO mode for device. 292 * 293 * LOCKING: 294 * None (inherited from caller). 295 */ 296 297 static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev) 298 { 299 unsigned int pio = adev->pio_mode - XFER_PIO_0; 300 u32 ctcr0, ctcr1; 301 302 ata_port_dbg(ap, "adev->pio_mode[%X]\n", adev->pio_mode); 303 304 /* Sanity check */ 305 if (pio > 4) { 306 ata_port_err(ap, "Unknown pio mode [%d] ignored\n", pio); 307 return; 308 309 } 310 311 /* Set the PIO timing registers using value table for 133MHz */ 312 ata_port_dbg(ap, "Set PIO regs...\n"); 313 314 ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0)); 315 ctcr0 &= 0xffff0000; 316 ctcr0 |= pdc2027x_pio_timing_tbl[pio].value0 | 317 (pdc2027x_pio_timing_tbl[pio].value1 << 8); 318 iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0)); 319 320 ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1)); 321 ctcr1 &= 0x00ffffff; 322 ctcr1 |= (pdc2027x_pio_timing_tbl[pio].value2 << 24); 323 iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1)); 324 325 ata_port_dbg(ap, "Set to PIO mode[%u]\n", pio); 326 } 327 328 /** 329 * pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings 330 * @ap: Port to configure 331 * @adev: um 332 * 333 * Set UDMA mode for device. 334 * 335 * LOCKING: 336 * None (inherited from caller). 337 */ 338 static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev) 339 { 340 unsigned int dma_mode = adev->dma_mode; 341 u32 ctcr0, ctcr1; 342 343 if ((dma_mode >= XFER_UDMA_0) && 344 (dma_mode <= XFER_UDMA_6)) { 345 /* Set the UDMA timing registers with value table for 133MHz */ 346 unsigned int udma_mode = dma_mode & 0x07; 347 348 if (dma_mode == XFER_UDMA_2) { 349 /* 350 * Turn off tHOLD. 351 * If tHOLD is '1', the hardware will add half clock for data hold time. 352 * This code segment seems to be no effect. tHOLD will be overwritten below. 353 */ 354 ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1)); 355 iowrite32(ctcr1 & ~(1 << 7), dev_mmio(ap, adev, PDC_CTCR1)); 356 } 357 358 ata_port_dbg(ap, "Set UDMA regs...\n"); 359 360 ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1)); 361 ctcr1 &= 0xff000000; 362 ctcr1 |= pdc2027x_udma_timing_tbl[udma_mode].value0 | 363 (pdc2027x_udma_timing_tbl[udma_mode].value1 << 8) | 364 (pdc2027x_udma_timing_tbl[udma_mode].value2 << 16); 365 iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1)); 366 367 ata_port_dbg(ap, "Set to UDMA mode[%u]\n", udma_mode); 368 369 } else if ((dma_mode >= XFER_MW_DMA_0) && 370 (dma_mode <= XFER_MW_DMA_2)) { 371 /* Set the MDMA timing registers with value table for 133MHz */ 372 unsigned int mdma_mode = dma_mode & 0x07; 373 374 ata_port_dbg(ap, "Set MDMA regs...\n"); 375 ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0)); 376 377 ctcr0 &= 0x0000ffff; 378 ctcr0 |= (pdc2027x_mdma_timing_tbl[mdma_mode].value0 << 16) | 379 (pdc2027x_mdma_timing_tbl[mdma_mode].value1 << 24); 380 381 iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0)); 382 383 ata_port_dbg(ap, "Set to MDMA mode[%u]\n", mdma_mode); 384 } else { 385 ata_port_err(ap, "Unknown dma mode [%u] ignored\n", dma_mode); 386 } 387 } 388 389 /** 390 * pdc2027x_set_mode - Set the timing registers back to correct values. 391 * @link: link to configure 392 * @r_failed: Returned device for failure 393 * 394 * The pdc2027x hardware will look at "SET FEATURES" and change the timing registers 395 * automatically. The values set by the hardware might be incorrect, under 133Mhz PLL. 396 * This function overwrites the possibly incorrect values set by the hardware to be correct. 397 */ 398 static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed) 399 { 400 struct ata_port *ap = link->ap; 401 struct ata_device *dev; 402 int rc; 403 404 rc = ata_set_mode(link, r_failed); 405 if (rc < 0) 406 return rc; 407 408 ata_for_each_dev(dev, link, ENABLED) { 409 pdc2027x_set_piomode(ap, dev); 410 411 /* 412 * Enable prefetch if the device support PIO only. 413 */ 414 if (dev->xfer_shift == ATA_SHIFT_PIO) { 415 u32 ctcr1 = ioread32(dev_mmio(ap, dev, PDC_CTCR1)); 416 ctcr1 |= (1 << 25); 417 iowrite32(ctcr1, dev_mmio(ap, dev, PDC_CTCR1)); 418 419 ata_dev_dbg(dev, "Turn on prefetch\n"); 420 } else { 421 pdc2027x_set_dmamode(ap, dev); 422 } 423 } 424 return 0; 425 } 426 427 /** 428 * pdc2027x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command 429 * @qc: Metadata associated with taskfile to check 430 * 431 * LOCKING: 432 * None (inherited from caller). 433 * 434 * RETURNS: 0 when ATAPI DMA can be used 435 * 1 otherwise 436 */ 437 static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc) 438 { 439 struct scsi_cmnd *cmd = qc->scsicmd; 440 u8 *scsicmd = cmd->cmnd; 441 int rc = 1; /* atapi dma off by default */ 442 443 /* 444 * This workaround is from Promise's GPL driver. 445 * If ATAPI DMA is used for commands not in the 446 * following white list, say MODE_SENSE and REQUEST_SENSE, 447 * pdc2027x might hit the irq lost problem. 448 */ 449 switch (scsicmd[0]) { 450 case READ_10: 451 case WRITE_10: 452 case READ_12: 453 case WRITE_12: 454 case READ_6: 455 case WRITE_6: 456 case 0xad: /* READ_DVD_STRUCTURE */ 457 case 0xbe: /* READ_CD */ 458 /* ATAPI DMA is ok */ 459 rc = 0; 460 break; 461 default: 462 ; 463 } 464 465 return rc; 466 } 467 468 /** 469 * pdc_read_counter - Read the ctr counter 470 * @host: target ATA host 471 */ 472 473 static long pdc_read_counter(struct ata_host *host) 474 { 475 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; 476 long counter; 477 int retry = 1; 478 u32 bccrl, bccrh, bccrlv, bccrhv; 479 480 retry: 481 bccrl = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff; 482 bccrh = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff; 483 484 /* Read the counter values again for verification */ 485 bccrlv = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff; 486 bccrhv = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff; 487 488 counter = (bccrh << 15) | bccrl; 489 490 dev_dbg(host->dev, "bccrh [%X] bccrl [%X]\n", bccrh, bccrl); 491 dev_dbg(host->dev, "bccrhv[%X] bccrlv[%X]\n", bccrhv, bccrlv); 492 493 /* 494 * The 30-bit decreasing counter are read by 2 pieces. 495 * Incorrect value may be read when both bccrh and bccrl are changing. 496 * Ex. When 7900 decrease to 78FF, wrong value 7800 might be read. 497 */ 498 if (retry && !(bccrh == bccrhv && bccrl >= bccrlv)) { 499 retry--; 500 dev_dbg(host->dev, "rereading counter\n"); 501 goto retry; 502 } 503 504 return counter; 505 } 506 507 /** 508 * pdc_adjust_pll - Adjust the PLL input clock in Hz. 509 * 510 * @host: target ATA host 511 * @pll_clock: The input of PLL in HZ 512 * @board_idx: board identifier 513 */ 514 static void pdc_adjust_pll(struct ata_host *host, long pll_clock, unsigned int board_idx) 515 { 516 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; 517 u16 pll_ctl; 518 long pll_clock_khz = pll_clock / 1000; 519 long pout_required = board_idx? PDC_133_MHZ:PDC_100_MHZ; 520 long ratio = pout_required / pll_clock_khz; 521 int F, R; 522 523 /* Sanity check */ 524 if (unlikely(pll_clock_khz < 5000L || pll_clock_khz > 70000L)) { 525 dev_err(host->dev, "Invalid PLL input clock %ldkHz, give up!\n", 526 pll_clock_khz); 527 return; 528 } 529 530 dev_dbg(host->dev, "pout_required is %ld\n", pout_required); 531 532 /* Show the current clock value of PLL control register 533 * (maybe already configured by the firmware) 534 */ 535 pll_ctl = ioread16(mmio_base + PDC_PLL_CTL); 536 537 dev_dbg(host->dev, "pll_ctl[%X]\n", pll_ctl); 538 539 /* 540 * Calculate the ratio of F, R and OD 541 * POUT = (F + 2) / (( R + 2) * NO) 542 */ 543 if (ratio < 8600L) { /* 8.6x */ 544 /* Using NO = 0x01, R = 0x0D */ 545 R = 0x0d; 546 } else if (ratio < 12900L) { /* 12.9x */ 547 /* Using NO = 0x01, R = 0x08 */ 548 R = 0x08; 549 } else if (ratio < 16100L) { /* 16.1x */ 550 /* Using NO = 0x01, R = 0x06 */ 551 R = 0x06; 552 } else if (ratio < 64000L) { /* 64x */ 553 R = 0x00; 554 } else { 555 /* Invalid ratio */ 556 dev_err(host->dev, "Invalid ratio %ld, give up!\n", ratio); 557 return; 558 } 559 560 F = (ratio * (R+2)) / 1000 - 2; 561 562 if (unlikely(F < 0 || F > 127)) { 563 /* Invalid F */ 564 dev_err(host->dev, "F[%d] invalid!\n", F); 565 return; 566 } 567 568 dev_dbg(host->dev, "F[%d] R[%d] ratio*1000[%ld]\n", F, R, ratio); 569 570 pll_ctl = (R << 8) | F; 571 572 dev_dbg(host->dev, "Writing pll_ctl[%X]\n", pll_ctl); 573 574 iowrite16(pll_ctl, mmio_base + PDC_PLL_CTL); 575 ioread16(mmio_base + PDC_PLL_CTL); /* flush */ 576 577 /* Wait the PLL circuit to be stable */ 578 msleep(30); 579 580 /* 581 * Show the current clock value of PLL control register 582 * (maybe configured by the firmware) 583 */ 584 pll_ctl = ioread16(mmio_base + PDC_PLL_CTL); 585 586 dev_dbg(host->dev, "pll_ctl[%X]\n", pll_ctl); 587 588 return; 589 } 590 591 /** 592 * pdc_detect_pll_input_clock - Detect the PLL input clock in Hz. 593 * @host: target ATA host 594 * Ex. 16949000 on 33MHz PCI bus for pdc20275. 595 * Half of the PCI clock. 596 */ 597 static long pdc_detect_pll_input_clock(struct ata_host *host) 598 { 599 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; 600 u32 scr; 601 long start_count, end_count; 602 ktime_t start_time, end_time; 603 long pll_clock, usec_elapsed; 604 605 /* Start the test mode */ 606 scr = ioread32(mmio_base + PDC_SYS_CTL); 607 dev_dbg(host->dev, "scr[%X]\n", scr); 608 iowrite32(scr | (0x01 << 14), mmio_base + PDC_SYS_CTL); 609 ioread32(mmio_base + PDC_SYS_CTL); /* flush */ 610 611 /* Read current counter value */ 612 start_count = pdc_read_counter(host); 613 start_time = ktime_get(); 614 615 /* Let the counter run for 100 ms. */ 616 msleep(100); 617 618 /* Read the counter values again */ 619 end_count = pdc_read_counter(host); 620 end_time = ktime_get(); 621 622 /* Stop the test mode */ 623 scr = ioread32(mmio_base + PDC_SYS_CTL); 624 dev_dbg(host->dev, "scr[%X]\n", scr); 625 iowrite32(scr & ~(0x01 << 14), mmio_base + PDC_SYS_CTL); 626 ioread32(mmio_base + PDC_SYS_CTL); /* flush */ 627 628 /* calculate the input clock in Hz */ 629 usec_elapsed = (long) ktime_us_delta(end_time, start_time); 630 631 pll_clock = ((start_count - end_count) & 0x3fffffff) / 100 * 632 (100000000 / usec_elapsed); 633 634 dev_dbg(host->dev, "start[%ld] end[%ld] PLL input clock[%ld]HZ\n", 635 start_count, end_count, pll_clock); 636 637 return pll_clock; 638 } 639 640 /** 641 * pdc_hardware_init - Initialize the hardware. 642 * @host: target ATA host 643 * @board_idx: board identifier 644 */ 645 static void pdc_hardware_init(struct ata_host *host, unsigned int board_idx) 646 { 647 long pll_clock; 648 649 /* 650 * Detect PLL input clock rate. 651 * On some system, where PCI bus is running at non-standard clock rate. 652 * Ex. 25MHz or 40MHz, we have to adjust the cycle_time. 653 * The pdc20275 controller employs PLL circuit to help correct timing registers setting. 654 */ 655 pll_clock = pdc_detect_pll_input_clock(host); 656 657 dev_info(host->dev, "PLL input clock %ld kHz\n", pll_clock/1000); 658 659 /* Adjust PLL control register */ 660 pdc_adjust_pll(host, pll_clock, board_idx); 661 } 662 663 /** 664 * pdc_ata_setup_port - setup the mmio address 665 * @port: ata ioports to setup 666 * @base: base address 667 */ 668 static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base) 669 { 670 port->cmd_addr = 671 port->data_addr = base; 672 port->feature_addr = 673 port->error_addr = base + 0x05; 674 port->nsect_addr = base + 0x0a; 675 port->lbal_addr = base + 0x0f; 676 port->lbam_addr = base + 0x10; 677 port->lbah_addr = base + 0x15; 678 port->device_addr = base + 0x1a; 679 port->command_addr = 680 port->status_addr = base + 0x1f; 681 port->altstatus_addr = 682 port->ctl_addr = base + 0x81a; 683 } 684 685 /** 686 * pdc2027x_init_one - PCI probe function 687 * Called when an instance of PCI adapter is inserted. 688 * This function checks whether the hardware is supported, 689 * initialize hardware and register an instance of ata_host to 690 * libata. (implements struct pci_driver.probe() ) 691 * 692 * @pdev: instance of pci_dev found 693 * @ent: matching entry in the id_tbl[] 694 */ 695 static int pdc2027x_init_one(struct pci_dev *pdev, 696 const struct pci_device_id *ent) 697 { 698 static const unsigned long cmd_offset[] = { 0x17c0, 0x15c0 }; 699 static const unsigned long bmdma_offset[] = { 0x1000, 0x1008 }; 700 unsigned int board_idx = (unsigned int) ent->driver_data; 701 const struct ata_port_info *ppi[] = 702 { &pdc2027x_port_info[board_idx], NULL }; 703 struct ata_host *host; 704 void __iomem *mmio_base; 705 int i, rc; 706 707 ata_print_version_once(&pdev->dev, DRV_VERSION); 708 709 /* alloc host */ 710 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); 711 if (!host) 712 return -ENOMEM; 713 714 /* acquire resources and fill host */ 715 rc = pcim_enable_device(pdev); 716 if (rc) 717 return rc; 718 719 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME); 720 if (rc) 721 return rc; 722 host->iomap = pcim_iomap_table(pdev); 723 724 rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK); 725 if (rc) 726 return rc; 727 728 mmio_base = host->iomap[PDC_MMIO_BAR]; 729 730 for (i = 0; i < 2; i++) { 731 struct ata_port *ap = host->ports[i]; 732 733 pdc_ata_setup_port(&ap->ioaddr, mmio_base + cmd_offset[i]); 734 ap->ioaddr.bmdma_addr = mmio_base + bmdma_offset[i]; 735 736 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio"); 737 ata_port_pbar_desc(ap, PDC_MMIO_BAR, cmd_offset[i], "cmd"); 738 } 739 740 //pci_enable_intx(pdev); 741 742 /* initialize adapter */ 743 pdc_hardware_init(host, board_idx); 744 745 pci_set_master(pdev); 746 return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt, 747 IRQF_SHARED, &pdc2027x_sht); 748 } 749 750 #ifdef CONFIG_PM_SLEEP 751 static int pdc2027x_reinit_one(struct pci_dev *pdev) 752 { 753 struct ata_host *host = pci_get_drvdata(pdev); 754 unsigned int board_idx; 755 int rc; 756 757 rc = ata_pci_device_do_resume(pdev); 758 if (rc) 759 return rc; 760 761 if (pdev->device == PCI_DEVICE_ID_PROMISE_20268 || 762 pdev->device == PCI_DEVICE_ID_PROMISE_20270) 763 board_idx = PDC_UDMA_100; 764 else 765 board_idx = PDC_UDMA_133; 766 767 pdc_hardware_init(host, board_idx); 768 769 ata_host_resume(host); 770 return 0; 771 } 772 #endif 773 774 module_pci_driver(pdc2027x_pci_driver); 775