1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/acpi.h> 7 #include <linux/clk.h> 8 #include <linux/cleanup.h> 9 #include <linux/delay.h> 10 #include <linux/devfreq.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/interconnect.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/phy/phy.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_domain.h> 18 #include <linux/reset-controller.h> 19 #include <linux/time.h> 20 #include <linux/unaligned.h> 21 #include <linux/units.h> 22 23 #include <soc/qcom/ice.h> 24 25 #include <ufs/ufshcd.h> 26 #include <ufs/ufshci.h> 27 #include <ufs/ufs_quirks.h> 28 #include <ufs/unipro.h> 29 #include "ufshcd-pltfrm.h" 30 #include "ufs-qcom.h" 31 32 #define MCQ_QCFGPTR_MASK GENMASK(7, 0) 33 #define MCQ_QCFGPTR_UNIT 0x200 34 #define MCQ_SQATTR_OFFSET(c) \ 35 ((((c) >> 16) & MCQ_QCFGPTR_MASK) * MCQ_QCFGPTR_UNIT) 36 #define MCQ_QCFG_SIZE 0x40 37 38 /* De-emphasis for gear-5 */ 39 #define DEEMPHASIS_3_5_dB 0x04 40 #define NO_DEEMPHASIS 0x0 41 42 #define UFS_ICE_SYNC_RST_SEL BIT(3) 43 #define UFS_ICE_SYNC_RST_SW BIT(4) 44 45 enum { 46 TSTBUS_UAWM, 47 TSTBUS_UARM, 48 TSTBUS_TXUC, 49 TSTBUS_RXUC, 50 TSTBUS_DFC, 51 TSTBUS_TRLUT, 52 TSTBUS_TMRLUT, 53 TSTBUS_OCSC, 54 TSTBUS_UTP_HCI, 55 TSTBUS_COMBINED, 56 TSTBUS_WRAPPER, 57 TSTBUS_UNIPRO, 58 TSTBUS_MAX, 59 }; 60 61 #define QCOM_UFS_MAX_GEAR 5 62 #define QCOM_UFS_MAX_LANE 2 63 64 enum { 65 MODE_MIN, 66 MODE_PWM, 67 MODE_HS_RA, 68 MODE_HS_RB, 69 MODE_MAX, 70 }; 71 72 static const struct __ufs_qcom_bw_table { 73 u32 mem_bw; 74 u32 cfg_bw; 75 } ufs_qcom_bw_table[MODE_MAX + 1][QCOM_UFS_MAX_GEAR + 1][QCOM_UFS_MAX_LANE + 1] = { 76 [MODE_MIN][0][0] = { 0, 0 }, /* Bandwidth values in KB/s */ 77 [MODE_PWM][UFS_PWM_G1][UFS_LANE_1] = { 922, 1000 }, 78 [MODE_PWM][UFS_PWM_G2][UFS_LANE_1] = { 1844, 1000 }, 79 [MODE_PWM][UFS_PWM_G3][UFS_LANE_1] = { 3688, 1000 }, 80 [MODE_PWM][UFS_PWM_G4][UFS_LANE_1] = { 7376, 1000 }, 81 [MODE_PWM][UFS_PWM_G5][UFS_LANE_1] = { 14752, 1000 }, 82 [MODE_PWM][UFS_PWM_G1][UFS_LANE_2] = { 1844, 1000 }, 83 [MODE_PWM][UFS_PWM_G2][UFS_LANE_2] = { 3688, 1000 }, 84 [MODE_PWM][UFS_PWM_G3][UFS_LANE_2] = { 7376, 1000 }, 85 [MODE_PWM][UFS_PWM_G4][UFS_LANE_2] = { 14752, 1000 }, 86 [MODE_PWM][UFS_PWM_G5][UFS_LANE_2] = { 29504, 1000 }, 87 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_1] = { 127796, 1000 }, 88 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_1] = { 255591, 1000 }, 89 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 }, 90 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 }, 91 [MODE_HS_RA][UFS_HS_G5][UFS_LANE_1] = { 5836800, 409600 }, 92 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_2] = { 255591, 1000 }, 93 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_2] = { 511181, 1000 }, 94 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 }, 95 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 }, 96 [MODE_HS_RA][UFS_HS_G5][UFS_LANE_2] = { 5836800, 819200 }, 97 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_1] = { 149422, 1000 }, 98 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_1] = { 298189, 1000 }, 99 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 }, 100 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 }, 101 [MODE_HS_RB][UFS_HS_G5][UFS_LANE_1] = { 5836800, 409600 }, 102 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_2] = { 298189, 1000 }, 103 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_2] = { 596378, 1000 }, 104 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 }, 105 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 }, 106 [MODE_HS_RB][UFS_HS_G5][UFS_LANE_2] = { 5836800, 819200 }, 107 [MODE_MAX][0][0] = { 7643136, 819200 }, 108 }; 109 110 static const struct { 111 int nminor; 112 char *prefix; 113 } testbus_info[TSTBUS_MAX] = { 114 [TSTBUS_UAWM] = {32, "TSTBUS_UAWM"}, 115 [TSTBUS_UARM] = {32, "TSTBUS_UARM"}, 116 [TSTBUS_TXUC] = {32, "TSTBUS_TXUC"}, 117 [TSTBUS_RXUC] = {32, "TSTBUS_RXUC"}, 118 [TSTBUS_DFC] = {32, "TSTBUS_DFC"}, 119 [TSTBUS_TRLUT] = {32, "TSTBUS_TRLUT"}, 120 [TSTBUS_TMRLUT] = {32, "TSTBUS_TMRLUT"}, 121 [TSTBUS_OCSC] = {32, "TSTBUS_OCSC"}, 122 [TSTBUS_UTP_HCI] = {32, "TSTBUS_UTP_HCI"}, 123 [TSTBUS_COMBINED] = {32, "TSTBUS_COMBINED"}, 124 [TSTBUS_WRAPPER] = {32, "TSTBUS_WRAPPER"}, 125 [TSTBUS_UNIPRO] = {256, "TSTBUS_UNIPRO"}, 126 }; 127 128 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host); 129 static unsigned long ufs_qcom_opp_freq_to_clk_freq(struct ufs_hba *hba, 130 unsigned long freq, char *name); 131 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up, unsigned long freq); 132 133 static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd) 134 { 135 return container_of(rcd, struct ufs_qcom_host, rcdev); 136 } 137 138 #ifdef CONFIG_SCSI_UFS_CRYPTO 139 /** 140 * ufs_qcom_config_ice_allocator() - ICE core allocator configuration 141 * 142 * @host: pointer to qcom specific variant structure. 143 */ 144 static void ufs_qcom_config_ice_allocator(struct ufs_qcom_host *host) 145 { 146 struct ufs_hba *hba = host->hba; 147 static const uint8_t val[4] = { NUM_RX_R1W0, NUM_TX_R0W1, NUM_RX_R1W1, NUM_TX_R1W1 }; 148 u32 config; 149 150 if (!(host->caps & UFS_QCOM_CAP_ICE_CONFIG) || 151 !(host->hba->caps & UFSHCD_CAP_CRYPTO)) 152 return; 153 154 config = get_unaligned_le32(val); 155 156 ufshcd_writel(hba, ICE_ALLOCATOR_TYPE, REG_UFS_MEM_ICE_CONFIG); 157 ufshcd_writel(hba, config, REG_UFS_MEM_ICE_NUM_CORE); 158 } 159 160 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host) 161 { 162 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 163 qcom_ice_enable(host->ice); 164 } 165 166 static const struct blk_crypto_ll_ops ufs_qcom_crypto_ops; /* forward decl */ 167 168 static int ufs_qcom_ice_init(struct ufs_qcom_host *host) 169 { 170 struct ufs_hba *hba = host->hba; 171 struct blk_crypto_profile *profile = &hba->crypto_profile; 172 struct device *dev = hba->dev; 173 struct qcom_ice *ice; 174 union ufs_crypto_capabilities caps; 175 union ufs_crypto_cap_entry cap; 176 int err; 177 int i; 178 179 ice = devm_of_qcom_ice_get(dev); 180 if (IS_ERR(ice)) { 181 if (ice != ERR_PTR(-EOPNOTSUPP)) 182 return PTR_ERR(ice); 183 184 dev_warn(dev, "Disabling inline encryption support\n"); 185 return 0; 186 } 187 188 host->ice = ice; 189 190 /* Initialize the blk_crypto_profile */ 191 192 caps.reg_val = cpu_to_le32(ufshcd_readl(hba, REG_UFS_CCAP)); 193 194 /* The number of keyslots supported is (CFGC+1) */ 195 err = devm_blk_crypto_profile_init(dev, profile, caps.config_count + 1); 196 if (err) 197 return err; 198 199 profile->ll_ops = ufs_qcom_crypto_ops; 200 profile->max_dun_bytes_supported = 8; 201 profile->key_types_supported = qcom_ice_get_supported_key_type(ice); 202 profile->dev = dev; 203 204 /* 205 * Currently this driver only supports AES-256-XTS. All known versions 206 * of ICE support it, but to be safe make sure it is really declared in 207 * the crypto capability registers. The crypto capability registers 208 * also give the supported data unit size(s). 209 */ 210 for (i = 0; i < caps.num_crypto_cap; i++) { 211 cap.reg_val = cpu_to_le32(ufshcd_readl(hba, 212 REG_UFS_CRYPTOCAP + 213 i * sizeof(__le32))); 214 if (cap.algorithm_id == UFS_CRYPTO_ALG_AES_XTS && 215 cap.key_size == UFS_CRYPTO_KEY_SIZE_256) 216 profile->modes_supported[BLK_ENCRYPTION_MODE_AES_256_XTS] |= 217 cap.sdus_mask * 512; 218 } 219 220 hba->caps |= UFSHCD_CAP_CRYPTO; 221 hba->quirks |= UFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE; 222 return 0; 223 } 224 225 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host) 226 { 227 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 228 return qcom_ice_resume(host->ice); 229 230 return 0; 231 } 232 233 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host) 234 { 235 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 236 return qcom_ice_suspend(host->ice); 237 238 return 0; 239 } 240 241 static int ufs_qcom_ice_keyslot_program(struct blk_crypto_profile *profile, 242 const struct blk_crypto_key *key, 243 unsigned int slot) 244 { 245 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile); 246 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 247 int err; 248 249 ufshcd_hold(hba); 250 err = qcom_ice_program_key(host->ice, slot, key); 251 ufshcd_release(hba); 252 return err; 253 } 254 255 static int ufs_qcom_ice_keyslot_evict(struct blk_crypto_profile *profile, 256 const struct blk_crypto_key *key, 257 unsigned int slot) 258 { 259 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile); 260 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 261 int err; 262 263 ufshcd_hold(hba); 264 err = qcom_ice_evict_key(host->ice, slot); 265 ufshcd_release(hba); 266 return err; 267 } 268 269 static int ufs_qcom_ice_derive_sw_secret(struct blk_crypto_profile *profile, 270 const u8 *eph_key, size_t eph_key_size, 271 u8 sw_secret[BLK_CRYPTO_SW_SECRET_SIZE]) 272 { 273 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile); 274 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 275 276 return qcom_ice_derive_sw_secret(host->ice, eph_key, eph_key_size, 277 sw_secret); 278 } 279 280 static int ufs_qcom_ice_import_key(struct blk_crypto_profile *profile, 281 const u8 *raw_key, size_t raw_key_size, 282 u8 lt_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE]) 283 { 284 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile); 285 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 286 287 return qcom_ice_import_key(host->ice, raw_key, raw_key_size, lt_key); 288 } 289 290 static int ufs_qcom_ice_generate_key(struct blk_crypto_profile *profile, 291 u8 lt_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE]) 292 { 293 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile); 294 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 295 296 return qcom_ice_generate_key(host->ice, lt_key); 297 } 298 299 static int ufs_qcom_ice_prepare_key(struct blk_crypto_profile *profile, 300 const u8 *lt_key, size_t lt_key_size, 301 u8 eph_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE]) 302 { 303 struct ufs_hba *hba = ufs_hba_from_crypto_profile(profile); 304 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 305 306 return qcom_ice_prepare_key(host->ice, lt_key, lt_key_size, eph_key); 307 } 308 309 static const struct blk_crypto_ll_ops ufs_qcom_crypto_ops = { 310 .keyslot_program = ufs_qcom_ice_keyslot_program, 311 .keyslot_evict = ufs_qcom_ice_keyslot_evict, 312 .derive_sw_secret = ufs_qcom_ice_derive_sw_secret, 313 .import_key = ufs_qcom_ice_import_key, 314 .generate_key = ufs_qcom_ice_generate_key, 315 .prepare_key = ufs_qcom_ice_prepare_key, 316 }; 317 318 #else 319 320 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host) 321 { 322 } 323 324 static int ufs_qcom_ice_init(struct ufs_qcom_host *host) 325 { 326 return 0; 327 } 328 329 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host) 330 { 331 return 0; 332 } 333 334 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host) 335 { 336 return 0; 337 } 338 339 static void ufs_qcom_config_ice_allocator(struct ufs_qcom_host *host) 340 { 341 } 342 343 #endif 344 345 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host) 346 { 347 if (!host->is_lane_clks_enabled) 348 return; 349 350 clk_bulk_disable_unprepare(host->num_clks, host->clks); 351 352 host->is_lane_clks_enabled = false; 353 } 354 355 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host) 356 { 357 int err; 358 359 err = clk_bulk_prepare_enable(host->num_clks, host->clks); 360 if (err) 361 return err; 362 363 host->is_lane_clks_enabled = true; 364 365 return 0; 366 } 367 368 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host) 369 { 370 int err; 371 struct device *dev = host->hba->dev; 372 373 if (has_acpi_companion(dev)) 374 return 0; 375 376 err = devm_clk_bulk_get_all(dev, &host->clks); 377 if (err <= 0) 378 return err; 379 380 host->num_clks = err; 381 382 return 0; 383 } 384 385 static int ufs_qcom_check_hibern8(struct ufs_hba *hba) 386 { 387 int err; 388 u32 tx_fsm_val; 389 unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS); 390 391 do { 392 err = ufshcd_dme_get(hba, 393 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 394 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 395 &tx_fsm_val); 396 if (err || tx_fsm_val == TX_FSM_HIBERN8) 397 break; 398 399 /* sleep for max. 200us */ 400 usleep_range(100, 200); 401 } while (time_before(jiffies, timeout)); 402 403 /* 404 * we might have scheduled out for long during polling so 405 * check the state again. 406 */ 407 if (time_after(jiffies, timeout)) 408 err = ufshcd_dme_get(hba, 409 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 410 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 411 &tx_fsm_val); 412 413 if (err) { 414 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n", 415 __func__, err); 416 } else if (tx_fsm_val != TX_FSM_HIBERN8) { 417 err = tx_fsm_val; 418 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n", 419 __func__, err); 420 } 421 422 return err; 423 } 424 425 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host) 426 { 427 ufshcd_rmwl(host->hba, QUNIPRO_SEL, QUNIPRO_SEL, REG_UFS_CFG1); 428 429 if (host->hw_ver.major >= 0x05) 430 ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0); 431 } 432 433 /* 434 * ufs_qcom_host_reset - reset host controller and PHY 435 */ 436 static int ufs_qcom_host_reset(struct ufs_hba *hba) 437 { 438 int ret; 439 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 440 bool reenable_intr; 441 442 if (!host->core_reset) 443 return 0; 444 445 reenable_intr = hba->is_irq_enabled; 446 ufshcd_disable_irq(hba); 447 448 ret = reset_control_assert(host->core_reset); 449 if (ret) { 450 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n", 451 __func__, ret); 452 return ret; 453 } 454 455 /* 456 * The hardware requirement for delay between assert/deassert 457 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to 458 * ~125us (4/32768). To be on the safe side add 200us delay. 459 */ 460 usleep_range(200, 210); 461 462 ret = reset_control_deassert(host->core_reset); 463 if (ret) { 464 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n", 465 __func__, ret); 466 return ret; 467 } 468 469 usleep_range(1000, 1100); 470 471 if (reenable_intr) 472 ufshcd_enable_irq(hba); 473 474 return 0; 475 } 476 477 static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba) 478 { 479 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 480 481 if (host->hw_ver.major >= 0x4) 482 return UFS_QCOM_MAX_GEAR(ufshcd_readl(hba, REG_UFS_PARAM0)); 483 484 /* Default is HS-G3 */ 485 return UFS_HS_G3; 486 } 487 488 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) 489 { 490 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 491 struct ufs_host_params *host_params = &host->host_params; 492 struct phy *phy = host->generic_phy; 493 enum phy_mode mode; 494 int ret; 495 496 /* 497 * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations. 498 * If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A, 499 * so that the subsequent power mode change shall stick to Rate-A. 500 */ 501 if (host->hw_ver.major == 0x5 && host->phy_gear == UFS_HS_G5) 502 host_params->hs_rate = PA_HS_MODE_A; 503 504 mode = host_params->hs_rate == PA_HS_MODE_B ? PHY_MODE_UFS_HS_B : PHY_MODE_UFS_HS_A; 505 506 /* Reset UFS Host Controller and PHY */ 507 ret = ufs_qcom_host_reset(hba); 508 if (ret) 509 return ret; 510 511 if (phy->power_count) 512 phy_power_off(phy); 513 514 515 /* phy initialization - calibrate the phy */ 516 ret = phy_init(phy); 517 if (ret) { 518 dev_err(hba->dev, "%s: phy init failed, ret = %d\n", 519 __func__, ret); 520 return ret; 521 } 522 523 ret = phy_set_mode_ext(phy, mode, host->phy_gear); 524 if (ret) 525 goto out_disable_phy; 526 527 /* power on phy - start serdes and phy's power and clocks */ 528 ret = phy_power_on(phy); 529 if (ret) { 530 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n", 531 __func__, ret); 532 goto out_disable_phy; 533 } 534 535 ret = phy_calibrate(phy); 536 if (ret) { 537 dev_err(hba->dev, "Failed to calibrate PHY: %d\n", ret); 538 goto out_disable_phy; 539 } 540 541 ufs_qcom_select_unipro_mode(host); 542 543 return 0; 544 545 out_disable_phy: 546 phy_exit(phy); 547 548 return ret; 549 } 550 551 /* 552 * The UTP controller has a number of internal clock gating cells (CGCs). 553 * Internal hardware sub-modules within the UTP controller control the CGCs. 554 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved 555 * in a specific operation, UTP controller CGCs are by default disabled and 556 * this function enables them (after every UFS link startup) to save some power 557 * leakage. 558 */ 559 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba) 560 { 561 int err; 562 563 /* Enable UTP internal clock gating */ 564 ufshcd_rmwl(hba, REG_UFS_CFG2_CGC_EN_ALL, REG_UFS_CFG2_CGC_EN_ALL, 565 REG_UFS_CFG2); 566 567 /* Ensure that HW clock gating is enabled before next operations */ 568 ufshcd_readl(hba, REG_UFS_CFG2); 569 570 /* Enable Unipro internal clock gating */ 571 err = ufshcd_dme_rmw(hba, DL_VS_CLK_CFG_MASK, 572 DL_VS_CLK_CFG_MASK, DL_VS_CLK_CFG); 573 if (err) 574 goto out; 575 576 err = ufshcd_dme_rmw(hba, PA_VS_CLK_CFG_REG_MASK, 577 PA_VS_CLK_CFG_REG_MASK, PA_VS_CLK_CFG_REG); 578 if (err) 579 goto out; 580 581 err = ufshcd_dme_rmw(hba, DME_VS_CORE_CLK_CTRL_DME_HW_CGC_EN, 582 DME_VS_CORE_CLK_CTRL_DME_HW_CGC_EN, 583 DME_VS_CORE_CLK_CTRL); 584 out: 585 if (err) 586 dev_err(hba->dev, "hw clk gating enabled failed\n"); 587 } 588 589 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba, 590 enum ufs_notify_change_status status) 591 { 592 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 593 int err; 594 595 switch (status) { 596 case PRE_CHANGE: 597 err = ufs_qcom_power_up_sequence(hba); 598 if (err) 599 return err; 600 601 /* 602 * The PHY PLL output is the source of tx/rx lane symbol 603 * clocks, hence, enable the lane clocks only after PHY 604 * is initialized. 605 */ 606 err = ufs_qcom_enable_lane_clks(host); 607 break; 608 case POST_CHANGE: 609 /* check if UFS PHY moved from DISABLED to HIBERN8 */ 610 err = ufs_qcom_check_hibern8(hba); 611 ufs_qcom_enable_hw_clk_gating(hba); 612 ufs_qcom_ice_enable(host); 613 ufs_qcom_config_ice_allocator(host); 614 break; 615 default: 616 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status); 617 err = -EINVAL; 618 break; 619 } 620 return err; 621 } 622 623 static int ufs_qcom_fw_managed_hce_enable_notify(struct ufs_hba *hba, 624 enum ufs_notify_change_status status) 625 { 626 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 627 628 switch (status) { 629 case PRE_CHANGE: 630 ufs_qcom_select_unipro_mode(host); 631 break; 632 case POST_CHANGE: 633 ufs_qcom_enable_hw_clk_gating(hba); 634 ufs_qcom_ice_enable(host); 635 break; 636 default: 637 dev_err(hba->dev, "Invalid status %d\n", status); 638 return -EINVAL; 639 } 640 641 return 0; 642 } 643 644 /** 645 * ufs_qcom_cfg_timers - Configure ufs qcom cfg timers 646 * 647 * @hba: host controller instance 648 * @is_pre_scale_up: flag to check if pre scale up condition. 649 * @freq: target opp freq 650 * Return: zero for success and non-zero in case of a failure. 651 */ 652 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, bool is_pre_scale_up, unsigned long freq) 653 { 654 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 655 struct ufs_clk_info *clki; 656 unsigned long clk_freq = 0; 657 u32 core_clk_cycles_per_us; 658 659 /* 660 * UTP controller uses SYS1CLK_1US_REG register for Interrupt 661 * Aggregation logic. 662 * It is mandatory to write SYS1CLK_1US_REG register on UFS host 663 * controller V4.0.0 onwards. 664 */ 665 if (host->hw_ver.major < 4 && !ufshcd_is_intr_aggr_allowed(hba)) 666 return 0; 667 668 if (hba->use_pm_opp && freq != ULONG_MAX) { 669 clk_freq = ufs_qcom_opp_freq_to_clk_freq(hba, freq, "core_clk"); 670 if (clk_freq) 671 goto cfg_timers; 672 } 673 674 list_for_each_entry(clki, &hba->clk_list_head, list) { 675 if (!strcmp(clki->name, "core_clk")) { 676 if (freq == ULONG_MAX) { 677 clk_freq = clki->max_freq; 678 break; 679 } 680 681 if (is_pre_scale_up) 682 clk_freq = clki->max_freq; 683 else 684 clk_freq = clk_get_rate(clki->clk); 685 break; 686 } 687 688 } 689 690 cfg_timers: 691 /* If frequency is smaller than 1MHz, set to 1MHz */ 692 if (clk_freq < DEFAULT_CLK_RATE_HZ) 693 clk_freq = DEFAULT_CLK_RATE_HZ; 694 695 core_clk_cycles_per_us = clk_freq / USEC_PER_SEC; 696 if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) { 697 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US); 698 /* 699 * make sure above write gets applied before we return from 700 * this function. 701 */ 702 ufshcd_readl(hba, REG_UFS_SYS1CLK_1US); 703 } 704 705 return 0; 706 } 707 708 static void ufs_qcom_link_startup_post_change(struct ufs_hba *hba) 709 { 710 if (ufshcd_is_auto_hibern8_supported(hba)) 711 ufshcd_rmwl(hba, UFS_HW_CLK_CTRL_EN, UFS_HW_CLK_CTRL_EN, 712 UFS_AH8_CFG); 713 } 714 715 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, 716 enum ufs_notify_change_status status) 717 { 718 int err = 0; 719 720 switch (status) { 721 case PRE_CHANGE: 722 if (ufs_qcom_cfg_timers(hba, false, ULONG_MAX)) { 723 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", 724 __func__); 725 return -EINVAL; 726 } 727 728 err = ufs_qcom_set_core_clk_ctrl(hba, true, ULONG_MAX); 729 if (err) 730 dev_err(hba->dev, "cfg core clk ctrl failed\n"); 731 /* 732 * Some UFS devices (and may be host) have issues if LCC is 733 * enabled. So we are setting PA_Local_TX_LCC_Enable to 0 734 * before link startup which will make sure that both host 735 * and device TX LCC are disabled once link startup is 736 * completed. 737 */ 738 err = ufshcd_disable_host_tx_lcc(hba); 739 740 break; 741 case POST_CHANGE: 742 ufs_qcom_link_startup_post_change(hba); 743 break; 744 default: 745 break; 746 } 747 748 return err; 749 } 750 751 static void ufs_qcom_device_reset_ctrl(struct ufs_hba *hba, bool asserted) 752 { 753 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 754 755 /* reset gpio is optional */ 756 if (!host->device_reset) 757 return; 758 759 gpiod_set_value_cansleep(host->device_reset, asserted); 760 } 761 762 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, 763 enum ufs_notify_change_status status) 764 { 765 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 766 767 if (status == PRE_CHANGE) 768 return 0; 769 770 if (!ufs_qcom_is_link_active(hba)) 771 ufs_qcom_disable_lane_clks(host); 772 773 774 /* reset the connected UFS device during power down */ 775 if (ufs_qcom_is_link_off(hba) && host->device_reset) { 776 ufs_qcom_device_reset_ctrl(hba, true); 777 /* 778 * After sending the SSU command, asserting the rst_n 779 * line causes the device firmware to wake up and 780 * execute its reset routine. 781 * 782 * During this process, the device may draw current 783 * beyond the permissible limit for low-power mode (LPM). 784 * A 10ms delay, based on experimental observations, 785 * allows the UFS device to complete its hardware reset 786 * before transitioning the power rail to LPM. 787 */ 788 usleep_range(10000, 11000); 789 } 790 791 return ufs_qcom_ice_suspend(host); 792 } 793 794 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) 795 { 796 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 797 int err; 798 u32 reg_val; 799 800 err = ufs_qcom_enable_lane_clks(host); 801 if (err) 802 return err; 803 804 if ((!ufs_qcom_is_link_active(hba)) && 805 host->hw_ver.major == 5 && 806 host->hw_ver.minor == 0 && 807 host->hw_ver.step == 0) { 808 ufshcd_writel(hba, UFS_ICE_SYNC_RST_SEL | UFS_ICE_SYNC_RST_SW, UFS_MEM_ICE_CFG); 809 reg_val = ufshcd_readl(hba, UFS_MEM_ICE_CFG); 810 reg_val &= ~(UFS_ICE_SYNC_RST_SEL | UFS_ICE_SYNC_RST_SW); 811 /* 812 * HW documentation doesn't recommend any delay between the 813 * reset set and clear. But we are enforcing an arbitrary delay 814 * to give flops enough time to settle in. 815 */ 816 usleep_range(50, 100); 817 ufshcd_writel(hba, reg_val, UFS_MEM_ICE_CFG); 818 ufshcd_readl(hba, UFS_MEM_ICE_CFG); 819 } 820 821 return ufs_qcom_ice_resume(host); 822 } 823 824 static int ufs_qcom_fw_managed_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, 825 enum ufs_notify_change_status status) 826 { 827 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 828 829 if (status == PRE_CHANGE) 830 return 0; 831 832 pm_runtime_put_sync(hba->dev); 833 834 return ufs_qcom_ice_suspend(host); 835 } 836 837 static int ufs_qcom_fw_managed_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) 838 { 839 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 840 int err; 841 842 err = pm_runtime_resume_and_get(hba->dev); 843 if (err) { 844 dev_err(hba->dev, "PM runtime resume failed: %d\n", err); 845 return err; 846 } 847 848 return ufs_qcom_ice_resume(host); 849 } 850 851 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable) 852 { 853 if (host->dev_ref_clk_ctrl_mmio && 854 (enable ^ host->is_dev_ref_clk_enabled)) { 855 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio); 856 857 if (enable) 858 temp |= host->dev_ref_clk_en_mask; 859 else 860 temp &= ~host->dev_ref_clk_en_mask; 861 862 /* 863 * If we are here to disable this clock it might be immediately 864 * after entering into hibern8 in which case we need to make 865 * sure that device ref_clk is active for specific time after 866 * hibern8 enter. 867 */ 868 if (!enable) { 869 unsigned long gating_wait; 870 871 gating_wait = host->hba->dev_info.clk_gating_wait_us; 872 if (!gating_wait) { 873 udelay(1); 874 } else { 875 /* 876 * bRefClkGatingWaitTime defines the minimum 877 * time for which the reference clock is 878 * required by device during transition from 879 * HS-MODE to LS-MODE or HIBERN8 state. Give it 880 * more delay to be on the safe side. 881 */ 882 gating_wait += 10; 883 usleep_range(gating_wait, gating_wait + 10); 884 } 885 } 886 887 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio); 888 889 /* 890 * Make sure the write to ref_clk reaches the destination and 891 * not stored in a Write Buffer (WB). 892 */ 893 readl(host->dev_ref_clk_ctrl_mmio); 894 895 /* 896 * If we call hibern8 exit after this, we need to make sure that 897 * device ref_clk is stable for at least 1us before the hibern8 898 * exit command. 899 */ 900 if (enable) 901 udelay(1); 902 903 host->is_dev_ref_clk_enabled = enable; 904 } 905 } 906 907 static int ufs_qcom_icc_set_bw(struct ufs_qcom_host *host, u32 mem_bw, u32 cfg_bw) 908 { 909 struct device *dev = host->hba->dev; 910 int ret; 911 912 ret = icc_set_bw(host->icc_ddr, 0, mem_bw); 913 if (ret < 0) { 914 dev_err(dev, "failed to set bandwidth request: %d\n", ret); 915 return ret; 916 } 917 918 ret = icc_set_bw(host->icc_cpu, 0, cfg_bw); 919 if (ret < 0) { 920 dev_err(dev, "failed to set bandwidth request: %d\n", ret); 921 return ret; 922 } 923 924 return 0; 925 } 926 927 static struct __ufs_qcom_bw_table ufs_qcom_get_bw_table(struct ufs_qcom_host *host) 928 { 929 struct ufs_pa_layer_attr *p = &host->dev_req_params; 930 int gear = max_t(u32, p->gear_rx, p->gear_tx); 931 int lane = max_t(u32, p->lane_rx, p->lane_tx); 932 933 if (WARN_ONCE(gear > QCOM_UFS_MAX_GEAR, 934 "ICC scaling for UFS Gear (%d) not supported. Using Gear (%d) bandwidth\n", 935 gear, QCOM_UFS_MAX_GEAR)) 936 gear = QCOM_UFS_MAX_GEAR; 937 938 if (WARN_ONCE(lane > QCOM_UFS_MAX_LANE, 939 "ICC scaling for UFS Lane (%d) not supported. Using Lane (%d) bandwidth\n", 940 lane, QCOM_UFS_MAX_LANE)) 941 lane = QCOM_UFS_MAX_LANE; 942 943 if (ufshcd_is_hs_mode(p)) { 944 if (p->hs_rate == PA_HS_MODE_B) 945 return ufs_qcom_bw_table[MODE_HS_RB][gear][lane]; 946 else 947 return ufs_qcom_bw_table[MODE_HS_RA][gear][lane]; 948 } else { 949 return ufs_qcom_bw_table[MODE_PWM][gear][lane]; 950 } 951 } 952 953 static int ufs_qcom_icc_update_bw(struct ufs_qcom_host *host) 954 { 955 struct __ufs_qcom_bw_table bw_table; 956 957 bw_table = ufs_qcom_get_bw_table(host); 958 959 return ufs_qcom_icc_set_bw(host, bw_table.mem_bw, bw_table.cfg_bw); 960 } 961 962 static void ufs_qcom_set_tx_hs_equalizer(struct ufs_hba *hba, u32 gear, u32 tx_lanes) 963 { 964 u32 equalizer_val; 965 int ret, i; 966 967 /* Determine the equalizer value based on the gear */ 968 equalizer_val = (gear == 5) ? DEEMPHASIS_3_5_dB : NO_DEEMPHASIS; 969 970 for (i = 0; i < tx_lanes; i++) { 971 ret = ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HS_EQUALIZER, i), 972 equalizer_val); 973 if (ret) 974 dev_err(hba->dev, "%s: failed equalizer lane %d\n", 975 __func__, i); 976 } 977 } 978 979 static int ufs_qcom_negotiate_pwr_mode(struct ufs_hba *hba, 980 const struct ufs_pa_layer_attr *dev_max_params, 981 struct ufs_pa_layer_attr *dev_req_params) 982 { 983 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 984 struct ufs_host_params *host_params = &host->host_params; 985 986 return ufshcd_negotiate_pwr_params(host_params, dev_max_params, dev_req_params); 987 } 988 989 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, 990 enum ufs_notify_change_status status, 991 struct ufs_pa_layer_attr *dev_req_params) 992 { 993 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 994 int ret = 0; 995 996 if (!dev_req_params) { 997 pr_err("%s: incoming dev_req_params is NULL\n", __func__); 998 return -EINVAL; 999 } 1000 1001 switch (status) { 1002 case PRE_CHANGE: 1003 /* 1004 * During UFS driver probe, always update the PHY gear to match the negotiated 1005 * gear, so that, if quirk UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH is enabled, 1006 * the second init can program the optimal PHY settings. This allows one to start 1007 * the first init with either the minimum or the maximum support gear. 1008 */ 1009 if (hba->ufshcd_state == UFSHCD_STATE_RESET) { 1010 /* 1011 * Skip REINIT if the negotiated gear matches with the 1012 * initial phy_gear. Otherwise, update the phy_gear to 1013 * program the optimal gear setting during REINIT. 1014 */ 1015 if (host->phy_gear == dev_req_params->gear_tx) 1016 hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; 1017 else 1018 host->phy_gear = dev_req_params->gear_tx; 1019 } 1020 1021 /* enable the device ref clock before changing to HS mode */ 1022 if (!ufshcd_is_hs_mode(&hba->pwr_info) && 1023 ufshcd_is_hs_mode(dev_req_params)) 1024 ufs_qcom_dev_ref_clk_ctrl(host, true); 1025 1026 if (host->hw_ver.major >= 0x4) { 1027 ufshcd_dme_configure_adapt(hba, 1028 dev_req_params->gear_tx, 1029 PA_INITIAL_ADAPT); 1030 } 1031 1032 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TX_DEEMPHASIS_TUNING) 1033 ufs_qcom_set_tx_hs_equalizer(hba, 1034 dev_req_params->gear_tx, dev_req_params->lane_tx); 1035 1036 break; 1037 case POST_CHANGE: 1038 /* cache the power mode parameters to use internally */ 1039 memcpy(&host->dev_req_params, 1040 dev_req_params, sizeof(*dev_req_params)); 1041 1042 ufs_qcom_icc_update_bw(host); 1043 1044 /* disable the device ref clock if entered PWM mode */ 1045 if (ufshcd_is_hs_mode(&hba->pwr_info) && 1046 !ufshcd_is_hs_mode(dev_req_params)) 1047 ufs_qcom_dev_ref_clk_ctrl(host, false); 1048 break; 1049 default: 1050 ret = -EINVAL; 1051 break; 1052 } 1053 1054 return ret; 1055 } 1056 1057 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba) 1058 { 1059 int err; 1060 u32 pa_vs_config_reg1; 1061 1062 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), 1063 &pa_vs_config_reg1); 1064 if (err) 1065 return err; 1066 1067 /* Allow extension of MSB bits of PA_SaveConfigTime attribute */ 1068 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), 1069 (pa_vs_config_reg1 | (1 << 12))); 1070 } 1071 1072 static void ufs_qcom_override_pa_tx_hsg1_sync_len(struct ufs_hba *hba) 1073 { 1074 int err; 1075 1076 err = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TX_HSG1_SYNC_LENGTH), 1077 PA_TX_HSG1_SYNC_LENGTH_VAL); 1078 if (err) 1079 dev_err(hba->dev, "Failed (%d) set PA_TX_HSG1_SYNC_LENGTH\n", err); 1080 } 1081 1082 /** 1083 * ufs_qcom_double_t_adapt_l0l1l2l3 - Create a new adapt that doubles the 1084 * adaptation duration TADAPT_L0_L1_L2_L3 derived from the old adapt. 1085 * 1086 * @old_adapt: Original ADAPT_L0_L1_L2_L3 capability 1087 * 1088 * ADAPT_length_L0_L1_L2_L3 formula from M-PHY spec: 1089 * if (ADAPT_range_L0_L1_L2_L3 == COARSE) { 1090 * ADAPT_length_L0_L1_L2_L3 = [0, 12] 1091 * ADAPT_L0_L1_L2_L3 = 215 x 2^ADAPT_length_L0_L1_L2_L3 1092 * } else if (ADAPT_range_L0_L1_L2_L3 == FINE) { 1093 * ADAPT_length_L0_L1_L2_L3 = [0, 127] 1094 * TADAPT_L0_L1_L2_L3 = 215 x (ADAPT_length_L0_L1_L2_L3 + 1) 1095 * } 1096 * 1097 * To double the adaptation duration TADAPT_L0_L1_L2_L3: 1098 * 1. If adapt range is COARSE (1'b1), new adapt = old adapt + 1. 1099 * 2. If adapt range is FINE (1'b0): 1100 * a) If old adapt length is < 64, (new adapt + 1) = 2 * (old adapt + 1). 1101 * b) If old adapt length is >= 64, set new adapt to 0x88 using COARSE 1102 * range, because new adapt get from equation in a) shall exceed 127. 1103 * 1104 * Examples: 1105 * ADAPT_range_L0_L1_L2_L3 | ADAPT_length_L0_L1_L2_L3 | TADAPT_L0_L1_L2_L3 (PAM-4 UI) 1106 * 0 3 131072 1107 * 0 7 262144 1108 * 0 63 2097152 1109 * 0 64 2129920 1110 * 0 127 4194304 1111 * 1 8 8388608 1112 * 1 9 16777216 1113 * 1 10 33554432 1114 * 1 11 67108864 1115 * 1 12 134217728 1116 * 1117 * Return: new adapt. 1118 */ 1119 static u32 ufs_qcom_double_t_adapt_l0l1l2l3(u32 old_adapt) 1120 { 1121 u32 adapt_length = old_adapt & ADAPT_LENGTH_MASK; 1122 u32 new_adapt; 1123 1124 if (IS_ADAPT_RANGE_COARSE(old_adapt)) { 1125 new_adapt = (adapt_length + 1) | ADAPT_RANGE_BIT; 1126 } else { 1127 if (adapt_length < 64) 1128 new_adapt = (adapt_length << 1) + 1; 1129 else 1130 /* 1131 * 0x88 is the very coarse Adapt value which is two 1132 * times of the largest fine Adapt value (0x7F) 1133 */ 1134 new_adapt = 0x88; 1135 } 1136 1137 return new_adapt; 1138 } 1139 1140 static void ufs_qcom_limit_max_gear(struct ufs_hba *hba, 1141 enum ufs_hs_gear_tag gear) 1142 { 1143 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1144 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info; 1145 struct ufs_host_params *host_params = &host->host_params; 1146 1147 host_params->hs_tx_gear = gear; 1148 host_params->hs_rx_gear = gear; 1149 pwr_info->gear_tx = gear; 1150 pwr_info->gear_rx = gear; 1151 1152 dev_warn(hba->dev, "Limited max gear of host and device to HS-G%d\n", gear); 1153 } 1154 1155 static void ufs_qcom_fixup_tx_adapt_l0l1l2l3(struct ufs_hba *hba) 1156 { 1157 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1158 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info; 1159 struct ufs_host_params *host_params = &host->host_params; 1160 u32 old_adapt, new_adapt, actual_adapt; 1161 bool limit_speed = false; 1162 int err; 1163 1164 if (host->hw_ver.major != 0x7 || host->hw_ver.minor > 0x1 || 1165 host_params->hs_tx_gear <= UFS_HS_G5 || 1166 pwr_info->gear_tx <= UFS_HS_G5) 1167 return; 1168 1169 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PEERRXHSG6ADAPTINITIALL0L1L2L3), &old_adapt); 1170 if (err) 1171 goto out; 1172 1173 if (old_adapt > ADAPT_L0L1L2L3_LENGTH_MAX) { 1174 dev_err(hba->dev, "PA_PeerRxHsG6AdaptInitialL0L1L2L3 value (0x%x) exceeds MAX\n", 1175 old_adapt); 1176 err = -ERANGE; 1177 goto out; 1178 } 1179 1180 new_adapt = ufs_qcom_double_t_adapt_l0l1l2l3(old_adapt); 1181 dev_dbg(hba->dev, "Original PA_PeerRxHsG6AdaptInitialL0L1L2L3 = 0x%x, new value = 0x%x\n", 1182 old_adapt, new_adapt); 1183 1184 /* 1185 * 0x8C is the max possible value allowed by UniPro v3.0 spec, some HWs 1186 * can accept 0x8D but some cannot. 1187 */ 1188 if (new_adapt <= ADAPT_L0L1L2L3_LENGTH_MAX || 1189 (new_adapt == ADAPT_L0L1L2L3_LENGTH_MAX + 1 && host->hw_ver.minor == 0x1)) { 1190 err = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PEERRXHSG6ADAPTINITIALL0L1L2L3), 1191 new_adapt); 1192 if (err) 1193 goto out; 1194 1195 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PEERRXHSG6ADAPTINITIALL0L1L2L3), 1196 &actual_adapt); 1197 if (err) 1198 goto out; 1199 1200 if (actual_adapt != new_adapt) { 1201 limit_speed = true; 1202 dev_warn(hba->dev, "PA_PeerRxHsG6AdaptInitialL0L1L2L3 0x%x, expect 0x%x\n", 1203 actual_adapt, new_adapt); 1204 } 1205 } else { 1206 limit_speed = true; 1207 dev_warn(hba->dev, "New PA_PeerRxHsG6AdaptInitialL0L1L2L3 (0x%x) is too large!\n", 1208 new_adapt); 1209 } 1210 1211 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PEERRXHSG6ADAPTREFRESHL0L1L2L3), &old_adapt); 1212 if (err) 1213 goto out; 1214 1215 if (old_adapt > ADAPT_L0L1L2L3_LENGTH_MAX) { 1216 dev_err(hba->dev, "PA_PeerRxHsG6AdaptRefreshL0L1L2L3 value (0x%x) exceeds MAX\n", 1217 old_adapt); 1218 err = -ERANGE; 1219 goto out; 1220 } 1221 1222 new_adapt = ufs_qcom_double_t_adapt_l0l1l2l3(old_adapt); 1223 dev_dbg(hba->dev, "Original PA_PeerRxHsG6AdaptRefreshL0L1L2L3 = 0x%x, new value = 0x%x\n", 1224 old_adapt, new_adapt); 1225 1226 /* 1227 * 0x8C is the max possible value allowed by UniPro v3.0 spec, some HWs 1228 * can accept 0x8D but some cannot. 1229 */ 1230 if (new_adapt <= ADAPT_L0L1L2L3_LENGTH_MAX || 1231 (new_adapt == ADAPT_L0L1L2L3_LENGTH_MAX + 1 && host->hw_ver.minor == 0x1)) { 1232 err = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PEERRXHSG6ADAPTREFRESHL0L1L2L3), 1233 new_adapt); 1234 if (err) 1235 goto out; 1236 1237 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PEERRXHSG6ADAPTREFRESHL0L1L2L3), 1238 &actual_adapt); 1239 if (err) 1240 goto out; 1241 1242 if (actual_adapt != new_adapt) { 1243 limit_speed = true; 1244 dev_warn(hba->dev, "PA_PeerRxHsG6AdaptRefreshL0L1L2L3 0x%x, expect 0x%x\n", 1245 new_adapt, actual_adapt); 1246 } 1247 } else { 1248 limit_speed = true; 1249 dev_warn(hba->dev, "New PA_PeerRxHsG6AdaptRefreshL0L1L2L3 (0x%x) is too large!\n", 1250 new_adapt); 1251 } 1252 1253 out: 1254 if (limit_speed || err) 1255 ufs_qcom_limit_max_gear(hba, UFS_HS_G5); 1256 } 1257 1258 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba) 1259 { 1260 int err = 0; 1261 1262 ufs_qcom_fixup_tx_adapt_l0l1l2l3(hba); 1263 1264 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME) 1265 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba); 1266 1267 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TX_HSG1_SYNC_LENGTH) 1268 ufs_qcom_override_pa_tx_hsg1_sync_len(hba); 1269 1270 return err; 1271 } 1272 1273 /* UFS device-specific quirks */ 1274 static struct ufs_dev_quirk ufs_qcom_dev_fixups[] = { 1275 { .wmanufacturerid = UFS_VENDOR_SKHYNIX, 1276 .model = UFS_ANY_MODEL, 1277 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM }, 1278 { .wmanufacturerid = UFS_VENDOR_WDC, 1279 .model = UFS_ANY_MODEL, 1280 .quirk = UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE }, 1281 { .wmanufacturerid = UFS_VENDOR_SAMSUNG, 1282 .model = UFS_ANY_MODEL, 1283 .quirk = UFS_DEVICE_QUIRK_PA_TX_HSG1_SYNC_LENGTH | 1284 UFS_DEVICE_QUIRK_PA_TX_DEEMPHASIS_TUNING }, 1285 {} 1286 }; 1287 1288 static void ufs_qcom_fixup_dev_quirks(struct ufs_hba *hba) 1289 { 1290 ufshcd_fixup_dev_quirks(hba, ufs_qcom_dev_fixups); 1291 } 1292 1293 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba) 1294 { 1295 return ufshci_version(2, 0); 1296 } 1297 1298 /** 1299 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks 1300 * @hba: host controller instance 1301 * 1302 * QCOM UFS host controller might have some non standard behaviours (quirks) 1303 * than what is specified by UFSHCI specification. Advertise all such 1304 * quirks to standard UFS host controller driver so standard takes them into 1305 * account. 1306 */ 1307 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba) 1308 { 1309 const struct ufs_qcom_drvdata *drvdata = of_device_get_match_data(hba->dev); 1310 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1311 1312 if (host->hw_ver.major == 0x2) 1313 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION; 1314 1315 if (host->hw_ver.major > 0x3) 1316 hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; 1317 1318 if (host->hw_ver.major == 0x7 && host->hw_ver.minor == 0x1) 1319 hba->quirks |= UFSHCD_QUIRK_EXTENDED_TX_EQTR_ADAPT_LENGTH_L0L1L2L3; 1320 1321 if (drvdata && drvdata->quirks) 1322 hba->quirks |= drvdata->quirks; 1323 } 1324 1325 static void ufs_qcom_set_phy_gear(struct ufs_qcom_host *host) 1326 { 1327 struct ufs_host_params *host_params = &host->host_params; 1328 u32 val, dev_major; 1329 1330 /* 1331 * Default to powering up the PHY to the max gear possible, which is 1332 * backwards compatible with lower gears but not optimal from 1333 * a power usage point of view. After device negotiation, if the 1334 * gear is lower a reinit will be performed to program the PHY 1335 * to the ideal gear for this combo of controller and device. 1336 */ 1337 host->phy_gear = host_params->hs_tx_gear; 1338 1339 if (host->hw_ver.major < 0x4) { 1340 /* 1341 * These controllers only have one PHY init sequence, 1342 * let's power up the PHY using that (the minimum supported 1343 * gear, UFS_HS_G2). 1344 */ 1345 host->phy_gear = UFS_HS_G2; 1346 } else if (host->hw_ver.major >= 0x5) { 1347 val = ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG); 1348 dev_major = FIELD_GET(UFS_DEV_VER_MAJOR_MASK, val); 1349 1350 /* 1351 * Since the UFS device version is populated, let's remove the 1352 * REINIT quirk as the negotiated gear won't change during boot. 1353 * So there is no need to do reinit. 1354 */ 1355 if (dev_major != 0x0) 1356 host->hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; 1357 1358 /* 1359 * For UFS 3.1 device and older, power up the PHY using HS-G4 1360 * PHY gear to save power. 1361 */ 1362 if (dev_major > 0x0 && dev_major < 0x4) 1363 host->phy_gear = UFS_HS_G4; 1364 } 1365 } 1366 1367 static void ufs_qcom_parse_gear_limits(struct ufs_hba *hba) 1368 { 1369 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1370 struct ufs_host_params *host_params = &host->host_params; 1371 u32 hs_gear_old = host_params->hs_tx_gear; 1372 1373 ufshcd_parse_gear_limits(hba, host_params); 1374 if (host_params->hs_tx_gear != hs_gear_old) { 1375 host->phy_gear = host_params->hs_tx_gear; 1376 } 1377 } 1378 1379 static void ufs_qcom_set_host_params(struct ufs_hba *hba) 1380 { 1381 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1382 struct ufs_host_params *host_params = &host->host_params; 1383 1384 ufshcd_init_host_params(host_params); 1385 1386 /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */ 1387 host_params->hs_tx_gear = host_params->hs_rx_gear = ufs_qcom_get_hs_gear(hba); 1388 } 1389 1390 static void ufs_qcom_set_host_caps(struct ufs_hba *hba) 1391 { 1392 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1393 1394 if (host->hw_ver.major >= 0x5) 1395 host->caps |= UFS_QCOM_CAP_ICE_CONFIG; 1396 } 1397 1398 static void ufs_qcom_set_caps(struct ufs_hba *hba) 1399 { 1400 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1401 1402 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; 1403 hba->caps |= UFSHCD_CAP_CLK_SCALING | UFSHCD_CAP_WB_WITH_CLK_SCALING; 1404 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND; 1405 hba->caps |= UFSHCD_CAP_WB_EN; 1406 hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE; 1407 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND; 1408 1409 if (host->hw_ver.major >= 0x7) 1410 hba->caps |= UFSHCD_CAP_TX_EQUALIZATION; 1411 1412 ufs_qcom_set_host_caps(hba); 1413 } 1414 1415 /** 1416 * ufs_qcom_setup_clocks - enables/disable clocks 1417 * @hba: host controller instance 1418 * @on: If true, enable clocks else disable them. 1419 * @status: PRE_CHANGE or POST_CHANGE notify 1420 * 1421 * There are certain clocks which comes from the PHY so it needs 1422 * to be managed together along with controller clocks which also 1423 * provides a better power saving. Hence keep phy_power_off/on calls 1424 * in ufs_qcom_setup_clocks, so that PHY's regulators & clks can be 1425 * turned on/off along with UFS's clocks. 1426 * 1427 * Return: 0 on success, non-zero on failure. 1428 */ 1429 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, 1430 enum ufs_notify_change_status status) 1431 { 1432 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1433 struct phy *phy; 1434 int err; 1435 1436 /* 1437 * In case ufs_qcom_init() is not yet done, simply ignore. 1438 * This ufs_qcom_setup_clocks() shall be called from 1439 * ufs_qcom_init() after init is done. 1440 */ 1441 if (!host) 1442 return 0; 1443 1444 phy = host->generic_phy; 1445 1446 switch (status) { 1447 case PRE_CHANGE: 1448 if (on) { 1449 ufs_qcom_icc_update_bw(host); 1450 if (ufs_qcom_is_link_hibern8(hba)) { 1451 err = ufs_qcom_enable_lane_clks(host); 1452 if (err) { 1453 dev_err(hba->dev, "enable lane clks failed, ret=%d\n", err); 1454 return err; 1455 } 1456 } 1457 } else { 1458 if (!ufs_qcom_is_link_active(hba)) { 1459 /* disable device ref_clk */ 1460 ufs_qcom_dev_ref_clk_ctrl(host, false); 1461 } 1462 1463 err = phy_power_off(phy); 1464 if (err) { 1465 dev_err(hba->dev, "phy power off failed, ret=%d\n", err); 1466 return err; 1467 } 1468 } 1469 break; 1470 case POST_CHANGE: 1471 if (on) { 1472 err = phy_power_on(phy); 1473 if (err) { 1474 dev_err(hba->dev, "phy power on failed, ret = %d\n", err); 1475 return err; 1476 } 1477 1478 /* enable the device ref clock for HS mode*/ 1479 if (ufshcd_is_hs_mode(&hba->pwr_info)) 1480 ufs_qcom_dev_ref_clk_ctrl(host, true); 1481 } else { 1482 if (ufs_qcom_is_link_hibern8(hba)) 1483 ufs_qcom_disable_lane_clks(host); 1484 1485 ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MIN][0][0].mem_bw, 1486 ufs_qcom_bw_table[MODE_MIN][0][0].cfg_bw); 1487 } 1488 break; 1489 } 1490 1491 return 0; 1492 } 1493 1494 static int 1495 ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) 1496 { 1497 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev); 1498 1499 ufs_qcom_assert_reset(host->hba); 1500 /* provide 1ms delay to let the reset pulse propagate. */ 1501 usleep_range(1000, 1100); 1502 return 0; 1503 } 1504 1505 static int 1506 ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) 1507 { 1508 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev); 1509 1510 ufs_qcom_deassert_reset(host->hba); 1511 1512 /* 1513 * after reset deassertion, phy will need all ref clocks, 1514 * voltage, current to settle down before starting serdes. 1515 */ 1516 usleep_range(1000, 1100); 1517 return 0; 1518 } 1519 1520 static const struct reset_control_ops ufs_qcom_reset_ops = { 1521 .assert = ufs_qcom_reset_assert, 1522 .deassert = ufs_qcom_reset_deassert, 1523 }; 1524 1525 static int ufs_qcom_icc_init(struct ufs_qcom_host *host) 1526 { 1527 struct device *dev = host->hba->dev; 1528 int ret; 1529 1530 host->icc_ddr = devm_of_icc_get(dev, "ufs-ddr"); 1531 if (IS_ERR(host->icc_ddr)) 1532 return dev_err_probe(dev, PTR_ERR(host->icc_ddr), 1533 "failed to acquire interconnect path\n"); 1534 1535 host->icc_cpu = devm_of_icc_get(dev, "cpu-ufs"); 1536 if (IS_ERR(host->icc_cpu)) 1537 return dev_err_probe(dev, PTR_ERR(host->icc_cpu), 1538 "failed to acquire interconnect path\n"); 1539 1540 /* 1541 * Set Maximum bandwidth vote before initializing the UFS controller and 1542 * device. Ideally, a minimal interconnect vote would suffice for the 1543 * initialization, but a max vote would allow faster initialization. 1544 */ 1545 ret = ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MAX][0][0].mem_bw, 1546 ufs_qcom_bw_table[MODE_MAX][0][0].cfg_bw); 1547 if (ret < 0) 1548 return dev_err_probe(dev, ret, "failed to set bandwidth request\n"); 1549 1550 return 0; 1551 } 1552 1553 /** 1554 * ufs_qcom_init - bind phy with controller 1555 * @hba: host controller instance 1556 * 1557 * Binds PHY with controller and powers up PHY enabling clocks 1558 * and regulators. 1559 * 1560 * Return: -EPROBE_DEFER if binding fails, returns negative error 1561 * on phy power up failure and returns zero on success. 1562 */ 1563 static int ufs_qcom_init(struct ufs_hba *hba) 1564 { 1565 int err; 1566 struct device *dev = hba->dev; 1567 struct ufs_qcom_host *host; 1568 struct ufs_clk_info *clki; 1569 const struct ufs_qcom_drvdata *drvdata = of_device_get_match_data(hba->dev); 1570 1571 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); 1572 if (!host) 1573 return -ENOMEM; 1574 1575 /* Make a two way bind between the qcom host and the hba */ 1576 host->hba = hba; 1577 ufshcd_set_variant(hba, host); 1578 1579 /* Setup the optional reset control of HCI */ 1580 host->core_reset = devm_reset_control_get_optional(hba->dev, "rst"); 1581 if (IS_ERR(host->core_reset)) { 1582 err = dev_err_probe(dev, PTR_ERR(host->core_reset), 1583 "Failed to get reset control\n"); 1584 goto out_variant_clear; 1585 } 1586 1587 /* Fire up the reset controller. Failure here is non-fatal. */ 1588 host->rcdev.of_node = dev->of_node; 1589 host->rcdev.ops = &ufs_qcom_reset_ops; 1590 host->rcdev.owner = dev->driver->owner; 1591 host->rcdev.nr_resets = 1; 1592 err = devm_reset_controller_register(dev, &host->rcdev); 1593 if (err) 1594 dev_warn(dev, "Failed to register reset controller\n"); 1595 1596 if (!has_acpi_companion(dev)) { 1597 host->generic_phy = devm_phy_get(dev, "ufsphy"); 1598 if (IS_ERR(host->generic_phy)) { 1599 err = dev_err_probe(dev, PTR_ERR(host->generic_phy), "Failed to get PHY\n"); 1600 goto out_variant_clear; 1601 } 1602 } 1603 1604 err = ufs_qcom_icc_init(host); 1605 if (err) 1606 goto out_variant_clear; 1607 1608 host->device_reset = devm_gpiod_get_optional(dev, "reset", 1609 GPIOD_OUT_HIGH); 1610 if (IS_ERR(host->device_reset)) { 1611 err = dev_err_probe(dev, PTR_ERR(host->device_reset), 1612 "Failed to acquire device reset gpio\n"); 1613 goto out_variant_clear; 1614 } 1615 1616 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major, 1617 &host->hw_ver.minor, &host->hw_ver.step); 1618 1619 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1; 1620 host->dev_ref_clk_en_mask = BIT(26); 1621 1622 list_for_each_entry(clki, &hba->clk_list_head, list) { 1623 if (!strcmp(clki->name, "core_clk_unipro")) 1624 clki->keep_link_active = true; 1625 } 1626 1627 err = ufs_qcom_init_lane_clks(host); 1628 if (err) 1629 goto out_variant_clear; 1630 1631 ufs_qcom_set_caps(hba); 1632 ufs_qcom_advertise_quirks(hba); 1633 ufs_qcom_set_host_params(hba); 1634 ufs_qcom_set_phy_gear(host); 1635 ufs_qcom_parse_gear_limits(hba); 1636 1637 err = ufs_qcom_ice_init(host); 1638 if (err) 1639 goto out_variant_clear; 1640 1641 ufs_qcom_setup_clocks(hba, true, POST_CHANGE); 1642 1643 ufs_qcom_get_default_testbus_cfg(host); 1644 err = ufs_qcom_testbus_config(host); 1645 if (err) 1646 /* Failure is non-fatal */ 1647 dev_warn(dev, "%s: failed to configure the testbus %d\n", 1648 __func__, err); 1649 1650 if (drvdata && drvdata->no_phy_retention) 1651 hba->spm_lvl = UFS_PM_LVL_5; 1652 1653 return 0; 1654 1655 out_variant_clear: 1656 ufshcd_set_variant(hba, NULL); 1657 1658 return err; 1659 } 1660 1661 static void ufs_qcom_exit(struct ufs_hba *hba) 1662 { 1663 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1664 1665 ufs_qcom_disable_lane_clks(host); 1666 phy_power_off(host->generic_phy); 1667 phy_exit(host->generic_phy); 1668 } 1669 1670 static int ufs_qcom_fw_managed_init(struct ufs_hba *hba) 1671 { 1672 struct device *dev = hba->dev; 1673 struct ufs_qcom_host *host; 1674 int err; 1675 1676 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); 1677 if (!host) 1678 return -ENOMEM; 1679 1680 host->hba = hba; 1681 ufshcd_set_variant(hba, host); 1682 1683 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major, 1684 &host->hw_ver.minor, &host->hw_ver.step); 1685 1686 err = ufs_qcom_ice_init(host); 1687 if (err) 1688 goto out_variant_clear; 1689 1690 ufs_qcom_get_default_testbus_cfg(host); 1691 err = ufs_qcom_testbus_config(host); 1692 if (err) 1693 /* Failure is non-fatal */ 1694 dev_warn(dev, "Failed to configure the testbus %d\n", err); 1695 1696 hba->caps |= UFSHCD_CAP_WB_EN; 1697 1698 ufs_qcom_advertise_quirks(hba); 1699 host->hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; 1700 1701 hba->spm_lvl = hba->rpm_lvl = hba->pm_lvl_min = UFS_PM_LVL_5; 1702 1703 ufs_qcom_set_host_params(hba); 1704 ufs_qcom_parse_gear_limits(hba); 1705 1706 return 0; 1707 1708 out_variant_clear: 1709 ufshcd_set_variant(hba, NULL); 1710 return err; 1711 } 1712 1713 static void ufs_qcom_fw_managed_exit(struct ufs_hba *hba) 1714 { 1715 pm_runtime_put_sync(hba->dev); 1716 } 1717 1718 /** 1719 * ufs_qcom_set_clk_40ns_cycles - Configure 40ns clk cycles 1720 * 1721 * @hba: host controller instance 1722 * @cycles_in_1us: No of cycles in 1us to be configured 1723 * 1724 * Returns error if dme get/set configuration for 40ns fails 1725 * and returns zero on success. 1726 */ 1727 static int ufs_qcom_set_clk_40ns_cycles(struct ufs_hba *hba, 1728 u32 cycles_in_1us) 1729 { 1730 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1731 u32 cycles_in_40ns; 1732 u32 reg; 1733 int err; 1734 1735 /* 1736 * UFS host controller V4.0.0 onwards needs to program 1737 * PA_VS_CORE_CLK_40NS_CYCLES attribute per programmed 1738 * frequency of unipro core clk of UFS host controller. 1739 */ 1740 if (host->hw_ver.major < 4) 1741 return 0; 1742 1743 /* 1744 * Generic formulae for cycles_in_40ns = (freq_unipro/25) is not 1745 * applicable for all frequencies. For ex: ceil(37.5 MHz/25) will 1746 * be 2 and ceil(403 MHZ/25) will be 17 whereas Hardware 1747 * specification expect to be 16. Hence use exact hardware spec 1748 * mandated value for cycles_in_40ns instead of calculating using 1749 * generic formulae. 1750 */ 1751 switch (cycles_in_1us) { 1752 case UNIPRO_CORE_CLK_FREQ_403_MHZ: 1753 cycles_in_40ns = 16; 1754 break; 1755 case UNIPRO_CORE_CLK_FREQ_300_MHZ: 1756 cycles_in_40ns = 12; 1757 break; 1758 case UNIPRO_CORE_CLK_FREQ_201_5_MHZ: 1759 cycles_in_40ns = 8; 1760 break; 1761 case UNIPRO_CORE_CLK_FREQ_150_MHZ: 1762 cycles_in_40ns = 6; 1763 break; 1764 case UNIPRO_CORE_CLK_FREQ_100_MHZ: 1765 cycles_in_40ns = 4; 1766 break; 1767 case UNIPRO_CORE_CLK_FREQ_75_MHZ: 1768 cycles_in_40ns = 3; 1769 break; 1770 case UNIPRO_CORE_CLK_FREQ_37_5_MHZ: 1771 cycles_in_40ns = 2; 1772 break; 1773 default: 1774 dev_err(hba->dev, "UNIPRO clk freq %u MHz not supported\n", 1775 cycles_in_1us); 1776 return -EINVAL; 1777 } 1778 1779 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), ®); 1780 if (err) 1781 return err; 1782 1783 reg &= ~PA_VS_CORE_CLK_40NS_CYCLES_MASK; 1784 reg |= cycles_in_40ns; 1785 1786 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), reg); 1787 } 1788 1789 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up, unsigned long freq) 1790 { 1791 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1792 struct list_head *head = &hba->clk_list_head; 1793 struct ufs_clk_info *clki; 1794 u32 cycles_in_1us = 0; 1795 u32 core_clk_ctrl_reg; 1796 unsigned long clk_freq; 1797 int err; 1798 1799 if (hba->use_pm_opp && freq != ULONG_MAX) { 1800 clk_freq = ufs_qcom_opp_freq_to_clk_freq(hba, freq, "core_clk_unipro"); 1801 if (clk_freq) { 1802 cycles_in_1us = ceil(clk_freq, HZ_PER_MHZ); 1803 goto set_core_clk_ctrl; 1804 } 1805 } 1806 1807 list_for_each_entry(clki, head, list) { 1808 if (!IS_ERR_OR_NULL(clki->clk) && 1809 !strcmp(clki->name, "core_clk_unipro")) { 1810 if (!clki->max_freq) { 1811 cycles_in_1us = 150; /* default for backwards compatibility */ 1812 break; 1813 } 1814 1815 if (freq == ULONG_MAX) { 1816 cycles_in_1us = ceil(clki->max_freq, HZ_PER_MHZ); 1817 break; 1818 } 1819 1820 if (is_scale_up) 1821 cycles_in_1us = ceil(clki->max_freq, HZ_PER_MHZ); 1822 else 1823 cycles_in_1us = ceil(clk_get_rate(clki->clk), HZ_PER_MHZ); 1824 break; 1825 } 1826 } 1827 1828 set_core_clk_ctrl: 1829 err = ufshcd_dme_get(hba, 1830 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1831 &core_clk_ctrl_reg); 1832 if (err) 1833 return err; 1834 1835 /* Bit mask is different for UFS host controller V4.0.0 onwards */ 1836 if (host->hw_ver.major >= 4) { 1837 if (!FIELD_FIT(CLK_1US_CYCLES_MASK_V4, cycles_in_1us)) 1838 return -ERANGE; 1839 core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK_V4; 1840 core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK_V4, cycles_in_1us); 1841 } else { 1842 if (!FIELD_FIT(CLK_1US_CYCLES_MASK, cycles_in_1us)) 1843 return -ERANGE; 1844 core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK; 1845 core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK, cycles_in_1us); 1846 } 1847 1848 /* Clear CORE_CLK_DIV_EN */ 1849 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; 1850 1851 err = ufshcd_dme_set(hba, 1852 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1853 core_clk_ctrl_reg); 1854 if (err) 1855 return err; 1856 1857 /* Configure unipro core clk 40ns attribute */ 1858 return ufs_qcom_set_clk_40ns_cycles(hba, cycles_in_1us); 1859 } 1860 1861 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba, unsigned long freq) 1862 { 1863 int ret; 1864 1865 ret = ufs_qcom_cfg_timers(hba, true, freq); 1866 if (ret) { 1867 dev_err(hba->dev, "%s ufs cfg timer failed\n", __func__); 1868 return ret; 1869 } 1870 /* set unipro core clock attributes and clear clock divider */ 1871 return ufs_qcom_set_core_clk_ctrl(hba, true, freq); 1872 } 1873 1874 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba) 1875 { 1876 return 0; 1877 } 1878 1879 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba) 1880 { 1881 int err; 1882 u32 core_clk_ctrl_reg; 1883 1884 err = ufshcd_dme_get(hba, 1885 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1886 &core_clk_ctrl_reg); 1887 1888 /* make sure CORE_CLK_DIV_EN is cleared */ 1889 if (!err && 1890 (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) { 1891 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; 1892 err = ufshcd_dme_set(hba, 1893 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1894 core_clk_ctrl_reg); 1895 } 1896 1897 return err; 1898 } 1899 1900 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba, unsigned long freq) 1901 { 1902 int ret; 1903 1904 ret = ufs_qcom_cfg_timers(hba, false, freq); 1905 if (ret) { 1906 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", __func__); 1907 return ret; 1908 } 1909 /* set unipro core clock attributes and clear clock divider */ 1910 return ufs_qcom_set_core_clk_ctrl(hba, false, freq); 1911 } 1912 1913 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, bool scale_up, 1914 unsigned long target_freq, 1915 enum ufs_notify_change_status status) 1916 { 1917 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1918 int err; 1919 1920 /* check the host controller state before sending hibern8 cmd */ 1921 if (!ufshcd_is_hba_active(hba)) 1922 return 0; 1923 1924 if (status == PRE_CHANGE) { 1925 err = ufshcd_uic_hibern8_enter(hba); 1926 if (err) 1927 return err; 1928 if (scale_up) 1929 err = ufs_qcom_clk_scale_up_pre_change(hba, target_freq); 1930 else 1931 err = ufs_qcom_clk_scale_down_pre_change(hba); 1932 1933 if (err) { 1934 ufshcd_uic_hibern8_exit(hba); 1935 return err; 1936 } 1937 } else { 1938 if (scale_up) 1939 err = ufs_qcom_clk_scale_up_post_change(hba); 1940 else 1941 err = ufs_qcom_clk_scale_down_post_change(hba, target_freq); 1942 1943 1944 if (err) { 1945 ufshcd_uic_hibern8_exit(hba); 1946 return err; 1947 } 1948 1949 ufs_qcom_icc_update_bw(host); 1950 ufshcd_uic_hibern8_exit(hba); 1951 } 1952 1953 return 0; 1954 } 1955 1956 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host) 1957 { 1958 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, 1959 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1); 1960 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1); 1961 } 1962 1963 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host) 1964 { 1965 /* provide a legal default configuration */ 1966 host->testbus.select_major = TSTBUS_UNIPRO; 1967 host->testbus.select_minor = 37; 1968 } 1969 1970 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host) 1971 { 1972 if (host->testbus.select_major >= TSTBUS_MAX) { 1973 dev_err(host->hba->dev, 1974 "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n", 1975 __func__, host->testbus.select_major); 1976 return false; 1977 } 1978 1979 return true; 1980 } 1981 1982 int ufs_qcom_testbus_config(struct ufs_qcom_host *host) 1983 { 1984 int reg; 1985 int offset; 1986 u32 mask = TEST_BUS_SUB_SEL_MASK; 1987 1988 if (!host) 1989 return -EINVAL; 1990 1991 if (!ufs_qcom_testbus_cfg_is_ok(host)) 1992 return -EPERM; 1993 1994 switch (host->testbus.select_major) { 1995 case TSTBUS_UAWM: 1996 reg = UFS_TEST_BUS_CTRL_0; 1997 offset = 24; 1998 break; 1999 case TSTBUS_UARM: 2000 reg = UFS_TEST_BUS_CTRL_0; 2001 offset = 16; 2002 break; 2003 case TSTBUS_TXUC: 2004 reg = UFS_TEST_BUS_CTRL_0; 2005 offset = 8; 2006 break; 2007 case TSTBUS_RXUC: 2008 reg = UFS_TEST_BUS_CTRL_0; 2009 offset = 0; 2010 break; 2011 case TSTBUS_DFC: 2012 reg = UFS_TEST_BUS_CTRL_1; 2013 offset = 24; 2014 break; 2015 case TSTBUS_TRLUT: 2016 reg = UFS_TEST_BUS_CTRL_1; 2017 offset = 16; 2018 break; 2019 case TSTBUS_TMRLUT: 2020 reg = UFS_TEST_BUS_CTRL_1; 2021 offset = 8; 2022 break; 2023 case TSTBUS_OCSC: 2024 reg = UFS_TEST_BUS_CTRL_1; 2025 offset = 0; 2026 break; 2027 case TSTBUS_WRAPPER: 2028 reg = UFS_TEST_BUS_CTRL_2; 2029 offset = 16; 2030 break; 2031 case TSTBUS_COMBINED: 2032 reg = UFS_TEST_BUS_CTRL_2; 2033 offset = 8; 2034 break; 2035 case TSTBUS_UTP_HCI: 2036 reg = UFS_TEST_BUS_CTRL_2; 2037 offset = 0; 2038 break; 2039 case TSTBUS_UNIPRO: 2040 reg = UFS_UNIPRO_CFG; 2041 offset = 20; 2042 mask = 0xFFF; 2043 break; 2044 /* 2045 * No need for a default case, since 2046 * ufs_qcom_testbus_cfg_is_ok() checks that the configuration 2047 * is legal 2048 */ 2049 } 2050 mask <<= offset; 2051 ufshcd_rmwl(host->hba, TEST_BUS_SEL, 2052 (u32)host->testbus.select_major << 19, 2053 REG_UFS_CFG1); 2054 ufshcd_rmwl(host->hba, mask, 2055 (u32)host->testbus.select_minor << offset, 2056 reg); 2057 ufs_qcom_enable_test_bus(host); 2058 2059 return 0; 2060 } 2061 2062 static void ufs_qcom_dump_testbus(struct ufs_hba *hba) 2063 { 2064 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 2065 int i, j, nminor = 0, testbus_len = 0; 2066 char *prefix; 2067 2068 u32 *testbus __free(kfree) = kmalloc_array(256, sizeof(u32), GFP_KERNEL); 2069 if (!testbus) 2070 return; 2071 2072 for (j = 0; j < TSTBUS_MAX; j++) { 2073 nminor = testbus_info[j].nminor; 2074 prefix = testbus_info[j].prefix; 2075 host->testbus.select_major = j; 2076 testbus_len = nminor * sizeof(u32); 2077 for (i = 0; i < nminor; i++) { 2078 host->testbus.select_minor = i; 2079 ufs_qcom_testbus_config(host); 2080 testbus[i] = ufshcd_readl(hba, UFS_TEST_BUS); 2081 } 2082 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 2083 16, 4, testbus, testbus_len, false); 2084 } 2085 } 2086 2087 static int ufs_qcom_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, 2088 const char *prefix, void __iomem *base) 2089 { 2090 size_t pos; 2091 2092 if (offset % 4 != 0 || len % 4 != 0) 2093 return -EINVAL; 2094 2095 u32 *regs __free(kfree) = kzalloc(len, GFP_ATOMIC); 2096 if (!regs) 2097 return -ENOMEM; 2098 2099 for (pos = 0; pos < len; pos += 4) 2100 regs[pos / 4] = readl(base + offset + pos); 2101 2102 print_hex_dump(KERN_ERR, prefix, 2103 len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE, 2104 16, 4, regs, len, false); 2105 2106 return 0; 2107 } 2108 2109 static void ufs_qcom_dump_mcq_hci_regs(struct ufs_hba *hba) 2110 { 2111 struct ufshcd_mcq_opr_info_t *opr = &hba->mcq_opr[0]; 2112 void __iomem *mcq_vs_base = hba->mcq_base + UFS_MEM_VS_BASE; 2113 2114 struct dump_info { 2115 void __iomem *base; 2116 size_t offset; 2117 size_t len; 2118 const char *prefix; 2119 }; 2120 2121 struct dump_info mcq_dumps[] = { 2122 {hba->mcq_base, 0x0, 256 * 4, "MCQ HCI-0 "}, 2123 {hba->mcq_base, 0x400, 256 * 4, "MCQ HCI-1 "}, 2124 {mcq_vs_base, 0x0, 5 * 4, "MCQ VS-0 "}, 2125 {opr->base, 0x0, 256 * 4, "MCQ SQD-0 "}, 2126 {opr->base, 0x400, 256 * 4, "MCQ SQD-1 "}, 2127 {opr->base, 0x800, 256 * 4, "MCQ SQD-2 "}, 2128 {opr->base, 0xc00, 256 * 4, "MCQ SQD-3 "}, 2129 {opr->base, 0x1000, 256 * 4, "MCQ SQD-4 "}, 2130 {opr->base, 0x1400, 256 * 4, "MCQ SQD-5 "}, 2131 {opr->base, 0x1800, 256 * 4, "MCQ SQD-6 "}, 2132 {opr->base, 0x1c00, 256 * 4, "MCQ SQD-7 "}, 2133 2134 }; 2135 2136 for (int i = 0; i < ARRAY_SIZE(mcq_dumps); i++) { 2137 ufs_qcom_dump_regs(hba, mcq_dumps[i].offset, mcq_dumps[i].len, 2138 mcq_dumps[i].prefix, mcq_dumps[i].base); 2139 cond_resched(); 2140 } 2141 } 2142 2143 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba) 2144 { 2145 u32 reg; 2146 struct ufs_qcom_host *host; 2147 2148 host = ufshcd_get_variant(hba); 2149 2150 dev_err(hba->dev, "HW_H8_ENTER_CNT=%d\n", ufshcd_readl(hba, REG_UFS_HW_H8_ENTER_CNT)); 2151 dev_err(hba->dev, "HW_H8_EXIT_CNT=%d\n", ufshcd_readl(hba, REG_UFS_HW_H8_EXIT_CNT)); 2152 2153 dev_err(hba->dev, "SW_H8_ENTER_CNT=%d\n", ufshcd_readl(hba, REG_UFS_SW_H8_ENTER_CNT)); 2154 dev_err(hba->dev, "SW_H8_EXIT_CNT=%d\n", ufshcd_readl(hba, REG_UFS_SW_H8_EXIT_CNT)); 2155 2156 dev_err(hba->dev, "SW_AFTER_HW_H8_ENTER_CNT=%d\n", 2157 ufshcd_readl(hba, REG_UFS_SW_AFTER_HW_H8_ENTER_CNT)); 2158 2159 ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4, 2160 "HCI Vendor Specific Registers "); 2161 2162 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC); 2163 ufshcd_dump_regs(hba, reg, 44 * 4, "UFS_UFS_DBG_RD_REG_OCSC "); 2164 2165 reg = ufshcd_readl(hba, REG_UFS_CFG1); 2166 reg |= UTP_DBG_RAMS_EN; 2167 ufshcd_writel(hba, reg, REG_UFS_CFG1); 2168 2169 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM); 2170 ufshcd_dump_regs(hba, reg, 32 * 4, "UFS_UFS_DBG_RD_EDTL_RAM "); 2171 2172 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM); 2173 ufshcd_dump_regs(hba, reg, 128 * 4, "UFS_UFS_DBG_RD_DESC_RAM "); 2174 2175 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM); 2176 ufshcd_dump_regs(hba, reg, 64 * 4, "UFS_UFS_DBG_RD_PRDT_RAM "); 2177 2178 /* clear bit 17 - UTP_DBG_RAMS_EN */ 2179 ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1); 2180 2181 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM); 2182 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UAWM "); 2183 2184 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM); 2185 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UARM "); 2186 2187 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC); 2188 ufshcd_dump_regs(hba, reg, 48 * 4, "UFS_DBG_RD_REG_TXUC "); 2189 2190 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC); 2191 ufshcd_dump_regs(hba, reg, 27 * 4, "UFS_DBG_RD_REG_RXUC "); 2192 2193 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC); 2194 ufshcd_dump_regs(hba, reg, 19 * 4, "UFS_DBG_RD_REG_DFC "); 2195 2196 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT); 2197 ufshcd_dump_regs(hba, reg, 34 * 4, "UFS_DBG_RD_REG_TRLUT "); 2198 2199 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT); 2200 ufshcd_dump_regs(hba, reg, 9 * 4, "UFS_DBG_RD_REG_TMRLUT "); 2201 2202 if (hba->mcq_enabled) { 2203 reg = ufs_qcom_get_debug_reg_offset(host, UFS_RD_REG_MCQ); 2204 ufshcd_dump_regs(hba, reg, 64 * 4, "HCI MCQ Debug Registers "); 2205 } 2206 2207 /* ensure below dumps occur only in task context due to blocking calls. */ 2208 if (in_task()) { 2209 /* Dump MCQ Host Vendor Specific Registers */ 2210 if (hba->mcq_enabled) 2211 ufs_qcom_dump_mcq_hci_regs(hba); 2212 2213 /* voluntarily yield the CPU as we are dumping too much data */ 2214 ufshcd_dump_regs(hba, UFS_TEST_BUS, 4, "UFS_TEST_BUS "); 2215 cond_resched(); 2216 ufs_qcom_dump_testbus(hba); 2217 } 2218 } 2219 2220 /** 2221 * ufs_qcom_device_reset() - toggle the (optional) device reset line 2222 * @hba: per-adapter instance 2223 * 2224 * Toggles the (optional) reset line to reset the attached device. 2225 */ 2226 static int ufs_qcom_device_reset(struct ufs_hba *hba) 2227 { 2228 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 2229 2230 /* reset gpio is optional */ 2231 if (!host->device_reset) 2232 return -EOPNOTSUPP; 2233 2234 /* 2235 * The UFS device shall detect reset pulses of 1us, sleep for 10us to 2236 * be on the safe side. 2237 */ 2238 ufs_qcom_device_reset_ctrl(hba, true); 2239 usleep_range(10, 15); 2240 2241 ufs_qcom_device_reset_ctrl(hba, false); 2242 usleep_range(10, 15); 2243 2244 return 0; 2245 } 2246 2247 /** 2248 * ufs_qcom_fw_managed_device_reset - Reset UFS device under FW-managed design 2249 * @hba: pointer to UFS host bus adapter 2250 * 2251 * In the firmware-managed reset model, the power domain is powered on by genpd 2252 * before the UFS controller driver probes. For subsequent resets (such as 2253 * suspend/resume or recovery), the UFS driver must explicitly invoke PM runtime 2254 * 2255 * Return: 0 on success or a negative error code on failure. 2256 */ 2257 static int ufs_qcom_fw_managed_device_reset(struct ufs_hba *hba) 2258 { 2259 static bool is_boot = true; 2260 int err; 2261 2262 /* Skip reset on cold boot; perform it on subsequent calls */ 2263 if (is_boot) { 2264 is_boot = false; 2265 return 0; 2266 } 2267 2268 pm_runtime_put_sync(hba->dev); 2269 err = pm_runtime_resume_and_get(hba->dev); 2270 if (err < 0) { 2271 dev_err(hba->dev, "PM runtime resume failed: %d\n", err); 2272 return err; 2273 } 2274 2275 return 0; 2276 } 2277 2278 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba, 2279 struct devfreq_dev_profile *p, 2280 struct devfreq_simple_ondemand_data *d) 2281 { 2282 p->polling_ms = 60; 2283 p->timer = DEVFREQ_TIMER_DELAYED; 2284 d->upthreshold = 70; 2285 d->downdifferential = 5; 2286 2287 hba->clk_scaling.suspend_on_no_request = true; 2288 } 2289 2290 static int ufs_qcom_mcq_config_resource(struct ufs_hba *hba) 2291 { 2292 struct platform_device *pdev = to_platform_device(hba->dev); 2293 struct resource *res; 2294 2295 /* Map the MCQ configuration region */ 2296 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mcq"); 2297 if (!res) { 2298 dev_err(hba->dev, "MCQ resource not found in device tree\n"); 2299 return -ENODEV; 2300 } 2301 2302 hba->mcq_base = devm_ioremap_resource(hba->dev, res); 2303 if (IS_ERR(hba->mcq_base)) { 2304 dev_err(hba->dev, "Failed to map MCQ region: %ld\n", 2305 PTR_ERR(hba->mcq_base)); 2306 return PTR_ERR(hba->mcq_base); 2307 } 2308 2309 return 0; 2310 } 2311 2312 static int ufs_qcom_op_runtime_config(struct ufs_hba *hba) 2313 { 2314 struct ufshcd_mcq_opr_info_t *opr; 2315 int i; 2316 u32 doorbell_offsets[OPR_MAX]; 2317 2318 /* 2319 * Configure doorbell address offsets in MCQ configuration registers. 2320 * These values are offsets relative to mmio_base (UFS_HCI_BASE). 2321 * 2322 * Memory Layout: 2323 * - mmio_base = UFS_HCI_BASE 2324 * - mcq_base = MCQ_CONFIG_BASE = mmio_base + (UFS_QCOM_MCQCAP_QCFGPTR * 0x200) 2325 * - Doorbell registers are at: mmio_base + (UFS_QCOM_MCQCAP_QCFGPTR * 0x200) + 2326 * - UFS_QCOM_MCQ_SQD_OFFSET 2327 * - Which is also: mcq_base + UFS_QCOM_MCQ_SQD_OFFSET 2328 */ 2329 2330 doorbell_offsets[OPR_SQD] = UFS_QCOM_SQD_ADDR_OFFSET; 2331 doorbell_offsets[OPR_SQIS] = UFS_QCOM_SQIS_ADDR_OFFSET; 2332 doorbell_offsets[OPR_CQD] = UFS_QCOM_CQD_ADDR_OFFSET; 2333 doorbell_offsets[OPR_CQIS] = UFS_QCOM_CQIS_ADDR_OFFSET; 2334 2335 /* 2336 * Configure MCQ operation registers. 2337 * 2338 * The doorbell registers are physically located within the MCQ region: 2339 * - doorbell_physical_addr = mmio_base + doorbell_offset 2340 * - doorbell_physical_addr = mcq_base + (doorbell_offset - MCQ_CONFIG_OFFSET) 2341 */ 2342 for (i = 0; i < OPR_MAX; i++) { 2343 opr = &hba->mcq_opr[i]; 2344 opr->offset = doorbell_offsets[i]; /* Offset relative to mmio_base */ 2345 opr->stride = UFS_QCOM_MCQ_STRIDE; /* 256 bytes between queues */ 2346 2347 /* 2348 * Calculate the actual doorbell base address within MCQ region: 2349 * base = mcq_base + (doorbell_offset - MCQ_CONFIG_OFFSET) 2350 */ 2351 opr->base = hba->mcq_base + (opr->offset - UFS_QCOM_MCQ_CONFIG_OFFSET); 2352 } 2353 2354 return 0; 2355 } 2356 2357 static int ufs_qcom_get_hba_mac(struct ufs_hba *hba) 2358 { 2359 /* Qualcomm HC supports up to 64 */ 2360 return MAX_SUPP_MAC; 2361 } 2362 2363 static int ufs_qcom_get_outstanding_cqs(struct ufs_hba *hba, 2364 unsigned long *ocqs) 2365 { 2366 /* Read from MCQ vendor-specific register in MCQ region */ 2367 *ocqs = readl(hba->mcq_base + UFS_MEM_CQIS_VS); 2368 2369 return 0; 2370 } 2371 2372 static void ufs_qcom_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg) 2373 { 2374 struct device *dev = msi_desc_to_dev(desc); 2375 struct ufs_hba *hba = dev_get_drvdata(dev); 2376 2377 ufshcd_mcq_config_esi(hba, msg); 2378 } 2379 2380 struct ufs_qcom_irq { 2381 unsigned int irq; 2382 unsigned int idx; 2383 struct ufs_hba *hba; 2384 }; 2385 2386 static irqreturn_t ufs_qcom_mcq_esi_handler(int irq, void *data) 2387 { 2388 struct ufs_qcom_irq *qi = data; 2389 struct ufs_hba *hba = qi->hba; 2390 struct ufs_hw_queue *hwq = &hba->uhq[qi->idx]; 2391 2392 ufshcd_mcq_write_cqis(hba, 0x1, qi->idx); 2393 ufshcd_mcq_poll_cqe_lock(hba, hwq); 2394 2395 return IRQ_HANDLED; 2396 } 2397 2398 static int ufs_qcom_config_esi(struct ufs_hba *hba) 2399 { 2400 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 2401 int nr_irqs, ret; 2402 2403 if (host->esi_enabled) 2404 return 0; 2405 2406 /* 2407 * 1. We only handle CQs as of now. 2408 * 2. Poll queues do not need ESI. 2409 */ 2410 nr_irqs = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; 2411 2412 ret = platform_device_msi_init_and_alloc_irqs(hba->dev, nr_irqs, 2413 ufs_qcom_write_msi_msg); 2414 if (ret) { 2415 dev_warn(hba->dev, "Platform MSI not supported or failed, continuing without ESI\n"); 2416 return ret; /* Continue without ESI */ 2417 } 2418 2419 struct ufs_qcom_irq *qi = devm_kcalloc(hba->dev, nr_irqs, sizeof(*qi), GFP_KERNEL); 2420 2421 if (!qi) { 2422 platform_device_msi_free_irqs_all(hba->dev); 2423 return -ENOMEM; 2424 } 2425 2426 for (int idx = 0; idx < nr_irqs; idx++) { 2427 qi[idx].irq = msi_get_virq(hba->dev, idx); 2428 qi[idx].idx = idx; 2429 qi[idx].hba = hba; 2430 2431 ret = devm_request_irq(hba->dev, qi[idx].irq, ufs_qcom_mcq_esi_handler, 2432 IRQF_SHARED, "qcom-mcq-esi", qi + idx); 2433 if (ret) { 2434 dev_err(hba->dev, "%s: Failed to request IRQ for %d, err = %d\n", 2435 __func__, qi[idx].irq, ret); 2436 /* Free previously allocated IRQs */ 2437 for (int j = 0; j < idx; j++) 2438 devm_free_irq(hba->dev, qi[j].irq, qi + j); 2439 platform_device_msi_free_irqs_all(hba->dev); 2440 devm_kfree(hba->dev, qi); 2441 return ret; 2442 } 2443 } 2444 2445 if (host->hw_ver.major >= 6) { 2446 ufshcd_rmwl(hba, ESI_VEC_MASK, FIELD_PREP(ESI_VEC_MASK, MAX_ESI_VEC - 1), 2447 REG_UFS_CFG3); 2448 } 2449 ufshcd_mcq_enable_esi(hba); 2450 host->esi_enabled = true; 2451 return 0; 2452 } 2453 2454 static unsigned long ufs_qcom_opp_freq_to_clk_freq(struct ufs_hba *hba, 2455 unsigned long freq, char *name) 2456 { 2457 struct ufs_clk_info *clki; 2458 struct dev_pm_opp *opp; 2459 unsigned long clk_freq; 2460 int idx = 0; 2461 bool found = false; 2462 2463 opp = dev_pm_opp_find_freq_exact_indexed(hba->dev, freq, 0, true); 2464 if (IS_ERR(opp)) { 2465 dev_err(hba->dev, "Failed to find OPP for exact frequency %lu\n", freq); 2466 return 0; 2467 } 2468 2469 list_for_each_entry(clki, &hba->clk_list_head, list) { 2470 if (!strcmp(clki->name, name)) { 2471 found = true; 2472 break; 2473 } 2474 2475 idx++; 2476 } 2477 2478 if (!found) { 2479 dev_err(hba->dev, "Failed to find clock '%s' in clk list\n", name); 2480 dev_pm_opp_put(opp); 2481 return 0; 2482 } 2483 2484 clk_freq = dev_pm_opp_get_freq_indexed(opp, idx); 2485 2486 dev_pm_opp_put(opp); 2487 2488 return clk_freq; 2489 } 2490 2491 static u32 ufs_qcom_freq_to_gear_speed(struct ufs_hba *hba, unsigned long freq) 2492 { 2493 u32 gear = UFS_HS_DONT_CHANGE; 2494 unsigned long unipro_freq; 2495 2496 if (!hba->use_pm_opp) 2497 return gear; 2498 2499 unipro_freq = ufs_qcom_opp_freq_to_clk_freq(hba, freq, "core_clk_unipro"); 2500 switch (unipro_freq) { 2501 case 403000000: 2502 gear = UFS_HS_G5; 2503 break; 2504 case 300000000: 2505 gear = UFS_HS_G4; 2506 break; 2507 case 201500000: 2508 gear = UFS_HS_G3; 2509 break; 2510 case 150000000: 2511 case 100000000: 2512 gear = UFS_HS_G2; 2513 break; 2514 case 75000000: 2515 case 37500000: 2516 gear = UFS_HS_G1; 2517 break; 2518 default: 2519 dev_err(hba->dev, "%s: Unsupported clock freq : %lu\n", __func__, freq); 2520 return UFS_HS_DONT_CHANGE; 2521 } 2522 2523 return min_t(u32, gear, hba->max_pwr_info.info.gear_rx); 2524 } 2525 2526 static int ufs_qcom_host_eom_config(struct ufs_hba *hba, int lane, 2527 const struct ufs_eom_coord *eom_coord, 2528 u32 target_test_count) 2529 { 2530 enum ufs_eom_eye_mask eye_mask = eom_coord->eye_mask; 2531 int v_step = eom_coord->v_step; 2532 int t_step = eom_coord->t_step; 2533 u32 volt_step, timing_step; 2534 int ret; 2535 2536 if (abs(v_step) > UFS_QCOM_EOM_VOLTAGE_STEPS_MAX) { 2537 dev_err(hba->dev, "Invalid EOM Voltage Step: %d\n", v_step); 2538 return -ERANGE; 2539 } 2540 2541 if (abs(t_step) > UFS_QCOM_EOM_TIMING_STEPS_MAX) { 2542 dev_err(hba->dev, "Invalid EOM Timing Step: %d\n", t_step); 2543 return -ERANGE; 2544 } 2545 2546 if (v_step < 0) 2547 volt_step = RX_EYEMON_NEGATIVE_STEP_BIT | (u32)(-v_step); 2548 else 2549 volt_step = (u32)v_step; 2550 2551 if (t_step < 0) 2552 timing_step = RX_EYEMON_NEGATIVE_STEP_BIT | (u32)(-t_step); 2553 else 2554 timing_step = (u32)t_step; 2555 2556 ret = ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_EYEMON_ENABLE, 2557 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)), 2558 BIT(eye_mask) | RX_EYEMON_EXTENDED_VRANGE_BIT); 2559 if (ret) { 2560 dev_err(hba->dev, "Failed to enable Host EOM on Lane %d: %d\n", 2561 lane, ret); 2562 return ret; 2563 } 2564 2565 ret = ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_EYEMON_TIMING_STEPS, 2566 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)), 2567 timing_step); 2568 if (ret) { 2569 dev_err(hba->dev, "Failed to set Host EOM timing step on Lane %d: %d\n", 2570 lane, ret); 2571 return ret; 2572 } 2573 2574 ret = ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_EYEMON_VOLTAGE_STEPS, 2575 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)), 2576 volt_step); 2577 if (ret) { 2578 dev_err(hba->dev, "Failed to set Host EOM voltage step on Lane %d: %d\n", 2579 lane, ret); 2580 return ret; 2581 } 2582 2583 ret = ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_EYEMON_TARGET_TEST_COUNT, 2584 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)), 2585 target_test_count); 2586 if (ret) 2587 dev_err(hba->dev, "Failed to set Host EOM target test count on Lane %d: %d\n", 2588 lane, ret); 2589 2590 return ret; 2591 } 2592 2593 static int ufs_qcom_host_eom_may_stop(struct ufs_hba *hba, int lane, 2594 u32 target_test_count, u32 *err_count) 2595 { 2596 u32 start, tested_count, error_count; 2597 int ret; 2598 2599 ret = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(RX_EYEMON_START, 2600 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)), 2601 &start); 2602 if (ret) { 2603 dev_err(hba->dev, "Failed to get Host EOM start status on Lane %d: %d\n", 2604 lane, ret); 2605 return ret; 2606 } 2607 2608 if (start & 0x1) 2609 return -EAGAIN; 2610 2611 ret = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(RX_EYEMON_TESTED_COUNT, 2612 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)), 2613 &tested_count); 2614 if (ret) { 2615 dev_err(hba->dev, "Failed to get Host EOM tested count on Lane %d: %d\n", 2616 lane, ret); 2617 return ret; 2618 } 2619 2620 ret = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(RX_EYEMON_ERROR_COUNT, 2621 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)), 2622 &error_count); 2623 if (ret) { 2624 dev_err(hba->dev, "Failed to get Host EOM error count on Lane %d: %d\n", 2625 lane, ret); 2626 return ret; 2627 } 2628 2629 /* EOM can stop */ 2630 if ((tested_count >= target_test_count - 3) || error_count > 0) { 2631 *err_count = error_count; 2632 2633 /* Disable EOM */ 2634 ret = ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_EYEMON_ENABLE, 2635 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane)), 2636 0x0); 2637 if (ret) { 2638 dev_err(hba->dev, "Failed to disable Host EOM on Lane %d: %d\n", 2639 lane, ret); 2640 return ret; 2641 } 2642 } else { 2643 return -EAGAIN; 2644 } 2645 2646 return 0; 2647 } 2648 2649 static int ufs_qcom_host_eom_scan(struct ufs_hba *hba, int num_lanes, 2650 const struct ufs_eom_coord *eom_coord, 2651 u32 target_test_count, u32 *err_count) 2652 { 2653 bool eom_stopped[PA_MAXDATALANES] = { 0 }; 2654 int lane, ret; 2655 u32 setting; 2656 2657 if (!err_count || !eom_coord) 2658 return -EINVAL; 2659 2660 if (target_test_count < UFS_QCOM_EOM_TARGET_TEST_COUNT_MIN) { 2661 dev_err(hba->dev, "Target test count (%u) too small for Host EOM\n", 2662 target_test_count); 2663 return -ERANGE; 2664 } 2665 2666 for (lane = 0; lane < num_lanes; lane++) { 2667 ret = ufs_qcom_host_eom_config(hba, lane, eom_coord, 2668 target_test_count); 2669 if (ret) { 2670 dev_err(hba->dev, "Failed to config Host RX EOM: %d\n", ret); 2671 return ret; 2672 } 2673 } 2674 2675 /* 2676 * Trigger a PACP_PWR_req to kick start EOM, but not to really change 2677 * the Power Mode. 2678 */ 2679 ret = ufshcd_uic_change_pwr_mode(hba, FAST_MODE << 4 | FAST_MODE); 2680 if (ret) { 2681 dev_err(hba->dev, "Failed to change power mode to kick start Host EOM: %d\n", 2682 ret); 2683 return ret; 2684 } 2685 2686 more_burst: 2687 /* Create burst on Host RX Lane. */ 2688 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_LOCALVERINFO), &setting); 2689 2690 for (lane = 0; lane < num_lanes; lane++) { 2691 if (eom_stopped[lane]) 2692 continue; 2693 2694 ret = ufs_qcom_host_eom_may_stop(hba, lane, target_test_count, 2695 &err_count[lane]); 2696 if (!ret) { 2697 eom_stopped[lane] = true; 2698 } else if (ret == -EAGAIN) { 2699 /* Need more burst to excercise EOM */ 2700 goto more_burst; 2701 } else { 2702 dev_err(hba->dev, "Failed to stop Host EOM: %d\n", ret); 2703 return ret; 2704 } 2705 2706 dev_dbg(hba->dev, "Host RX Lane %d EOM, v_step %d, t_step %d, error count %u\n", 2707 lane, eom_coord->v_step, eom_coord->t_step, 2708 err_count[lane]); 2709 } 2710 2711 return 0; 2712 } 2713 2714 static int ufs_qcom_host_sw_rx_fom(struct ufs_hba *hba, int num_lanes, u32 *fom) 2715 { 2716 const struct ufs_eom_coord *eom_coord = sw_rx_fom_eom_coords_g6; 2717 u32 eom_err_count[PA_MAXDATALANES] = { 0 }; 2718 u32 curr_ahit; 2719 int lane, i, ret; 2720 2721 if (!fom) 2722 return -EINVAL; 2723 2724 /* Stop the auto hibernate idle timer */ 2725 curr_ahit = ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER); 2726 if (curr_ahit) 2727 ufshcd_writel(hba, 0, REG_AUTO_HIBERNATE_IDLE_TIMER); 2728 2729 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXHSADAPTTYPE), PA_NO_ADAPT); 2730 if (ret) { 2731 dev_err(hba->dev, "Failed to select NO_ADAPT before starting Host EOM: %d\n", ret); 2732 goto out; 2733 } 2734 2735 for (i = 0; i < SW_RX_FOM_EOM_COORDS; i++, eom_coord++) { 2736 ret = ufs_qcom_host_eom_scan(hba, num_lanes, eom_coord, 2737 UFS_QCOM_EOM_TARGET_TEST_COUNT_G6, 2738 eom_err_count); 2739 if (ret) { 2740 dev_err(hba->dev, "Failed to run Host EOM scan: %d\n", ret); 2741 break; 2742 } 2743 2744 for (lane = 0; lane < num_lanes; lane++) { 2745 /* Bad coordinates have no weights */ 2746 if (eom_err_count[lane]) 2747 continue; 2748 fom[lane] += SW_RX_FOM_EOM_COORDS_WEIGHT; 2749 } 2750 } 2751 2752 out: 2753 /* Restore the auto hibernate idle timer */ 2754 if (curr_ahit) 2755 ufshcd_writel(hba, curr_ahit, REG_AUTO_HIBERNATE_IDLE_TIMER); 2756 2757 return ret; 2758 } 2759 2760 static int ufs_qcom_get_rx_fom(struct ufs_hba *hba, 2761 struct ufs_pa_layer_attr *pwr_mode, 2762 struct tx_eqtr_iter *h_iter, 2763 struct tx_eqtr_iter *d_iter) 2764 { 2765 struct ufshcd_tx_eq_params *params __free(kfree) = 2766 kzalloc(sizeof(*params), GFP_KERNEL); 2767 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 2768 struct ufs_pa_layer_attr old_pwr_info; 2769 u32 fom[PA_MAXDATALANES] = { 0 }; 2770 u32 gear = pwr_mode->gear_tx; 2771 u32 rate = pwr_mode->hs_rate; 2772 int lane, ret; 2773 2774 if (host->hw_ver.major != 0x7 || host->hw_ver.minor > 0x1 || 2775 gear <= UFS_HS_G5 || !d_iter || !d_iter->is_updated) 2776 return 0; 2777 2778 if (gear < UFS_HS_G1 || gear > UFS_HS_GEAR_MAX) 2779 return -ERANGE; 2780 2781 if (!params) 2782 return -ENOMEM; 2783 2784 memcpy(&old_pwr_info, &hba->pwr_info, sizeof(struct ufs_pa_layer_attr)); 2785 2786 memcpy(params, &hba->tx_eq_params[gear - 1], sizeof(struct ufshcd_tx_eq_params)); 2787 for (lane = 0; lane < pwr_mode->lane_rx; lane++) { 2788 params->device[lane].preshoot = d_iter->preshoot; 2789 params->device[lane].deemphasis = d_iter->deemphasis; 2790 } 2791 2792 /* Use TX EQTR settings as Device's TX Equalization settings. */ 2793 ret = ufshcd_apply_tx_eq_settings(hba, params, gear); 2794 if (ret) { 2795 dev_err(hba->dev, "%s: Failed to apply TX EQ settings for HS-G%u: %d\n", 2796 __func__, gear, ret); 2797 return ret; 2798 } 2799 2800 /* Force PMC to target HS Gear to use new TX Equalization settings. */ 2801 ret = ufshcd_change_power_mode(hba, pwr_mode, UFSHCD_PMC_POLICY_FORCE); 2802 if (ret) { 2803 dev_err(hba->dev, "%s: Failed to change power mode to HS-G%u, Rate-%s: %d\n", 2804 __func__, gear, ufs_hs_rate_to_str(rate), ret); 2805 return ret; 2806 } 2807 2808 ret = ufs_qcom_host_sw_rx_fom(hba, pwr_mode->lane_rx, fom); 2809 if (ret) { 2810 dev_err(hba->dev, "Failed to get SW FOM of TX (PreShoot: %u, DeEmphasis: %u): %d\n", 2811 d_iter->preshoot, d_iter->deemphasis, ret); 2812 return ret; 2813 } 2814 2815 /* Restore Device's TX Equalization settings. */ 2816 ret = ufshcd_apply_tx_eq_settings(hba, &hba->tx_eq_params[gear - 1], gear); 2817 if (ret) { 2818 dev_err(hba->dev, "%s: Failed to apply TX EQ settings for HS-G%u: %d\n", 2819 __func__, gear, ret); 2820 return ret; 2821 } 2822 2823 /* Restore Power Mode. */ 2824 ret = ufshcd_change_power_mode(hba, &old_pwr_info, UFSHCD_PMC_POLICY_FORCE); 2825 if (ret) { 2826 dev_err(hba->dev, "%s: Failed to restore power mode to HS-G%u: %d\n", 2827 __func__, old_pwr_info.gear_tx, ret); 2828 return ret; 2829 } 2830 2831 for (lane = 0; lane < pwr_mode->lane_rx; lane++) 2832 d_iter->fom[lane] = fom[lane]; 2833 2834 return 0; 2835 } 2836 2837 static int ufs_qcom_apply_tx_eqtr_settings(struct ufs_hba *hba, 2838 struct ufs_pa_layer_attr *pwr_mode, 2839 struct tx_eqtr_iter *h_iter, 2840 struct tx_eqtr_iter *d_iter) 2841 { 2842 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 2843 u32 setting = 0; 2844 int lane; 2845 2846 if (host->hw_ver.major != 0x7 || host->hw_ver.minor > 0x1) 2847 return 0; 2848 2849 for (lane = 0; lane < pwr_mode->lane_tx; lane++) { 2850 setting |= TX_HS_PRESHOOT_BITS(lane, h_iter->preshoot); 2851 setting |= TX_HS_DEEMPHASIS_BITS(lane, h_iter->deemphasis); 2852 } 2853 2854 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXEQG1SETTING), setting); 2855 } 2856 2857 static int ufs_qcom_tx_eqtr_notify(struct ufs_hba *hba, 2858 enum ufs_notify_change_status status, 2859 struct ufs_pa_layer_attr *pwr_mode) 2860 { 2861 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 2862 struct ufs_pa_layer_attr pwr_mode_hs_g1 = { 2863 .gear_rx = UFS_HS_G1, 2864 .gear_tx = UFS_HS_G1, 2865 .lane_rx = pwr_mode->lane_rx, 2866 .lane_tx = pwr_mode->lane_tx, 2867 .pwr_rx = FAST_MODE, 2868 .pwr_tx = FAST_MODE, 2869 .hs_rate = pwr_mode->hs_rate, 2870 }; 2871 u32 gear = pwr_mode->gear_tx; 2872 u32 rate = pwr_mode->hs_rate; 2873 int ret; 2874 2875 if (host->hw_ver.major != 0x7 || host->hw_ver.minor > 0x1) 2876 return 0; 2877 2878 if (status == PRE_CHANGE) { 2879 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TXEQG1SETTING), 2880 &host->saved_tx_eq_g1_setting); 2881 if (ret) 2882 return ret; 2883 2884 /* PMC to target HS Gear. */ 2885 ret = ufshcd_change_power_mode(hba, pwr_mode, 2886 UFSHCD_PMC_POLICY_DONT_FORCE); 2887 if (ret) 2888 dev_err(hba->dev, "%s: Failed to PMC to target HS-G%u, Rate-%s: %d\n", 2889 __func__, gear, ufs_hs_rate_to_str(rate), ret); 2890 } else { 2891 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXEQG1SETTING), 2892 host->saved_tx_eq_g1_setting); 2893 if (ret) 2894 return ret; 2895 2896 /* PMC back to HS-G1. */ 2897 ret = ufshcd_change_power_mode(hba, &pwr_mode_hs_g1, 2898 UFSHCD_PMC_POLICY_DONT_FORCE); 2899 if (ret) 2900 dev_err(hba->dev, "%s: Failed to PMC to HS-G1, Rate-%s: %d\n", 2901 __func__, ufs_hs_rate_to_str(rate), ret); 2902 } 2903 2904 return ret; 2905 } 2906 2907 /* 2908 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations 2909 * 2910 * The variant operations configure the necessary controller and PHY 2911 * handshake during initialization. 2912 */ 2913 static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = { 2914 .name = "qcom", 2915 .init = ufs_qcom_init, 2916 .exit = ufs_qcom_exit, 2917 .get_ufs_hci_version = ufs_qcom_get_ufs_hci_version, 2918 .clk_scale_notify = ufs_qcom_clk_scale_notify, 2919 .setup_clocks = ufs_qcom_setup_clocks, 2920 .hce_enable_notify = ufs_qcom_hce_enable_notify, 2921 .link_startup_notify = ufs_qcom_link_startup_notify, 2922 .negotiate_pwr_mode = ufs_qcom_negotiate_pwr_mode, 2923 .pwr_change_notify = ufs_qcom_pwr_change_notify, 2924 .apply_dev_quirks = ufs_qcom_apply_dev_quirks, 2925 .fixup_dev_quirks = ufs_qcom_fixup_dev_quirks, 2926 .suspend = ufs_qcom_suspend, 2927 .resume = ufs_qcom_resume, 2928 .dbg_register_dump = ufs_qcom_dump_dbg_regs, 2929 .device_reset = ufs_qcom_device_reset, 2930 .config_scaling_param = ufs_qcom_config_scaling_param, 2931 .mcq_config_resource = ufs_qcom_mcq_config_resource, 2932 .get_hba_mac = ufs_qcom_get_hba_mac, 2933 .op_runtime_config = ufs_qcom_op_runtime_config, 2934 .get_outstanding_cqs = ufs_qcom_get_outstanding_cqs, 2935 .config_esi = ufs_qcom_config_esi, 2936 .freq_to_gear_speed = ufs_qcom_freq_to_gear_speed, 2937 .get_rx_fom = ufs_qcom_get_rx_fom, 2938 .apply_tx_eqtr_settings = ufs_qcom_apply_tx_eqtr_settings, 2939 .tx_eqtr_notify = ufs_qcom_tx_eqtr_notify, 2940 }; 2941 2942 static const struct ufs_hba_variant_ops ufs_hba_qcom_sa8255p_vops = { 2943 .name = "qcom-sa8255p", 2944 .init = ufs_qcom_fw_managed_init, 2945 .exit = ufs_qcom_fw_managed_exit, 2946 .hce_enable_notify = ufs_qcom_fw_managed_hce_enable_notify, 2947 .pwr_change_notify = ufs_qcom_pwr_change_notify, 2948 .apply_dev_quirks = ufs_qcom_apply_dev_quirks, 2949 .fixup_dev_quirks = ufs_qcom_fixup_dev_quirks, 2950 .suspend = ufs_qcom_fw_managed_suspend, 2951 .resume = ufs_qcom_fw_managed_resume, 2952 .dbg_register_dump = ufs_qcom_dump_dbg_regs, 2953 .device_reset = ufs_qcom_fw_managed_device_reset, 2954 }; 2955 2956 /** 2957 * ufs_qcom_probe - probe routine of the driver 2958 * @pdev: pointer to Platform device handle 2959 * 2960 * Return: zero for success and non-zero for failure. 2961 */ 2962 static int ufs_qcom_probe(struct platform_device *pdev) 2963 { 2964 int err; 2965 struct device *dev = &pdev->dev; 2966 const struct ufs_hba_variant_ops *vops; 2967 const struct ufs_qcom_drvdata *drvdata = device_get_match_data(dev); 2968 2969 if (drvdata && drvdata->vops) 2970 vops = drvdata->vops; 2971 else 2972 vops = &ufs_hba_qcom_vops; 2973 2974 /* Perform generic probe */ 2975 err = ufshcd_pltfrm_init(pdev, vops); 2976 if (err) 2977 return dev_err_probe(dev, err, "ufshcd_pltfrm_init() failed\n"); 2978 2979 return 0; 2980 } 2981 2982 /** 2983 * ufs_qcom_remove - set driver_data of the device to NULL 2984 * @pdev: pointer to platform device handle 2985 * 2986 * Always returns 0 2987 */ 2988 static void ufs_qcom_remove(struct platform_device *pdev) 2989 { 2990 struct ufs_hba *hba = platform_get_drvdata(pdev); 2991 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 2992 2993 ufshcd_pltfrm_remove(pdev); 2994 if (host->esi_enabled) 2995 platform_device_msi_free_irqs_all(hba->dev); 2996 } 2997 2998 static const struct ufs_qcom_drvdata ufs_qcom_sm8550_drvdata = { 2999 .quirks = UFSHCD_QUIRK_BROKEN_LSDBS_CAP, 3000 .no_phy_retention = true, 3001 }; 3002 3003 static const struct ufs_qcom_drvdata ufs_qcom_sa8255p_drvdata = { 3004 .vops = &ufs_hba_qcom_sa8255p_vops 3005 }; 3006 3007 static const struct of_device_id ufs_qcom_of_match[] __maybe_unused = { 3008 { .compatible = "qcom,ufshc" }, 3009 { .compatible = "qcom,sm8550-ufshc", .data = &ufs_qcom_sm8550_drvdata }, 3010 { .compatible = "qcom,sm8650-ufshc", .data = &ufs_qcom_sm8550_drvdata }, 3011 { .compatible = "qcom,sa8255p-ufshc", .data = &ufs_qcom_sa8255p_drvdata }, 3012 {}, 3013 }; 3014 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match); 3015 3016 #ifdef CONFIG_ACPI 3017 static const struct acpi_device_id ufs_qcom_acpi_match[] = { 3018 { "QCOM24A5" }, 3019 { }, 3020 }; 3021 MODULE_DEVICE_TABLE(acpi, ufs_qcom_acpi_match); 3022 #endif 3023 3024 static const struct dev_pm_ops ufs_qcom_pm_ops = { 3025 SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL) 3026 .prepare = ufshcd_suspend_prepare, 3027 .complete = ufshcd_resume_complete, 3028 #ifdef CONFIG_PM_SLEEP 3029 .suspend = ufshcd_system_suspend, 3030 .resume = ufshcd_system_resume, 3031 .freeze = ufshcd_system_freeze, 3032 .restore = ufshcd_system_restore, 3033 .thaw = ufshcd_system_thaw, 3034 #endif 3035 }; 3036 3037 static struct platform_driver ufs_qcom_pltform = { 3038 .probe = ufs_qcom_probe, 3039 .remove = ufs_qcom_remove, 3040 .driver = { 3041 .name = "ufshcd-qcom", 3042 .pm = &ufs_qcom_pm_ops, 3043 .of_match_table = of_match_ptr(ufs_qcom_of_match), 3044 .acpi_match_table = ACPI_PTR(ufs_qcom_acpi_match), 3045 }, 3046 }; 3047 module_platform_driver(ufs_qcom_pltform); 3048 3049 MODULE_DESCRIPTION("Qualcomm UFS host controller driver"); 3050 MODULE_LICENSE("GPL v2"); 3051