1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // rt1320-sdw.c -- rt1320 SDCA ALSA SoC amplifier audio driver 4 // 5 // Copyright(c) 2024 Realtek Semiconductor Corp. 6 // 7 // 8 #include <linux/delay.h> 9 #include <linux/device.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/module.h> 12 #include <linux/regmap.h> 13 #include <linux/dmi.h> 14 #include <linux/firmware.h> 15 #include <sound/core.h> 16 #include <sound/pcm.h> 17 #include <sound/pcm_params.h> 18 #include <sound/soc-dapm.h> 19 #include <sound/initval.h> 20 #include <sound/tlv.h> 21 #include <sound/sdw.h> 22 #include "rt1320-sdw.h" 23 #include "rt-sdw-common.h" 24 25 /* 26 * The 'blind writes' is an SDCA term to deal with platform-specific initialization. 27 * It might include vendor-specific or SDCA control registers. 28 */ 29 static const struct reg_sequence rt1320_blind_write[] = { 30 { 0xc003, 0xe0 }, 31 { 0xc01b, 0xfc }, 32 { 0xc5c3, 0xf2 }, 33 { 0xc5c2, 0x00 }, 34 { 0xc5c6, 0x10 }, 35 { 0xc5c4, 0x12 }, 36 { 0xc5c8, 0x03 }, 37 { 0xc5d8, 0x0a }, 38 { 0xc5f7, 0x22 }, 39 { 0xc5f6, 0x22 }, 40 { 0xc5d0, 0x0f }, 41 { 0xc5d1, 0x89 }, 42 { 0xc057, 0x51 }, 43 { 0xc054, 0x35 }, 44 { 0xc053, 0x55 }, 45 { 0xc052, 0x55 }, 46 { 0xc051, 0x13 }, 47 { 0xc050, 0x15 }, 48 { 0xc060, 0x77 }, 49 { 0xc061, 0x55 }, 50 { 0xc063, 0x55 }, 51 { 0xc065, 0xa5 }, 52 { 0xc06b, 0x0a }, 53 { 0xca05, 0xd6 }, 54 { 0xca25, 0xd6 }, 55 { 0xcd00, 0x05 }, 56 { 0xc604, 0x40 }, 57 { 0xc609, 0x40 }, 58 { 0xc046, 0xff }, 59 { 0xc045, 0xff }, 60 { 0xc044, 0xff }, 61 { 0xc043, 0xff }, 62 { 0xc042, 0xff }, 63 { 0xc041, 0xff }, 64 { 0xc040, 0xff }, 65 { 0xcc10, 0x01 }, 66 { 0xc700, 0xf0 }, 67 { 0xc701, 0x13 }, 68 { 0xc901, 0x04 }, 69 { 0xc900, 0x73 }, 70 { 0xde03, 0x05 }, 71 { 0xdd0b, 0x0d }, 72 { 0xdd0a, 0xff }, 73 { 0xdd09, 0x0d }, 74 { 0xdd08, 0xff }, 75 { 0xc570, 0x08 }, 76 { 0xe803, 0xbe }, 77 { 0xc003, 0xc0 }, 78 { 0xc081, 0xfe }, 79 { 0xce31, 0x0d }, 80 { 0xce30, 0xae }, 81 { 0xce37, 0x0b }, 82 { 0xce36, 0xd2 }, 83 { 0xce39, 0x04 }, 84 { 0xce38, 0x80 }, 85 { 0xce3f, 0x00 }, 86 { 0xce3e, 0x00 }, 87 { 0xd470, 0x8b }, 88 { 0xd471, 0x18 }, 89 { 0xc019, 0x10 }, 90 { 0xd487, 0x3f }, 91 { 0xd486, 0xc3 }, 92 { 0x3fc2bfc7, 0x00 }, 93 { 0x3fc2bfc6, 0x00 }, 94 { 0x3fc2bfc5, 0x00 }, 95 { 0x3fc2bfc4, 0x01 }, 96 { 0x0000d486, 0x43 }, 97 { 0x1000db00, 0x02 }, 98 { 0x1000db01, 0x00 }, 99 { 0x1000db02, 0x11 }, 100 { 0x1000db03, 0x00 }, 101 { 0x1000db04, 0x00 }, 102 { 0x1000db05, 0x82 }, 103 { 0x1000db06, 0x04 }, 104 { 0x1000db07, 0xf1 }, 105 { 0x1000db08, 0x00 }, 106 { 0x1000db09, 0x00 }, 107 { 0x1000db0a, 0x40 }, 108 { 0x0000d540, 0x01 }, 109 { 0xd172, 0x2a }, 110 { 0xc5d6, 0x01 }, 111 { 0xd478, 0xff }, 112 }; 113 114 static const struct reg_sequence rt1320_vc_blind_write[] = { 115 { 0xc003, 0xe0 }, 116 { 0xe80a, 0x01 }, 117 { 0xc5c3, 0xf2 }, 118 { 0xc5c8, 0x03 }, 119 { 0xc057, 0x51 }, 120 { 0xc054, 0x35 }, 121 { 0xca05, 0xd6 }, 122 { 0xca07, 0x07 }, 123 { 0xca25, 0xd6 }, 124 { 0xca27, 0x07 }, 125 { 0xc604, 0x40 }, 126 { 0xc609, 0x40 }, 127 { 0xc046, 0xff }, 128 { 0xc045, 0xff }, 129 { 0xc044, 0xff }, 130 { 0xc043, 0xff }, 131 { 0xc042, 0xff }, 132 { 0xc041, 0x7f }, 133 { 0xc040, 0xff }, 134 { 0xcc10, 0x01 }, 135 { 0xc700, 0xf0 }, 136 { 0xc701, 0x13 }, 137 { 0xc901, 0x04 }, 138 { 0xc900, 0x73 }, 139 { 0xde03, 0x05 }, 140 { 0xdd0b, 0x0d }, 141 { 0xdd0a, 0xff }, 142 { 0xdd09, 0x0d }, 143 { 0xdd08, 0xff }, 144 { 0xc570, 0x08 }, 145 { 0xc086, 0x02 }, 146 { 0xc085, 0x7f }, 147 { 0xc084, 0x00 }, 148 { 0xc081, 0xfe }, 149 { 0xf084, 0x0f }, 150 { 0xf083, 0xff }, 151 { 0xf082, 0xff }, 152 { 0xf081, 0xff }, 153 { 0xf080, 0xff }, 154 { 0xe801, 0x01 }, 155 { 0xe802, 0xf8 }, 156 { 0xe803, 0xbe }, 157 { 0xc003, 0xc0 }, 158 { 0xd470, 0xec }, 159 { 0xd471, 0x3a }, 160 { 0xd474, 0x11 }, 161 { 0xd475, 0x32 }, 162 { 0xd478, 0xff }, 163 { 0xd479, 0x20 }, 164 { 0xd47a, 0x10 }, 165 { 0xd47c, 0xff }, 166 { 0xc019, 0x10 }, 167 { 0xd487, 0x0b }, 168 { 0xd487, 0x3b }, 169 { 0xd486, 0xc3 }, 170 { 0xc598, 0x04 }, 171 { 0xdb03, 0xf0 }, 172 { 0xdb09, 0x00 }, 173 { 0xdb08, 0x7a }, 174 { 0xdb19, 0x02 }, 175 { 0xdb07, 0x5a }, 176 { 0xdb05, 0x45 }, 177 { 0xd500, 0x00 }, 178 { 0xd500, 0x17 }, 179 { 0xd600, 0x01 }, 180 { 0xd601, 0x02 }, 181 { 0xd602, 0x03 }, 182 { 0xd603, 0x04 }, 183 { 0xd64c, 0x03 }, 184 { 0xd64d, 0x03 }, 185 { 0xd64e, 0x03 }, 186 { 0xd64f, 0x03 }, 187 { 0xd650, 0x03 }, 188 { 0xd651, 0x03 }, 189 { 0xd652, 0x03 }, 190 { 0xd610, 0x01 }, 191 { 0xd608, 0x03 }, 192 { 0xd609, 0x00 }, 193 { 0x3fc2bf83, 0x00 }, 194 { 0x3fc2bf82, 0x00 }, 195 { 0x3fc2bf81, 0x00 }, 196 { 0x3fc2bf80, 0x00 }, 197 { 0x3fc2bfc7, 0x00 }, 198 { 0x3fc2bfc6, 0x00 }, 199 { 0x3fc2bfc5, 0x00 }, 200 { 0x3fc2bfc4, 0x00 }, 201 { 0x3fc2bfc3, 0x00 }, 202 { 0x3fc2bfc2, 0x00 }, 203 { 0x3fc2bfc1, 0x00 }, 204 { 0x3fc2bfc0, 0x07 }, 205 { 0x1000cc46, 0x00 }, 206 { 0x0000d486, 0x43 }, 207 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00 }, 208 { 0x1000db00, 0x07 }, 209 { 0x1000db01, 0x00 }, 210 { 0x1000db02, 0x11 }, 211 { 0x1000db03, 0x00 }, 212 { 0x1000db04, 0x00 }, 213 { 0x1000db05, 0x82 }, 214 { 0x1000db06, 0x04 }, 215 { 0x1000db07, 0xf1 }, 216 { 0x1000db08, 0x00 }, 217 { 0x1000db09, 0x00 }, 218 { 0x1000db0a, 0x40 }, 219 { 0x1000db0b, 0x02 }, 220 { 0x1000db0c, 0xf2 }, 221 { 0x1000db0d, 0x00 }, 222 { 0x1000db0e, 0x00 }, 223 { 0x1000db0f, 0xe0 }, 224 { 0x1000db10, 0x00 }, 225 { 0x1000db11, 0x10 }, 226 { 0x1000db12, 0x00 }, 227 { 0x1000db13, 0x00 }, 228 { 0x1000db14, 0x45 }, 229 { 0x1000db15, 0x0d }, 230 { 0x1000db16, 0x01 }, 231 { 0x1000db17, 0x00 }, 232 { 0x1000db18, 0x00 }, 233 { 0x1000db19, 0xbf }, 234 { 0x1000db1a, 0x13 }, 235 { 0x1000db1b, 0x09 }, 236 { 0x1000db1c, 0x00 }, 237 { 0x1000db1d, 0x00 }, 238 { 0x1000db1e, 0x00 }, 239 { 0x1000db1f, 0x12 }, 240 { 0x1000db20, 0x09 }, 241 { 0x1000db21, 0x00 }, 242 { 0x1000db22, 0x00 }, 243 { 0x1000db23, 0x00 }, 244 { 0x0000d540, 0x21 }, 245 { 0xc01b, 0xfc }, 246 { 0xc5d1, 0x89 }, 247 { 0xc5d8, 0x0a }, 248 { 0xc5f7, 0x22 }, 249 { 0xc5f6, 0x22 }, 250 { 0xc065, 0xa5 }, 251 { 0xc06b, 0x0a }, 252 { 0xd172, 0x2a }, 253 { 0xc5d6, 0x01 }, 254 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 255 }; 256 257 static const struct reg_sequence rt1321_blind_write[] = { 258 { 0x0000c003, 0xf0 }, 259 { 0x0000c01b, 0xfc }, 260 { 0x0000c5c3, 0xf2 }, 261 { 0x0000c5c2, 0x00 }, 262 { 0x0000c5c1, 0x10 }, 263 { 0x0000c5c0, 0x04 }, 264 { 0x0000c5c7, 0x03 }, 265 { 0x0000c5c6, 0x10 }, 266 { 0x0000c526, 0x47 }, 267 { 0x0000c5c4, 0x12 }, 268 { 0x0000c5c5, 0x60 }, 269 { 0x0000c520, 0x10 }, 270 { 0x0000c521, 0x32 }, 271 { 0x0000c5c7, 0x00 }, 272 { 0x0000c5c8, 0x03 }, 273 { 0x0000c5d3, 0x08 }, 274 { 0x0000c5d2, 0x0a }, 275 { 0x0000c5d1, 0x49 }, 276 { 0x0000c5d0, 0x0f }, 277 { 0x0000c580, 0x10 }, 278 { 0x0000c581, 0x32 }, 279 { 0x0000c582, 0x01 }, 280 { 0x0000cb00, 0x03 }, 281 { 0x0000cb02, 0x52 }, 282 { 0x0000cb04, 0x80 }, 283 { 0x0000cb0b, 0x01 }, 284 { 0x0000c682, 0x60 }, 285 { 0x0000c019, 0x10 }, 286 { 0x0000c5f0, 0x01 }, 287 { 0x0000c5f7, 0x22 }, 288 { 0x0000c5f6, 0x22 }, 289 { 0x0000c057, 0x51 }, 290 { 0x0000c054, 0x55 }, 291 { 0x0000c053, 0x55 }, 292 { 0x0000c052, 0x55 }, 293 { 0x0000c051, 0x01 }, 294 { 0x0000c050, 0x15 }, 295 { 0x0000c060, 0x99 }, 296 { 0x0000c030, 0x55 }, 297 { 0x0000c061, 0x55 }, 298 { 0x0000c063, 0x55 }, 299 { 0x0000c065, 0xa5 }, 300 { 0x0000c06b, 0x0a }, 301 { 0x0000ca05, 0xd6 }, 302 { 0x0000ca07, 0x07 }, 303 { 0x0000ca25, 0xd6 }, 304 { 0x0000ca27, 0x07 }, 305 { 0x0000cd00, 0x05 }, 306 { 0x0000c604, 0x40 }, 307 { 0x0000c609, 0x40 }, 308 { 0x0000c046, 0xf7 }, 309 { 0x0000c045, 0xff }, 310 { 0x0000c044, 0xff }, 311 { 0x0000c043, 0xff }, 312 { 0x0000c042, 0xff }, 313 { 0x0000c041, 0xff }, 314 { 0x0000c040, 0xff }, 315 { 0x0000c049, 0xff }, 316 { 0x0000c028, 0x3f }, 317 { 0x0000c020, 0x3f }, 318 { 0x0000c032, 0x13 }, 319 { 0x0000c033, 0x01 }, 320 { 0x0000cc10, 0x01 }, 321 { 0x0000dc20, 0x03 }, 322 { 0x0000de03, 0x05 }, 323 { 0x0000dc00, 0x00 }, 324 { 0x0000c700, 0xf0 }, 325 { 0x0000c701, 0x13 }, 326 { 0x0000c900, 0xc3 }, 327 { 0x0000c570, 0x08 }, 328 { 0x0000c086, 0x02 }, 329 { 0x0000c085, 0x7f }, 330 { 0x0000c084, 0x00 }, 331 { 0x0000c081, 0xff }, 332 { 0x0000f084, 0x0f }, 333 { 0x0000f083, 0xff }, 334 { 0x0000f082, 0xff }, 335 { 0x0000f081, 0xff }, 336 { 0x0000f080, 0xff }, 337 { 0x20003003, 0x3f }, 338 { 0x20005818, 0x81 }, 339 { 0x20009018, 0x81 }, 340 { 0x2000301c, 0x81 }, 341 { 0x0000c003, 0xc0 }, 342 { 0x0000c047, 0x80 }, 343 { 0x0000d541, 0x80 }, 344 { 0x0000d487, 0x0b }, 345 { 0x0000d487, 0x3b }, 346 { 0x0000d486, 0xc3 }, 347 { 0x0000d470, 0x89 }, 348 { 0x0000d471, 0x3a }, 349 { 0x0000d472, 0x1d }, 350 { 0x0000d478, 0xff }, 351 { 0x0000d479, 0x20 }, 352 { 0x0000d47a, 0x10 }, 353 { 0x0000d73c, 0xb7 }, 354 { 0x0000d73d, 0xd7 }, 355 { 0x0000d73e, 0x00 }, 356 { 0x0000d73f, 0x10 }, 357 { 0x1000cd56, 0x00 }, 358 { 0x3fc2dfc3, 0x00 }, 359 { 0x3fc2dfc2, 0x00 }, 360 { 0x3fc2dfc1, 0x00 }, 361 { 0x3fc2dfc0, 0x07 }, 362 { 0x3fc2dfc7, 0x00 }, 363 { 0x3fc2dfc6, 0x00 }, 364 { 0x3fc2dfc5, 0x00 }, 365 { 0x3fc2dfc4, 0x01 }, 366 { 0x3fc2df83, 0x00 }, 367 { 0x3fc2df82, 0x00 }, 368 { 0x3fc2df81, 0x00 }, 369 { 0x3fc2df80, 0x00 }, 370 { 0x0000d541, 0x40 }, 371 { 0x0000d486, 0x43 }, 372 { 0x1000db00, 0x03 }, 373 { 0x1000db01, 0x00 }, 374 { 0x1000db02, 0x10 }, 375 { 0x1000db03, 0x00 }, 376 { 0x1000db04, 0x00 }, 377 { 0x1000db05, 0x45 }, 378 { 0x1000db06, 0x12 }, 379 { 0x1000db07, 0x09 }, 380 { 0x1000db08, 0x00 }, 381 { 0x1000db09, 0x00 }, 382 { 0x1000db0a, 0x00 }, 383 { 0x1000db0b, 0x13 }, 384 { 0x1000db0c, 0x09 }, 385 { 0x1000db0d, 0x00 }, 386 { 0x1000db0e, 0x00 }, 387 { 0x1000db0f, 0x00 }, 388 { 0x0000d540, 0x21 }, 389 { 0x41000189, 0x00 }, 390 { 0x4100018a, 0x00 }, 391 { 0x41001988, 0x00 }, 392 { 0x41081400, 0x09 }, 393 { 0x40801508, 0x03 }, 394 { 0x40801588, 0x03 }, 395 { 0x40801809, 0x00 }, 396 { 0x4080180a, 0x00 }, 397 { 0x4080180b, 0x00 }, 398 { 0x4080180c, 0x00 }, 399 { 0x40801b09, 0x00 }, 400 { 0x40801b0a, 0x00 }, 401 { 0x40801b0b, 0x00 }, 402 { 0x40801b0c, 0x00 }, 403 { 0x0000d714, 0x17 }, 404 { 0x20009012, 0x00 }, 405 { 0x0000dd0b, 0x0d }, 406 { 0x0000dd0a, 0xff }, 407 { 0x0000dd09, 0x0d }, 408 { 0x0000dd08, 0xff }, 409 { 0x0000d172, 0x2a }, 410 { 0x41001988, 0x03 }, 411 }; 412 413 static const struct reg_sequence rt1321_va1_blind_write[] = { 414 { 0x0000c003, 0xf0 }, 415 { 0x0000c01b, 0xfc }, 416 { 0x0000c5c3, 0xf2 }, 417 { 0x0000c5c2, 0x00 }, 418 { 0x0000c5c1, 0x10 }, 419 { 0x0000c5c0, 0x04 }, 420 { 0x0000c5c7, 0x03 }, 421 { 0x0000c5c6, 0x10 }, 422 { 0x0000c526, 0x47 }, 423 { 0x0000c5c4, 0x12 }, 424 { 0x0000c5c5, 0x60 }, 425 { 0x0000c520, 0x10 }, 426 { 0x0000c521, 0x32 }, 427 { 0x0000c5c7, 0x00 }, 428 { 0x0000c5c8, 0x03 }, 429 { 0x0000c5d3, 0x08 }, 430 { 0x0000c5d2, 0x0a }, 431 { 0x0000c5d1, 0x49 }, 432 { 0x0000c5d0, 0x0f }, 433 { 0x0000c580, 0x10 }, 434 { 0x0000c581, 0x32 }, 435 { 0x0000c582, 0x01 }, 436 { 0x0000c682, 0x60 }, 437 { 0x0000c019, 0x10 }, 438 { 0x0000c5f0, 0x01 }, 439 { 0x0000c5f7, 0x22 }, 440 { 0x0000c5f6, 0x22 }, 441 { 0x0000c057, 0x51 }, 442 { 0x0000c054, 0x55 }, 443 { 0x0000c053, 0x55 }, 444 { 0x0000c052, 0x55 }, 445 { 0x0000c051, 0x01 }, 446 { 0x0000c050, 0x15 }, 447 { 0x0000c060, 0x99 }, 448 { 0x0000c030, 0x55 }, 449 { 0x0000c061, 0x55 }, 450 { 0x0000c063, 0x55 }, 451 { 0x0000c065, 0xa5 }, 452 { 0x0000c06b, 0x0a }, 453 { 0x0000ca05, 0xd6 }, 454 { 0x0000ca06, 0x11 }, 455 { 0x0000ca07, 0x1e }, 456 { 0x0000ca25, 0xd6 }, 457 { 0x0000ca26, 0x11 }, 458 { 0x0000ca27, 0x1e }, 459 { 0x0000cd00, 0x05 }, 460 { 0x0000cd81, 0x49 }, 461 { 0x0000cd82, 0x49 }, 462 { 0x0000c604, 0x40 }, 463 { 0x0000c609, 0x40 }, 464 { 0x0000c046, 0xf7 }, 465 { 0x0000c045, 0xff }, 466 { 0x0000c044, 0xff }, 467 { 0x0000c043, 0xff }, 468 { 0x0000c042, 0xff }, 469 { 0x0000c041, 0xff }, 470 { 0x0000c040, 0xff }, 471 { 0x0000c049, 0xff }, 472 { 0x0000c028, 0x3f }, 473 { 0x0000c020, 0x3f }, 474 { 0x0000c032, 0x13 }, 475 { 0x0000c033, 0x01 }, 476 { 0x0000cc10, 0x01 }, 477 { 0x0000dc20, 0x03 }, 478 { 0x0000de03, 0x05 }, 479 { 0x0000dc00, 0x00 }, 480 { 0x0000c700, 0xf0 }, 481 { 0x0000c701, 0x13 }, 482 { 0x0000c900, 0xc3 }, 483 { 0x0000c570, 0x08 }, 484 { 0x0000c086, 0x02 }, 485 { 0x0000c085, 0x7f }, 486 { 0x0000c084, 0x00 }, 487 { 0x0000c081, 0xff }, 488 { 0x0000f084, 0x0f }, 489 { 0x0000f083, 0xff }, 490 { 0x0000f082, 0xff }, 491 { 0x0000f081, 0xff }, 492 { 0x0000f080, 0xff }, 493 { 0x20003003, 0x3f }, 494 { 0x20005818, 0x81 }, 495 { 0x20009018, 0x81 }, 496 { 0x2000301c, 0x81 }, 497 { 0x0000c003, 0xc0 }, 498 { 0x0000c047, 0x80 }, 499 { 0x0000d541, 0x80 }, 500 { 0x0000d487, 0x0b }, 501 { 0x0000d487, 0x3b }, 502 { 0x0000d486, 0xc3 }, 503 { 0x0000d470, 0x89 }, 504 { 0x0000d471, 0x3a }, 505 { 0x0000d472, 0x3d }, 506 { 0x0000d474, 0x11 }, 507 { 0x0000d475, 0x32 }, 508 { 0x0000d476, 0x64 }, 509 { 0x0000d477, 0x10 }, 510 { 0x0000d478, 0xff }, 511 { 0x0000d479, 0x20 }, 512 { 0x0000d47a, 0x10 }, 513 { 0x0000d73c, 0xb7 }, 514 { 0x0000d73d, 0xd7 }, 515 { 0x0000d73e, 0x00 }, 516 { 0x0000d73f, 0x10 }, 517 { 0x1000cd56, 0x00 }, 518 { 0x3fc2dfc0, 0x03 }, 519 { 0x3fc2dfc1, 0x00 }, 520 { 0x3fc2dfc2, 0x00 }, 521 { 0x3fc2dfc3, 0x00 }, 522 { 0x3fc2dfc4, 0x01 }, 523 { 0x3fc2dfc5, 0x00 }, 524 { 0x3fc2dfc6, 0x00 }, 525 { 0x3fc2dfc7, 0x00 }, 526 { 0x3fc2df80, 0x00 }, 527 { 0x3fc2df81, 0x00 }, 528 { 0x3fc2df82, 0x00 }, 529 { 0x3fc2df83, 0x00 }, 530 { 0x0000d541, 0x40 }, 531 { 0x0000d486, 0x43 }, 532 { 0x1000db00, 0x04 }, 533 { 0x1000db01, 0x00 }, 534 { 0x1000db02, 0x10 }, 535 { 0x1000db03, 0x00 }, 536 { 0x1000db04, 0x00 }, 537 { 0x1000db05, 0x45 }, 538 { 0x1000db06, 0x0d }, 539 { 0x1000db07, 0x01 }, 540 { 0x1000db08, 0x00 }, 541 { 0x1000db09, 0x00 }, 542 { 0x1000db0a, 0xbf }, 543 { 0x1000db0b, 0x0b }, 544 { 0x1000db0c, 0x11 }, 545 { 0x1000db0d, 0x00 }, 546 { 0x1000db0e, 0x00 }, 547 { 0x1000db0f, 0x00 }, 548 { 0x1000db10, 0x2c }, 549 { 0x1000db11, 0xfa }, 550 { 0x1000db12, 0x00 }, 551 { 0x1000db13, 0x00 }, 552 { 0x1000db14, 0x09 }, 553 { 0x0000d540, 0x21 }, 554 { 0x0000c570, 0x08 }, 555 { 0x0000d714, 0x17 }, 556 { 0x0000c5c3, 0xf2 }, 557 { 0x0000c5c8, 0x03 }, 558 { 0x20009012, 0x00 }, 559 { 0x0000dd08, 0x17 }, 560 { 0x0000dd09, 0x0e }, 561 { 0x0000dd0a, 0x17 }, 562 { 0x0000dd0b, 0x0e }, 563 { 0x0000c570, 0x08 }, 564 { 0x0000d471, 0x3a }, 565 { 0x0000db00, 0x00 }, 566 { 0x0000db01, 0x00 }, 567 { 0x0000db02, 0x73 }, 568 { 0x0000db03, 0x00 }, 569 { 0x0000db04, 0x00 }, 570 { 0x0000db05, 0x00 }, 571 { 0x0000db06, 0x00 }, 572 { 0x0000db07, 0x00 }, 573 { 0x0000db08, 0x7f }, 574 { 0x0000db09, 0x00 }, 575 { 0x0000db1a, 0x00 }, 576 { 0x0000db1b, 0x00 }, 577 { 0x0000db19, 0x00 }, 578 }; 579 580 static const struct reg_sequence rt1321_va2_blind_write[] = { 581 { 0x0000c003, 0xf0 }, 582 { 0x0000c01b, 0xfc }, 583 { 0x0000c5c3, 0xf2 }, 584 { 0x0000c5c2, 0x00 }, 585 { 0x0000c5c1, 0x10 }, 586 { 0x0000c5c0, 0x04 }, 587 { 0x0000c5c7, 0x03 }, 588 { 0x0000c5c6, 0x10 }, 589 { 0x0000c526, 0x47 }, 590 { 0x0000c5c4, 0x12 }, 591 { 0x0000c5c5, 0x60 }, 592 { 0x0000c520, 0x10 }, 593 { 0x0000c521, 0x32 }, 594 { 0x0000c5c7, 0x00 }, 595 { 0x0000c5c8, 0x03 }, 596 { 0x0000c5d3, 0x08 }, 597 { 0x0000c5d2, 0x0a }, 598 { 0x0000c5d1, 0x49 }, 599 { 0x0000c5d0, 0x0f }, 600 { 0x0000c580, 0x10 }, 601 { 0x0000c581, 0x32 }, 602 { 0x0000c582, 0x01 }, 603 { 0x0000c682, 0x60 }, 604 { 0x0000c019, 0x10 }, 605 { 0x0000c5f0, 0x01 }, 606 { 0x0000c5f7, 0x22 }, 607 { 0x0000c5f6, 0x22 }, 608 { 0x0000c057, 0x51 }, 609 { 0x0000c054, 0x55 }, 610 { 0x0000c053, 0x55 }, 611 { 0x0000c052, 0x55 }, 612 { 0x0000c051, 0x01 }, 613 { 0x0000c050, 0x15 }, 614 { 0x0000c060, 0x99 }, 615 { 0x0000c030, 0x55 }, 616 { 0x0000c061, 0x55 }, 617 { 0x0000c063, 0x55 }, 618 { 0x0000c065, 0xa5 }, 619 { 0x0000c06b, 0x0a }, 620 { 0x0000ca05, 0xd6 }, 621 { 0x0000ca06, 0x11 }, 622 { 0x0000ca07, 0x1e }, 623 { 0x0000ca25, 0xd6 }, 624 { 0x0000ca26, 0x11 }, 625 { 0x0000ca27, 0x1e }, 626 { 0x0000cd00, 0x05 }, 627 { 0x0000cd81, 0x49 }, 628 { 0x0000cd82, 0x49 }, 629 { 0x0000c604, 0x40 }, 630 { 0x0000c609, 0x40 }, 631 { 0x0000c046, 0xf7 }, 632 { 0x0000c045, 0xff }, 633 { 0x0000c044, 0xff }, 634 { 0x0000c043, 0xff }, 635 { 0x0000c042, 0xff }, 636 { 0x0000c041, 0xff }, 637 { 0x0000c040, 0xff }, 638 { 0x0000c049, 0xff }, 639 { 0x0000c028, 0x3f }, 640 { 0x0000c020, 0x3f }, 641 { 0x0000c032, 0x13 }, 642 { 0x0000c033, 0x01 }, 643 { 0x0000cc10, 0x01 }, 644 { 0x0000dc20, 0x03 }, 645 { 0x0000de03, 0x05 }, 646 { 0x0000dc00, 0x00 }, 647 { 0x0000c700, 0xf0 }, 648 { 0x0000c701, 0x13 }, 649 { 0x0000c900, 0xc3 }, 650 { 0x0000c570, 0x08 }, 651 { 0x0000c086, 0x02 }, 652 { 0x0000c085, 0x7f }, 653 { 0x0000c084, 0x00 }, 654 { 0x0000c081, 0xff }, 655 { 0x0000f084, 0x0f }, 656 { 0x0000f083, 0xff }, 657 { 0x0000f082, 0xff }, 658 { 0x0000f081, 0xff }, 659 { 0x0000f080, 0xff }, 660 { 0x20003003, 0x3f }, 661 { 0x20005818, 0x81 }, 662 { 0x20009018, 0x81 }, 663 { 0x2000301c, 0x81 }, 664 { 0x0000c003, 0xc0 }, 665 { 0x0000c047, 0x80 }, 666 { 0x0000d541, 0x80 }, 667 { 0x0000d487, 0x0b }, 668 { 0x0000d487, 0x3b }, 669 { 0x0000d486, 0xc3 }, 670 { 0x0000d470, 0x89 }, 671 { 0x0000d471, 0x3a }, 672 { 0x0000d472, 0x3d }, 673 { 0x0000d474, 0x11 }, 674 { 0x0000d475, 0x32 }, 675 { 0x0000d476, 0x64 }, 676 { 0x0000d477, 0x10 }, 677 { 0x0000d478, 0xff }, 678 { 0x0000d479, 0x20 }, 679 { 0x0000d47a, 0x10 }, 680 { 0x10008000, 0x67 }, 681 { 0x10008001, 0x80 }, 682 { 0x10008002, 0x00 }, 683 { 0x10008003, 0x00 }, 684 { 0x1000cd56, 0x00 }, 685 { 0x0000d486, 0x43 }, 686 { 0x3fc2dfc3, 0x00 }, 687 { 0x3fc2dfc2, 0x00 }, 688 { 0x3fc2dfc1, 0x00 }, 689 { 0x3fc2dfc0, 0x03 }, 690 { 0x3fc2dfc7, 0x00 }, 691 { 0x3fc2dfc6, 0x00 }, 692 { 0x3fc2dfc5, 0x00 }, 693 { 0x3fc2dfc4, 0x01 }, 694 { 0x3fc2dfa3, 0x00 }, 695 { 0x3fc2dfa2, 0x00 }, 696 { 0x3fc2dfa1, 0x00 }, 697 { 0x3fc2dfa0, 0x00 }, 698 { 0x3fc2df80, 0x10 }, 699 { 0x3fc2df81, 0x20 }, 700 { 0x3fc2df82, 0x00 }, 701 { 0x3fc2df83, 0x00 }, 702 { 0x3fc2df84, 0x50 }, 703 { 0x3fc2df85, 0x19 }, 704 { 0x3fc2df86, 0x00 }, 705 { 0x3fc2df87, 0x00 }, 706 { 0x3fc2df88, 0x52 }, 707 { 0x3fc2df89, 0x23 }, 708 { 0x3fc2df8a, 0x00 }, 709 { 0x3fc2df8b, 0x00 }, 710 { 0x3fc2df8c, 0xe0 }, 711 { 0x3fc2df8d, 0x2e }, 712 { 0x3fc2df8e, 0x00 }, 713 { 0x3fc2df8f, 0x00 }, 714 { 0x3fc2df90, 0xe0 }, 715 { 0x3fc2df91, 0x2e }, 716 { 0x3fc2df92, 0x00 }, 717 { 0x3fc2df93, 0x00 }, 718 { 0x3fc2df94, 0x01 }, 719 { 0x3fc2df95, 0x08 }, 720 { 0x3fc2df96, 0x00 }, 721 { 0x3fc2df97, 0x00 }, 722 { 0x3fc2df40, 0x80 }, 723 { 0x3fc2df41, 0xbb }, 724 { 0x3fc2df42, 0x00 }, 725 { 0x3fc2df43, 0x00 }, 726 { 0x3fc2df44, 0xc0 }, 727 { 0x3fc2df45, 0x99 }, 728 { 0x3fc2df46, 0x01 }, 729 { 0x3fc2df47, 0x00 }, 730 { 0x3fc2df48, 0x00 }, 731 { 0x3fc2df49, 0x00 }, 732 { 0x3fc2df4a, 0x00 }, 733 { 0x3fc2df4b, 0x00 }, 734 { 0x3fc2df4c, 0x00 }, 735 { 0x3fc2df4d, 0x00 }, 736 { 0x3fc2df4e, 0x00 }, 737 { 0x3fc2df4f, 0x00 }, 738 { 0x3fc2df50, 0x01 }, 739 { 0x3fc2df51, 0x00 }, 740 { 0x3fc2df52, 0x00 }, 741 { 0x3fc2df53, 0x00 }, 742 { 0x3fc2df54, 0x01 }, 743 { 0x3fc2df55, 0x00 }, 744 { 0x3fc2df56, 0x00 }, 745 { 0x3fc2df57, 0x00 }, 746 { 0x3fc2df58, 0x00 }, 747 { 0x3fc2df59, 0x00 }, 748 { 0x3fc2df5a, 0x00 }, 749 { 0x3fc2df5b, 0x00 }, 750 { 0x3fc2df5c, 0x01 }, 751 { 0x3fc2df5d, 0x00 }, 752 { 0x3fc2df5e, 0x00 }, 753 { 0x3fc2df5f, 0x00 }, 754 { 0x3fc2df60, 0x00 }, 755 { 0x3fc2df61, 0x00 }, 756 { 0x3fc2df62, 0x00 }, 757 { 0x3fc2df63, 0x00 }, 758 { 0x3fc2df64, 0x00 }, 759 { 0x3fc2df65, 0x00 }, 760 { 0x3fc2df66, 0x00 }, 761 { 0x3fc2df67, 0x10 }, 762 { 0x3fc2df68, 0x01 }, 763 { 0x3fc2df69, 0x00 }, 764 { 0x3fc2df6a, 0x00 }, 765 { 0x3fc2df6b, 0x00 }, 766 { 0x3fc2df6c, 0x01 }, 767 { 0x3fc2df6d, 0x00 }, 768 { 0x3fc2df6e, 0x00 }, 769 { 0x3fc2df6f, 0x00 }, 770 { 0x3fc2df70, 0x04 }, 771 { 0x3fc2df71, 0x00 }, 772 { 0x3fc2df72, 0x00 }, 773 { 0x3fc2df73, 0x00 }, 774 { 0x3fc2df74, 0x01 }, 775 { 0x3fc2df75, 0x00 }, 776 { 0x3fc2df76, 0x00 }, 777 { 0x3fc2df77, 0x00 }, 778 { 0x1000db00, 0x04 }, 779 { 0x1000db01, 0x00 }, 780 { 0x1000db02, 0x10 }, 781 { 0x1000db03, 0x00 }, 782 { 0x1000db04, 0x00 }, 783 { 0x1000db05, 0x45 }, 784 { 0x1000db06, 0x0d }, 785 { 0x1000db07, 0x01 }, 786 { 0x1000db08, 0x00 }, 787 { 0x1000db09, 0x00 }, 788 { 0x1000db0a, 0xbf }, 789 { 0x1000db0b, 0x0b }, 790 { 0x1000db0c, 0x11 }, 791 { 0x1000db0d, 0x00 }, 792 { 0x1000db0e, 0x00 }, 793 { 0x1000db0f, 0x00 }, 794 { 0x1000db10, 0x2c }, 795 { 0x1000db11, 0xfa }, 796 { 0x1000db12, 0x00 }, 797 { 0x1000db13, 0x00 }, 798 { 0x1000db14, 0x09 }, 799 { 0x0000d540, 0x21 }, 800 { 0x0000d714, 0x17 }, 801 { 0x0000dd0b, 0x0d }, 802 { 0x0000dd0a, 0xff }, 803 { 0x0000dd09, 0x0d }, 804 { 0x0000dd08, 0xff }, 805 { 0x0000c5fb, 0x12 }, 806 { 0x0000c570, 0x08 }, 807 }; 808 809 static const struct reg_default rt1320_reg_defaults[] = { 810 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 811 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 }, 812 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 }, 813 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 }, 814 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 }, 815 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 }, 816 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x0b }, 817 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), 0x03 }, 818 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 }, 819 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 }, 820 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 821 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 822 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0x00 }, 823 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 }, 824 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), 0x03 }, 825 }; 826 827 static const struct reg_default rt1320_mbq_defaults[] = { 828 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 }, 829 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 }, 830 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 }, 831 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 }, 832 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 }, 833 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 }, 834 }; 835 836 static bool rt1320_readable_register(struct device *dev, unsigned int reg) 837 { 838 switch (reg) { 839 case 0x004d: 840 case 0xc000 ... 0xc086: 841 case 0xc400 ... 0xc409: 842 case 0xc480 ... 0xc48f: 843 case 0xc4c0 ... 0xc4c4: 844 case 0xc4e0 ... 0xc4e7: 845 case 0xc500: 846 case 0xc560 ... 0xc56b: 847 case 0xc570: 848 case 0xc580 ... 0xc59a: 849 case 0xc5b0 ... 0xc60f: 850 case 0xc640 ... 0xc64f: 851 case 0xc670: 852 case 0xc680 ... 0xc683: 853 case 0xc700 ... 0xc76f: 854 case 0xc800 ... 0xc801: 855 case 0xc820: 856 case 0xc900 ... 0xc901: 857 case 0xc920 ... 0xc921: 858 case 0xca00 ... 0xca07: 859 case 0xca20 ... 0xca27: 860 case 0xca40 ... 0xca4b: 861 case 0xca60 ... 0xca68: 862 case 0xca80 ... 0xca88: 863 case 0xcb00 ... 0xcb0c: 864 case 0xcc00 ... 0xcc12: 865 case 0xcc80 ... 0xcc81: 866 case 0xcd00: 867 case 0xcd80 ... 0xcd82: 868 case 0xce00 ... 0xce4d: 869 case 0xcf00 ... 0xcf25: 870 case 0xd000 ... 0xd0ff: 871 case 0xd100 ... 0xd1ff: 872 case 0xd200 ... 0xd2ff: 873 case 0xd300 ... 0xd3ff: 874 case 0xd400 ... 0xd403: 875 case 0xd410 ... 0xd417: 876 case 0xd470 ... 0xd497: 877 case 0xd4dc ... 0xd50f: 878 case 0xd520 ... 0xd543: 879 case 0xd560 ... 0xd5ef: 880 case 0xd600 ... 0xd663: 881 case 0xda00 ... 0xda6e: 882 case 0xda80 ... 0xda9e: 883 case 0xdb00 ... 0xdb7f: 884 case 0xdc00: 885 case 0xdc20 ... 0xdc21: 886 case 0xdd00 ... 0xdd17: 887 case 0xde00 ... 0xde09: 888 case 0xdf00 ... 0xdf1b: 889 case 0xe000 ... 0xe847: 890 case 0xf01e: 891 case 0xf717 ... 0xf719: 892 case 0xf720 ... 0xf723: 893 case 0x10000000 ... 0x10008fff: 894 case 0x1000c000 ... 0x1000cfff: 895 case 0x1000d800 ... 0x1000dfff: 896 case 0x1000f008: 897 case 0x1000f021: 898 case 0x20003000 ... 0x2000300f: 899 case 0x2000301c: 900 case 0x20003040 ... 0x20003059: 901 case 0x20005800 ... 0x2000580f: 902 case 0x20005818: 903 case 0x20005840 ... 0x20005859: 904 case 0x20009000 ... 0x2000900f: 905 case 0x20009018: 906 case 0x20009040 ... 0x20009059: 907 case 0x3fc000c0 ... 0x3fc2dfc8: 908 case 0x3fe00000 ... 0x3fe36fff: 909 /* 0x40801508/0x40801809/0x4080180a/0x40801909/0x4080190a */ 910 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): 911 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01): 912 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_02): 913 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_01): 914 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_02): 915 /* 0x40880900/0x40880980 */ 916 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 917 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 918 /* 0x40881500 */ 919 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): 920 /* 0x41000189/0x4100018a */ 921 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01): 922 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02): 923 /* 0x41001388 */ 924 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): 925 /* 0x41001988 */ 926 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): 927 /* 0x41080000 */ 928 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0): 929 /* 0x41080200 */ 930 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0): 931 /* 0x41080900 */ 932 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 933 /* 0x41080980 */ 934 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 935 /* 0x41081080 */ 936 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 937 /* 0x41081480/0x41081488 */ 938 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0): 939 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0): 940 /* 0x41081980 */ 941 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): 942 return true; 943 default: 944 return false; 945 } 946 } 947 948 static bool rt1320_volatile_register(struct device *dev, unsigned int reg) 949 { 950 switch (reg) { 951 case 0x004d: 952 case 0xc000: 953 case 0xc003: 954 case 0xc081: 955 case 0xc402 ... 0xc406: 956 case 0xc48c ... 0xc48f: 957 case 0xc560: 958 case 0xc5b5 ... 0xc5b7: 959 case 0xc5c3: 960 case 0xc5c8: 961 case 0xc5fc ... 0xc5ff: 962 case 0xc680 ... 0xc683: 963 case 0xc820: 964 case 0xc900: 965 case 0xc920: 966 case 0xca42: 967 case 0xca62: 968 case 0xca82: 969 case 0xcd00: 970 case 0xce03: 971 case 0xce10: 972 case 0xce14 ... 0xce17: 973 case 0xce44 ... 0xce49: 974 case 0xce4c ... 0xce4d: 975 case 0xcf0c: 976 case 0xcf10 ... 0xcf25: 977 case 0xd486 ... 0xd487: 978 case 0xd4e5 ... 0xd4e6: 979 case 0xd4e8 ... 0xd4ff: 980 case 0xd530: 981 case 0xd540 ... 0xd541: 982 case 0xd543: 983 case 0xdb58 ... 0xdb5f: 984 case 0xdb60 ... 0xdb63: 985 case 0xdb68 ... 0xdb69: 986 case 0xdb6d: 987 case 0xdb70 ... 0xdb71: 988 case 0xdb76: 989 case 0xdb7a: 990 case 0xdb7c ... 0xdb7f: 991 case 0xdd0c ... 0xdd13: 992 case 0xde02: 993 case 0xdf14 ... 0xdf1b: 994 case 0xe80b: 995 case 0xe83c ... 0xe847: 996 case 0xf01e: 997 case 0xf717 ... 0xf719: 998 case 0xf720 ... 0xf723: 999 case 0x10000000 ... 0x10008fff: 1000 case 0x1000c000 ... 0x1000cfff: 1001 case 0x1000d800 ... 0x1000dfff: 1002 case 0x1000f008: 1003 case 0x1000f021: 1004 case 0x2000300e ... 0x2000300f: 1005 case 0x2000301c: 1006 case 0x20003040 ... 0x20003059: 1007 case 0x2000580e ... 0x2000580f: 1008 case 0x20005818: 1009 case 0x20005840 ... 0x20005859: 1010 case 0x2000900e ... 0x2000900f: 1011 case 0x20009018: 1012 case 0x20009040 ... 0x20009059: 1013 case 0x3fc2ab80 ... 0x3fc2ac4c: 1014 case 0x3fc2b780: 1015 case 0x3fc2bf80 ... 0x3fc2bf83: 1016 case 0x3fc2bfc0 ... 0x3fc2bfc8: 1017 case 0x3fc2d300 ... 0x3fc2d3cc: 1018 case 0x3fc2dfc0 ... 0x3fc2dfc8: 1019 case 0x3fe2e000 ... 0x3fe2e003: 1020 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): 1021 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0): 1022 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0): 1023 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0): 1024 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): 1025 return true; 1026 default: 1027 return false; 1028 } 1029 } 1030 1031 static bool rt1320_mbq_readable_register(struct device *dev, unsigned int reg) 1032 { 1033 switch (reg) { 1034 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01): 1035 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_02): 1036 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01): 1037 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_02): 1038 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01): 1039 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02): 1040 return true; 1041 default: 1042 return false; 1043 } 1044 } 1045 1046 static const struct regmap_config rt1320_sdw_regmap = { 1047 .reg_bits = 32, 1048 .val_bits = 8, 1049 .readable_reg = rt1320_readable_register, 1050 .volatile_reg = rt1320_volatile_register, 1051 .max_register = 0x41081980, 1052 .reg_defaults = rt1320_reg_defaults, 1053 .num_reg_defaults = ARRAY_SIZE(rt1320_reg_defaults), 1054 .cache_type = REGCACHE_MAPLE, 1055 .use_single_read = true, 1056 .use_single_write = true, 1057 }; 1058 1059 static const struct regmap_config rt1320_mbq_regmap = { 1060 .name = "sdw-mbq", 1061 .reg_bits = 32, 1062 .val_bits = 16, 1063 .readable_reg = rt1320_mbq_readable_register, 1064 .max_register = 0x41000192, 1065 .reg_defaults = rt1320_mbq_defaults, 1066 .num_reg_defaults = ARRAY_SIZE(rt1320_mbq_defaults), 1067 .cache_type = REGCACHE_MAPLE, 1068 .use_single_read = true, 1069 .use_single_write = true, 1070 }; 1071 1072 static int rt1320_read_prop(struct sdw_slave *slave) 1073 { 1074 struct sdw_slave_prop *prop = &slave->prop; 1075 int nval; 1076 int i, j; 1077 u32 bit; 1078 unsigned long addr; 1079 struct sdw_dpn_prop *dpn; 1080 1081 /* 1082 * Due to support the multi-lane, we call 'sdw_slave_read_prop' to get the lane mapping 1083 */ 1084 sdw_slave_read_prop(slave); 1085 1086 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; 1087 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY; 1088 1089 prop->paging_support = true; 1090 prop->lane_control_support = true; 1091 1092 /* first we need to allocate memory for set bits in port lists */ 1093 prop->source_ports = BIT(4) | BIT(8) | BIT(10); 1094 prop->sink_ports = BIT(1); 1095 1096 nval = hweight32(prop->source_ports); 1097 prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval, 1098 sizeof(*prop->src_dpn_prop), GFP_KERNEL); 1099 if (!prop->src_dpn_prop) 1100 return -ENOMEM; 1101 1102 i = 0; 1103 dpn = prop->src_dpn_prop; 1104 addr = prop->source_ports; 1105 for_each_set_bit(bit, &addr, 32) { 1106 dpn[i].num = bit; 1107 dpn[i].type = SDW_DPN_FULL; 1108 dpn[i].simple_ch_prep_sm = true; 1109 dpn[i].ch_prep_timeout = 10; 1110 i++; 1111 } 1112 1113 /* do this again for sink now */ 1114 nval = hweight32(prop->sink_ports); 1115 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval, 1116 sizeof(*prop->sink_dpn_prop), GFP_KERNEL); 1117 if (!prop->sink_dpn_prop) 1118 return -ENOMEM; 1119 1120 j = 0; 1121 dpn = prop->sink_dpn_prop; 1122 addr = prop->sink_ports; 1123 for_each_set_bit(bit, &addr, 32) { 1124 dpn[j].num = bit; 1125 dpn[j].type = SDW_DPN_FULL; 1126 dpn[j].simple_ch_prep_sm = true; 1127 dpn[j].ch_prep_timeout = 10; 1128 j++; 1129 } 1130 1131 prop->dp0_prop = devm_kzalloc(&slave->dev, sizeof(*prop->dp0_prop), GFP_KERNEL); 1132 if (!prop->dp0_prop) 1133 return -ENOMEM; 1134 1135 prop->dp0_prop->simple_ch_prep_sm = true; 1136 prop->dp0_prop->ch_prep_timeout = 10; 1137 1138 /* set the timeout values */ 1139 prop->clk_stop_timeout = 64; 1140 1141 /* BIOS may set wake_capable. Make sure it is 0 as wake events are disabled. */ 1142 prop->wake_capable = 0; 1143 1144 return 0; 1145 } 1146 1147 static int rt1320_pde_transition_delay(struct rt1320_sdw_priv *rt1320, unsigned char func, 1148 unsigned char entity, unsigned char ps) 1149 { 1150 unsigned int delay = 2000, val; 1151 1152 pm_runtime_mark_last_busy(&rt1320->sdw_slave->dev); 1153 1154 /* waiting for Actual PDE becomes to PS0/PS3 */ 1155 while (delay) { 1156 regmap_read(rt1320->regmap, 1157 SDW_SDCA_CTL(func, entity, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), &val); 1158 if (val == ps) 1159 break; 1160 1161 usleep_range(1000, 1500); 1162 delay--; 1163 } 1164 if (!delay) { 1165 dev_warn(&rt1320->sdw_slave->dev, "%s PDE to %s is NOT ready", __func__, ps?"PS3":"PS0"); 1166 return -ETIMEDOUT; 1167 } 1168 1169 return 0; 1170 } 1171 1172 static void rt1320_data_rw(struct rt1320_sdw_priv *rt1320, unsigned int start, 1173 unsigned char *data, unsigned int size, enum rt1320_rw_type rw) 1174 { 1175 struct device *dev = &rt1320->sdw_slave->dev; 1176 unsigned int tmp; 1177 int ret = -1; 1178 int i, j; 1179 1180 pm_runtime_set_autosuspend_delay(dev, 20000); 1181 pm_runtime_mark_last_busy(dev); 1182 1183 switch (rw) { 1184 case RT1320_BRA_WRITE: 1185 case RT1320_BRA_READ: 1186 ret = sdw_bpt_send_sync(rt1320->sdw_slave->bus, rt1320->sdw_slave, &rt1320->bra_msg); 1187 if (ret < 0) 1188 dev_err(dev, "%s: Failed to send BRA message: %d\n", __func__, ret); 1189 fallthrough; 1190 case RT1320_PARAM_WRITE: 1191 case RT1320_PARAM_READ: 1192 if (ret < 0) { 1193 /* if BRA fails, we try to access by the control word */ 1194 if (rw == RT1320_BRA_WRITE || rw == RT1320_BRA_READ) { 1195 for (i = 0; i < rt1320->bra_msg.sections; i++) { 1196 pm_runtime_mark_last_busy(dev); 1197 for (j = 0; j < rt1320->bra_msg.sec[i].len; j++) { 1198 if (rw == RT1320_BRA_WRITE) { 1199 regmap_write(rt1320->regmap, 1200 rt1320->bra_msg.sec[i].addr + j, rt1320->bra_msg.sec[i].buf[j]); 1201 } else { 1202 regmap_read(rt1320->regmap, rt1320->bra_msg.sec[i].addr + j, &tmp); 1203 rt1320->bra_msg.sec[i].buf[j] = tmp; 1204 } 1205 } 1206 } 1207 } else { 1208 for (i = 0; i < size; i++) { 1209 if (rw == RT1320_PARAM_WRITE) 1210 regmap_write(rt1320->regmap, start + i, data[i]); 1211 else { 1212 regmap_read(rt1320->regmap, start + i, &tmp); 1213 data[i] = tmp; 1214 } 1215 } 1216 } 1217 } 1218 break; 1219 } 1220 1221 pm_runtime_set_autosuspend_delay(dev, 3000); 1222 pm_runtime_mark_last_busy(dev); 1223 } 1224 1225 static unsigned long long rt1320_rsgain_to_rsratio(struct rt1320_sdw_priv *rt1320, unsigned int rsgain) 1226 { 1227 unsigned long long base = 1000000000U; 1228 unsigned long long step = 1960784U; 1229 unsigned long long tmp, result; 1230 1231 if (rsgain == 0 || rsgain == 0x1ff) 1232 result = 1000000000; 1233 else if (rsgain & 0x100) { 1234 tmp = 0xff - (rsgain & 0xff); 1235 tmp = tmp * step; 1236 result = base + tmp; 1237 } else { 1238 tmp = (rsgain & 0xff); 1239 tmp = tmp * step; 1240 result = base - tmp; 1241 } 1242 1243 return result; 1244 } 1245 1246 static void rt1320_pr_read(struct rt1320_sdw_priv *rt1320, unsigned int reg, unsigned int *val) 1247 { 1248 unsigned int byte3, byte2, byte1, byte0; 1249 1250 regmap_write(rt1320->regmap, 0xc483, 0x80); 1251 regmap_write(rt1320->regmap, 0xc482, 0x40); 1252 regmap_write(rt1320->regmap, 0xc481, 0x0c); 1253 regmap_write(rt1320->regmap, 0xc480, 0x10); 1254 1255 regmap_write(rt1320->regmap, 0xc487, ((reg & 0xff000000) >> 24)); 1256 regmap_write(rt1320->regmap, 0xc486, ((reg & 0x00ff0000) >> 16)); 1257 regmap_write(rt1320->regmap, 0xc485, ((reg & 0x0000ff00) >> 8)); 1258 regmap_write(rt1320->regmap, 0xc484, (reg & 0x000000ff)); 1259 1260 regmap_write(rt1320->regmap, 0xc482, 0xc0); 1261 1262 regmap_read(rt1320->regmap, 0xc48f, &byte3); 1263 regmap_read(rt1320->regmap, 0xc48e, &byte2); 1264 regmap_read(rt1320->regmap, 0xc48d, &byte1); 1265 regmap_read(rt1320->regmap, 0xc48c, &byte0); 1266 1267 *val = (byte3 << 24) | (byte2 << 16) | (byte1 << 8) | byte0; 1268 } 1269 1270 static int rt1320_check_fw_ready(struct rt1320_sdw_priv *rt1320) 1271 { 1272 struct device *dev = &rt1320->sdw_slave->dev; 1273 unsigned int tmp, retry = 0; 1274 unsigned int cmd_addr; 1275 1276 switch (rt1320->dev_id) { 1277 case RT1320_DEV_ID: 1278 cmd_addr = RT1320_CMD_ID; 1279 break; 1280 case RT1321_DEV_ID: 1281 cmd_addr = RT1321_CMD_ID; 1282 break; 1283 default: 1284 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 1285 return -EINVAL; 1286 } 1287 1288 pm_runtime_mark_last_busy(dev); 1289 /* check the value of cmd_addr becomes to zero */ 1290 while (retry < 500) { 1291 regmap_read(rt1320->regmap, cmd_addr, &tmp); 1292 if (tmp == 0) 1293 break; 1294 usleep_range(1000, 1100); 1295 retry++; 1296 } 1297 if (retry == 500) { 1298 dev_warn(dev, "%s FW is NOT ready!", __func__); 1299 return -ETIMEDOUT; 1300 } 1301 1302 return 0; 1303 } 1304 1305 static int rt1320_dspfw_status(struct rt1320_sdw_priv *rt1320) 1306 { 1307 struct device *dev = &rt1320->sdw_slave->dev; 1308 unsigned int fw_status_addr, fw_ready; 1309 unsigned int dspfw_run; 1310 1311 switch (rt1320->dev_id) { 1312 case RT1320_DEV_ID: 1313 fw_status_addr = RT1320_DSPFW_STATUS_ADDR; 1314 break; 1315 case RT1321_DEV_ID: 1316 fw_status_addr = RT1321_DSPFW_STATUS_ADDR; 1317 break; 1318 default: 1319 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 1320 return -EINVAL; 1321 } 1322 1323 regmap_read(rt1320->regmap, fw_status_addr, &fw_ready); 1324 fw_ready &= 0x1; 1325 1326 if (rt1320->dev_id == RT1321_DEV_ID) { 1327 regmap_read(rt1320->regmap, 0xf01e, &dspfw_run); 1328 dspfw_run &= 0x1; 1329 fw_ready = (!dspfw_run && fw_ready); 1330 } 1331 1332 if (fw_ready) { 1333 dev_dbg(dev, "%s, DSP FW was already\n", __func__); 1334 return 1; 1335 } 1336 1337 dev_dbg(dev, "%s, DSP FW is NOT ready. Please load DSP FW first\n", __func__); 1338 return 0; 1339 } 1340 1341 static int rt1320_check_power_state_ready(struct rt1320_sdw_priv *rt1320, enum rt1320_power_state ps) 1342 { 1343 struct device *dev = &rt1320->sdw_slave->dev; 1344 unsigned int retry = 0, tmp; 1345 1346 pm_runtime_mark_last_busy(dev); 1347 while (retry < 200) { 1348 regmap_read(rt1320->regmap, RT1320_POWER_STATE, &tmp); 1349 dev_dbg(dev, "%s, RT1320_POWER_STATE=0x%x\n", __func__, tmp); 1350 if (tmp >= ps) 1351 break; 1352 usleep_range(1000, 1500); 1353 retry++; 1354 } 1355 if (retry == 200) { 1356 dev_warn(dev, "%s FW Power State is NOT ready!", __func__); 1357 return -ETIMEDOUT; 1358 } 1359 1360 return 0; 1361 } 1362 1363 static int rt1320_process_fw_param(struct rt1320_sdw_priv *rt1320, unsigned char *buf, unsigned int buf_size) 1364 { 1365 struct device *dev = &rt1320->sdw_slave->dev; 1366 struct rt1320_paramcmd *paramhr = (struct rt1320_paramcmd *)buf; 1367 unsigned char moudleid = paramhr->moudleid; 1368 unsigned char cmdtype = paramhr->commandtype; 1369 unsigned int fw_param_addr; 1370 unsigned int start_addr; 1371 int ret = 0; 1372 1373 switch (rt1320->dev_id) { 1374 case RT1320_DEV_ID: 1375 fw_param_addr = RT1320_FW_PARAM_ADDR; 1376 start_addr = RT1320_CMD_PARAM_ADDR; 1377 break; 1378 case RT1321_DEV_ID: 1379 fw_param_addr = RT1321_FW_PARAM_ADDR; 1380 start_addr = RT1321_CMD_PARAM_ADDR; 1381 break; 1382 default: 1383 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 1384 return -EINVAL; 1385 } 1386 1387 ret = rt1320_check_fw_ready(rt1320); 1388 if (ret < 0) 1389 goto _timeout_; 1390 1391 /* don't set offset 0x0/0x1, it will be set later*/ 1392 paramhr->moudleid = 0; 1393 paramhr->commandtype = 0; 1394 rt1320_data_rw(rt1320, fw_param_addr, buf, buf_size, RT1320_PARAM_WRITE); 1395 1396 dev_dbg(dev, "%s, moudleid=%d, cmdtype=%d, paramid=%d, paramlength=%d\n", __func__, 1397 moudleid, cmdtype, paramhr->paramid, paramhr->paramlength); 1398 1399 if (cmdtype == RT1320_SET_PARAM) { 1400 regmap_write(rt1320->regmap, fw_param_addr, moudleid); 1401 regmap_write(rt1320->regmap, fw_param_addr + 1, 0x01); 1402 } 1403 if (cmdtype == RT1320_GET_PARAM) { 1404 regmap_write(rt1320->regmap, fw_param_addr, moudleid); 1405 regmap_write(rt1320->regmap, fw_param_addr + 1, 0x02); 1406 ret = rt1320_check_fw_ready(rt1320); 1407 if (ret < 0) 1408 goto _timeout_; 1409 1410 rt1320_data_rw(rt1320, start_addr, buf + 0x10, paramhr->commandlength, RT1320_PARAM_READ); 1411 } 1412 return 0; 1413 1414 _timeout_: 1415 dev_err(&rt1320->sdw_slave->dev, "%s: FW is NOT ready for SET/GET_PARAM\n", __func__); 1416 return ret; 1417 } 1418 1419 static int rt1320_fw_param_protocol(struct rt1320_sdw_priv *rt1320, enum rt1320_fw_cmdid cmdid, 1420 unsigned int paramid, void *parambuf, unsigned int paramsize) 1421 { 1422 struct device *dev = &rt1320->sdw_slave->dev; 1423 unsigned char *tempbuf = NULL; 1424 struct rt1320_paramcmd paramhr; 1425 int ret = 0; 1426 1427 tempbuf = kzalloc(sizeof(paramhr) + paramsize, GFP_KERNEL); 1428 if (!tempbuf) 1429 return -ENOMEM; 1430 1431 if (rt1320->dev_id == RT1321_DEV_ID && rt1320->version_id == RT1321_VA2) 1432 paramid += 0x0bff0000; 1433 1434 paramhr.moudleid = 1; 1435 paramhr.commandtype = cmdid; 1436 /* 8 is "sizeof(paramid) + sizeof(paramlength)" */ 1437 paramhr.commandlength = 8 + paramsize; 1438 paramhr.paramid = paramid; 1439 paramhr.paramlength = paramsize; 1440 1441 memcpy(tempbuf, ¶mhr, sizeof(paramhr)); 1442 if (cmdid == RT1320_SET_PARAM) 1443 memcpy(tempbuf + sizeof(paramhr), parambuf, paramsize); 1444 1445 ret = rt1320_process_fw_param(rt1320, tempbuf, sizeof(paramhr) + paramsize); 1446 if (ret < 0) { 1447 dev_err(dev, "%s: process_fw_param failed\n", __func__); 1448 goto _finish_; 1449 } 1450 1451 if (cmdid == RT1320_GET_PARAM) 1452 memcpy(parambuf, tempbuf + sizeof(paramhr), paramsize); 1453 1454 _finish_: 1455 kfree(tempbuf); 1456 return ret; 1457 } 1458 1459 static void rt1320_set_advancemode(struct rt1320_sdw_priv *rt1320) 1460 { 1461 struct device *dev = &rt1320->sdw_slave->dev; 1462 struct rt1320_datafixpoint r0_data[2]; 1463 unsigned short l_advancegain, r_advancegain; 1464 FwPara_Get_HwSwGain audDriverDataHwSwGain = {0}; 1465 unsigned int HwAdvGain = 0; 1466 int ret; 1467 1468 /* Get new hardware advance gain by ID 1300 */ 1469 ret = rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 1300, 1470 &audDriverDataHwSwGain, sizeof(audDriverDataHwSwGain)); 1471 if (ret == 0) { 1472 HwAdvGain = audDriverDataHwSwGain.HwAdvGain; 1473 dev_dbg(dev, "%s, HwAdvGain=%d\n", __func__, HwAdvGain); 1474 dev_dbg(dev, "%s, HwBasGain=%d\n", __func__, audDriverDataHwSwGain.HwBasGain); 1475 dev_dbg(dev, "%s, SwAdvGain=%d\n", __func__, audDriverDataHwSwGain.SwAdvGain); 1476 dev_dbg(dev, "%s, SwBasGain=%d\n", __func__, audDriverDataHwSwGain.SwBasGain); 1477 } else { 1478 dev_dbg(dev, "%s: param 1300 not supported, ret=%d\n", __func__, ret); 1479 } 1480 1481 /* Get advance gain/r0 */ 1482 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 6, &r0_data[0], sizeof(struct rt1320_datafixpoint)); 1483 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 7, &r0_data[1], sizeof(struct rt1320_datafixpoint)); 1484 1485 if (HwAdvGain != 0) { 1486 l_advancegain = HwAdvGain & 0xffff; 1487 r_advancegain = (HwAdvGain >> 16) & 0xffff; 1488 } else { 1489 l_advancegain = r0_data[0].advancegain; 1490 r_advancegain = r0_data[1].advancegain; 1491 } 1492 dev_dbg(dev, "%s, LR advanceGain=0x%x 0x%x\n", __func__, l_advancegain, r_advancegain); 1493 1494 /* set R0 and enable protection by SetParameter id 6, 7 */ 1495 r0_data[0].silencedetect = 0; 1496 r0_data[0].r0 = rt1320->r0_l_reg; 1497 r0_data[1].silencedetect = 0; 1498 r0_data[1].r0 = rt1320->r0_r_reg; 1499 dev_dbg(dev, "%s, write LR r0=%d, %d\n", __func__, r0_data[0].r0, r0_data[1].r0); 1500 1501 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 6, &r0_data[0], sizeof(struct rt1320_datafixpoint)); 1502 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 7, &r0_data[1], sizeof(struct rt1320_datafixpoint)); 1503 ret = rt1320_check_fw_ready(rt1320); 1504 if (ret < 0) 1505 dev_err(dev, "%s: Failed to set FW param 6,7!\n", __func__); 1506 1507 if (l_advancegain != 0 && r_advancegain != 0) { 1508 regmap_write(rt1320->regmap, 0xdd0b, (l_advancegain & 0xff00) >> 8); 1509 regmap_write(rt1320->regmap, 0xdd0a, (l_advancegain & 0xff)); 1510 regmap_write(rt1320->regmap, 0xdd09, (r_advancegain & 0xff00) >> 8); 1511 regmap_write(rt1320->regmap, 0xdd08, (r_advancegain & 0xff)); 1512 dev_dbg(dev, "%s, set Advance mode gain\n", __func__); 1513 } 1514 } 1515 1516 static int rt1320_invrs_load(struct rt1320_sdw_priv *rt1320) 1517 { 1518 struct device *dev = &rt1320->sdw_slave->dev; 1519 unsigned long long l_rsratio, r_rsratio; 1520 unsigned int pr_1058, pr_1059, pr_105a; 1521 unsigned long long l_invrs, r_invrs; 1522 unsigned long long factor = (1 << 28); 1523 unsigned int l_rsgain, r_rsgain; 1524 struct rt1320_datafixpoint r0_data[2]; 1525 int ret; 1526 1527 /* read L/Rch Rs Gain - it uses for compensating the R0 value */ 1528 rt1320_pr_read(rt1320, 0x1058, &pr_1058); 1529 rt1320_pr_read(rt1320, 0x1059, &pr_1059); 1530 rt1320_pr_read(rt1320, 0x105a, &pr_105a); 1531 l_rsgain = ((pr_1059 & 0x7f) << 2) | ((pr_105a & 0xc0) >> 6); 1532 r_rsgain = ((pr_1058 & 0xff) << 1) | ((pr_1059 & 0x80) >> 7); 1533 dev_dbg(dev, "%s, LR rsgain=0x%x, 0x%x\n", __func__, l_rsgain, r_rsgain); 1534 1535 l_rsratio = rt1320_rsgain_to_rsratio(rt1320, l_rsgain); 1536 r_rsratio = rt1320_rsgain_to_rsratio(rt1320, r_rsgain); 1537 dev_dbg(dev, "%s, LR rsratio=%lld, %lld\n", __func__, l_rsratio, r_rsratio); 1538 1539 l_invrs = div_u64(l_rsratio * factor, 1000000000U); 1540 r_invrs = div_u64(r_rsratio * factor, 1000000000U); 1541 1542 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 6, &r0_data[0], sizeof(struct rt1320_datafixpoint)); 1543 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 7, &r0_data[1], sizeof(struct rt1320_datafixpoint)); 1544 1545 r0_data[0].invrs = l_invrs; 1546 r0_data[1].invrs = r_invrs; 1547 dev_dbg(dev, "%s, write DSP LR invrs=0x%x, 0x%x\n", __func__, r0_data[0].invrs, r0_data[1].invrs); 1548 1549 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 6, &r0_data[0], sizeof(struct rt1320_datafixpoint)); 1550 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 7, &r0_data[1], sizeof(struct rt1320_datafixpoint)); 1551 ret = rt1320_check_fw_ready(rt1320); 1552 if (ret < 0) 1553 dev_err(dev, "%s: Failed to set FW param 6,7!\n", __func__); 1554 1555 return ret; 1556 } 1557 1558 static void rt1320_calc_r0(struct rt1320_sdw_priv *rt1320) 1559 { 1560 struct device *dev = &rt1320->sdw_slave->dev; 1561 unsigned long long l_calir0, r_calir0, l_calir0_lo, r_calir0_lo; 1562 1563 l_calir0 = rt1320->r0_l_reg >> 27; 1564 r_calir0 = rt1320->r0_r_reg >> 27; 1565 l_calir0_lo = ((rt1320->r0_l_reg & ((1ull << 27) - 1)) * 1000) >> 27; 1566 r_calir0_lo = ((rt1320->r0_r_reg & ((1ull << 27) - 1)) * 1000) >> 27; 1567 1568 dev_dbg(dev, "%s, l_calir0=%lld.%03lld ohm, r_calir0=%lld.%03lld ohm\n", __func__, 1569 l_calir0, l_calir0_lo, r_calir0, r_calir0_lo); 1570 } 1571 1572 static int rt1320_pilot_tone_output(struct rt1320_sdw_priv *rt1320) 1573 { 1574 struct device *dev = &rt1320->sdw_slave->dev; 1575 int l_targetpostgain, r_targetpostgain; 1576 unsigned long long factor = (1 << 12); 1577 int l_pilotgain[9], r_pilotgain[9]; 1578 const int postgain_step = 234; 1579 int targetGain; 1580 1581 switch (rt1320->dev_id) { 1582 case RT1320_DEV_ID: 1583 targetGain = -320000; 1584 break; 1585 case RT1321_DEV_ID: 1586 targetGain = -420000; 1587 if (rt1320->version_id == RT1321_VA0) 1588 targetGain = -320000; 1589 break; 1590 default: 1591 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 1592 return -EINVAL; 1593 } 1594 1595 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 70, &l_pilotgain[0], sizeof(l_pilotgain)); 1596 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 71, &r_pilotgain[0], sizeof(r_pilotgain)); 1597 dev_dbg(dev, "%s, LR pilotgain %d, %d\n", __func__, l_pilotgain[2], r_pilotgain[2]); 1598 1599 /* calculate pilot tone gain */ 1600 l_pilotgain[2] = (l_pilotgain[2] * 10000) / factor; 1601 r_pilotgain[2] = (r_pilotgain[2] * 10000) / factor; 1602 1603 /* calculate post gain to meet target gain */ 1604 l_targetpostgain = abs(targetGain - l_pilotgain[2]) / postgain_step; 1605 r_targetpostgain = abs(targetGain - r_pilotgain[2]) / postgain_step; 1606 l_targetpostgain = 0xfff - l_targetpostgain; 1607 r_targetpostgain = 0xfff - r_targetpostgain; 1608 dev_dbg(dev, "%s, LR targetpostgain=0x%x, 0x%x\n", __func__, l_targetpostgain, r_targetpostgain); 1609 1610 regmap_write(rt1320->regmap, 0xdd0b, (l_targetpostgain & 0xf00) >> 8); 1611 regmap_write(rt1320->regmap, 0xdd0a, l_targetpostgain & 0xff); 1612 regmap_write(rt1320->regmap, 0xdd09, (r_targetpostgain & 0xf00) >> 8); 1613 regmap_write(rt1320->regmap, 0xdd08, r_targetpostgain & 0xff); 1614 1615 return 0; 1616 } 1617 1618 static void rt1320_calibrate(struct rt1320_sdw_priv *rt1320) 1619 { 1620 struct device *dev = &rt1320->sdw_slave->dev; 1621 struct rt1320_datafixpoint audfixpoint[2]; 1622 unsigned int reg_c5fb, reg_c570, reg_cd00; 1623 unsigned int vol_reg[4]; 1624 unsigned long long l_meanr0, r_meanr0; 1625 int l_re[5], r_re[5]; 1626 int ret, tmp; 1627 unsigned long long factor = (1 << 27); 1628 unsigned short l_advancegain, r_advancegain; 1629 unsigned int delay_s = 7; /* delay seconds for the calibration */ 1630 int dspfw_status; 1631 1632 if (!rt1320->component) 1633 return; 1634 1635 regmap_read(rt1320->regmap, 0xdd0b, &vol_reg[3]); 1636 regmap_read(rt1320->regmap, 0xdd0a, &vol_reg[2]); 1637 regmap_read(rt1320->regmap, 0xdd09, &vol_reg[1]); 1638 regmap_read(rt1320->regmap, 0xdd08, &vol_reg[0]); 1639 regmap_read(rt1320->regmap, 0xc5fb, ®_c5fb); 1640 regmap_read(rt1320->regmap, 0xc570, ®_c570); 1641 regmap_read(rt1320->regmap, 0xcd00, ®_cd00); 1642 1643 regmap_write(rt1320->regmap, 1644 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00); 1645 ret = rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x00); 1646 if (ret < 0) { 1647 dev_dbg(dev, "%s, PDE=PS0 is NOT ready\n", __func__); 1648 goto _finish_; 1649 } 1650 1651 dspfw_status = rt1320_dspfw_status(rt1320); 1652 if (dspfw_status <= 0) { 1653 dev_dbg(dev, "%s, DSP FW is NOT ready. Please load DSP FW first\n", __func__); 1654 goto _finish_; 1655 } 1656 1657 ret = rt1320_check_power_state_ready(rt1320, RT1320_NORMAL_STATE); 1658 if (ret < 0) { 1659 dev_dbg(dev, "%s, DSP FW PS is NOT ready\n", __func__); 1660 goto _finish_; 1661 } 1662 1663 /* fine tune pilot tone output */ 1664 ret = rt1320_pilot_tone_output(rt1320); 1665 if (ret < 0) { 1666 dev_dbg(dev, "%s, Failed to tune pilot tone output\n", __func__); 1667 goto _finish_; 1668 } 1669 1670 if (rt1320->dev_id == RT1321_DEV_ID) { 1671 regmap_update_bits(rt1320->regmap, 0xc047, 0x80, 0x00); 1672 regmap_write(rt1320->regmap, 0xc5c4, 0x12); 1673 } 1674 1675 regmap_write(rt1320->regmap, 0xc5fb, 0x00); 1676 regmap_write(rt1320->regmap, 0xc570, 0x0b); 1677 regmap_write(rt1320->regmap, 0xcd00, 0xc5); 1678 1679 /* disable silence detection */ 1680 regmap_update_bits(rt1320->regmap, 0xc044, 0xe0, 0x00); 1681 dev_dbg(dev, "%s, disable silence detection\n", __func__); 1682 1683 ret = rt1320_check_power_state_ready(rt1320, RT1320_K_R0_STATE); 1684 if (ret < 0) { 1685 dev_dbg(dev, "%s, check class D status before k r0\n", __func__); 1686 goto _finish_; 1687 } 1688 1689 for (tmp = 0; tmp < delay_s; tmp++) { 1690 msleep(1000); 1691 pm_runtime_mark_last_busy(dev); 1692 1693 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 11, &l_re[0], sizeof(l_re)); 1694 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 12, &r_re[0], sizeof(r_re)); 1695 1696 dev_dbg(dev, "%s, LR re=0x%x, 0x%x\n", __func__, l_re[4], r_re[4]); 1697 dev_dbg(dev, "%s, waiting for calibration R0...%d seconds\n", __func__, tmp + 1); 1698 } 1699 1700 /* Get Calibration data */ 1701 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 11, &l_re[0], sizeof(l_re)); 1702 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 12, &r_re[0], sizeof(r_re)); 1703 dev_dbg(dev, "%s, LR re=0x%x, 0x%x\n", __func__, l_re[4], r_re[4]); 1704 1705 /* Get advance gain/mean r0 */ 1706 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 6, &audfixpoint[0], sizeof(struct rt1320_datafixpoint)); 1707 l_meanr0 = audfixpoint[0].meanr0; 1708 l_advancegain = audfixpoint[0].advancegain; 1709 l_meanr0 = ((l_meanr0 * 1000U) / factor); 1710 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 7, &audfixpoint[1], sizeof(struct rt1320_datafixpoint)); 1711 r_meanr0 = audfixpoint[1].meanr0; 1712 r_advancegain = audfixpoint[1].advancegain; 1713 r_meanr0 = ((r_meanr0 * 1000U) / factor); 1714 dev_dbg(dev, "%s, LR meanr0=%lld, %lld\n", __func__, l_meanr0, r_meanr0); 1715 dev_dbg(dev, "%s, LR advanceGain=0x%x, 0x%x\n", __func__, l_advancegain, r_advancegain); 1716 dev_dbg(dev, "%s, LR invrs=0x%x, 0x%x\n", __func__, audfixpoint[0].invrs, audfixpoint[1].invrs); 1717 1718 /* enable silence detection */ 1719 regmap_update_bits(rt1320->regmap, 0xc044, 0xe0, 0xe0); 1720 dev_dbg(dev, "%s, enable silence detection\n", __func__); 1721 1722 regmap_write(rt1320->regmap, 0xc5fb, reg_c5fb); 1723 regmap_write(rt1320->regmap, 0xc570, reg_c570); 1724 regmap_write(rt1320->regmap, 0xcd00, reg_cd00); 1725 1726 rt1320->r0_l_reg = l_re[4]; 1727 rt1320->r0_r_reg = r_re[4]; 1728 rt1320->cali_done = true; 1729 rt1320_calc_r0(rt1320); 1730 1731 _finish_: 1732 regmap_write(rt1320->regmap, 1733 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03); 1734 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x03); 1735 1736 if (rt1320->dev_id == RT1321_DEV_ID) { 1737 regmap_update_bits(rt1320->regmap, 0xc047, 0x80, 0x80); 1738 regmap_write(rt1320->regmap, 0xc5c4, 0x10); 1739 } 1740 1741 /* advance gain will be set when R0 load, not here */ 1742 regmap_write(rt1320->regmap, 0xdd0b, vol_reg[3]); 1743 regmap_write(rt1320->regmap, 0xdd0a, vol_reg[2]); 1744 regmap_write(rt1320->regmap, 0xdd09, vol_reg[1]); 1745 regmap_write(rt1320->regmap, 0xdd08, vol_reg[0]); 1746 } 1747 1748 static int rt1320_r0_cali_get(struct snd_kcontrol *kcontrol, 1749 struct snd_ctl_elem_value *ucontrol) 1750 { 1751 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1752 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 1753 1754 ucontrol->value.integer.value[0] = rt1320->cali_done; 1755 return 0; 1756 } 1757 1758 static int rt1320_r0_cali_put(struct snd_kcontrol *kcontrol, 1759 struct snd_ctl_elem_value *ucontrol) 1760 { 1761 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1762 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 1763 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(rt1320->component); 1764 int ret; 1765 1766 if (!rt1320->hw_init) 1767 return 0; 1768 1769 ret = pm_runtime_resume(component->dev); 1770 if (ret < 0 && ret != -EACCES) 1771 return ret; 1772 1773 rt1320->cali_done = false; 1774 snd_soc_dapm_mutex_lock(dapm); 1775 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF && 1776 ucontrol->value.integer.value[0]) { 1777 rt1320_calibrate(rt1320); 1778 } 1779 snd_soc_dapm_mutex_unlock(dapm); 1780 1781 return 0; 1782 } 1783 1784 /* 1785 * The 'patch code' is written to the patch code area. 1786 * The patch code area is used for SDCA register expansion flexibility. 1787 */ 1788 static void rt1320_load_mcu_patch(struct rt1320_sdw_priv *rt1320) 1789 { 1790 struct sdw_slave *slave = rt1320->sdw_slave; 1791 const struct firmware *patch __free(firmware) = NULL; 1792 const char *filename; 1793 unsigned int addr, val, min_addr, max_addr; 1794 const unsigned char *ptr; 1795 int ret, i; 1796 1797 switch (rt1320->dev_id) { 1798 case RT1320_DEV_ID: 1799 if (rt1320->version_id <= RT1320_VB) 1800 filename = RT1320_VAB_MCU_PATCH; 1801 else 1802 filename = RT1320_VC_MCU_PATCH; 1803 min_addr = 0x10007000; 1804 max_addr = 0x10007fff; 1805 break; 1806 case RT1321_DEV_ID: 1807 if (rt1320->version_id == RT1321_VA2) 1808 return; 1809 1810 filename = RT1321_VA_MCU_PATCH; 1811 min_addr = 0x10008000; 1812 max_addr = 0x10008fff; 1813 break; 1814 default: 1815 dev_err(&slave->dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 1816 return; 1817 } 1818 1819 /* load the patch code here */ 1820 ret = request_firmware(&patch, filename, &slave->dev); 1821 if (ret) { 1822 dev_err(&slave->dev, "%s: Failed to load %s firmware", __func__, filename); 1823 regmap_write(rt1320->regmap, 0xc598, 0x00); 1824 regmap_write(rt1320->regmap, min_addr, 0x67); 1825 regmap_write(rt1320->regmap, min_addr + 0x1, 0x80); 1826 regmap_write(rt1320->regmap, min_addr + 0x2, 0x00); 1827 regmap_write(rt1320->regmap, min_addr + 0x3, 0x00); 1828 if (rt1320->dev_id == RT1321_DEV_ID) { 1829 regmap_write(rt1320->regmap, 0xd73c, 0x67); 1830 regmap_write(rt1320->regmap, 0xd73d, 0x80); 1831 regmap_write(rt1320->regmap, 0xd73e, 0x00); 1832 regmap_write(rt1320->regmap, 0xd73f, 0x00); 1833 } 1834 } else { 1835 ptr = (const unsigned char *)patch->data; 1836 if ((patch->size % 8) == 0) { 1837 for (i = 0; i < patch->size; i += 8) { 1838 addr = (ptr[i] & 0xff) | (ptr[i + 1] & 0xff) << 8 | 1839 (ptr[i + 2] & 0xff) << 16 | (ptr[i + 3] & 0xff) << 24; 1840 val = (ptr[i + 4] & 0xff) | (ptr[i + 5] & 0xff) << 8 | 1841 (ptr[i + 6] & 0xff) << 16 | (ptr[i + 7] & 0xff) << 24; 1842 1843 if (addr > max_addr || addr < min_addr) { 1844 dev_err(&slave->dev, "%s: the address 0x%x is wrong", __func__, addr); 1845 return; 1846 } 1847 if (val > 0xff) { 1848 dev_err(&slave->dev, "%s: the value 0x%x is wrong", __func__, val); 1849 return; 1850 } 1851 regmap_write(rt1320->regmap, addr, val); 1852 } 1853 } 1854 } 1855 } 1856 1857 static void rt1320_vab_preset(struct rt1320_sdw_priv *rt1320) 1858 { 1859 unsigned int i, reg, val, delay; 1860 1861 for (i = 0; i < ARRAY_SIZE(rt1320_blind_write); i++) { 1862 reg = rt1320_blind_write[i].reg; 1863 val = rt1320_blind_write[i].def; 1864 delay = rt1320_blind_write[i].delay_us; 1865 1866 if (reg == 0x3fc2bfc7) 1867 rt1320_load_mcu_patch(rt1320); 1868 1869 regmap_write(rt1320->regmap, reg, val); 1870 if (delay) 1871 usleep_range(delay, delay + 1000); 1872 } 1873 } 1874 1875 static void rt1320_t0_load(struct rt1320_sdw_priv *rt1320, unsigned int l_t0, unsigned int r_t0) 1876 { 1877 struct device *dev = &rt1320->sdw_slave->dev; 1878 unsigned int factor = (1 << 22); 1879 int l_t0_data[38], r_t0_data[38]; 1880 int dspfw_status; 1881 1882 regmap_write(rt1320->regmap, 1883 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 1884 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00); 1885 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x00); 1886 1887 dspfw_status = rt1320_dspfw_status(rt1320); 1888 if (dspfw_status <= 0) { 1889 dev_warn(dev, "%s, DSP FW is NOT ready\n", __func__); 1890 goto _exit_; 1891 } 1892 1893 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 3, &l_t0_data[0], sizeof(l_t0_data)); 1894 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 4, &r_t0_data[0], sizeof(r_t0_data)); 1895 1896 l_t0_data[37] = l_t0 * factor; 1897 r_t0_data[37] = r_t0 * factor; 1898 1899 dev_dbg(dev, "%s, write LR t0=0x%x, 0x%x\n", __func__, l_t0_data[37], r_t0_data[37]); 1900 1901 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 3, &l_t0_data[0], sizeof(l_t0_data)); 1902 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 4, &r_t0_data[0], sizeof(r_t0_data)); 1903 if (rt1320_check_fw_ready(rt1320) < 0) 1904 dev_err(dev, "%s: Failed to set FW param 3,4!\n", __func__); 1905 1906 rt1320->temp_l_calib = l_t0; 1907 rt1320->temp_r_calib = r_t0; 1908 1909 memset(&l_t0_data[0], 0x00, sizeof(l_t0_data)); 1910 memset(&r_t0_data[0], 0x00, sizeof(r_t0_data)); 1911 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 3, &l_t0_data[0], sizeof(l_t0_data)); 1912 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 4, &r_t0_data[0], sizeof(r_t0_data)); 1913 dev_dbg(dev, "%s, read after writing LR t0=0x%x, 0x%x\n", __func__, l_t0_data[37], r_t0_data[37]); 1914 1915 _exit_: 1916 regmap_write(rt1320->regmap, 1917 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 1918 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03); 1919 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x03); 1920 } 1921 1922 static int rt1320_rae_load(struct rt1320_sdw_priv *rt1320) 1923 { 1924 struct device *dev = &rt1320->sdw_slave->dev; 1925 static const char func_tag[] = "FUNC"; 1926 static const char xu_tag[] = "XU"; 1927 const struct firmware *rae_fw __free(firmware) = NULL; 1928 unsigned int fw_offset; 1929 unsigned char *fw_data; 1930 unsigned char *param_data; 1931 unsigned int addr, size; 1932 unsigned int func, value; 1933 const char *dmi_vendor, *dmi_product, *dmi_sku; 1934 int len_vendor, len_product, len_sku; 1935 char rae_filename[512]; 1936 char tag[5]; 1937 int ret = 0; 1938 int retry = 200; 1939 1940 dmi_vendor = dmi_get_system_info(DMI_SYS_VENDOR); 1941 dmi_product = dmi_get_system_info(DMI_PRODUCT_NAME); 1942 dmi_sku = dmi_get_system_info(DMI_PRODUCT_SKU); 1943 1944 if (dmi_vendor && dmi_product && dmi_sku) { 1945 len_vendor = strchrnul(dmi_vendor, ' ') - dmi_vendor; 1946 len_product = strchrnul(dmi_product, ' ') - dmi_product; 1947 len_sku = strchrnul(dmi_sku, ' ') - dmi_sku; 1948 1949 snprintf(rae_filename, sizeof(rae_filename), 1950 "realtek/rt1320/rt1320_RAE_%.*s_%.*s_%.*s.dat", 1951 len_vendor, dmi_vendor, len_product, dmi_product, len_sku, dmi_sku); 1952 dev_dbg(dev, "%s: try to load RAE file %s\n", __func__, rae_filename); 1953 } else { 1954 dev_warn(dev, "%s: Can't find proper RAE file name\n", __func__); 1955 return -EINVAL; 1956 } 1957 1958 regmap_write(rt1320->regmap, 1959 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 1960 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00); 1961 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x00); 1962 1963 request_firmware(&rae_fw, rae_filename, dev); 1964 if (rae_fw) { 1965 1966 switch (rt1320->dev_id) { 1967 case RT1320_DEV_ID: 1968 /* RAE CRC clear */ 1969 regmap_write(rt1320->regmap, 0xe80b, 0x0f); 1970 /* RAE stop & CRC disable */ 1971 regmap_update_bits(rt1320->regmap, 0xe803, 0xbc, 0x00); 1972 while (--retry) { 1973 regmap_read(rt1320->regmap, 0xe83f, &value); 1974 if (value & 0x40) 1975 break; 1976 usleep_range(1000, 1100); 1977 } 1978 if (!retry && !(value & 0x40)) { 1979 dev_err(dev, "%s: RAE is not ready to load\n", __func__); 1980 return -ETIMEDOUT; 1981 } 1982 break; 1983 case RT1321_DEV_ID: 1984 /* RAE CRC clear */ 1985 regmap_write(rt1320->regmap, 0x2000300e, 0xc0); 1986 regmap_write(rt1320->regmap, 0x2000300f, 0x0f); 1987 /* RAE stop & Phase sync & CRC disable */ 1988 regmap_update_bits(rt1320->regmap, 0x20003003, 0xfe, 0x00); 1989 regmap_update_bits(rt1320->regmap, 0xc047, 0x80, 0x00); 1990 regmap_update_bits(rt1320->regmap, 0x2000301c, 0x01, 0x00); 1991 /* check whether write state is ready */ 1992 while (--retry) { 1993 regmap_read(rt1320->regmap, 0x20003043, &value); 1994 if (value & 0x40) 1995 break; 1996 usleep_range(1000, 1100); 1997 } 1998 if (!retry && !(value & 0x40)) { 1999 dev_err(dev, "%s: RAE is not ready to load\n", __func__); 2000 return -ETIMEDOUT; 2001 } 2002 break; 2003 default: 2004 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 2005 return -EINVAL; 2006 } 2007 2008 dev_dbg(dev, "%s, rae_fw size=0x%zx\n", __func__, rae_fw->size); 2009 regcache_cache_bypass(rt1320->regmap, true); 2010 for (fw_offset = 0; fw_offset < rae_fw->size;) { 2011 2012 dev_dbg(dev, "%s, fw_offset=0x%x\n", __func__, fw_offset); 2013 2014 fw_data = (unsigned char *)&rae_fw->data[fw_offset]; 2015 2016 memcpy(tag, fw_data, 4); 2017 tag[4] = '\0'; 2018 dev_dbg(dev, "%s, tag=%s\n", __func__, tag); 2019 if (strcmp(tag, xu_tag) == 0) { 2020 dev_dbg(dev, "%s: This is a XU tag", __func__); 2021 memcpy(&addr, (fw_data + 4), 4); 2022 memcpy(&size, (fw_data + 8), 4); 2023 param_data = (unsigned char *)(fw_data + 12); 2024 2025 dev_dbg(dev, "%s: addr=0x%x, size=0x%x\n", __func__, addr, size); 2026 2027 /* 2028 * UI register ranges from 0x1000d000 to 0x1000d7ff 2029 * UI registers should be accessed by tuning tool. 2030 * So, there registers should be cached. 2031 */ 2032 if (addr <= 0x1000d7ff && addr >= 0x1000d000) 2033 regcache_cache_bypass(rt1320->regmap, false); 2034 2035 rt1320_data_rw(rt1320, addr, param_data, size, RT1320_PARAM_WRITE); 2036 2037 regcache_cache_bypass(rt1320->regmap, true); 2038 2039 fw_offset += (size + 12); 2040 } else if (strcmp(tag, func_tag) == 0) { 2041 dev_err(dev, "%s: This is a FUNC tag", __func__); 2042 2043 memcpy(&func, (fw_data + 4), 4); 2044 memcpy(&value, (fw_data + 8), 4); 2045 2046 dev_dbg(dev, "%s: func=0x%x, value=0x%x\n", __func__, func, value); 2047 if (func == 1) //DelayMs 2048 msleep(value); 2049 2050 fw_offset += 12; 2051 } else { 2052 dev_err(dev, "%s: This is NOT a XU file (wrong tag)", __func__); 2053 break; 2054 } 2055 } 2056 2057 regcache_cache_bypass(rt1320->regmap, false); 2058 2059 } else { 2060 dev_err(dev, "%s: Failed to load %s firmware\n", __func__, rae_filename); 2061 ret = -EINVAL; 2062 goto _exit_; 2063 } 2064 2065 switch (rt1320->dev_id) { 2066 case RT1320_DEV_ID: 2067 /* RAE CRC enable */ 2068 regmap_update_bits(rt1320->regmap, 0xe803, 0x0c, 0x0c); 2069 /* RAE update */ 2070 regmap_update_bits(rt1320->regmap, 0xe80b, 0x80, 0x00); 2071 regmap_update_bits(rt1320->regmap, 0xe80b, 0x80, 0x80); 2072 /* RAE run */ 2073 regmap_update_bits(rt1320->regmap, 0xe803, 0x80, 0x80); 2074 regmap_read(rt1320->regmap, 0xe80b, &value); 2075 dev_dbg(dev, "%s: CAE run => 0xe80b reg = 0x%x\n", __func__, value); 2076 break; 2077 case RT1321_DEV_ID: 2078 /* RAE CRC enable */ 2079 regmap_update_bits(rt1320->regmap, 0x20003003, 0x30, 0x30); 2080 /* RAE update */ 2081 regmap_update_bits(rt1320->regmap, 0x2000301c, 0x80, 0x00); 2082 regmap_update_bits(rt1320->regmap, 0x2000301c, 0x80, 0x80); 2083 regmap_update_bits(rt1320->regmap, 0x20009018, 0x80, 0x00); 2084 regmap_update_bits(rt1320->regmap, 0x20009018, 0x80, 0x80); 2085 regmap_update_bits(rt1320->regmap, 0x20005818, 0x80, 0x00); 2086 regmap_update_bits(rt1320->regmap, 0x20005818, 0x80, 0x80); 2087 /* RAE run */ 2088 regmap_update_bits(rt1320->regmap, 0x2000301c, 0x01, 0x01); 2089 /* Phase sync enable */ 2090 regmap_update_bits(rt1320->regmap, 0xc047, 0x80, 0x80); 2091 break; 2092 } 2093 2094 rt1320->rae_update_done = true; 2095 2096 _exit_: 2097 regmap_write(rt1320->regmap, 2098 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 2099 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03); 2100 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x03); 2101 2102 return ret; 2103 } 2104 2105 static void rt1320_dspfw_load_code(struct rt1320_sdw_priv *rt1320) 2106 { 2107 struct rt1320_imageinfo { 2108 unsigned int addr; 2109 unsigned int size; 2110 }; 2111 2112 struct rt1320_dspfwheader { 2113 unsigned int sync; 2114 short num; 2115 short crc; 2116 }; 2117 2118 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(rt1320->component); 2119 struct device *dev = &rt1320->sdw_slave->dev; 2120 unsigned int val, i, fw_offset; 2121 struct rt1320_dspfwheader *fwheader; 2122 struct rt1320_imageinfo *ptr_img; 2123 struct sdw_bpt_section sec[10]; 2124 const struct firmware *fw __free(firmware) = NULL; 2125 unsigned char *fw_data; 2126 bool dev_fw_match = false; 2127 static const char hdr_sig[] = "AFX"; 2128 unsigned int hdr_size = 0; 2129 const char *dmi_vendor, *dmi_product, *dmi_sku; 2130 int len_vendor, len_product, len_sku; 2131 unsigned char boot_mode = 0; /* 0: from RAM; 1: from ROM */ 2132 unsigned char has_0x3fc00000 = 0; 2133 char filename[512]; 2134 2135 dmi_vendor = dmi_get_system_info(DMI_SYS_VENDOR); 2136 dmi_product = dmi_get_system_info(DMI_PRODUCT_NAME); 2137 dmi_sku = dmi_get_system_info(DMI_PRODUCT_SKU); 2138 2139 if (dmi_vendor && dmi_product && dmi_sku) { 2140 len_vendor = strchrnul(dmi_vendor, ' ') - dmi_vendor; 2141 len_product = strchrnul(dmi_product, ' ') - dmi_product; 2142 len_sku = strchrnul(dmi_sku, ' ') - dmi_sku; 2143 2144 snprintf(filename, sizeof(filename), 2145 "realtek/rt1320/rt1320_%.*s_%.*s_%.*s.dat", 2146 len_vendor, dmi_vendor, len_product, dmi_product, len_sku, dmi_sku); 2147 2148 dev_dbg(dev, "%s: try to load FW file %s\n", __func__, filename); 2149 } else if (rt1320->dspfw_name) { 2150 snprintf(filename, sizeof(filename), "rt1320_%s.dat", 2151 rt1320->dspfw_name); 2152 dev_dbg(dev, "%s: try to load FW file %s\n", __func__, filename); 2153 } else { 2154 dev_warn(dev, "%s: Can't find proper FW file name\n", __func__); 2155 return; 2156 } 2157 2158 snd_soc_dapm_mutex_lock(dapm); 2159 regmap_write(rt1320->regmap, 2160 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 2161 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00); 2162 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x00); 2163 2164 if (rt1320_dspfw_status(rt1320)) { 2165 dev_dbg(dev, "%s, DSP FW was already\n", __func__); 2166 rt1320->fw_load_done = true; 2167 goto _exit_; 2168 } 2169 2170 request_firmware(&fw, filename, dev); 2171 if (fw) { 2172 fwheader = (struct rt1320_dspfwheader *)fw->data; 2173 dev_dbg(dev, "%s, fw sync = 0x%x, num=%d, crc=0x%x\n", __func__, 2174 fwheader->sync, fwheader->num, fwheader->crc); 2175 2176 if (fwheader->sync != 0x0a1c5679) { 2177 dev_err(dev, "%s: FW sync error\n", __func__); 2178 goto _exit_; 2179 } 2180 2181 fw_offset = sizeof(struct rt1320_dspfwheader) + (sizeof(struct rt1320_imageinfo) * fwheader->num); 2182 dev_dbg(dev, "%s, fw_offset = 0x%x\n", __func__, fw_offset); 2183 2184 regcache_cache_bypass(rt1320->regmap, true); 2185 2186 for (i = 0; i < fwheader->num; i++) { 2187 ptr_img = (struct rt1320_imageinfo *)&fw->data[sizeof(struct rt1320_dspfwheader) + (sizeof(struct rt1320_imageinfo) * i)]; 2188 2189 dev_dbg(dev, "%s, fw_offset=0x%x, load fw addr=0x%x, size=%d\n", __func__, 2190 fw_offset, ptr_img->addr, ptr_img->size); 2191 2192 fw_data = (unsigned char *)&fw->data[fw_offset]; 2193 2194 /* The binary file has a header of 64 bytes */ 2195 if (memcmp(fw_data, hdr_sig, sizeof(hdr_sig)) == 0) 2196 hdr_size = 64; 2197 else 2198 hdr_size = 0; 2199 2200 sec[i].addr = ptr_img->addr; 2201 sec[i].len = ptr_img->size - hdr_size; 2202 sec[i].buf = fw_data + hdr_size; 2203 2204 dev_dbg(dev, "%s, hdr_size=%d, sec[%d].buf[0]=0x%x\n", 2205 __func__, hdr_size, i, sec[i].buf[0]); 2206 2207 switch (rt1320->dev_id) { 2208 case RT1320_DEV_ID: 2209 if (ptr_img->addr == 0x3fc29d80) 2210 if (fw_data[9] == '0') 2211 dev_fw_match = true; 2212 break; 2213 case RT1321_DEV_ID: 2214 if (ptr_img->addr == 0x3fc00000) { 2215 if (fw_data[7] == '1') 2216 dev_fw_match = true; 2217 has_0x3fc00000 = 1; 2218 } 2219 break; 2220 default: 2221 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 2222 goto _exit_; 2223 } 2224 2225 fw_offset += ptr_img->size; 2226 } 2227 2228 if (rt1320->dev_id == RT1321_DEV_ID && rt1320->version_id == RT1321_VA2) { 2229 /* 2230 * For 1321 VA2, if the FW doesn't include the section for address 0x3fc00000, 2231 * it means the FW will boot from ROM and force dev_fw_match to true to download FW by BRA. 2232 */ 2233 if (!has_0x3fc00000) { 2234 boot_mode = 1; 2235 dev_fw_match = true; 2236 } 2237 dev_dbg(dev, "%s: Boot from %s for VA2\n", __func__, (boot_mode ? "ROM" : "RAM")); 2238 } 2239 2240 /* change to IRAM */ 2241 if (!boot_mode) 2242 regmap_update_bits(rt1320->regmap, 0xf01e, 0x80, 0x00); 2243 2244 if (dev_fw_match) { 2245 dev_dbg(dev, "%s, starting BRA downloading FW..\n", __func__); 2246 rt1320->bra_msg.dev_num = rt1320->sdw_slave->dev_num; 2247 rt1320->bra_msg.flags = SDW_MSG_FLAG_WRITE; 2248 rt1320->bra_msg.sections = fwheader->num; 2249 rt1320->bra_msg.sec = &sec[0]; 2250 rt1320_data_rw(rt1320, 0, NULL, 0, RT1320_BRA_WRITE); 2251 dev_dbg(dev, "%s, BRA downloading FW done..\n", __func__); 2252 } 2253 2254 regcache_cache_bypass(rt1320->regmap, false); 2255 2256 if (!dev_fw_match) { 2257 dev_err(dev, "%s: FW file doesn't match to device\n", __func__); 2258 goto _exit_; 2259 } 2260 } else { 2261 dev_err(dev, "%s: Failed to load %s firmware\n", __func__, filename); 2262 goto _exit_; 2263 } 2264 2265 switch (rt1320->dev_id) { 2266 case RT1320_DEV_ID: 2267 /* run RAM code */ 2268 regmap_read(rt1320->regmap, 0x3fc2bfc0, &val); 2269 val |= 0x8; 2270 regmap_write(rt1320->regmap, 0x3fc2bfc0, val); 2271 /* clear frame counter */ 2272 regmap_write(rt1320->regmap, 0x3fc2bfcb, 0x00); 2273 regmap_write(rt1320->regmap, 0x3fc2bfca, 0x00); 2274 regmap_write(rt1320->regmap, 0x3fc2bfc9, 0x00); 2275 regmap_write(rt1320->regmap, 0x3fc2bfc8, 0x00); 2276 break; 2277 case RT1321_DEV_ID: 2278 if (!boot_mode) { 2279 /* run RAM code */ 2280 regmap_read(rt1320->regmap, 0x3fc2dfc0, &val); 2281 val |= 0x8; 2282 regmap_write(rt1320->regmap, 0x3fc2dfc0, val); 2283 } 2284 /* clear frame counter */ 2285 regmap_write(rt1320->regmap, 0x3fc2dfcb, 0x00); 2286 regmap_write(rt1320->regmap, 0x3fc2dfca, 0x00); 2287 regmap_write(rt1320->regmap, 0x3fc2dfc9, 0x00); 2288 regmap_write(rt1320->regmap, 0x3fc2dfc8, 0x00); 2289 /* enable handshake */ 2290 regmap_write(rt1320->regmap, 0x3fc2dfc4, 0x00); 2291 regmap_write(rt1320->regmap, 0xd470, 0xad); 2292 /* minimum phase settings */ 2293 regmap_write(rt1320->regmap, 0xc5c4, 0x10); 2294 regmap_write(rt1320->regmap, 0x20003003, 0x31); 2295 regmap_update_bits(rt1320->regmap, 0x20003002, 0x40, 0x00); 2296 regmap_write(rt1320->regmap, 0xc5b3, 0x01); 2297 regmap_write(rt1320->regmap, 0xc052, 0x11); 2298 break; 2299 } 2300 2301 /* enable DSP FW */ 2302 regmap_write(rt1320->regmap, 0xc081, 0xfc); 2303 regmap_update_bits(rt1320->regmap, 0xf01e, 0x1, 0x0); 2304 2305 /* RsRatio should restore into DSP FW when FW was ready */ 2306 rt1320_invrs_load(rt1320); 2307 2308 /* DSP clock switches to PLL */ 2309 regmap_write(rt1320->regmap, 0xc081, 0xfc); 2310 /* pass DSP settings */ 2311 regmap_write(rt1320->regmap, 0xc5c3, 0xf3); 2312 regmap_write(rt1320->regmap, 0xc5c8, 0x05); 2313 2314 rt1320->fw_load_done = true; 2315 2316 pm_runtime_set_autosuspend_delay(dev, 3000); 2317 pm_runtime_mark_last_busy(dev); 2318 2319 _exit_: 2320 regmap_write(rt1320->regmap, 2321 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 2322 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03); 2323 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x03); 2324 2325 snd_soc_dapm_mutex_unlock(dapm); 2326 } 2327 2328 static void rt1320_load_dspfw_work(struct work_struct *work) 2329 { 2330 struct rt1320_sdw_priv *rt1320 = 2331 container_of(work, struct rt1320_sdw_priv, load_dspfw_work); 2332 int ret; 2333 2334 ret = pm_runtime_resume(rt1320->component->dev); 2335 if (ret < 0 && ret != -EACCES) 2336 return; 2337 2338 dev_dbg(&rt1320->sdw_slave->dev, "%s, Starting to reload DSP FW", __func__); 2339 rt1320_dspfw_load_code(rt1320); 2340 } 2341 2342 static void rt1320_vc_preset(struct rt1320_sdw_priv *rt1320) 2343 { 2344 struct sdw_slave *slave = rt1320->sdw_slave; 2345 unsigned int i, reg, val, delay, retry, tmp; 2346 2347 for (i = 0; i < ARRAY_SIZE(rt1320_vc_blind_write); i++) { 2348 reg = rt1320_vc_blind_write[i].reg; 2349 val = rt1320_vc_blind_write[i].def; 2350 delay = rt1320_vc_blind_write[i].delay_us; 2351 2352 if (reg == 0x3fc2bf83) 2353 rt1320_load_mcu_patch(rt1320); 2354 2355 if ((reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0)) && 2356 (val == 0x00)) { 2357 retry = 200; 2358 while (retry) { 2359 regmap_read(rt1320->regmap, RT1320_KR0_INT_READY, &tmp); 2360 dev_dbg(&slave->dev, "%s, RT1320_KR0_INT_READY=0x%x\n", __func__, tmp); 2361 if (tmp == 0x1f) 2362 break; 2363 usleep_range(1000, 1500); 2364 retry--; 2365 } 2366 if (!retry) 2367 dev_warn(&slave->dev, "%s MCU is NOT ready!", __func__); 2368 } 2369 regmap_write(rt1320->regmap, reg, val); 2370 if (delay) 2371 usleep_range(delay, delay + 1000); 2372 2373 if (reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0)) 2374 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, val); 2375 } 2376 } 2377 2378 static void rt1321_preset(struct rt1320_sdw_priv *rt1320) 2379 { 2380 const struct reg_sequence *blindwrite; 2381 unsigned int i, reg, val, delay; 2382 unsigned int array_size; 2383 2384 switch (rt1320->version_id) { 2385 case RT1321_VA0: 2386 blindwrite = rt1321_blind_write; 2387 array_size = ARRAY_SIZE(rt1321_blind_write); 2388 break; 2389 case RT1321_VA1: 2390 blindwrite = rt1321_va1_blind_write; 2391 array_size = ARRAY_SIZE(rt1321_va1_blind_write); 2392 break; 2393 case RT1321_VA2: 2394 blindwrite = rt1321_va2_blind_write; 2395 array_size = ARRAY_SIZE(rt1321_va2_blind_write); 2396 break; 2397 default: 2398 dev_err(&rt1320->sdw_slave->dev, "%s: Unknown version ID %d\n", 2399 __func__, rt1320->version_id); 2400 return; 2401 } 2402 2403 for (i = 0; i < array_size; i++) { 2404 reg = blindwrite[i].reg; 2405 val = blindwrite[i].def; 2406 delay = blindwrite[i].delay_us; 2407 2408 if (reg == 0x1000cd56) 2409 rt1320_load_mcu_patch(rt1320); 2410 2411 regmap_write(rt1320->regmap, reg, val); 2412 2413 if (delay) 2414 usleep_range(delay, delay + 1000); 2415 2416 if (reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0)) 2417 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, val); 2418 } 2419 } 2420 2421 static int rt1320_io_init(struct device *dev, struct sdw_slave *slave) 2422 { 2423 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); 2424 unsigned int amp_func_status, val, tmp; 2425 2426 if (rt1320->hw_init) 2427 return 0; 2428 2429 regcache_cache_only(rt1320->regmap, false); 2430 regcache_cache_only(rt1320->mbq_regmap, false); 2431 if (rt1320->first_hw_init) { 2432 regcache_cache_bypass(rt1320->regmap, true); 2433 regcache_cache_bypass(rt1320->mbq_regmap, true); 2434 } else { 2435 /* 2436 * PM runtime status is marked as 'active' only when a Slave reports as Attached 2437 */ 2438 /* update count of parent 'active' children */ 2439 pm_runtime_set_active(&slave->dev); 2440 } 2441 2442 pm_runtime_get_noresume(&slave->dev); 2443 2444 if (rt1320->version_id < 0) { 2445 regmap_read(rt1320->regmap, RT1320_DEV_VERSION_ID_1, &val); 2446 rt1320->version_id = val; 2447 regmap_read(rt1320->regmap, RT1320_DEV_ID_0, &val); 2448 regmap_read(rt1320->regmap, RT1320_DEV_ID_1, &tmp); 2449 rt1320->dev_id = (val << 8) | tmp; 2450 2451 /* This is a workaround that reads the value twice to obtain the correct result. */ 2452 rt1320_pr_read(rt1320, RT1320_HV_DEV_ID_0, &val); 2453 rt1320_pr_read(rt1320, RT1320_HV_DEV_ID_1, &tmp); 2454 rt1320_pr_read(rt1320, RT1320_HV_DEV_ID_0, &val); 2455 rt1320_pr_read(rt1320, RT1320_HV_DEV_ID_1, &tmp); 2456 val = (val << 8) | tmp; 2457 2458 if (rt1320->dev_id == RT1321_DEV_ID) { 2459 if (rt1320->version_id == 0x01) 2460 rt1320->version_id = RT1321_VA2; 2461 else if (val == RT1321_DEV_HV_VA0_ID) 2462 rt1320->version_id = RT1321_VA0; 2463 else if (val == RT1321_DEV_HV_VA1_ID) 2464 rt1320->version_id = RT1321_VA1; 2465 else 2466 dev_err(dev, "%s: Unknown version ID 0x%x for RT1321\n", __func__, rt1320->version_id); 2467 } 2468 } 2469 2470 regmap_read(rt1320->regmap, 2471 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0), &_func_status); 2472 dev_dbg(dev, "%s amp func_status=0x%x\n", __func__, amp_func_status); 2473 2474 /* initialization write */ 2475 if ((amp_func_status & FUNCTION_NEEDS_INITIALIZATION)) { 2476 switch (rt1320->dev_id) { 2477 case RT1320_DEV_ID: 2478 if (rt1320->version_id < RT1320_VC) 2479 rt1320_vab_preset(rt1320); 2480 else 2481 rt1320_vc_preset(rt1320); 2482 break; 2483 case RT1321_DEV_ID: 2484 rt1321_preset(rt1320); 2485 break; 2486 default: 2487 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 2488 } 2489 2490 regmap_write(rt1320->regmap, 2491 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0), 2492 FUNCTION_NEEDS_INITIALIZATION); 2493 2494 /* reload DSP FW */ 2495 if (rt1320->fw_load_done) 2496 schedule_work(&rt1320->load_dspfw_work); 2497 } 2498 if (!rt1320->first_hw_init && rt1320->version_id == RT1320_VA && rt1320->dev_id == RT1320_DEV_ID) { 2499 regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 2500 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0); 2501 regmap_read(rt1320->regmap, RT1320_HIFI_VER_0, &val); 2502 regmap_read(rt1320->regmap, RT1320_HIFI_VER_1, &tmp); 2503 val = (tmp << 8) | val; 2504 regmap_read(rt1320->regmap, RT1320_HIFI_VER_2, &tmp); 2505 val = (tmp << 16) | val; 2506 regmap_read(rt1320->regmap, RT1320_HIFI_VER_3, &tmp); 2507 val = (tmp << 24) | val; 2508 dev_dbg(dev, "%s ROM version=0x%x\n", __func__, val); 2509 /* 2510 * We call the version b which has the new DSP ROM code against version a. 2511 * Therefore, we read the DSP address to check the ID. 2512 */ 2513 if (val == RT1320_VER_B_ID) 2514 rt1320->version_id = RT1320_VB; 2515 regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 2516 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 3); 2517 } 2518 dev_dbg(dev, "%s version_id=%d, dev_id=0x%x\n", __func__, rt1320->version_id, rt1320->dev_id); 2519 2520 if (rt1320->first_hw_init) { 2521 regcache_cache_bypass(rt1320->regmap, false); 2522 regcache_cache_bypass(rt1320->mbq_regmap, false); 2523 regcache_mark_dirty(rt1320->regmap); 2524 regcache_mark_dirty(rt1320->mbq_regmap); 2525 } 2526 2527 /* Mark Slave initialization complete */ 2528 rt1320->first_hw_init = true; 2529 rt1320->hw_init = true; 2530 2531 pm_runtime_put_autosuspend(&slave->dev); 2532 2533 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__); 2534 return 0; 2535 } 2536 2537 static int rt1320_update_status(struct sdw_slave *slave, 2538 enum sdw_slave_status status) 2539 { 2540 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(&slave->dev); 2541 2542 if (status == SDW_SLAVE_UNATTACHED) 2543 rt1320->hw_init = false; 2544 2545 /* 2546 * Perform initialization only if slave status is present and 2547 * hw_init flag is false 2548 */ 2549 if (rt1320->hw_init || status != SDW_SLAVE_ATTACHED) 2550 return 0; 2551 2552 /* perform I/O transfers required for Slave initialization */ 2553 return rt1320_io_init(&slave->dev, slave); 2554 } 2555 2556 static int rt1320_pde11_event(struct snd_soc_dapm_widget *w, 2557 struct snd_kcontrol *kcontrol, int event) 2558 { 2559 struct snd_soc_component *component = 2560 snd_soc_dapm_to_component(w->dapm); 2561 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2562 unsigned char ps0 = 0x0, ps3 = 0x3; 2563 2564 switch (event) { 2565 case SND_SOC_DAPM_POST_PMU: 2566 regmap_write(rt1320->regmap, 2567 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, 2568 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 2569 rt1320_pde_transition_delay(rt1320, FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, ps0); 2570 break; 2571 case SND_SOC_DAPM_PRE_PMD: 2572 regmap_write(rt1320->regmap, 2573 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, 2574 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 2575 rt1320_pde_transition_delay(rt1320, FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, ps3); 2576 break; 2577 default: 2578 break; 2579 } 2580 2581 return 0; 2582 } 2583 2584 static int rt1320_pde23_event(struct snd_soc_dapm_widget *w, 2585 struct snd_kcontrol *kcontrol, int event) 2586 { 2587 struct snd_soc_component *component = 2588 snd_soc_dapm_to_component(w->dapm); 2589 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2590 unsigned char ps0 = 0x0, ps3 = 0x3; 2591 2592 switch (event) { 2593 case SND_SOC_DAPM_POST_PMU: 2594 regmap_write(rt1320->regmap, 2595 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 2596 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 2597 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, ps0); 2598 break; 2599 case SND_SOC_DAPM_PRE_PMD: 2600 regmap_write(rt1320->regmap, 2601 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 2602 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 2603 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, ps3); 2604 break; 2605 default: 2606 break; 2607 } 2608 2609 return 0; 2610 } 2611 2612 static int rt1320_set_gain_put(struct snd_kcontrol *kcontrol, 2613 struct snd_ctl_elem_value *ucontrol) 2614 { 2615 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2616 struct soc_mixer_control *mc = 2617 (struct soc_mixer_control *)kcontrol->private_value; 2618 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2619 unsigned int gain_l_val, gain_r_val; 2620 unsigned int lvalue, rvalue; 2621 const unsigned int interval_offset = 0xc0; 2622 unsigned int changed = 0, reg_base; 2623 struct rt_sdca_dmic_kctrl_priv *p; 2624 unsigned int regvalue[4], gain_val[4], i; 2625 int err; 2626 2627 if (strstr(ucontrol->id.name, "FU Capture Volume")) 2628 goto _dmic_vol_; 2629 2630 regmap_read(rt1320->mbq_regmap, mc->reg, &lvalue); 2631 regmap_read(rt1320->mbq_regmap, mc->rreg, &rvalue); 2632 2633 /* L Channel */ 2634 gain_l_val = ucontrol->value.integer.value[0]; 2635 if (gain_l_val > mc->max) 2636 gain_l_val = mc->max; 2637 gain_l_val = 0 - ((mc->max - gain_l_val) * interval_offset); 2638 gain_l_val &= 0xffff; 2639 2640 /* R Channel */ 2641 gain_r_val = ucontrol->value.integer.value[1]; 2642 if (gain_r_val > mc->max) 2643 gain_r_val = mc->max; 2644 gain_r_val = 0 - ((mc->max - gain_r_val) * interval_offset); 2645 gain_r_val &= 0xffff; 2646 2647 if (lvalue == gain_l_val && rvalue == gain_r_val) 2648 return 0; 2649 2650 /* Lch*/ 2651 regmap_write(rt1320->mbq_regmap, mc->reg, gain_l_val); 2652 /* Rch */ 2653 regmap_write(rt1320->mbq_regmap, mc->rreg, gain_r_val); 2654 goto _done_; 2655 2656 _dmic_vol_: 2657 p = (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 2658 2659 /* check all channels */ 2660 for (i = 0; i < p->count; i++) { 2661 switch (rt1320->dev_id) { 2662 case RT1320_DEV_ID: 2663 if (i < 2) { 2664 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 2665 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value[i]); 2666 } else { 2667 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 2668 regmap_read(rt1320->mbq_regmap, reg_base + i - 2, ®value[i]); 2669 } 2670 break; 2671 case RT1321_DEV_ID: 2672 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 2673 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value[i]); 2674 break; 2675 } 2676 2677 gain_val[i] = ucontrol->value.integer.value[i]; 2678 if (gain_val[i] > p->max) 2679 gain_val[i] = p->max; 2680 2681 gain_val[i] = 0x1e00 - ((p->max - gain_val[i]) * interval_offset); 2682 gain_val[i] &= 0xffff; 2683 if (regvalue[i] != gain_val[i]) 2684 changed = 1; 2685 } 2686 2687 if (!changed) 2688 return 0; 2689 2690 for (i = 0; i < p->count; i++) { 2691 switch (rt1320->dev_id) { 2692 case RT1320_DEV_ID: 2693 if (i < 2) { 2694 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 2695 err = regmap_write(rt1320->mbq_regmap, reg_base + i, gain_val[i]); 2696 } else { 2697 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 2698 err = regmap_write(rt1320->mbq_regmap, reg_base + i - 2, gain_val[i]); 2699 } 2700 break; 2701 case RT1321_DEV_ID: 2702 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 2703 err = regmap_write(rt1320->mbq_regmap, reg_base + i, gain_val[i]); 2704 break; 2705 } 2706 2707 if (err < 0) 2708 dev_err(&rt1320->sdw_slave->dev, "0x%08x can't be set\n", reg_base + i); 2709 } 2710 2711 _done_: 2712 return 1; 2713 } 2714 2715 static int rt1320_set_gain_get(struct snd_kcontrol *kcontrol, 2716 struct snd_ctl_elem_value *ucontrol) 2717 { 2718 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2719 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2720 struct soc_mixer_control *mc = 2721 (struct soc_mixer_control *)kcontrol->private_value; 2722 unsigned int read_l, read_r, ctl_l = 0, ctl_r = 0; 2723 const unsigned int interval_offset = 0xc0; 2724 unsigned int reg_base, regvalue, ctl, i; 2725 struct rt_sdca_dmic_kctrl_priv *p; 2726 2727 if (strstr(ucontrol->id.name, "FU Capture Volume")) 2728 goto _dmic_vol_; 2729 2730 regmap_read(rt1320->mbq_regmap, mc->reg, &read_l); 2731 regmap_read(rt1320->mbq_regmap, mc->rreg, &read_r); 2732 2733 ctl_l = mc->max - (((0 - read_l) & 0xffff) / interval_offset); 2734 2735 if (read_l != read_r) 2736 ctl_r = mc->max - (((0 - read_r) & 0xffff) / interval_offset); 2737 else 2738 ctl_r = ctl_l; 2739 2740 ucontrol->value.integer.value[0] = ctl_l; 2741 ucontrol->value.integer.value[1] = ctl_r; 2742 goto _done_; 2743 2744 _dmic_vol_: 2745 p = (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 2746 2747 /* check all channels */ 2748 for (i = 0; i < p->count; i++) { 2749 switch (rt1320->dev_id) { 2750 case RT1320_DEV_ID: 2751 if (i < 2) { 2752 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 2753 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value); 2754 } else { 2755 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 2756 regmap_read(rt1320->mbq_regmap, reg_base + i - 2, ®value); 2757 } 2758 break; 2759 case RT1321_DEV_ID: 2760 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01); 2761 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value); 2762 break; 2763 } 2764 2765 ctl = p->max - (((0x1e00 - regvalue) & 0xffff) / interval_offset); 2766 ucontrol->value.integer.value[i] = ctl; 2767 } 2768 _done_: 2769 return 0; 2770 } 2771 2772 static int rt1320_set_fu_capture_ctl(struct rt1320_sdw_priv *rt1320) 2773 { 2774 int err, i; 2775 unsigned int ch_mute; 2776 2777 for (i = 0; i < ARRAY_SIZE(rt1320->fu_mixer_mute); i++) { 2778 ch_mute = (rt1320->fu_dapm_mute || rt1320->fu_mixer_mute[i]) ? 0x01 : 0x00; 2779 2780 switch (rt1320->dev_id) { 2781 case RT1320_DEV_ID: 2782 if (i < 2) 2783 err = regmap_write(rt1320->regmap, 2784 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, 2785 RT1320_SDCA_CTL_FU_MUTE, CH_01) + i, ch_mute); 2786 else 2787 err = regmap_write(rt1320->regmap, 2788 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, 2789 RT1320_SDCA_CTL_FU_MUTE, CH_01) + i - 2, ch_mute); 2790 break; 2791 case RT1321_DEV_ID: 2792 err = regmap_write(rt1320->regmap, 2793 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, 2794 RT1320_SDCA_CTL_FU_MUTE, CH_01) + i, ch_mute); 2795 break; 2796 default: 2797 dev_err(&rt1320->sdw_slave->dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 2798 return -EINVAL; 2799 } 2800 if (err < 0) 2801 return err; 2802 } 2803 2804 return 0; 2805 } 2806 2807 static int rt1320_dmic_fu_capture_get(struct snd_kcontrol *kcontrol, 2808 struct snd_ctl_elem_value *ucontrol) 2809 { 2810 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2811 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2812 struct rt_sdca_dmic_kctrl_priv *p = 2813 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 2814 unsigned int i; 2815 2816 for (i = 0; i < p->count; i++) 2817 ucontrol->value.integer.value[i] = !rt1320->fu_mixer_mute[i]; 2818 2819 return 0; 2820 } 2821 2822 static int rt1320_dmic_fu_capture_put(struct snd_kcontrol *kcontrol, 2823 struct snd_ctl_elem_value *ucontrol) 2824 { 2825 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2826 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2827 struct rt_sdca_dmic_kctrl_priv *p = 2828 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 2829 int err, changed = 0, i; 2830 2831 for (i = 0; i < p->count; i++) { 2832 if (rt1320->fu_mixer_mute[i] != !ucontrol->value.integer.value[i]) 2833 changed = 1; 2834 rt1320->fu_mixer_mute[i] = !ucontrol->value.integer.value[i]; 2835 } 2836 2837 err = rt1320_set_fu_capture_ctl(rt1320); 2838 if (err < 0) 2839 return err; 2840 2841 return changed; 2842 } 2843 2844 static int rt1320_dmic_fu_info(struct snd_kcontrol *kcontrol, 2845 struct snd_ctl_elem_info *uinfo) 2846 { 2847 struct rt_sdca_dmic_kctrl_priv *p = 2848 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value; 2849 2850 if (p->max == 1) 2851 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 2852 else 2853 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2854 uinfo->count = p->count; 2855 uinfo->value.integer.min = 0; 2856 uinfo->value.integer.max = p->max; 2857 return 0; 2858 } 2859 2860 static int rt1320_dmic_fu_event(struct snd_soc_dapm_widget *w, 2861 struct snd_kcontrol *kcontrol, int event) 2862 { 2863 struct snd_soc_component *component = 2864 snd_soc_dapm_to_component(w->dapm); 2865 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2866 2867 switch (event) { 2868 case SND_SOC_DAPM_POST_PMU: 2869 rt1320->fu_dapm_mute = false; 2870 rt1320_set_fu_capture_ctl(rt1320); 2871 break; 2872 case SND_SOC_DAPM_PRE_PMD: 2873 rt1320->fu_dapm_mute = true; 2874 rt1320_set_fu_capture_ctl(rt1320); 2875 break; 2876 } 2877 return 0; 2878 } 2879 2880 static const char * const rt1320_rx_data_ch_select[] = { 2881 "L,R", 2882 "R,L", 2883 "L,L", 2884 "R,R", 2885 "L,L+R", 2886 "R,L+R", 2887 "L+R,L", 2888 "L+R,R", 2889 "L+R,L+R", 2890 }; 2891 2892 static SOC_ENUM_SINGLE_DECL(rt1320_rx_data_ch_enum, 2893 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0, 2894 rt1320_rx_data_ch_select); 2895 2896 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0); 2897 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -1725, 75, 0); 2898 2899 static int rt1320_r0_load(struct rt1320_sdw_priv *rt1320) 2900 { 2901 struct device *dev = regmap_get_device(rt1320->regmap); 2902 int dspfw_status; 2903 int ret = 0; 2904 2905 if (!rt1320->r0_l_reg || !rt1320->r0_r_reg) 2906 return -EINVAL; 2907 2908 regmap_write(rt1320->regmap, 2909 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00); 2910 ret = rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x00); 2911 if (ret < 0) { 2912 dev_dbg(dev, "%s, PDE=PS0 is NOT ready\n", __func__); 2913 goto _timeout_; 2914 } 2915 2916 dspfw_status = rt1320_dspfw_status(rt1320); 2917 if (dspfw_status <= 0) { 2918 dev_dbg(dev, "%s, DSP FW is NOT ready\n", __func__); 2919 goto _timeout_; 2920 } 2921 2922 ret = rt1320_check_power_state_ready(rt1320, RT1320_NORMAL_STATE); 2923 if (ret < 0) { 2924 dev_dbg(dev, "%s, DSP FW PS is NOT ready\n", __func__); 2925 goto _timeout_; 2926 } 2927 2928 rt1320_set_advancemode(rt1320); 2929 2930 _timeout_: 2931 regmap_write(rt1320->regmap, 2932 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03); 2933 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x03); 2934 2935 return ret; 2936 } 2937 2938 static int rt1320_r0_load_mode_get(struct snd_kcontrol *kcontrol, 2939 struct snd_ctl_elem_value *ucontrol) 2940 { 2941 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2942 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2943 2944 ucontrol->value.integer.value[0] = rt1320->r0_l_reg; 2945 ucontrol->value.integer.value[1] = rt1320->r0_r_reg; 2946 2947 return 0; 2948 } 2949 2950 static int rt1320_r0_load_mode_put(struct snd_kcontrol *kcontrol, 2951 struct snd_ctl_elem_value *ucontrol) 2952 { 2953 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2954 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 2955 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(rt1320->component); 2956 int ret; 2957 2958 if (!rt1320->hw_init) 2959 return 0; 2960 2961 if (ucontrol->value.integer.value[0] == 0 || 2962 ucontrol->value.integer.value[1] == 0) 2963 return -EINVAL; 2964 2965 ret = pm_runtime_resume(component->dev); 2966 if (ret < 0 && ret != -EACCES) 2967 return ret; 2968 2969 snd_soc_dapm_mutex_lock(dapm); 2970 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) { 2971 rt1320->r0_l_reg = ucontrol->value.integer.value[0]; 2972 rt1320->r0_r_reg = ucontrol->value.integer.value[1]; 2973 rt1320_calc_r0(rt1320); 2974 rt1320_r0_load(rt1320); 2975 } 2976 snd_soc_dapm_mutex_unlock(dapm); 2977 2978 return 0; 2979 } 2980 2981 static int rt1320_t0_r0_load_info(struct snd_kcontrol *kcontrol, 2982 struct snd_ctl_elem_info *uinfo) 2983 { 2984 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2985 uinfo->count = 2; 2986 uinfo->value.integer.max = kcontrol->private_value; 2987 2988 return 0; 2989 } 2990 2991 #define RT1320_T0_R0_LOAD(xname, xmax, xhandler_get, xhandler_put) \ 2992 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 2993 .info = rt1320_t0_r0_load_info, \ 2994 .get = xhandler_get, \ 2995 .put = xhandler_put, \ 2996 .private_value = xmax, \ 2997 } 2998 2999 static int rt1320_dspfw_load_get(struct snd_kcontrol *kcontrol, 3000 struct snd_ctl_elem_value *ucontrol) 3001 { 3002 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 3003 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 3004 3005 ucontrol->value.integer.value[0] = rt1320->fw_load_done; 3006 return 0; 3007 } 3008 3009 static int rt1320_dspfw_load_put(struct snd_kcontrol *kcontrol, 3010 struct snd_ctl_elem_value *ucontrol) 3011 { 3012 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 3013 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 3014 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 3015 int ret; 3016 3017 if (!rt1320->hw_init) 3018 return 0; 3019 3020 ret = pm_runtime_resume_and_get(component->dev); 3021 if (ret < 0 && ret != -EACCES) 3022 return ret; 3023 3024 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF && 3025 ucontrol->value.integer.value[0]) 3026 rt1320_dspfw_load_code(rt1320); 3027 3028 if (!ucontrol->value.integer.value[0]) 3029 rt1320->fw_load_done = false; 3030 3031 pm_runtime_mark_last_busy(component->dev); 3032 pm_runtime_put_autosuspend(component->dev); 3033 return 0; 3034 } 3035 3036 static int rt1320_rae_update_get(struct snd_kcontrol *kcontrol, 3037 struct snd_ctl_elem_value *ucontrol) 3038 { 3039 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 3040 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 3041 3042 ucontrol->value.integer.value[0] = rt1320->rae_update_done; 3043 return 0; 3044 } 3045 3046 static int rt1320_rae_update_put(struct snd_kcontrol *kcontrol, 3047 struct snd_ctl_elem_value *ucontrol) 3048 { 3049 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 3050 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 3051 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 3052 int ret; 3053 3054 if (!rt1320->hw_init) 3055 return 0; 3056 3057 ret = pm_runtime_resume(component->dev); 3058 if (ret < 0 && ret != -EACCES) 3059 return ret; 3060 3061 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF && 3062 ucontrol->value.integer.value[0] && rt1320->fw_load_done) 3063 rt1320_rae_load(rt1320); 3064 3065 if (!ucontrol->value.integer.value[0]) 3066 rt1320->rae_update_done = false; 3067 3068 return 0; 3069 } 3070 3071 static int rt1320_brown_out_put(struct snd_kcontrol *kcontrol, 3072 struct snd_ctl_elem_value *ucontrol) 3073 { 3074 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 3075 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 3076 int ret, changed = 0; 3077 3078 if (!rt1320->hw_init) 3079 return 0; 3080 3081 ret = pm_runtime_resume(component->dev); 3082 if (ret < 0 && ret != -EACCES) 3083 return ret; 3084 3085 if (rt1320->brown_out != ucontrol->value.integer.value[0]) { 3086 changed = 1; 3087 rt1320->brown_out = ucontrol->value.integer.value[0]; 3088 } 3089 3090 if (rt1320->brown_out == 0) 3091 regmap_write(rt1320->regmap, 0xdb03, 0x00); 3092 else 3093 regmap_write(rt1320->regmap, 0xdb03, 0xf0); 3094 3095 3096 return changed; 3097 } 3098 3099 static int rt1320_brown_out_get(struct snd_kcontrol *kcontrol, 3100 struct snd_ctl_elem_value *ucontrol) 3101 { 3102 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 3103 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 3104 3105 ucontrol->value.integer.value[0] = rt1320->brown_out; 3106 3107 return 0; 3108 } 3109 3110 static int rt1320_r0_temperature_get(struct snd_kcontrol *kcontrol, 3111 struct snd_ctl_elem_value *ucontrol) 3112 { 3113 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 3114 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 3115 3116 ucontrol->value.integer.value[0] = rt1320->temp_l_calib; 3117 ucontrol->value.integer.value[1] = rt1320->temp_r_calib; 3118 return 0; 3119 } 3120 3121 static int rt1320_r0_temperature_put(struct snd_kcontrol *kcontrol, 3122 struct snd_ctl_elem_value *ucontrol) 3123 { 3124 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 3125 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 3126 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(rt1320->component); 3127 int ret; 3128 3129 if (!rt1320->hw_init) 3130 return 0; 3131 3132 ret = pm_runtime_resume(component->dev); 3133 if (ret < 0 && ret != -EACCES) 3134 return ret; 3135 3136 snd_soc_dapm_mutex_lock(dapm); 3137 if ((snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) && 3138 ucontrol->value.integer.value[0] && ucontrol->value.integer.value[1]) 3139 rt1320_t0_load(rt1320, ucontrol->value.integer.value[0], ucontrol->value.integer.value[1]); 3140 snd_soc_dapm_mutex_unlock(dapm); 3141 3142 return 0; 3143 } 3144 3145 static const struct snd_kcontrol_new rt1320_snd_controls[] = { 3146 SOC_DOUBLE_R_EXT_TLV("FU21 Playback Volume", 3147 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 3148 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 3149 0, 0x57, 0, rt1320_set_gain_get, rt1320_set_gain_put, out_vol_tlv), 3150 SOC_ENUM("RX Channel Select", rt1320_rx_data_ch_enum), 3151 3152 RT_SDCA_FU_CTRL("FU Capture Switch", 3153 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01), 3154 1, 1, 4, rt1320_dmic_fu_info, rt1320_dmic_fu_capture_get, rt1320_dmic_fu_capture_put), 3155 RT_SDCA_EXT_TLV("FU Capture Volume", 3156 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 3157 rt1320_set_gain_get, rt1320_set_gain_put, 4, 0x3f, in_vol_tlv, rt1320_dmic_fu_info), 3158 3159 SOC_SINGLE_EXT("R0 Calibration", SND_SOC_NOPM, 0, 1, 0, 3160 rt1320_r0_cali_get, rt1320_r0_cali_put), 3161 SOC_SINGLE_EXT("DSP FW Update", SND_SOC_NOPM, 0, 1, 0, 3162 rt1320_dspfw_load_get, rt1320_dspfw_load_put), 3163 RT1320_T0_R0_LOAD("R0 Load Mode", 0xffffffff, 3164 rt1320_r0_load_mode_get, rt1320_r0_load_mode_put), 3165 RT1320_T0_R0_LOAD("R0 Temperature", 0xff, 3166 rt1320_r0_temperature_get, rt1320_r0_temperature_put), 3167 SOC_SINGLE_EXT("RAE Update", SND_SOC_NOPM, 0, 1, 0, 3168 rt1320_rae_update_get, rt1320_rae_update_put), 3169 SOC_SINGLE_EXT("Brown Out Switch", SND_SOC_NOPM, 0, 1, 0, 3170 rt1320_brown_out_get, rt1320_brown_out_put), 3171 }; 3172 3173 static const struct snd_kcontrol_new rt1320_spk_l_dac = 3174 SOC_DAPM_SINGLE_AUTODISABLE("Switch", 3175 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01), 3176 0, 1, 1); 3177 static const struct snd_kcontrol_new rt1320_spk_r_dac = 3178 SOC_DAPM_SINGLE_AUTODISABLE("Switch", 3179 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02), 3180 0, 1, 1); 3181 3182 static const struct snd_soc_dapm_widget rt1320_dapm_widgets[] = { 3183 /* Audio Interface */ 3184 SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0), 3185 SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0), 3186 SND_SOC_DAPM_AIF_OUT("DP8-10TX", "DP8-10 Capture", 0, SND_SOC_NOPM, 0, 0), 3187 3188 /* Digital Interface */ 3189 SND_SOC_DAPM_PGA("FU21", SND_SOC_NOPM, 0, 0, NULL, 0), 3190 SND_SOC_DAPM_SUPPLY("PDE 23", SND_SOC_NOPM, 0, 0, 3191 rt1320_pde23_event, 3192 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 3193 SND_SOC_DAPM_SUPPLY("PDE 11", SND_SOC_NOPM, 0, 0, 3194 rt1320_pde11_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 3195 SND_SOC_DAPM_ADC("FU 113", NULL, SND_SOC_NOPM, 0, 0), 3196 SND_SOC_DAPM_ADC("FU 14", NULL, SND_SOC_NOPM, 0, 0), 3197 SND_SOC_DAPM_PGA_E("FU", SND_SOC_NOPM, 0, 0, NULL, 0, 3198 rt1320_dmic_fu_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 3199 3200 /* Output */ 3201 SND_SOC_DAPM_SWITCH("OT23 L", SND_SOC_NOPM, 0, 0, &rt1320_spk_l_dac), 3202 SND_SOC_DAPM_SWITCH("OT23 R", SND_SOC_NOPM, 0, 0, &rt1320_spk_r_dac), 3203 SND_SOC_DAPM_OUTPUT("SPOL"), 3204 SND_SOC_DAPM_OUTPUT("SPOR"), 3205 3206 /* Input */ 3207 SND_SOC_DAPM_PGA("AEC Data", SND_SOC_NOPM, 0, 0, NULL, 0), 3208 SND_SOC_DAPM_SIGGEN("AEC Gen"), 3209 SND_SOC_DAPM_INPUT("DMIC1"), 3210 SND_SOC_DAPM_INPUT("DMIC2"), 3211 }; 3212 3213 static const struct snd_soc_dapm_route rt1320_dapm_routes[] = { 3214 { "FU21", NULL, "DP1RX" }, 3215 { "FU21", NULL, "PDE 23" }, 3216 { "OT23 L", "Switch", "FU21" }, 3217 { "OT23 R", "Switch", "FU21" }, 3218 { "SPOL", NULL, "OT23 L" }, 3219 { "SPOR", NULL, "OT23 R" }, 3220 3221 { "AEC Data", NULL, "AEC Gen" }, 3222 { "DP4TX", NULL, "AEC Data" }, 3223 3224 {"DP8-10TX", NULL, "FU"}, 3225 {"FU", NULL, "PDE 11"}, 3226 {"FU", NULL, "FU 113"}, 3227 {"FU", NULL, "FU 14"}, 3228 {"FU 113", NULL, "DMIC1"}, 3229 {"FU 14", NULL, "DMIC2"}, 3230 }; 3231 3232 static int rt1320_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, 3233 int direction) 3234 { 3235 snd_soc_dai_dma_data_set(dai, direction, sdw_stream); 3236 return 0; 3237 } 3238 3239 static void rt1320_sdw_shutdown(struct snd_pcm_substream *substream, 3240 struct snd_soc_dai *dai) 3241 { 3242 snd_soc_dai_set_dma_data(dai, substream, NULL); 3243 } 3244 3245 static int rt1320_sdw_hw_params(struct snd_pcm_substream *substream, 3246 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 3247 { 3248 struct snd_soc_component *component = dai->component; 3249 struct rt1320_sdw_priv *rt1320 = 3250 snd_soc_component_get_drvdata(component); 3251 struct sdw_stream_config stream_config = {0}; 3252 struct sdw_port_config port_config; 3253 struct sdw_port_config dmic_port_config[2]; 3254 struct sdw_stream_runtime *sdw_stream; 3255 int retval, num_channels; 3256 unsigned int sampling_rate; 3257 3258 dev_dbg(dai->dev, "%s %s", __func__, dai->name); 3259 sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 3260 3261 if (!sdw_stream) 3262 return -EINVAL; 3263 3264 if (!rt1320->sdw_slave) 3265 return -EINVAL; 3266 3267 /* SoundWire specific configuration */ 3268 snd_sdw_params_to_config(substream, params, &stream_config, &port_config); 3269 3270 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 3271 if (dai->id == RT1320_AIF1) 3272 port_config.num = 1; 3273 else 3274 return -EINVAL; 3275 } else { 3276 if (dai->id == RT1320_AIF1) 3277 port_config.num = 4; 3278 else if (dai->id == RT1320_AIF2) { 3279 switch (rt1320->dev_id) { 3280 case RT1320_DEV_ID: 3281 dmic_port_config[0].ch_mask = BIT(0) | BIT(1); 3282 dmic_port_config[0].num = 8; 3283 dmic_port_config[1].ch_mask = BIT(0) | BIT(1); 3284 dmic_port_config[1].num = 10; 3285 break; 3286 case RT1321_DEV_ID: 3287 num_channels = params_channels(params); 3288 dmic_port_config[0].ch_mask = GENMASK(num_channels - 1, 0); 3289 dmic_port_config[0].num = 8; 3290 break; 3291 default: 3292 return -EINVAL; 3293 } 3294 } else 3295 return -EINVAL; 3296 } 3297 3298 if (dai->id == RT1320_AIF1) 3299 retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config, 3300 &port_config, 1, sdw_stream); 3301 else if (dai->id == RT1320_AIF2) { 3302 switch (rt1320->dev_id) { 3303 case RT1320_DEV_ID: 3304 retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config, 3305 dmic_port_config, 2, sdw_stream); 3306 break; 3307 case RT1321_DEV_ID: 3308 retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config, 3309 dmic_port_config, 1, sdw_stream); 3310 break; 3311 default: 3312 dev_err(dai->dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id); 3313 return -EINVAL; 3314 } 3315 } else 3316 return -EINVAL; 3317 if (retval) { 3318 dev_err(dai->dev, "%s: Unable to configure port\n", __func__); 3319 return retval; 3320 } 3321 3322 /* sampling rate configuration */ 3323 switch (params_rate(params)) { 3324 case 16000: 3325 sampling_rate = RT1320_SDCA_RATE_16000HZ; 3326 break; 3327 case 32000: 3328 sampling_rate = RT1320_SDCA_RATE_32000HZ; 3329 break; 3330 case 44100: 3331 sampling_rate = RT1320_SDCA_RATE_44100HZ; 3332 break; 3333 case 48000: 3334 sampling_rate = RT1320_SDCA_RATE_48000HZ; 3335 break; 3336 case 96000: 3337 sampling_rate = RT1320_SDCA_RATE_96000HZ; 3338 break; 3339 case 192000: 3340 sampling_rate = RT1320_SDCA_RATE_192000HZ; 3341 break; 3342 default: 3343 dev_err(component->dev, "%s: Rate %d is not supported\n", 3344 __func__, params_rate(params)); 3345 return -EINVAL; 3346 } 3347 3348 /* set sampling frequency */ 3349 if (dai->id == RT1320_AIF1) 3350 regmap_write(rt1320->regmap, 3351 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 3352 sampling_rate); 3353 else { 3354 regmap_write(rt1320->regmap, 3355 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 3356 sampling_rate); 3357 3358 if (rt1320->dev_id == RT1320_DEV_ID) 3359 regmap_write(rt1320->regmap, 3360 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 3361 sampling_rate); 3362 } 3363 3364 return 0; 3365 } 3366 3367 static int rt1320_sdw_pcm_hw_free(struct snd_pcm_substream *substream, 3368 struct snd_soc_dai *dai) 3369 { 3370 struct snd_soc_component *component = dai->component; 3371 struct rt1320_sdw_priv *rt1320 = 3372 snd_soc_component_get_drvdata(component); 3373 struct sdw_stream_runtime *sdw_stream = 3374 snd_soc_dai_get_dma_data(dai, substream); 3375 3376 if (!rt1320->sdw_slave) 3377 return -EINVAL; 3378 3379 sdw_stream_remove_slave(rt1320->sdw_slave, sdw_stream); 3380 return 0; 3381 } 3382 3383 static int rt1320_bus_config(struct sdw_slave *slave, 3384 struct sdw_bus_params *params) 3385 { 3386 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(&slave->dev); 3387 unsigned int clk_base; 3388 3389 regmap_read(rt1320->regmap, 0x004d, &clk_base); 3390 dev_dbg(&rt1320->sdw_slave->dev, "%s clk_base=%x", __func__, clk_base); 3391 3392 switch (clk_base) { 3393 case RT1320_CLK_FREQ_19_2_MHZ: 3394 case RT1320_CLK_FREQ_24MHZ: 3395 regmap_write(rt1320->regmap, 0xc600, 0x04); 3396 regmap_write(rt1320->regmap, 0xc601, 0x83); 3397 regmap_write(rt1320->regmap, 0xc602, 0x1f); 3398 regmap_write(rt1320->regmap, 0xc603, 0x40); 3399 break; 3400 case RT1320_CLK_FREQ_24_576MHZ: 3401 case RT1320_CLK_FREQ_22_5792MHZ: 3402 regmap_write(rt1320->regmap, 0xc600, 0x07); 3403 regmap_write(rt1320->regmap, 0xc601, 0x80); 3404 regmap_write(rt1320->regmap, 0xc602, 0x0f); 3405 regmap_write(rt1320->regmap, 0xc603, 0x40); 3406 break; 3407 default: 3408 return -EINVAL; 3409 } 3410 3411 return 0; 3412 } 3413 3414 /* 3415 * slave_ops: callbacks for get_clock_stop_mode, clock_stop and 3416 * port_prep are not defined for now 3417 */ 3418 static const struct sdw_slave_ops rt1320_slave_ops = { 3419 .read_prop = rt1320_read_prop, 3420 .update_status = rt1320_update_status, 3421 .bus_config = rt1320_bus_config, 3422 }; 3423 3424 static int rt1320_sdw_component_probe(struct snd_soc_component *component) 3425 { 3426 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); 3427 int ret; 3428 3429 rt1320->component = component; 3430 3431 if (!rt1320->first_hw_init) 3432 return 0; 3433 3434 ret = pm_runtime_resume(component->dev); 3435 dev_dbg(&rt1320->sdw_slave->dev, "%s pm_runtime_resume, ret=%d", __func__, ret); 3436 if (ret < 0 && ret != -EACCES) 3437 return ret; 3438 3439 /* Apply temperature and calibration data from device property */ 3440 if ((rt1320->temp_l_calib <= 0xff) && (rt1320->temp_l_calib > 0) && 3441 (rt1320->temp_r_calib <= 0xff) && (rt1320->temp_r_calib > 0)) 3442 rt1320_t0_load(rt1320, rt1320->temp_l_calib, rt1320->temp_r_calib); 3443 3444 if (rt1320->r0_l_calib && rt1320->r0_r_calib) { 3445 rt1320->r0_l_reg = rt1320->r0_l_calib; 3446 rt1320->r0_r_reg = rt1320->r0_r_calib; 3447 rt1320_calc_r0(rt1320); 3448 rt1320_r0_load(rt1320); 3449 } 3450 3451 return 0; 3452 } 3453 3454 static const struct snd_soc_component_driver soc_component_sdw_rt1320 = { 3455 .probe = rt1320_sdw_component_probe, 3456 .controls = rt1320_snd_controls, 3457 .num_controls = ARRAY_SIZE(rt1320_snd_controls), 3458 .dapm_widgets = rt1320_dapm_widgets, 3459 .num_dapm_widgets = ARRAY_SIZE(rt1320_dapm_widgets), 3460 .dapm_routes = rt1320_dapm_routes, 3461 .num_dapm_routes = ARRAY_SIZE(rt1320_dapm_routes), 3462 .endianness = 1, 3463 }; 3464 3465 static const struct snd_soc_dai_ops rt1320_aif_dai_ops = { 3466 .hw_params = rt1320_sdw_hw_params, 3467 .hw_free = rt1320_sdw_pcm_hw_free, 3468 .set_stream = rt1320_set_sdw_stream, 3469 .shutdown = rt1320_sdw_shutdown, 3470 }; 3471 3472 #define RT1320_STEREO_RATES (SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ 3473 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 3474 #define RT1320_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \ 3475 SNDRV_PCM_FMTBIT_S32_LE) 3476 3477 static struct snd_soc_dai_driver rt1320_sdw_dai[] = { 3478 { 3479 .name = "rt1320-aif1", 3480 .id = RT1320_AIF1, 3481 .playback = { 3482 .stream_name = "DP1 Playback", 3483 .channels_min = 1, 3484 .channels_max = 2, 3485 .rates = RT1320_STEREO_RATES, 3486 .formats = RT1320_FORMATS, 3487 }, 3488 .capture = { 3489 .stream_name = "DP4 Capture", 3490 .channels_min = 1, 3491 .channels_max = 2, 3492 .rates = RT1320_STEREO_RATES, 3493 .formats = RT1320_FORMATS, 3494 }, 3495 .ops = &rt1320_aif_dai_ops, 3496 }, 3497 /* DMIC: DP8 2ch + DP10 2ch */ 3498 { 3499 .name = "rt1320-aif2", 3500 .id = RT1320_AIF2, 3501 .capture = { 3502 .stream_name = "DP8-10 Capture", 3503 .channels_min = 1, 3504 .channels_max = 4, 3505 .rates = RT1320_STEREO_RATES, 3506 .formats = RT1320_FORMATS, 3507 }, 3508 .ops = &rt1320_aif_dai_ops, 3509 }, 3510 }; 3511 3512 static int rt1320_parse_dp(struct rt1320_sdw_priv *rt1320, struct device *dev) 3513 { 3514 device_property_read_u32(dev, "realtek,temperature_l_calib", 3515 &rt1320->temp_l_calib); 3516 device_property_read_u32(dev, "realtek,temperature_r_calib", 3517 &rt1320->temp_r_calib); 3518 device_property_read_u32(dev, "realtek,r0_l_calib", 3519 &rt1320->r0_l_calib); 3520 device_property_read_u32(dev, "realtek,r0_r_calib", 3521 &rt1320->r0_r_calib); 3522 device_property_read_string(dev, "realtek,dspfw-name", 3523 &rt1320->dspfw_name); 3524 3525 dev_dbg(dev, "%s: temp_l_calib: %d temp_r_calib: %d r0_l_calib: %d, r0_r_calib: %d", 3526 __func__, rt1320->temp_l_calib, rt1320->temp_r_calib, rt1320->r0_l_calib, rt1320->r0_r_calib); 3527 dev_dbg(dev, "%s: dspfw_name: %s", __func__, rt1320->dspfw_name); 3528 3529 return 0; 3530 } 3531 3532 static int rt1320_sdw_init(struct device *dev, struct regmap *regmap, 3533 struct regmap *mbq_regmap, struct sdw_slave *slave) 3534 { 3535 struct rt1320_sdw_priv *rt1320; 3536 int ret; 3537 3538 rt1320 = devm_kzalloc(dev, sizeof(*rt1320), GFP_KERNEL); 3539 if (!rt1320) 3540 return -ENOMEM; 3541 3542 dev_set_drvdata(dev, rt1320); 3543 rt1320->sdw_slave = slave; 3544 rt1320->mbq_regmap = mbq_regmap; 3545 rt1320->regmap = regmap; 3546 3547 regcache_cache_only(rt1320->regmap, true); 3548 regcache_cache_only(rt1320->mbq_regmap, true); 3549 3550 rt1320_parse_dp(rt1320, dev); 3551 3552 /* 3553 * Mark hw_init to false 3554 * HW init will be performed when device reports present 3555 */ 3556 rt1320->hw_init = false; 3557 rt1320->first_hw_init = false; 3558 rt1320->version_id = -1; 3559 rt1320->fu_dapm_mute = true; 3560 rt1320->fu_mixer_mute[0] = rt1320->fu_mixer_mute[1] = 3561 rt1320->fu_mixer_mute[2] = rt1320->fu_mixer_mute[3] = true; 3562 rt1320->brown_out = 1; 3563 3564 INIT_WORK(&rt1320->load_dspfw_work, rt1320_load_dspfw_work); 3565 3566 ret = devm_snd_soc_register_component(dev, 3567 &soc_component_sdw_rt1320, 3568 rt1320_sdw_dai, 3569 ARRAY_SIZE(rt1320_sdw_dai)); 3570 if (ret < 0) 3571 return ret; 3572 3573 /* set autosuspend parameters */ 3574 pm_runtime_set_autosuspend_delay(dev, 3000); 3575 pm_runtime_use_autosuspend(dev); 3576 3577 /* make sure the device does not suspend immediately */ 3578 pm_runtime_mark_last_busy(dev); 3579 3580 pm_runtime_enable(dev); 3581 3582 /* important note: the device is NOT tagged as 'active' and will remain 3583 * 'suspended' until the hardware is enumerated/initialized. This is required 3584 * to make sure the ASoC framework use of pm_runtime_get_sync() does not silently 3585 * fail with -EACCESS because of race conditions between card creation and enumeration 3586 */ 3587 3588 dev_dbg(dev, "%s\n", __func__); 3589 3590 return ret; 3591 } 3592 3593 static int rt1320_sdw_probe(struct sdw_slave *slave, 3594 const struct sdw_device_id *id) 3595 { 3596 struct regmap *regmap, *mbq_regmap; 3597 3598 /* Regmap Initialization */ 3599 mbq_regmap = devm_regmap_init_sdw_mbq(slave, &rt1320_mbq_regmap); 3600 if (IS_ERR(mbq_regmap)) 3601 return PTR_ERR(mbq_regmap); 3602 3603 regmap = devm_regmap_init_sdw(slave, &rt1320_sdw_regmap); 3604 if (IS_ERR(regmap)) 3605 return PTR_ERR(regmap); 3606 3607 return rt1320_sdw_init(&slave->dev, regmap, mbq_regmap, slave); 3608 } 3609 3610 static void rt1320_sdw_remove(struct sdw_slave *slave) 3611 { 3612 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(&slave->dev); 3613 3614 cancel_work_sync(&rt1320->load_dspfw_work); 3615 pm_runtime_disable(&slave->dev); 3616 } 3617 3618 /* 3619 * Version A/B will use the class id 0 3620 * The newer version than A/B will use the class id 1, so add it in advance 3621 */ 3622 static const struct sdw_device_id rt1320_id[] = { 3623 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x0, 0), 3624 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x1, 0), 3625 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1321, 0x3, 0x1, 0), 3626 {}, 3627 }; 3628 MODULE_DEVICE_TABLE(sdw, rt1320_id); 3629 3630 static int rt1320_dev_suspend(struct device *dev) 3631 { 3632 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); 3633 3634 if (!rt1320->hw_init) 3635 return 0; 3636 3637 regcache_cache_only(rt1320->regmap, true); 3638 regcache_cache_only(rt1320->mbq_regmap, true); 3639 return 0; 3640 } 3641 3642 #define RT1320_PROBE_TIMEOUT 5000 3643 3644 static int rt1320_dev_resume(struct device *dev) 3645 { 3646 struct sdw_slave *slave = dev_to_sdw_dev(dev); 3647 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); 3648 int ret; 3649 3650 if (!rt1320->first_hw_init) 3651 return 0; 3652 3653 ret = sdw_slave_wait_for_init(slave, RT1320_PROBE_TIMEOUT); 3654 if (ret) 3655 return ret; 3656 3657 regcache_cache_only(rt1320->regmap, false); 3658 ret = regcache_sync(rt1320->regmap); 3659 if (ret) 3660 goto err_sync; 3661 3662 regcache_cache_only(rt1320->mbq_regmap, false); 3663 ret = regcache_sync(rt1320->mbq_regmap); 3664 if (ret) 3665 goto err_sync; 3666 3667 return 0; 3668 3669 err_sync: 3670 regcache_cache_only(rt1320->regmap, true); 3671 regcache_cache_only(rt1320->mbq_regmap, true); 3672 regcache_mark_dirty(rt1320->regmap); 3673 regcache_mark_dirty(rt1320->mbq_regmap); 3674 return ret; 3675 } 3676 3677 static const struct dev_pm_ops rt1320_pm = { 3678 SYSTEM_SLEEP_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume) 3679 RUNTIME_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume, NULL) 3680 }; 3681 3682 static struct sdw_driver rt1320_sdw_driver = { 3683 .driver = { 3684 .name = "rt1320-sdca", 3685 .pm = pm_ptr(&rt1320_pm), 3686 }, 3687 .probe = rt1320_sdw_probe, 3688 .remove = rt1320_sdw_remove, 3689 .ops = &rt1320_slave_ops, 3690 .id_table = rt1320_id, 3691 }; 3692 module_sdw_driver(rt1320_sdw_driver); 3693 3694 MODULE_DESCRIPTION("ASoC RT1320 driver SDCA SDW"); 3695 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>"); 3696 MODULE_LICENSE("GPL"); 3697