1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * FTDI MPSSE GPIO support
4 *
5 * Based on code by Anatolij Gustschin
6 *
7 * Copyright (C) 2024 Mary Strodl <mstrodl@csh.rit.edu>
8 */
9
10 #include <linux/cleanup.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/mutex.h>
13 #include <linux/spinlock.h>
14 #include <linux/usb.h>
15
16 struct mpsse_priv {
17 struct gpio_chip gpio;
18 struct usb_device *udev; /* USB device encompassing all MPSSEs */
19 struct usb_interface *intf; /* USB interface for this MPSSE */
20 u8 intf_id; /* USB interface number for this MPSSE */
21 struct list_head workers; /* polling work threads */
22 struct mutex irq_mutex; /* lock over irq_data */
23 struct mutex irq_race; /* race for polling worker teardown */
24 raw_spinlock_t irq_spin; /* protects worker list */
25 atomic_t irq_type[16]; /* pin -> edge detection type */
26 atomic_t irq_enabled;
27 int id;
28
29 u8 gpio_outputs[2]; /* Output states for GPIOs [L, H] */
30 u8 gpio_dir[2]; /* Directions for GPIOs [L, H] */
31
32 unsigned long dir_in; /* Bitmask of valid input pins */
33 unsigned long dir_out; /* Bitmask of valid output pins */
34
35 u8 *bulk_in_buf; /* Extra recv buffer to grab status bytes */
36
37 struct usb_endpoint_descriptor *bulk_in;
38 struct usb_endpoint_descriptor *bulk_out;
39
40 struct mutex io_mutex; /* sync I/O with disconnect */
41 };
42
43 struct mpsse_worker {
44 struct mpsse_priv *priv;
45 struct work_struct work;
46 atomic_t cancelled;
47 struct list_head list; /* linked list */
48 struct list_head destroy; /* teardown linked list */
49 };
50
51 struct bulk_desc {
52 bool tx; /* direction of bulk transfer */
53 u8 *data; /* input (tx) or output (rx) */
54 int len; /* Length of `data` if tx, or length of */
55 /* Data to read if rx */
56 int len_actual; /* Length successfully transferred */
57 int timeout;
58 };
59
60 #define MPSSE_NGPIO 16
61
62 struct mpsse_quirk {
63 const char *names[MPSSE_NGPIO]; /* Pin names, if applicable */
64 unsigned long dir_in; /* Bitmask of valid input pins */
65 unsigned long dir_out; /* Bitmask of valid output pins */
66 };
67
68 static struct mpsse_quirk bryx_brik_quirk = {
69 .names = {
70 [3] = "Push to Talk",
71 [5] = "Channel Activity",
72 },
73 .dir_out = BIT(3), /* Push to Talk */
74 .dir_in = BIT(5), /* Channel Activity */
75 };
76
77 static const struct usb_device_id gpio_mpsse_table[] = {
78 { USB_DEVICE(0x0c52, 0xa064) }, /* SeaLevel Systems, Inc. */
79 { USB_DEVICE(0x0403, 0x6988), /* FTDI, assigned to Bryx */
80 .driver_info = (kernel_ulong_t)&bryx_brik_quirk},
81 { } /* Terminating entry */
82 };
83
84 MODULE_DEVICE_TABLE(usb, gpio_mpsse_table);
85
86 static DEFINE_IDA(gpio_mpsse_ida);
87
88 /* MPSSE commands */
89 #define SET_BITS_CMD 0x80
90 #define GET_BITS_CMD 0x81
91
92 #define SET_BITMODE_REQUEST 0x0B
93 #define MODE_MPSSE (2 << 8)
94 #define MODE_RESET 0
95
96 /* Arbitrarily decided. This could probably be much less */
97 #define MPSSE_WRITE_TIMEOUT 5000
98 #define MPSSE_READ_TIMEOUT 5000
99
100 /* 1 millisecond, also pretty arbitrary */
101 #define MPSSE_POLL_INTERVAL 1000
102
mpsse_bulk_xfer(struct usb_interface * intf,struct bulk_desc * desc)103 static int mpsse_bulk_xfer(struct usb_interface *intf, struct bulk_desc *desc)
104 {
105 struct mpsse_priv *priv = usb_get_intfdata(intf);
106 struct usb_device *udev = priv->udev;
107 unsigned int pipe;
108 int ret;
109
110 if (desc->tx)
111 pipe = usb_sndbulkpipe(udev, priv->bulk_out->bEndpointAddress);
112 else
113 pipe = usb_rcvbulkpipe(udev, priv->bulk_in->bEndpointAddress);
114
115 ret = usb_bulk_msg(udev, pipe, desc->data, desc->len,
116 &desc->len_actual, desc->timeout);
117 if (ret)
118 dev_dbg(&udev->dev, "mpsse: bulk transfer failed: %d\n", ret);
119
120 return ret;
121 }
122
mpsse_write(struct usb_interface * intf,u8 * buf,size_t len)123 static int mpsse_write(struct usb_interface *intf,
124 u8 *buf, size_t len)
125 {
126 int ret;
127 struct bulk_desc desc;
128
129 desc.len_actual = 0;
130 desc.tx = true;
131 desc.data = buf;
132 desc.len = len;
133 desc.timeout = MPSSE_WRITE_TIMEOUT;
134
135 ret = mpsse_bulk_xfer(intf, &desc);
136
137 return ret;
138 }
139
mpsse_read(struct usb_interface * intf,u8 * buf,size_t len)140 static int mpsse_read(struct usb_interface *intf, u8 *buf, size_t len)
141 {
142 int ret;
143 struct bulk_desc desc;
144 struct mpsse_priv *priv = usb_get_intfdata(intf);
145
146 desc.len_actual = 0;
147 desc.tx = false;
148 desc.data = priv->bulk_in_buf;
149 /* Device sends 2 additional status bytes, read len + 2 */
150 desc.len = min_t(size_t, len + 2, usb_endpoint_maxp(priv->bulk_in));
151 desc.timeout = MPSSE_READ_TIMEOUT;
152
153 ret = mpsse_bulk_xfer(intf, &desc);
154 if (ret)
155 return ret;
156
157 /* Did we get enough data? */
158 if (desc.len_actual < desc.len)
159 return -EIO;
160
161 memcpy(buf, desc.data + 2, desc.len_actual - 2);
162
163 return ret;
164 }
165
gpio_mpsse_set_bank(struct mpsse_priv * priv,u8 bank)166 static int gpio_mpsse_set_bank(struct mpsse_priv *priv, u8 bank)
167 {
168 int ret;
169 u8 tx_buf[3] = {
170 SET_BITS_CMD | (bank << 1),
171 priv->gpio_outputs[bank],
172 priv->gpio_dir[bank],
173 };
174
175 ret = mpsse_write(priv->intf, tx_buf, 3);
176
177 return ret;
178 }
179
gpio_mpsse_get_bank(struct mpsse_priv * priv,u8 bank)180 static int gpio_mpsse_get_bank(struct mpsse_priv *priv, u8 bank)
181 {
182 int ret;
183 u8 buf = GET_BITS_CMD | (bank << 1);
184
185 ret = mpsse_write(priv->intf, &buf, 1);
186 if (ret)
187 return ret;
188
189 ret = mpsse_read(priv->intf, &buf, 1);
190 if (ret)
191 return ret;
192
193 return buf;
194 }
195
mpsse_ensure_supported(struct gpio_chip * chip,unsigned long mask,int direction)196 static int mpsse_ensure_supported(struct gpio_chip *chip,
197 unsigned long mask, int direction)
198 {
199 unsigned long supported, unsupported;
200 char *type = "input";
201 struct mpsse_priv *priv = gpiochip_get_data(chip);
202
203 supported = priv->dir_in;
204 if (direction == GPIO_LINE_DIRECTION_OUT) {
205 supported = priv->dir_out;
206 type = "output";
207 }
208
209 /* An invalid bit was in the provided mask */
210 unsupported = mask & ~supported;
211 if (unsupported) {
212 dev_err(&priv->udev->dev,
213 "mpsse: GPIO %lu doesn't support %s\n",
214 find_first_bit(&unsupported, sizeof(unsupported) * 8),
215 type);
216 return -EOPNOTSUPP;
217 }
218
219 return 0;
220 }
221
gpio_mpsse_set_multiple(struct gpio_chip * chip,unsigned long * mask,unsigned long * bits)222 static int gpio_mpsse_set_multiple(struct gpio_chip *chip, unsigned long *mask,
223 unsigned long *bits)
224 {
225 unsigned long i, bank, bank_mask, bank_bits;
226 int ret;
227 struct mpsse_priv *priv = gpiochip_get_data(chip);
228
229 ret = mpsse_ensure_supported(chip, *mask, GPIO_LINE_DIRECTION_OUT);
230 if (ret)
231 return ret;
232
233 guard(mutex)(&priv->io_mutex);
234 for_each_set_clump8(i, bank_mask, mask, chip->ngpio) {
235 bank = i / 8;
236
237 if (bank_mask) {
238 bank_bits = bitmap_get_value8(bits, i);
239 /* Zero out pins we want to change */
240 priv->gpio_outputs[bank] &= ~bank_mask;
241 /* Set pins we care about */
242 priv->gpio_outputs[bank] |= bank_bits & bank_mask;
243
244 ret = gpio_mpsse_set_bank(priv, bank);
245 if (ret)
246 return ret;
247 }
248 }
249
250 return 0;
251 }
252
gpio_mpsse_get_multiple(struct gpio_chip * chip,unsigned long * mask,unsigned long * bits)253 static int gpio_mpsse_get_multiple(struct gpio_chip *chip, unsigned long *mask,
254 unsigned long *bits)
255 {
256 unsigned long i, bank, bank_mask;
257 int ret;
258 struct mpsse_priv *priv = gpiochip_get_data(chip);
259
260 ret = mpsse_ensure_supported(chip, *mask, GPIO_LINE_DIRECTION_IN);
261 if (ret)
262 return ret;
263
264 guard(mutex)(&priv->io_mutex);
265 for_each_set_clump8(i, bank_mask, mask, chip->ngpio) {
266 bank = i / 8;
267
268 if (bank_mask) {
269 ret = gpio_mpsse_get_bank(priv, bank);
270 if (ret < 0)
271 return ret;
272
273 bitmap_set_value8(bits, ret & bank_mask, i);
274 }
275 }
276
277 return 0;
278 }
279
gpio_mpsse_gpio_get(struct gpio_chip * chip,unsigned int offset)280 static int gpio_mpsse_gpio_get(struct gpio_chip *chip, unsigned int offset)
281 {
282 int err;
283 unsigned long mask = 0, bits = 0;
284
285 __set_bit(offset, &mask);
286 err = gpio_mpsse_get_multiple(chip, &mask, &bits);
287 if (err)
288 return err;
289
290 /* == is not guaranteed to give 1 if true */
291 if (bits)
292 return 1;
293 else
294 return 0;
295 }
296
gpio_mpsse_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)297 static int gpio_mpsse_gpio_set(struct gpio_chip *chip, unsigned int offset,
298 int value)
299 {
300 unsigned long mask = 0, bits = 0;
301
302 __set_bit(offset, &mask);
303 if (value)
304 __set_bit(offset, &bits);
305
306 return gpio_mpsse_set_multiple(chip, &mask, &bits);
307 }
308
gpio_mpsse_direction_output(struct gpio_chip * chip,unsigned int offset,int value)309 static int gpio_mpsse_direction_output(struct gpio_chip *chip,
310 unsigned int offset, int value)
311 {
312 int ret;
313 struct mpsse_priv *priv = gpiochip_get_data(chip);
314 int bank = (offset & 8) >> 3;
315 int bank_offset = offset & 7;
316
317 ret = mpsse_ensure_supported(chip, BIT(offset), GPIO_LINE_DIRECTION_OUT);
318 if (ret)
319 return ret;
320
321 scoped_guard(mutex, &priv->io_mutex)
322 priv->gpio_dir[bank] |= BIT(bank_offset);
323
324 return gpio_mpsse_gpio_set(chip, offset, value);
325 }
326
gpio_mpsse_direction_input(struct gpio_chip * chip,unsigned int offset)327 static int gpio_mpsse_direction_input(struct gpio_chip *chip,
328 unsigned int offset)
329 {
330 int ret;
331 struct mpsse_priv *priv = gpiochip_get_data(chip);
332 int bank = (offset & 8) >> 3;
333 int bank_offset = offset & 7;
334
335 ret = mpsse_ensure_supported(chip, BIT(offset), GPIO_LINE_DIRECTION_IN);
336 if (ret)
337 return ret;
338
339 guard(mutex)(&priv->io_mutex);
340 priv->gpio_dir[bank] &= ~BIT(bank_offset);
341
342 return gpio_mpsse_set_bank(priv, bank);
343 }
344
gpio_mpsse_get_direction(struct gpio_chip * chip,unsigned int offset)345 static int gpio_mpsse_get_direction(struct gpio_chip *chip,
346 unsigned int offset)
347 {
348 int ret;
349 int bank = (offset & 8) >> 3;
350 int bank_offset = offset & 7;
351 struct mpsse_priv *priv = gpiochip_get_data(chip);
352
353 guard(mutex)(&priv->io_mutex);
354 /* MPSSE directions are inverted */
355 if (priv->gpio_dir[bank] & BIT(bank_offset))
356 ret = GPIO_LINE_DIRECTION_OUT;
357 else
358 ret = GPIO_LINE_DIRECTION_IN;
359
360 return ret;
361 }
362
363 /*
364 * Stops all workers except `my_worker`.
365 * Safe to call only when `irq_race` is held.
366 */
gpio_mpsse_stop_all_except(struct mpsse_priv * priv,struct mpsse_worker * my_worker)367 static void gpio_mpsse_stop_all_except(struct mpsse_priv *priv,
368 struct mpsse_worker *my_worker)
369 {
370 struct mpsse_worker *worker, *worker_tmp;
371 struct list_head destructors = LIST_HEAD_INIT(destructors);
372
373 scoped_guard(raw_spinlock_irqsave, &priv->irq_spin) {
374 list_for_each_entry_safe(worker, worker_tmp,
375 &priv->workers, list) {
376 /* Don't stop ourselves */
377 if (worker == my_worker)
378 continue;
379
380 list_del(&worker->list);
381
382 /* Give worker a chance to terminate itself */
383 atomic_set(&worker->cancelled, 1);
384 /* Keep track of stuff to cancel */
385 INIT_LIST_HEAD(&worker->destroy);
386 list_add(&worker->destroy, &destructors);
387 }
388 }
389
390 list_for_each_entry_safe(worker, worker_tmp,
391 &destructors, destroy) {
392 list_del(&worker->destroy);
393 cancel_work_sync(&worker->work);
394 kfree(worker);
395 }
396 }
397
gpio_mpsse_poll(struct work_struct * my_work)398 static void gpio_mpsse_poll(struct work_struct *my_work)
399 {
400 unsigned long pin_mask, pin_states, flags;
401 int irq_enabled, offset, err, value, fire_irq,
402 irq, old_value[16], irq_type[16];
403 struct mpsse_worker *my_worker = container_of(my_work, struct mpsse_worker, work);
404 struct mpsse_priv *priv = my_worker->priv;
405
406 for (offset = 0; offset < priv->gpio.ngpio; ++offset)
407 old_value[offset] = -1;
408
409 /*
410 * We only want one worker. Workers race to acquire irq_race and tear
411 * down all other workers. This is a cond guard so that we don't deadlock
412 * trying to cancel a worker.
413 */
414 scoped_cond_guard(mutex_try, return, &priv->irq_race)
415 gpio_mpsse_stop_all_except(priv, my_worker);
416
417 while ((irq_enabled = atomic_read(&priv->irq_enabled)) &&
418 !atomic_read(&my_worker->cancelled)) {
419 usleep_range(MPSSE_POLL_INTERVAL, MPSSE_POLL_INTERVAL + 1000);
420 /* Cleanup will trigger at the end of the loop */
421 guard(mutex)(&priv->irq_mutex);
422
423 pin_mask = 0;
424 pin_states = 0;
425 for (offset = 0; offset < priv->gpio.ngpio; ++offset) {
426 irq_type[offset] = atomic_read(&priv->irq_type[offset]);
427 if (irq_type[offset] != IRQ_TYPE_NONE &&
428 irq_enabled & BIT(offset))
429 pin_mask |= BIT(offset);
430 else
431 old_value[offset] = -1;
432 }
433
434 err = gpio_mpsse_get_multiple(&priv->gpio, &pin_mask,
435 &pin_states);
436 if (err) {
437 dev_err_ratelimited(&priv->intf->dev,
438 "Error polling!\n");
439 continue;
440 }
441
442 /* Check each value */
443 for (offset = 0; offset < priv->gpio.ngpio; ++offset) {
444 if (old_value[offset] == -1)
445 continue;
446
447 fire_irq = 0;
448 value = pin_states & BIT(offset);
449
450 switch (irq_type[offset]) {
451 case IRQ_TYPE_EDGE_RISING:
452 fire_irq = value > old_value[offset];
453 break;
454 case IRQ_TYPE_EDGE_FALLING:
455 fire_irq = value < old_value[offset];
456 break;
457 case IRQ_TYPE_EDGE_BOTH:
458 fire_irq = value != old_value[offset];
459 break;
460 }
461 if (!fire_irq)
462 continue;
463
464 irq = irq_find_mapping(priv->gpio.irq.domain,
465 offset);
466 local_irq_save(flags);
467 generic_handle_irq(irq);
468 local_irq_disable();
469 local_irq_restore(flags);
470 }
471
472 /* Sync back values so we can refer to them next tick */
473 for (offset = 0; offset < priv->gpio.ngpio; ++offset)
474 if (irq_type[offset] != IRQ_TYPE_NONE &&
475 irq_enabled & BIT(offset))
476 old_value[offset] = pin_states & BIT(offset);
477 }
478 }
479
gpio_mpsse_set_irq_type(struct irq_data * irqd,unsigned int type)480 static int gpio_mpsse_set_irq_type(struct irq_data *irqd, unsigned int type)
481 {
482 int offset;
483 struct mpsse_priv *priv = irq_data_get_irq_chip_data(irqd);
484
485 offset = irqd->hwirq;
486 atomic_set(&priv->irq_type[offset], type & IRQ_TYPE_EDGE_BOTH);
487
488 return 0;
489 }
490
gpio_mpsse_irq_disable(struct irq_data * irqd)491 static void gpio_mpsse_irq_disable(struct irq_data *irqd)
492 {
493 struct mpsse_worker *worker;
494 struct mpsse_priv *priv = irq_data_get_irq_chip_data(irqd);
495
496 atomic_and(~BIT(irqd->hwirq), &priv->irq_enabled);
497 gpiochip_disable_irq(&priv->gpio, irqd->hwirq);
498
499 /*
500 * Can't actually do teardown in IRQ context (it blocks).
501 * As a result, these workers will stick around until irq is reenabled
502 * or device gets disconnected
503 */
504 scoped_guard(raw_spinlock_irqsave, &priv->irq_spin)
505 list_for_each_entry(worker, &priv->workers, list)
506 atomic_set(&worker->cancelled, 1);
507 }
508
gpio_mpsse_irq_enable(struct irq_data * irqd)509 static void gpio_mpsse_irq_enable(struct irq_data *irqd)
510 {
511 struct mpsse_worker *worker;
512 struct mpsse_priv *priv = irq_data_get_irq_chip_data(irqd);
513
514 gpiochip_enable_irq(&priv->gpio, irqd->hwirq);
515 /* If no-one else was using the IRQ, enable it */
516 if (!atomic_fetch_or(BIT(irqd->hwirq), &priv->irq_enabled)) {
517 /*
518 * Can't be devm because it uses a non-raw spinlock (illegal in
519 * this context, where a raw spinlock is held by our caller)
520 */
521 worker = kzalloc(sizeof(*worker), GFP_NOWAIT);
522 if (!worker)
523 return;
524
525 worker->priv = priv;
526 INIT_LIST_HEAD(&worker->list);
527 INIT_WORK(&worker->work, gpio_mpsse_poll);
528 schedule_work(&worker->work);
529
530 scoped_guard(raw_spinlock_irqsave, &priv->irq_spin)
531 list_add(&worker->list, &priv->workers);
532 }
533 }
534
535 static const struct irq_chip gpio_mpsse_irq_chip = {
536 .name = "gpio-mpsse-irq",
537 .irq_enable = gpio_mpsse_irq_enable,
538 .irq_disable = gpio_mpsse_irq_disable,
539 .irq_set_type = gpio_mpsse_set_irq_type,
540 .flags = IRQCHIP_IMMUTABLE,
541 GPIOCHIP_IRQ_RESOURCE_HELPERS,
542 };
543
gpio_mpsse_ida_remove(void * data)544 static void gpio_mpsse_ida_remove(void *data)
545 {
546 struct mpsse_priv *priv = data;
547
548 ida_free(&gpio_mpsse_ida, priv->id);
549 }
550
gpio_mpsse_usb_put_dev(void * data)551 static void gpio_mpsse_usb_put_dev(void *data)
552 {
553 struct mpsse_priv *priv = data;
554
555 usb_put_dev(priv->udev);
556 }
557
mpsse_init_valid_mask(struct gpio_chip * chip,unsigned long * valid_mask,unsigned int ngpios)558 static int mpsse_init_valid_mask(struct gpio_chip *chip,
559 unsigned long *valid_mask,
560 unsigned int ngpios)
561 {
562 struct mpsse_priv *priv = gpiochip_get_data(chip);
563
564 if (WARN_ON(priv == NULL))
565 return -ENODEV;
566
567 *valid_mask = priv->dir_in | priv->dir_out;
568
569 return 0;
570 }
571
mpsse_irq_init_valid_mask(struct gpio_chip * chip,unsigned long * valid_mask,unsigned int ngpios)572 static void mpsse_irq_init_valid_mask(struct gpio_chip *chip,
573 unsigned long *valid_mask,
574 unsigned int ngpios)
575 {
576 struct mpsse_priv *priv = gpiochip_get_data(chip);
577
578 if (WARN_ON(priv == NULL))
579 return;
580
581 /* Can only use IRQ on input capable pins */
582 *valid_mask = priv->dir_in;
583 }
584
gpio_mpsse_probe(struct usb_interface * interface,const struct usb_device_id * id)585 static int gpio_mpsse_probe(struct usb_interface *interface,
586 const struct usb_device_id *id)
587 {
588 struct mpsse_priv *priv;
589 struct device *dev;
590 char *serial;
591 int err;
592 struct mpsse_quirk *quirk = (void *)id->driver_info;
593
594 dev = &interface->dev;
595 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
596 if (!priv)
597 return -ENOMEM;
598
599 INIT_LIST_HEAD(&priv->workers);
600
601 priv->udev = usb_get_dev(interface_to_usbdev(interface));
602 err = devm_add_action_or_reset(dev, gpio_mpsse_usb_put_dev, priv);
603 if (err)
604 return err;
605
606 priv->intf = interface;
607 priv->intf_id = interface->cur_altsetting->desc.bInterfaceNumber;
608
609 priv->id = ida_alloc(&gpio_mpsse_ida, GFP_KERNEL);
610 if (priv->id < 0)
611 return priv->id;
612
613 err = devm_add_action_or_reset(dev, gpio_mpsse_ida_remove, priv);
614 if (err)
615 return err;
616
617 err = devm_mutex_init(dev, &priv->io_mutex);
618 if (err)
619 return err;
620
621 err = devm_mutex_init(dev, &priv->irq_mutex);
622 if (err)
623 return err;
624
625 err = devm_mutex_init(dev, &priv->irq_race);
626 if (err)
627 return err;
628
629 raw_spin_lock_init(&priv->irq_spin);
630
631 serial = priv->udev->serial;
632 if (!serial)
633 serial = "NONE";
634
635 priv->gpio.label = devm_kasprintf(dev, GFP_KERNEL,
636 "MPSSE%04x:%04x.%d.%d.%s",
637 id->idVendor, id->idProduct,
638 priv->intf_id, priv->id,
639 serial);
640 if (!priv->gpio.label)
641 return -ENOMEM;
642
643 priv->gpio.owner = THIS_MODULE;
644 priv->gpio.parent = interface->usb_dev;
645 priv->gpio.get_direction = gpio_mpsse_get_direction;
646 priv->gpio.direction_input = gpio_mpsse_direction_input;
647 priv->gpio.direction_output = gpio_mpsse_direction_output;
648 priv->gpio.get = gpio_mpsse_gpio_get;
649 priv->gpio.set = gpio_mpsse_gpio_set;
650 priv->gpio.get_multiple = gpio_mpsse_get_multiple;
651 priv->gpio.set_multiple = gpio_mpsse_set_multiple;
652 priv->gpio.base = -1;
653 priv->gpio.ngpio = MPSSE_NGPIO;
654 priv->gpio.offset = priv->intf_id * priv->gpio.ngpio;
655 priv->gpio.can_sleep = 1;
656
657 if (quirk) {
658 priv->dir_out = quirk->dir_out;
659 priv->dir_in = quirk->dir_in;
660 priv->gpio.names = quirk->names;
661 priv->gpio.init_valid_mask = mpsse_init_valid_mask;
662 } else {
663 priv->dir_in = U16_MAX;
664 priv->dir_out = U16_MAX;
665 }
666
667 err = usb_find_common_endpoints(interface->cur_altsetting,
668 &priv->bulk_in, &priv->bulk_out,
669 NULL, NULL);
670 if (err)
671 return err;
672
673 priv->bulk_in_buf = devm_kmalloc(dev, usb_endpoint_maxp(priv->bulk_in),
674 GFP_KERNEL);
675 if (!priv->bulk_in_buf)
676 return -ENOMEM;
677
678 usb_set_intfdata(interface, priv);
679
680 /* Reset mode, needed to correctly enter MPSSE mode */
681 err = usb_control_msg(priv->udev, usb_sndctrlpipe(priv->udev, 0),
682 SET_BITMODE_REQUEST,
683 USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_OUT,
684 MODE_RESET, priv->intf_id + 1, NULL, 0,
685 USB_CTRL_SET_TIMEOUT);
686 if (err)
687 return err;
688
689 /* Enter MPSSE mode */
690 err = usb_control_msg(priv->udev, usb_sndctrlpipe(priv->udev, 0),
691 SET_BITMODE_REQUEST,
692 USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_OUT,
693 MODE_MPSSE, priv->intf_id + 1, NULL, 0,
694 USB_CTRL_SET_TIMEOUT);
695 if (err)
696 return err;
697
698 gpio_irq_chip_set_chip(&priv->gpio.irq, &gpio_mpsse_irq_chip);
699
700 priv->gpio.irq.parent_handler = NULL;
701 priv->gpio.irq.num_parents = 0;
702 priv->gpio.irq.parents = NULL;
703 priv->gpio.irq.default_type = IRQ_TYPE_NONE;
704 priv->gpio.irq.handler = handle_simple_irq;
705 priv->gpio.irq.init_valid_mask = mpsse_irq_init_valid_mask;
706
707 err = devm_gpiochip_add_data(dev, &priv->gpio, priv);
708 if (err)
709 return err;
710
711 return 0;
712 }
713
gpio_mpsse_disconnect(struct usb_interface * intf)714 static void gpio_mpsse_disconnect(struct usb_interface *intf)
715 {
716 struct mpsse_priv *priv = usb_get_intfdata(intf);
717
718 /*
719 * Lock prevents double-free of worker from here and the teardown
720 * step at the beginning of gpio_mpsse_poll
721 */
722 scoped_guard(mutex, &priv->irq_race)
723 gpio_mpsse_stop_all_except(priv, NULL);
724
725 priv->intf = NULL;
726 usb_set_intfdata(intf, NULL);
727 }
728
729 static struct usb_driver gpio_mpsse_driver = {
730 .name = "gpio-mpsse",
731 .probe = gpio_mpsse_probe,
732 .disconnect = gpio_mpsse_disconnect,
733 .id_table = gpio_mpsse_table,
734 };
735
736 module_usb_driver(gpio_mpsse_driver);
737
738 MODULE_AUTHOR("Mary Strodl <mstrodl@csh.rit.edu>");
739 MODULE_DESCRIPTION("MPSSE GPIO driver");
740 MODULE_LICENSE("GPL");
741