1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2012, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef _LINUX_CORESIGHT_H 7 #define _LINUX_CORESIGHT_H 8 9 #include <linux/amba/bus.h> 10 #include <linux/clk.h> 11 #include <linux/device.h> 12 #include <linux/io.h> 13 #include <linux/perf_event.h> 14 #include <linux/sched.h> 15 #include <linux/platform_device.h> 16 17 /* Peripheral id registers (0xFD0-0xFEC) */ 18 #define CORESIGHT_PERIPHIDR4 0xfd0 19 #define CORESIGHT_PERIPHIDR5 0xfd4 20 #define CORESIGHT_PERIPHIDR6 0xfd8 21 #define CORESIGHT_PERIPHIDR7 0xfdC 22 #define CORESIGHT_PERIPHIDR0 0xfe0 23 #define CORESIGHT_PERIPHIDR1 0xfe4 24 #define CORESIGHT_PERIPHIDR2 0xfe8 25 #define CORESIGHT_PERIPHIDR3 0xfeC 26 /* Component id registers (0xFF0-0xFFC) */ 27 #define CORESIGHT_COMPIDR0 0xff0 28 #define CORESIGHT_COMPIDR1 0xff4 29 #define CORESIGHT_COMPIDR2 0xff8 30 #define CORESIGHT_COMPIDR3 0xffC 31 32 #define ETM_ARCH_V3_3 0x23 33 #define ETM_ARCH_V3_5 0x25 34 #define PFT_ARCH_V1_0 0x30 35 #define PFT_ARCH_V1_1 0x31 36 37 #define CORESIGHT_UNLOCK 0xc5acce55 38 39 extern const struct bus_type coresight_bustype; 40 41 enum coresight_dev_type { 42 CORESIGHT_DEV_TYPE_SINK, 43 CORESIGHT_DEV_TYPE_LINK, 44 CORESIGHT_DEV_TYPE_LINKSINK, 45 CORESIGHT_DEV_TYPE_SOURCE, 46 CORESIGHT_DEV_TYPE_HELPER, 47 CORESIGHT_DEV_TYPE_MAX 48 }; 49 50 enum coresight_dev_subtype_sink { 51 CORESIGHT_DEV_SUBTYPE_SINK_DUMMY, 52 CORESIGHT_DEV_SUBTYPE_SINK_PORT, 53 CORESIGHT_DEV_SUBTYPE_SINK_BUFFER, 54 CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM, 55 CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM, 56 }; 57 58 enum coresight_dev_subtype_link { 59 CORESIGHT_DEV_SUBTYPE_LINK_MERG, 60 CORESIGHT_DEV_SUBTYPE_LINK_SPLIT, 61 CORESIGHT_DEV_SUBTYPE_LINK_FIFO, 62 }; 63 64 enum coresight_dev_subtype_source { 65 CORESIGHT_DEV_SUBTYPE_SOURCE_PROC, 66 CORESIGHT_DEV_SUBTYPE_SOURCE_BUS, 67 CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE, 68 CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM, 69 CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS, 70 }; 71 72 enum coresight_dev_subtype_helper { 73 CORESIGHT_DEV_SUBTYPE_HELPER_CATU, 74 CORESIGHT_DEV_SUBTYPE_HELPER_ECT_CTI 75 }; 76 77 /** 78 * union coresight_dev_subtype - further characterisation of a type 79 * @sink_subtype: type of sink this component is, as defined 80 * by @coresight_dev_subtype_sink. 81 * @link_subtype: type of link this component is, as defined 82 * by @coresight_dev_subtype_link. 83 * @source_subtype: type of source this component is, as defined 84 * by @coresight_dev_subtype_source. 85 * @helper_subtype: type of helper this component is, as defined 86 * by @coresight_dev_subtype_helper. 87 */ 88 union coresight_dev_subtype { 89 /* We have some devices which acts as LINK and SINK */ 90 struct { 91 enum coresight_dev_subtype_sink sink_subtype; 92 enum coresight_dev_subtype_link link_subtype; 93 }; 94 enum coresight_dev_subtype_source source_subtype; 95 enum coresight_dev_subtype_helper helper_subtype; 96 }; 97 98 /** 99 * struct coresight_platform_data - data harvested from the firmware 100 * specification. 101 * 102 * @nr_inconns: Number of elements for the input connections. 103 * @nr_outconns: Number of elements for the output connections. 104 * @out_conns: Array of nr_outconns pointers to connections from this 105 * component. 106 * @in_conns: Sparse array of pointers to input connections. Sparse 107 * because the source device owns the connection so when it's 108 * unloaded the connection leaves an empty slot. 109 */ 110 struct coresight_platform_data { 111 int nr_inconns; 112 int nr_outconns; 113 struct coresight_connection **out_conns; 114 struct coresight_connection **in_conns; 115 }; 116 117 /** 118 * struct csdev_access - Abstraction of a CoreSight device access. 119 * 120 * @io_mem : True if the device has memory mapped I/O 121 * @base : When io_mem == true, base address of the component 122 * @read : Read from the given "offset" of the given instance. 123 * @write : Write "val" to the given "offset". 124 */ 125 struct csdev_access { 126 bool io_mem; 127 union { 128 void __iomem *base; 129 struct { 130 u64 (*read)(u32 offset, bool relaxed, bool _64bit); 131 void (*write)(u64 val, u32 offset, bool relaxed, 132 bool _64bit); 133 }; 134 }; 135 }; 136 137 #define CSDEV_ACCESS_IOMEM(_addr) \ 138 ((struct csdev_access) { \ 139 .io_mem = true, \ 140 .base = (_addr), \ 141 }) 142 143 /** 144 * struct coresight_desc - description of a component required from drivers 145 * @type: as defined by @coresight_dev_type. 146 * @subtype: as defined by @coresight_dev_subtype. 147 * @ops: generic operations for this component, as defined 148 * by @coresight_ops. 149 * @pdata: platform data collected from DT. 150 * @dev: The device entity associated to this component. 151 * @groups: operations specific to this component. These will end up 152 * in the component's sysfs sub-directory. 153 * @name: name for the coresight device, also shown under sysfs. 154 * @access: Describe access to the device 155 */ 156 struct coresight_desc { 157 enum coresight_dev_type type; 158 union coresight_dev_subtype subtype; 159 const struct coresight_ops *ops; 160 struct coresight_platform_data *pdata; 161 struct device *dev; 162 const struct attribute_group **groups; 163 const char *name; 164 struct csdev_access access; 165 }; 166 167 /** 168 * struct coresight_connection - representation of a single connection 169 * @src_port: a connection's output port number. 170 * @dest_port: destination's input port number @src_port is connected to. 171 * @dest_fwnode: destination component's fwnode handle. 172 * @dest_dev: a @coresight_device representation of the component 173 connected to @src_port. NULL until the device is created 174 * @link: Representation of the connection as a sysfs link. 175 * @filter_src_fwnode: filter source component's fwnode handle. 176 * @filter_src_dev: a @coresight_device representation of the component that 177 needs to be filtered. 178 * 179 * The full connection structure looks like this, where in_conns store 180 * references to same connection as the source device's out_conns. 181 * 182 * +-----------------------------+ +-----------------------------+ 183 * |coresight_device | |coresight_connection | 184 * |-----------------------------| |-----------------------------| 185 * | | | | 186 * | | | dest_dev*|<-- 187 * |pdata->out_conns[nr_outconns]|<->|src_dev* | | 188 * | | | | | 189 * +-----------------------------+ +-----------------------------+ | 190 * | 191 * +-----------------------------+ | 192 * |coresight_device | | 193 * |------------------------------ | 194 * | | | 195 * | pdata->in_conns[nr_inconns]|<-- 196 * | | 197 * +-----------------------------+ 198 */ 199 struct coresight_connection { 200 int src_port; 201 int dest_port; 202 struct fwnode_handle *dest_fwnode; 203 struct coresight_device *dest_dev; 204 struct coresight_sysfs_link *link; 205 struct coresight_device *src_dev; 206 struct fwnode_handle *filter_src_fwnode; 207 struct coresight_device *filter_src_dev; 208 int src_refcnt; 209 int dest_refcnt; 210 }; 211 212 /** 213 * struct coresight_sysfs_link - representation of a connection in sysfs. 214 * @orig: Originating (master) coresight device for the link. 215 * @orig_name: Name to use for the link orig->target. 216 * @target: Target (slave) coresight device for the link. 217 * @target_name: Name to use for the link target->orig. 218 */ 219 struct coresight_sysfs_link { 220 struct coresight_device *orig; 221 const char *orig_name; 222 struct coresight_device *target; 223 const char *target_name; 224 }; 225 226 /* architecturally we have 128 IDs some of which are reserved */ 227 #define CORESIGHT_TRACE_IDS_MAX 128 228 229 /** 230 * Trace ID map. 231 * 232 * @used_ids: Bitmap to register available (bit = 0) and in use (bit = 1) IDs. 233 * Initialised so that the reserved IDs are permanently marked as 234 * in use. 235 * @perf_cs_etm_session_active: Number of Perf sessions using this ID map. 236 */ 237 struct coresight_trace_id_map { 238 DECLARE_BITMAP(used_ids, CORESIGHT_TRACE_IDS_MAX); 239 atomic_t __percpu *cpu_map; 240 atomic_t perf_cs_etm_session_active; 241 spinlock_t lock; 242 }; 243 244 /** 245 * struct coresight_device - representation of a device as used by the framework 246 * @pdata: Platform data with device connections associated to this device. 247 * @type: as defined by @coresight_dev_type. 248 * @subtype: as defined by @coresight_dev_subtype. 249 * @ops: generic operations for this component, as defined 250 * by @coresight_ops. 251 * @access: Device i/o access abstraction for this device. 252 * @dev: The device entity associated to this component. 253 * @mode: This tracer's mode, i.e sysFS, Perf or disabled. This is 254 * actually an 'enum cs_mode', but is stored in an atomic type. 255 * This is always accessed through local_read() and local_set(), 256 * but wherever it's done from within the Coresight device's lock, 257 * a non-atomic read would also work. This is the main point of 258 * synchronisation between code happening inside the sysfs mode's 259 * coresight_mutex and outside when running in Perf mode. A compare 260 * and exchange swap is done to atomically claim one mode or the 261 * other. 262 * @refcnt: keep track of what is in use. Only access this outside of the 263 * device's spinlock when the coresight_mutex held and mode == 264 * CS_MODE_SYSFS. Otherwise it must be accessed from inside the 265 * spinlock. 266 * @orphan: true if the component has connections that haven't been linked. 267 * @sysfs_sink_activated: 'true' when a sink has been selected for use via sysfs 268 * by writing a 1 to the 'enable_sink' file. A sink can be 269 * activated but not yet enabled. Enabling for a _sink_ happens 270 * when a source has been selected and a path is enabled from 271 * source to that sink. A sink can also become enabled but not 272 * activated if it's used via Perf. 273 * @ea: Device attribute for sink representation under PMU directory. 274 * @def_sink: cached reference to default sink found for this device. 275 * @nr_links: number of sysfs links created to other components from this 276 * device. These will appear in the "connections" group. 277 * @has_conns_grp: Have added a "connections" group for sysfs links. 278 * @feature_csdev_list: List of complex feature programming added to the device. 279 * @config_csdev_list: List of system configurations added to the device. 280 * @cscfg_csdev_lock: Protect the lists of configurations and features. 281 * @active_cscfg_ctxt: Context information for current active system configuration. 282 */ 283 struct coresight_device { 284 struct coresight_platform_data *pdata; 285 enum coresight_dev_type type; 286 union coresight_dev_subtype subtype; 287 const struct coresight_ops *ops; 288 struct csdev_access access; 289 struct device dev; 290 local_t mode; 291 int refcnt; 292 bool orphan; 293 /* sink specific fields */ 294 bool sysfs_sink_activated; 295 struct dev_ext_attribute *ea; 296 struct coresight_device *def_sink; 297 struct coresight_trace_id_map perf_sink_id_map; 298 /* sysfs links between components */ 299 int nr_links; 300 bool has_conns_grp; 301 /* system configuration and feature lists */ 302 struct list_head feature_csdev_list; 303 struct list_head config_csdev_list; 304 spinlock_t cscfg_csdev_lock; 305 void *active_cscfg_ctxt; 306 }; 307 308 /* 309 * coresight_dev_list - Mapping for devices to "name" index for device 310 * names. 311 * 312 * @nr_idx: Number of entries already allocated. 313 * @pfx: Prefix pattern for device name. 314 * @fwnode_list: Array of fwnode_handles associated with each allocated 315 * index, upto nr_idx entries. 316 */ 317 struct coresight_dev_list { 318 int nr_idx; 319 const char *pfx; 320 struct fwnode_handle **fwnode_list; 321 }; 322 323 #define DEFINE_CORESIGHT_DEVLIST(var, dev_pfx) \ 324 static struct coresight_dev_list (var) = { \ 325 .pfx = dev_pfx, \ 326 .nr_idx = 0, \ 327 .fwnode_list = NULL, \ 328 } 329 330 #define to_coresight_device(d) container_of(d, struct coresight_device, dev) 331 332 enum cs_mode { 333 CS_MODE_DISABLED, 334 CS_MODE_SYSFS, 335 CS_MODE_PERF, 336 }; 337 338 #define source_ops(csdev) csdev->ops->source_ops 339 #define sink_ops(csdev) csdev->ops->sink_ops 340 #define link_ops(csdev) csdev->ops->link_ops 341 #define helper_ops(csdev) csdev->ops->helper_ops 342 #define ect_ops(csdev) csdev->ops->ect_ops 343 344 /** 345 * struct coresight_ops_sink - basic operations for a sink 346 * Operations available for sinks 347 * @enable: enables the sink. 348 * @disable: disables the sink. 349 * @alloc_buffer: initialises perf's ring buffer for trace collection. 350 * @free_buffer: release memory allocated in @get_config. 351 * @update_buffer: update buffer pointers after a trace session. 352 */ 353 struct coresight_ops_sink { 354 int (*enable)(struct coresight_device *csdev, enum cs_mode mode, 355 void *data); 356 int (*disable)(struct coresight_device *csdev); 357 void *(*alloc_buffer)(struct coresight_device *csdev, 358 struct perf_event *event, void **pages, 359 int nr_pages, bool overwrite); 360 void (*free_buffer)(void *config); 361 unsigned long (*update_buffer)(struct coresight_device *csdev, 362 struct perf_output_handle *handle, 363 void *sink_config); 364 }; 365 366 /** 367 * struct coresight_ops_link - basic operations for a link 368 * Operations available for links. 369 * @enable: enables flow between iport and oport. 370 * @disable: disables flow between iport and oport. 371 */ 372 struct coresight_ops_link { 373 int (*enable)(struct coresight_device *csdev, 374 struct coresight_connection *in, 375 struct coresight_connection *out); 376 void (*disable)(struct coresight_device *csdev, 377 struct coresight_connection *in, 378 struct coresight_connection *out); 379 }; 380 381 /** 382 * struct coresight_ops_source - basic operations for a source 383 * Operations available for sources. 384 * @cpu_id: returns the value of the CPU number this component 385 * is associated to. 386 * @enable: enables tracing for a source. 387 * @disable: disables tracing for a source. 388 */ 389 struct coresight_ops_source { 390 int (*cpu_id)(struct coresight_device *csdev); 391 int (*enable)(struct coresight_device *csdev, struct perf_event *event, 392 enum cs_mode mode, struct coresight_trace_id_map *id_map); 393 void (*disable)(struct coresight_device *csdev, 394 struct perf_event *event); 395 }; 396 397 /** 398 * struct coresight_ops_helper - Operations for a helper device. 399 * 400 * All operations could pass in a device specific data, which could 401 * help the helper device to determine what to do. 402 * 403 * @enable : Enable the device 404 * @disable : Disable the device 405 */ 406 struct coresight_ops_helper { 407 int (*enable)(struct coresight_device *csdev, enum cs_mode mode, 408 void *data); 409 int (*disable)(struct coresight_device *csdev, void *data); 410 }; 411 412 struct coresight_ops { 413 const struct coresight_ops_sink *sink_ops; 414 const struct coresight_ops_link *link_ops; 415 const struct coresight_ops_source *source_ops; 416 const struct coresight_ops_helper *helper_ops; 417 }; 418 419 static inline u32 csdev_access_relaxed_read32(struct csdev_access *csa, 420 u32 offset) 421 { 422 if (likely(csa->io_mem)) 423 return readl_relaxed(csa->base + offset); 424 425 return csa->read(offset, true, false); 426 } 427 428 #define CORESIGHT_CIDRn(i) (0xFF0 + ((i) * 4)) 429 430 static inline u32 coresight_get_cid(void __iomem *base) 431 { 432 u32 i, cid = 0; 433 434 for (i = 0; i < 4; i++) 435 cid |= readl(base + CORESIGHT_CIDRn(i)) << (i * 8); 436 437 return cid; 438 } 439 440 static inline bool is_coresight_device(void __iomem *base) 441 { 442 u32 cid = coresight_get_cid(base); 443 444 return cid == CORESIGHT_CID; 445 } 446 447 /* 448 * Attempt to find and enable "APB clock" for the given device 449 * 450 * Returns: 451 * 452 * clk - Clock is found and enabled 453 * NULL - clock is not found 454 * ERROR - Clock is found but failed to enable 455 */ 456 static inline struct clk *coresight_get_enable_apb_pclk(struct device *dev) 457 { 458 struct clk *pclk; 459 int ret; 460 461 pclk = clk_get(dev, "apb_pclk"); 462 if (IS_ERR(pclk)) 463 return NULL; 464 465 ret = clk_prepare_enable(pclk); 466 if (ret) { 467 clk_put(pclk); 468 return ERR_PTR(ret); 469 } 470 return pclk; 471 } 472 473 #define CORESIGHT_PIDRn(i) (0xFE0 + ((i) * 4)) 474 475 static inline u32 coresight_get_pid(struct csdev_access *csa) 476 { 477 u32 i, pid = 0; 478 479 for (i = 0; i < 4; i++) 480 pid |= csdev_access_relaxed_read32(csa, CORESIGHT_PIDRn(i)) << (i * 8); 481 482 return pid; 483 } 484 485 static inline u64 csdev_access_relaxed_read_pair(struct csdev_access *csa, 486 u32 lo_offset, u32 hi_offset) 487 { 488 if (likely(csa->io_mem)) { 489 return readl_relaxed(csa->base + lo_offset) | 490 ((u64)readl_relaxed(csa->base + hi_offset) << 32); 491 } 492 493 return csa->read(lo_offset, true, false) | (csa->read(hi_offset, true, false) << 32); 494 } 495 496 static inline void csdev_access_relaxed_write_pair(struct csdev_access *csa, u64 val, 497 u32 lo_offset, u32 hi_offset) 498 { 499 if (likely(csa->io_mem)) { 500 writel_relaxed((u32)val, csa->base + lo_offset); 501 writel_relaxed((u32)(val >> 32), csa->base + hi_offset); 502 } else { 503 csa->write((u32)val, lo_offset, true, false); 504 csa->write((u32)(val >> 32), hi_offset, true, false); 505 } 506 } 507 508 static inline u32 csdev_access_read32(struct csdev_access *csa, u32 offset) 509 { 510 if (likely(csa->io_mem)) 511 return readl(csa->base + offset); 512 513 return csa->read(offset, false, false); 514 } 515 516 static inline void csdev_access_relaxed_write32(struct csdev_access *csa, 517 u32 val, u32 offset) 518 { 519 if (likely(csa->io_mem)) 520 writel_relaxed(val, csa->base + offset); 521 else 522 csa->write(val, offset, true, false); 523 } 524 525 static inline void csdev_access_write32(struct csdev_access *csa, u32 val, u32 offset) 526 { 527 if (likely(csa->io_mem)) 528 writel(val, csa->base + offset); 529 else 530 csa->write(val, offset, false, false); 531 } 532 533 #ifdef CONFIG_64BIT 534 535 static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa, 536 u32 offset) 537 { 538 if (likely(csa->io_mem)) 539 return readq_relaxed(csa->base + offset); 540 541 return csa->read(offset, true, true); 542 } 543 544 static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset) 545 { 546 if (likely(csa->io_mem)) 547 return readq(csa->base + offset); 548 549 return csa->read(offset, false, true); 550 } 551 552 static inline void csdev_access_relaxed_write64(struct csdev_access *csa, 553 u64 val, u32 offset) 554 { 555 if (likely(csa->io_mem)) 556 writeq_relaxed(val, csa->base + offset); 557 else 558 csa->write(val, offset, true, true); 559 } 560 561 static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset) 562 { 563 if (likely(csa->io_mem)) 564 writeq(val, csa->base + offset); 565 else 566 csa->write(val, offset, false, true); 567 } 568 569 #else /* !CONFIG_64BIT */ 570 571 static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa, 572 u32 offset) 573 { 574 WARN_ON(1); 575 return 0; 576 } 577 578 static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset) 579 { 580 WARN_ON(1); 581 return 0; 582 } 583 584 static inline void csdev_access_relaxed_write64(struct csdev_access *csa, 585 u64 val, u32 offset) 586 { 587 WARN_ON(1); 588 } 589 590 static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset) 591 { 592 WARN_ON(1); 593 } 594 #endif /* CONFIG_64BIT */ 595 596 static inline bool coresight_is_device_source(struct coresight_device *csdev) 597 { 598 return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SOURCE); 599 } 600 601 static inline bool coresight_is_percpu_source(struct coresight_device *csdev) 602 { 603 return csdev && coresight_is_device_source(csdev) && 604 (csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_PROC); 605 } 606 607 static inline bool coresight_is_percpu_sink(struct coresight_device *csdev) 608 { 609 return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SINK) && 610 (csdev->subtype.sink_subtype == CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM); 611 } 612 613 /* 614 * Atomically try to take the device and set a new mode. Returns true on 615 * success, false if the device is already taken by someone else. 616 */ 617 static inline bool coresight_take_mode(struct coresight_device *csdev, 618 enum cs_mode new_mode) 619 { 620 return local_cmpxchg(&csdev->mode, CS_MODE_DISABLED, new_mode) == 621 CS_MODE_DISABLED; 622 } 623 624 static inline enum cs_mode coresight_get_mode(struct coresight_device *csdev) 625 { 626 return local_read(&csdev->mode); 627 } 628 629 static inline void coresight_set_mode(struct coresight_device *csdev, 630 enum cs_mode new_mode) 631 { 632 enum cs_mode current_mode = coresight_get_mode(csdev); 633 634 /* 635 * Changing to a new mode must be done from an already disabled state 636 * unless it's synchronized with coresight_take_mode(). Otherwise the 637 * device is already in use and signifies a locking issue. 638 */ 639 WARN(new_mode != CS_MODE_DISABLED && current_mode != CS_MODE_DISABLED && 640 current_mode != new_mode, "Device already in use\n"); 641 642 local_set(&csdev->mode, new_mode); 643 } 644 645 extern struct coresight_device * 646 coresight_register(struct coresight_desc *desc); 647 extern void coresight_unregister(struct coresight_device *csdev); 648 extern int coresight_enable_sysfs(struct coresight_device *csdev); 649 extern void coresight_disable_sysfs(struct coresight_device *csdev); 650 extern int coresight_timeout(struct csdev_access *csa, u32 offset, 651 int position, int value); 652 653 extern int coresight_claim_device(struct coresight_device *csdev); 654 extern int coresight_claim_device_unlocked(struct coresight_device *csdev); 655 656 extern void coresight_disclaim_device(struct coresight_device *csdev); 657 extern void coresight_disclaim_device_unlocked(struct coresight_device *csdev); 658 extern char *coresight_alloc_device_name(struct coresight_dev_list *devs, 659 struct device *dev); 660 661 extern bool coresight_loses_context_with_cpu(struct device *dev); 662 663 u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset); 664 u32 coresight_read32(struct coresight_device *csdev, u32 offset); 665 void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset); 666 void coresight_relaxed_write32(struct coresight_device *csdev, 667 u32 val, u32 offset); 668 u64 coresight_relaxed_read64(struct coresight_device *csdev, u32 offset); 669 u64 coresight_read64(struct coresight_device *csdev, u32 offset); 670 void coresight_relaxed_write64(struct coresight_device *csdev, 671 u64 val, u32 offset); 672 void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset); 673 674 extern int coresight_get_cpu(struct device *dev); 675 extern int coresight_get_static_trace_id(struct device *dev, u32 *id); 676 677 struct coresight_platform_data *coresight_get_platform_data(struct device *dev); 678 struct coresight_connection * 679 coresight_add_out_conn(struct device *dev, 680 struct coresight_platform_data *pdata, 681 const struct coresight_connection *new_conn); 682 int coresight_add_in_conn(struct coresight_connection *conn); 683 struct coresight_device * 684 coresight_find_input_type(struct coresight_platform_data *pdata, 685 enum coresight_dev_type type, 686 union coresight_dev_subtype subtype); 687 struct coresight_device * 688 coresight_find_output_type(struct coresight_platform_data *pdata, 689 enum coresight_dev_type type, 690 union coresight_dev_subtype subtype); 691 692 int coresight_init_driver(const char *drv, struct amba_driver *amba_drv, 693 struct platform_driver *pdev_drv); 694 695 void coresight_remove_driver(struct amba_driver *amba_drv, 696 struct platform_driver *pdev_drv); 697 #endif /* _LINUX_COREISGHT_H */ 698