1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #ifndef __AMDGPU_DM_H__
28 #define __AMDGPU_DM_H__
29
30 #include <drm/display/drm_dp_mst_helper.h>
31 #include <drm/drm_atomic.h>
32 #include <drm/drm_connector.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_plane.h>
35 #include "link_service_types.h"
36 #include <drm/drm_writeback.h>
37
38 /*
39 * This file contains the definition for amdgpu_display_manager
40 * and its API for amdgpu driver's use.
41 * This component provides all the display related functionality
42 * and this is the only component that calls DAL API.
43 * The API contained here intended for amdgpu driver use.
44 * The API that is called directly from KMS framework is located
45 * in amdgpu_dm_kms.h file
46 */
47
48 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31
49
50 #define AMDGPU_DM_MAX_CRTC 6
51
52 #define AMDGPU_DM_MAX_NUM_EDP 2
53
54 #define AMDGPU_DMUB_NOTIFICATION_MAX 8
55
56 enum amd_vsdb_panel_type {
57 AMD_VSDB_PANEL_TYPE_DEFAULT = 0,
58 AMD_VSDB_PANEL_TYPE_MINILED,
59 AMD_VSDB_PANEL_TYPE_OLED,
60 AMD_VSDB_PANEL_TYPE_RESERVED,
61 };
62
63 #define AMDGPU_HDR_MULT_DEFAULT (0x100000000LL)
64
65 /*
66 * Maximum HDMI HPD debounce delay in milliseconds
67 */
68 #define AMDGPU_DM_MAX_HDMI_HPD_DEBOUNCE_MS 5000
69 /*
70 #include "include/amdgpu_dal_power_if.h"
71 #include "amdgpu_dm_irq.h"
72 */
73
74 #include "irq_types.h"
75 #include "signal_types.h"
76 #include "amdgpu_dm_crc.h"
77 #include "mod_info_packet.h"
78 struct aux_payload;
79 struct set_config_cmd_payload;
80 enum aux_return_code_type;
81 enum set_config_status;
82
83 /* Forward declarations */
84 struct amdgpu_device;
85 struct amdgpu_crtc;
86 struct drm_device;
87 struct dc;
88 struct amdgpu_bo;
89 struct dmub_srv;
90 struct dc_plane_state;
91 struct dmub_notification;
92 struct dmub_cmd_fused_request;
93
94 struct common_irq_params {
95 struct amdgpu_device *adev;
96 enum dc_irq_source irq_src;
97 atomic64_t previous_timestamp;
98 };
99
100 /**
101 * struct dm_compressor_info - Buffer info used by frame buffer compression
102 * @cpu_addr: MMIO cpu addr
103 * @bo_ptr: Pointer to the buffer object
104 * @gpu_addr: MMIO gpu addr
105 */
106 struct dm_compressor_info {
107 void *cpu_addr;
108 struct amdgpu_bo *bo_ptr;
109 uint64_t gpu_addr;
110 };
111
112 /**
113 * struct dm_boot_time_crc_info - Buffer info used by boot time CRC
114 * @cpu_addr: MMIO cpu addr
115 * @bo_ptr: Pointer to the buffer object
116 * @gpu_addr: MMIO gpu addr
117 * @size: Size of the buffer
118 */
119 struct dm_boot_time_crc_info {
120 void *cpu_addr;
121 struct amdgpu_bo *bo_ptr;
122 uint64_t gpu_addr;
123 uint32_t size;
124 };
125
126 typedef void (*dmub_notify_interrupt_callback_t)(struct amdgpu_device *adev, struct dmub_notification *notify);
127
128 /**
129 * struct dmub_hpd_work - Handle time consuming work in low priority outbox IRQ
130 *
131 * @handle_hpd_work: Work to be executed in a separate thread to handle hpd_low_irq
132 * @dmub_notify: notification for callback function
133 * @adev: amdgpu_device pointer
134 */
135 struct dmub_hpd_work {
136 struct work_struct handle_hpd_work;
137 struct dmub_notification *dmub_notify;
138 struct amdgpu_device *adev;
139 };
140
141 /**
142 * struct vblank_control_work - Work data for vblank control
143 * @work: Kernel work data for the work event
144 * @dm: amdgpu display manager device
145 * @acrtc: amdgpu CRTC instance for which the event has occurred
146 * @stream: DC stream for which the event has occurred
147 * @enable: true if enabling vblank
148 */
149 struct vblank_control_work {
150 struct work_struct work;
151 struct amdgpu_display_manager *dm;
152 struct amdgpu_crtc *acrtc;
153 struct dc_stream_state *stream;
154 bool enable;
155 };
156
157 /**
158 * struct idle_workqueue - Work data for periodic action in idle
159 * @work: Kernel work data for the work event
160 * @dm: amdgpu display manager device
161 * @enable: true if idle worker is enabled
162 * @running: true if idle worker is running
163 */
164 struct idle_workqueue {
165 struct work_struct work;
166 struct amdgpu_display_manager *dm;
167 bool enable;
168 bool running;
169 };
170
171 /**
172 * struct vupdate_offload_work - Work data for offloading task from vupdate handler
173 * @work: Kernel work data for the work event
174 * @adev: amdgpu_device back pointer
175 * @stream: DC stream associated with the crtc
176 * @adjust: DC CRTC timing adjust to be applied to the crtc
177 */
178 struct vupdate_offload_work {
179 struct work_struct work;
180 struct amdgpu_device *adev;
181 struct dc_stream_state *stream;
182 struct dc_crtc_timing_adjust *adjust;
183 };
184
185 #define MAX_LUMINANCE_DATA_POINTS 99
186
187 /**
188 * struct amdgpu_dm_luminance_data - Custom luminance data
189 * @luminance: Luminance in percent
190 * @input_signal: Input signal in range 0-255
191 */
192 struct amdgpu_dm_luminance_data {
193 u8 luminance;
194 u8 input_signal;
195 } __packed;
196
197 /**
198 * struct amdgpu_dm_backlight_caps - Information about backlight
199 *
200 * Describe the backlight support for ACPI or eDP AUX.
201 */
202 struct amdgpu_dm_backlight_caps {
203 /**
204 * @ext_caps: Keep the data struct with all the information about the
205 * display support for HDR.
206 */
207 union dpcd_sink_ext_caps *ext_caps;
208 /**
209 * @aux_min_input_signal: Min brightness value supported by the display
210 */
211 u32 aux_min_input_signal;
212 /**
213 * @aux_max_input_signal: Max brightness value supported by the display
214 * in nits.
215 */
216 u32 aux_max_input_signal;
217 /**
218 * @min_input_signal: minimum possible input in range 0-255.
219 */
220 int min_input_signal;
221 /**
222 * @max_input_signal: maximum possible input in range 0-255.
223 */
224 int max_input_signal;
225 /**
226 * @caps_valid: true if these values are from the ACPI interface.
227 */
228 bool caps_valid;
229 /**
230 * @aux_support: Describes if the display supports AUX backlight.
231 */
232 bool aux_support;
233 /**
234 * @brightness_mask: After deriving brightness, OR it with this mask.
235 * Workaround for panels with issues with certain brightness values.
236 */
237 u32 brightness_mask;
238 /**
239 * @ac_level: the default brightness if booted on AC
240 */
241 u8 ac_level;
242 /**
243 * @dc_level: the default brightness if booted on DC
244 */
245 u8 dc_level;
246 /**
247 * @data_points: the number of custom luminance data points
248 */
249 u8 data_points;
250 /**
251 * @luminance_data: custom luminance data
252 */
253 struct amdgpu_dm_luminance_data luminance_data[MAX_LUMINANCE_DATA_POINTS];
254 };
255
256 /**
257 * struct dal_allocation - Tracks mapped FB memory for SMU communication
258 * @list: list of dal allocations
259 * @bo: GPU buffer object
260 * @cpu_ptr: CPU virtual address of the GPU buffer object
261 * @gpu_addr: GPU virtual address of the GPU buffer object
262 */
263 struct dal_allocation {
264 struct list_head list;
265 struct amdgpu_bo *bo;
266 void *cpu_ptr;
267 u64 gpu_addr;
268 };
269
270 /**
271 * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq
272 * offload work
273 */
274 struct hpd_rx_irq_offload_work_queue {
275 /**
276 * @wq: workqueue structure to queue offload work.
277 */
278 struct workqueue_struct *wq;
279 /**
280 * @offload_lock: To protect fields of offload work queue.
281 */
282 spinlock_t offload_lock;
283 /**
284 * @is_handling_link_loss: Used to prevent inserting link loss event when
285 * we're handling link loss
286 */
287 bool is_handling_link_loss;
288 /**
289 * @is_handling_mst_msg_rdy_event: Used to prevent inserting mst message
290 * ready event when we're already handling mst message ready event
291 */
292 bool is_handling_mst_msg_rdy_event;
293 /**
294 * @aconnector: The aconnector that this work queue is attached to
295 */
296 struct amdgpu_dm_connector *aconnector;
297 };
298
299 /**
300 * struct hpd_rx_irq_offload_work - hpd_rx_irq offload work structure
301 */
302 struct hpd_rx_irq_offload_work {
303 /**
304 * @work: offload work
305 */
306 struct work_struct work;
307 /**
308 * @data: reference irq data which is used while handling offload work
309 */
310 union hpd_irq_data data;
311 /**
312 * @offload_wq: offload work queue that this work is queued to
313 */
314 struct hpd_rx_irq_offload_work_queue *offload_wq;
315 /**
316 * @adev: amdgpu_device pointer
317 */
318 struct amdgpu_device *adev;
319 };
320
321 /**
322 * struct amdgpu_display_manager - Central amdgpu display manager device
323 *
324 * @dc: Display Core control structure
325 * @adev: AMDGPU base driver structure
326 * @ddev: DRM base driver structure
327 * @display_indexes_num: Max number of display streams supported
328 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables
329 * @backlight_dev: Backlight control device
330 * @backlight_link: Link on which to control backlight
331 * @backlight_caps: Capabilities of the backlight device
332 * @freesync_module: Module handling freesync calculations
333 * @hdcp_workqueue: AMDGPU content protection queue
334 * @fw_dmcu: Reference to DMCU firmware
335 * @dmcu_fw_version: Version of the DMCU firmware
336 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW
337 * @cached_state: Caches device atomic state for suspend/resume
338 * @cached_dc_state: Cached state of content streams
339 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info
340 * @force_timing_sync: set via debugfs. When set, indicates that all connected
341 * displays will be forced to synchronize.
342 * @dmcub_trace_event_en: enable dmcub trace events
343 * @dmub_outbox_params: DMUB Outbox parameters
344 * @num_of_edps: number of backlight eDPs
345 * @disable_hpd_irq: disables all HPD and HPD RX interrupt handling in the
346 * driver when true
347 * @dmub_aux_transfer_done: struct completion used to indicate when DMUB
348 * transfers are done
349 * @delayed_hpd_wq: work queue used to delay DMUB HPD work
350 */
351 struct amdgpu_display_manager {
352
353 struct dc *dc;
354
355 /**
356 * @dmub_srv:
357 *
358 * DMUB service, used for controlling the DMUB on hardware
359 * that supports it. The pointer to the dmub_srv will be
360 * NULL on hardware that does not support it.
361 */
362 struct dmub_srv *dmub_srv;
363
364 /**
365 * @dmub_notify:
366 *
367 * Notification from DMUB.
368 */
369
370 struct dmub_notification *dmub_notify;
371
372 /**
373 * @dmub_callback:
374 *
375 * Callback functions to handle notification from DMUB.
376 */
377
378 dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX];
379
380 /**
381 * @dmub_thread_offload:
382 *
383 * Flag to indicate if callback is offload.
384 */
385
386 bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX];
387
388 /**
389 * @dmub_fb_info:
390 *
391 * Framebuffer regions for the DMUB.
392 */
393 struct dmub_srv_fb_info *dmub_fb_info;
394
395 /**
396 * @dmub_fw:
397 *
398 * DMUB firmware, required on hardware that has DMUB support.
399 */
400 const struct firmware *dmub_fw;
401
402 /**
403 * @dmub_bo:
404 *
405 * Buffer object for the DMUB.
406 */
407 struct amdgpu_bo *dmub_bo;
408
409 /**
410 * @dmub_bo_gpu_addr:
411 *
412 * GPU virtual address for the DMUB buffer object.
413 */
414 u64 dmub_bo_gpu_addr;
415
416 /**
417 * @dmub_bo_cpu_addr:
418 *
419 * CPU address for the DMUB buffer object.
420 */
421 void *dmub_bo_cpu_addr;
422
423 /**
424 * @dmcub_fw_version:
425 *
426 * DMCUB firmware version.
427 */
428 uint32_t dmcub_fw_version;
429
430 /**
431 * @fw_inst_size:
432 *
433 * Size of the firmware instruction buffer.
434 */
435 uint32_t fw_inst_size;
436
437 /**
438 * @cgs_device:
439 *
440 * The Common Graphics Services device. It provides an interface for
441 * accessing registers.
442 */
443 struct cgs_device *cgs_device;
444
445 struct amdgpu_device *adev;
446 struct drm_device *ddev;
447 u16 display_indexes_num;
448
449 /**
450 * @atomic_obj:
451 *
452 * In combination with &dm_atomic_state it helps manage
453 * global atomic state that doesn't map cleanly into existing
454 * drm resources, like &dc_context.
455 */
456 struct drm_private_obj atomic_obj;
457
458 /**
459 * @dc_lock:
460 *
461 * Guards access to DC functions that can issue register write
462 * sequences.
463 */
464 struct mutex dc_lock;
465
466 /**
467 * @audio_lock:
468 *
469 * Guards access to audio instance changes.
470 */
471 struct mutex audio_lock;
472
473 /**
474 * @audio_component:
475 *
476 * Used to notify ELD changes to sound driver.
477 */
478 struct drm_audio_component *audio_component;
479
480 /**
481 * @audio_registered:
482 *
483 * True if the audio component has been registered
484 * successfully, false otherwise.
485 */
486 bool audio_registered;
487
488 /**
489 * @irq_handler_list_low_tab:
490 *
491 * Low priority IRQ handler table.
492 *
493 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ
494 * source. Low priority IRQ handlers are deferred to a workqueue to be
495 * processed. Hence, they can sleep.
496 *
497 * Note that handlers are called in the same order as they were
498 * registered (FIFO).
499 */
500 struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
501
502 /**
503 * @irq_handler_list_high_tab:
504 *
505 * High priority IRQ handler table.
506 *
507 * It is a n*m table, same as &irq_handler_list_low_tab. However,
508 * handlers in this table are not deferred and are called immediately.
509 */
510 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER];
511
512 /**
513 * @pflip_params:
514 *
515 * Page flip IRQ parameters, passed to registered handlers when
516 * triggered.
517 */
518 struct common_irq_params
519 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1];
520
521 /**
522 * @vblank_params:
523 *
524 * Vertical blanking IRQ parameters, passed to registered handlers when
525 * triggered.
526 */
527 struct common_irq_params
528 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1];
529
530 /**
531 * @vline0_params:
532 *
533 * OTG vertical interrupt0 IRQ parameters, passed to registered
534 * handlers when triggered.
535 */
536 struct common_irq_params
537 vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1];
538
539 /**
540 * @vupdate_params:
541 *
542 * Vertical update IRQ parameters, passed to registered handlers when
543 * triggered.
544 */
545 struct common_irq_params
546 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1];
547
548 /**
549 * @dmub_trace_params:
550 *
551 * DMUB trace event IRQ parameters, passed to registered handlers when
552 * triggered.
553 */
554 struct common_irq_params
555 dmub_trace_params[1];
556
557 struct common_irq_params
558 dmub_outbox_params[1];
559
560 spinlock_t irq_handler_list_table_lock;
561
562 struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP];
563
564 const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP];
565
566 uint8_t num_of_edps;
567
568 struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP];
569
570 struct mod_freesync *freesync_module;
571 struct hdcp_workqueue *hdcp_workqueue;
572
573 /**
574 * @vblank_control_workqueue:
575 *
576 * Deferred work for vblank control events.
577 */
578 struct workqueue_struct *vblank_control_workqueue;
579
580 /**
581 * @idle_workqueue:
582 *
583 * Periodic work for idle events.
584 */
585 struct idle_workqueue *idle_workqueue;
586
587 struct drm_atomic_state *cached_state;
588 struct dc_state *cached_dc_state;
589
590 struct dm_compressor_info compressor;
591
592 const struct firmware *fw_dmcu;
593 uint32_t dmcu_fw_version;
594 /**
595 * @soc_bounding_box:
596 *
597 * gpu_info FW provided soc bounding box struct or 0 if not
598 * available in FW
599 */
600 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
601
602 /**
603 * @active_vblank_irq_count:
604 *
605 * number of currently active vblank irqs
606 */
607 uint32_t active_vblank_irq_count;
608
609 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
610 /**
611 * @secure_display_ctx:
612 *
613 * Store secure display relevant info. e.g. the ROI information
614 * , the work_struct to command dmub, etc.
615 */
616 struct secure_display_context secure_display_ctx;
617 #endif
618 /**
619 * @hpd_rx_offload_wq:
620 *
621 * Work queue to offload works of hpd_rx_irq
622 */
623 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq;
624 /**
625 * @mst_encoders:
626 *
627 * fake encoders used for DP MST.
628 */
629 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC];
630 bool force_timing_sync;
631 bool disable_hpd_irq;
632 bool dmcub_trace_event_en;
633 /**
634 * @da_list:
635 *
636 * DAL fb memory allocation list, for communication with SMU.
637 */
638 struct list_head da_list;
639 struct completion dmub_aux_transfer_done;
640 struct workqueue_struct *delayed_hpd_wq;
641
642 /**
643 * @brightness:
644 *
645 * cached backlight values.
646 */
647 u32 brightness[AMDGPU_DM_MAX_NUM_EDP];
648 /**
649 * @actual_brightness:
650 *
651 * last successfully applied backlight values.
652 */
653 u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP];
654
655 /**
656 * @aux_hpd_discon_quirk:
657 *
658 * quirk for hpd discon while aux is on-going.
659 * occurred on certain intel platform
660 */
661 bool aux_hpd_discon_quirk;
662
663 /**
664 * @edp0_on_dp1_quirk:
665 *
666 * quirk for platforms that put edp0 on DP1.
667 */
668 bool edp0_on_dp1_quirk;
669
670 /**
671 * @dpia_aux_lock:
672 *
673 * Guards access to DPIA AUX
674 */
675 struct mutex dpia_aux_lock;
676
677 /**
678 * @bb_from_dmub:
679 *
680 * Bounding box data read from dmub during early initialization for DCN4+
681 * Data is stored as a byte array that should be casted to the appropriate bb struct
682 */
683 void *bb_from_dmub;
684
685 /**
686 * @oem_i2c:
687 *
688 * OEM i2c bus
689 */
690 struct amdgpu_i2c_adapter *oem_i2c;
691
692 /**
693 * @fused_io:
694 *
695 * dmub fused io interface
696 */
697 struct fused_io_sync {
698 struct completion replied;
699 char reply_data[0x40]; // Cannot include dmub_cmd here
700 } fused_io[8];
701
702 /**
703 * @dm_boot_time_crc_info:
704 *
705 * Buffer info for the boot time crc.
706 */
707 struct dm_boot_time_crc_info boot_time_crc_info;
708 };
709
710 enum dsc_clock_force_state {
711 DSC_CLK_FORCE_DEFAULT = 0,
712 DSC_CLK_FORCE_ENABLE,
713 DSC_CLK_FORCE_DISABLE,
714 };
715
716 struct dsc_preferred_settings {
717 enum dsc_clock_force_state dsc_force_enable;
718 uint32_t dsc_num_slices_v;
719 uint32_t dsc_num_slices_h;
720 uint32_t dsc_bits_per_pixel;
721 bool dsc_force_disable_passthrough;
722 };
723
724 enum mst_progress_status {
725 MST_STATUS_DEFAULT = 0,
726 MST_PROBE = BIT(0),
727 MST_REMOTE_EDID = BIT(1),
728 MST_ALLOCATE_NEW_PAYLOAD = BIT(2),
729 MST_CLEAR_ALLOCATED_PAYLOAD = BIT(3),
730 };
731
732 /**
733 * struct amdgpu_hdmi_vsdb_info - Keep track of the VSDB info
734 *
735 * AMDGPU supports FreeSync over HDMI by using the VSDB section, and this
736 * struct is useful to keep track of the display-specific information about
737 * FreeSync.
738 */
739 struct amdgpu_hdmi_vsdb_info {
740 /**
741 * @amd_vsdb_version: Vendor Specific Data Block Version, should be
742 * used to determine which Vendor Specific InfoFrame (VSIF) to send.
743 */
744 unsigned int amd_vsdb_version;
745
746 /**
747 * @freesync_supported: FreeSync Supported.
748 */
749 bool freesync_supported;
750
751 /**
752 * @min_refresh_rate_hz: FreeSync Minimum Refresh Rate in Hz.
753 */
754 unsigned int min_refresh_rate_hz;
755
756 /**
757 * @max_refresh_rate_hz: FreeSync Maximum Refresh Rate in Hz
758 */
759 unsigned int max_refresh_rate_hz;
760
761 /**
762 * @freesync_mccs_vcp_code: MCCS VCP code for freesync state
763 */
764 unsigned int freesync_mccs_vcp_code;
765
766 /**
767 * @replay_mode: Replay supported
768 */
769 bool replay_mode;
770 };
771
772 struct amdgpu_dm_connector {
773
774 struct drm_connector base;
775 uint32_t connector_id;
776 int bl_idx;
777
778 struct cec_notifier *notifier;
779
780 /* we need to mind the EDID between detect
781 and get modes due to analog/digital/tvencoder */
782 const struct drm_edid *drm_edid;
783
784 /* shared with amdgpu */
785 struct amdgpu_hpd hpd;
786
787 /* number of modes generated from EDID at 'dc_sink' */
788 int num_modes;
789
790 /* The 'old' sink - before an HPD.
791 * The 'current' sink is in dc_link->sink. */
792 struct dc_sink *dc_sink;
793 struct dc_link *dc_link;
794
795 /**
796 * @dc_em_sink: Reference to the emulated (virtual) sink.
797 */
798 struct dc_sink *dc_em_sink;
799
800 /* DM only */
801 struct drm_dp_mst_topology_mgr mst_mgr;
802 struct amdgpu_dm_dp_aux dm_dp_aux;
803 struct drm_dp_mst_port *mst_output_port;
804 struct amdgpu_dm_connector *mst_root;
805 struct drm_dp_aux *dsc_aux;
806 uint32_t mst_local_bw;
807 uint16_t vc_full_pbn;
808 struct mutex handle_mst_msg_ready;
809
810 /* branch device specific data */
811 uint32_t branch_ieee_oui;
812
813 /* TODO see if we can merge with ddc_bus or make a dm_connector */
814 struct amdgpu_i2c_adapter *i2c;
815
816 /* Monitor range limits */
817 /**
818 * @min_vfreq: Minimal frequency supported by the display in Hz. This
819 * value is set to zero when there is no FreeSync support.
820 */
821 int min_vfreq;
822
823 /**
824 * @max_vfreq: Maximum frequency supported by the display in Hz. This
825 * value is set to zero when there is no FreeSync support.
826 */
827 int max_vfreq ;
828
829 /* Audio instance - protected by audio_lock. */
830 int audio_inst;
831
832 struct mutex hpd_lock;
833
834 bool fake_enable;
835 bool force_yuv420_output;
836 bool force_yuv422_output;
837 struct dsc_preferred_settings dsc_settings;
838 union dp_downstream_port_present mst_downstream_port_present;
839 /* Cached display modes */
840 struct drm_display_mode freesync_vid_base;
841
842 int sr_skip_count;
843 bool disallow_edp_enter_psr;
844 bool disallow_edp_enter_replay;
845
846 /* Record progress status of mst*/
847 uint8_t mst_status;
848
849 /* Automated testing */
850 bool timing_changed;
851 struct dc_crtc_timing *timing_requested;
852
853 /* Adaptive Sync */
854 bool pack_sdp_v1_3;
855 enum adaptive_sync_type as_type;
856 struct amdgpu_hdmi_vsdb_info vsdb_info;
857
858 /* HDMI HPD debounce support */
859 unsigned int hdmi_hpd_debounce_delay_ms;
860 struct delayed_work hdmi_hpd_debounce_work;
861 struct dc_sink *hdmi_prev_sink;
862 };
863
amdgpu_dm_set_mst_status(uint8_t * status,uint8_t flags,bool set)864 static inline void amdgpu_dm_set_mst_status(uint8_t *status,
865 uint8_t flags, bool set)
866 {
867 if (set)
868 *status |= flags;
869 else
870 *status &= ~flags;
871 }
872
873 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base)
874
875 struct amdgpu_dm_wb_connector {
876 struct drm_writeback_connector base;
877 struct dc_link *link;
878 };
879
880 #define to_amdgpu_dm_wb_connector(x) container_of(x, struct amdgpu_dm_wb_connector, base)
881
882 extern const struct amdgpu_ip_block_version dm_ip_block;
883
884 /* enum amdgpu_transfer_function: pre-defined transfer function supported by AMD.
885 *
886 * It includes standardized transfer functions and pure power functions. The
887 * transfer function coefficients are available at modules/color/color_gamma.c
888 */
889 enum amdgpu_transfer_function {
890 AMDGPU_TRANSFER_FUNCTION_DEFAULT,
891 AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF,
892 AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF,
893 AMDGPU_TRANSFER_FUNCTION_PQ_EOTF,
894 AMDGPU_TRANSFER_FUNCTION_IDENTITY,
895 AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF,
896 AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF,
897 AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF,
898 AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF,
899 AMDGPU_TRANSFER_FUNCTION_BT709_OETF,
900 AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF,
901 AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF,
902 AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF,
903 AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF,
904 AMDGPU_TRANSFER_FUNCTION_COUNT
905 };
906
907 struct dm_plane_state {
908 struct drm_plane_state base;
909 struct dc_plane_state *dc_state;
910
911 /* Plane color mgmt */
912 /**
913 * @degamma_lut:
914 *
915 * 1D LUT for mapping framebuffer/plane pixel data before sampling or
916 * blending operations. It's usually applied to linearize input space.
917 * The blob (if not NULL) is an array of &struct drm_color_lut.
918 */
919 struct drm_property_blob *degamma_lut;
920 /**
921 * @degamma_tf:
922 *
923 * Predefined transfer function to tell DC driver the input space to
924 * linearize.
925 */
926 enum amdgpu_transfer_function degamma_tf;
927 /**
928 * @hdr_mult:
929 *
930 * Multiplier to 'gain' the plane. When PQ is decoded using the fixed
931 * func transfer function to the internal FP16 fb, 1.0 -> 80 nits (on
932 * AMD at least). When sRGB is decoded, 1.0 -> 1.0, obviously.
933 * Therefore, 1.0 multiplier = 80 nits for SDR content. So if you
934 * want, 203 nits for SDR content, pass in (203.0 / 80.0). Format is
935 * S31.32 sign-magnitude.
936 *
937 * HDR multiplier can wide range beyond [0.0, 1.0]. This means that PQ
938 * TF is needed for any subsequent linear-to-non-linear transforms.
939 */
940 __u64 hdr_mult;
941 /**
942 * @ctm:
943 *
944 * Color transformation matrix. The blob (if not NULL) is a &struct
945 * drm_color_ctm_3x4.
946 */
947 struct drm_property_blob *ctm;
948 /**
949 * @shaper_lut: shaper lookup table blob. The blob (if not NULL) is an
950 * array of &struct drm_color_lut.
951 */
952 struct drm_property_blob *shaper_lut;
953 /**
954 * @shaper_tf:
955 *
956 * Predefined transfer function to delinearize color space.
957 */
958 enum amdgpu_transfer_function shaper_tf;
959 /**
960 * @lut3d: 3D lookup table blob. The blob (if not NULL) is an array of
961 * &struct drm_color_lut.
962 */
963 struct drm_property_blob *lut3d;
964 /**
965 * @blend_lut: blend lut lookup table blob. The blob (if not NULL) is an
966 * array of &struct drm_color_lut.
967 */
968 struct drm_property_blob *blend_lut;
969 /**
970 * @blend_tf:
971 *
972 * Pre-defined transfer function for converting plane pixel data before
973 * applying blend LUT.
974 */
975 enum amdgpu_transfer_function blend_tf;
976 };
977
978 enum amdgpu_dm_cursor_mode {
979 DM_CURSOR_NATIVE_MODE = 0,
980 DM_CURSOR_OVERLAY_MODE,
981 };
982
983 struct dm_crtc_state {
984 struct drm_crtc_state base;
985 struct dc_stream_state *stream;
986
987 bool cm_has_degamma;
988 bool cm_is_degamma_srgb;
989
990 bool mpo_requested;
991
992 int update_type;
993 int active_planes;
994
995 int crc_skip_count;
996
997 bool freesync_vrr_info_changed;
998
999 bool mode_changed_independent_from_dsc;
1000 bool dsc_force_changed;
1001 bool vrr_supported;
1002 struct mod_freesync_config freesync_config;
1003 struct dc_info_packet vrr_infopacket;
1004
1005 int abm_level;
1006
1007 /**
1008 * @regamma_tf:
1009 *
1010 * Pre-defined transfer function for converting internal FB -> wire
1011 * encoding.
1012 */
1013 enum amdgpu_transfer_function regamma_tf;
1014
1015 enum amdgpu_dm_cursor_mode cursor_mode;
1016 };
1017
1018 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
1019
1020 struct dm_atomic_state {
1021 struct drm_private_state base;
1022
1023 struct dc_state *context;
1024 };
1025
1026 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base)
1027
1028 struct dm_connector_state {
1029 struct drm_connector_state base;
1030
1031 enum amdgpu_rmx_type scaling;
1032 uint8_t underscan_vborder;
1033 uint8_t underscan_hborder;
1034 bool underscan_enable;
1035 bool freesync_capable;
1036 bool update_hdcp;
1037 bool abm_sysfs_forbidden;
1038 uint8_t abm_level;
1039 int vcpi_slots;
1040 uint64_t pbn;
1041 };
1042
1043 #define to_dm_connector_state(x)\
1044 container_of((x), struct dm_connector_state, base)
1045
1046 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector);
1047 struct drm_connector_state *
1048 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector);
1049 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
1050 struct drm_connector_state *state,
1051 struct drm_property *property,
1052 uint64_t val);
1053
1054 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
1055 const struct drm_connector_state *state,
1056 struct drm_property *property,
1057 uint64_t *val);
1058
1059 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev);
1060
1061 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
1062 struct amdgpu_dm_connector *aconnector,
1063 int connector_type,
1064 struct dc_link *link,
1065 int link_index);
1066
1067 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
1068 const struct drm_display_mode *mode);
1069
1070 void dm_restore_drm_connector_state(struct drm_device *dev,
1071 struct drm_connector *connector);
1072
1073 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
1074 const struct drm_edid *drm_edid, bool do_mccs);
1075
1076 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev);
1077
1078 /* 3D LUT max size is 17x17x17 (4913 entries) */
1079 #define MAX_COLOR_3DLUT_SIZE 17
1080 #define MAX_COLOR_3DLUT_BITDEPTH 12
1081 int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev,
1082 struct drm_plane_state *plane_state);
1083 /* 1D LUT size */
1084 #define MAX_COLOR_LUT_ENTRIES 4096
1085 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */
1086 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256
1087
1088 void amdgpu_dm_init_color_mod(void);
1089 int amdgpu_dm_create_color_properties(struct amdgpu_device *adev);
1090 int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state);
1091 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc);
1092 int amdgpu_dm_check_crtc_color_mgmt(struct dm_crtc_state *crtc,
1093 bool check_only);
1094 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
1095 struct drm_plane_state *plane_state,
1096 struct dc_plane_state *dc_plane_state);
1097
1098 void amdgpu_dm_update_connector_after_detect(
1099 struct amdgpu_dm_connector *aconnector);
1100
1101 void populate_hdmi_info_from_connector(struct drm_hdmi_info *info,
1102 struct dc_edid_caps *edid_caps);
1103
1104 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;
1105
1106 int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int link_index,
1107 struct aux_payload *payload, enum aux_return_code_type *operation_result);
1108
1109 bool amdgpu_dm_execute_fused_io(
1110 struct amdgpu_device *dev,
1111 struct dc_link *link,
1112 union dmub_rb_cmd *commands,
1113 uint8_t count,
1114 uint32_t timeout_us
1115 );
1116
1117 int amdgpu_dm_process_dmub_set_config_sync(struct dc_context *ctx, unsigned int link_index,
1118 struct set_config_cmd_payload *payload, enum set_config_status *operation_result);
1119
1120 struct dc_stream_state *
1121 create_validate_stream_for_sink(struct drm_connector *connector,
1122 const struct drm_display_mode *drm_mode,
1123 const struct dm_connector_state *dm_state,
1124 const struct dc_stream_state *old_stream);
1125
1126 int dm_atomic_get_state(struct drm_atomic_state *state,
1127 struct dm_atomic_state **dm_state);
1128
1129 struct drm_connector *
1130 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
1131 struct drm_crtc *crtc);
1132
1133 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth);
1134 struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev);
1135
1136 void *dm_allocate_gpu_mem(struct amdgpu_device *adev,
1137 enum dc_gpu_mem_alloc_type type,
1138 size_t size,
1139 long long *addr);
1140 void dm_free_gpu_mem(struct amdgpu_device *adev,
1141 enum dc_gpu_mem_alloc_type type,
1142 void *addr);
1143
1144 bool amdgpu_dm_is_headless(struct amdgpu_device *adev);
1145
1146 void hdmi_cec_set_edid(struct amdgpu_dm_connector *aconnector);
1147 void hdmi_cec_unset_edid(struct amdgpu_dm_connector *aconnector);
1148 int amdgpu_dm_initialize_hdmi_connector(struct amdgpu_dm_connector *aconnector);
1149
1150 void retrieve_dmi_info(struct amdgpu_display_manager *dm);
1151
1152 #endif /* __AMDGPU_DM_H__ */
1153